1 /* 2 * 3 * CDDL HEADER START 4 * 5 * The contents of this file are subject to the terms of the 6 * Common Development and Distribution License (the "License"). 7 * You may not use this file except in compliance with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright (c) 2003, 2010, Oracle and/or its affiliates. All rights reserved. 24 * Copyright 2019 Joyent, Inc. 25 * Copyright 2020 Robert Mustacchi 26 */ 27 28 /* 29 * Copyright (c) 2010, Intel Corporation. 30 * All rights reserved. 31 */ 32 33 /* Copyright (c) 1988 AT&T */ 34 /* All Rights Reserved */ 35 36 /* 37 * $FreeBSD$ 38 */ 39 40 #include "dis_tables.h" 41 42 /* BEGIN CSTYLED */ 43 44 /* 45 * Disassembly begins in dis_distable, which is equivalent to the One-byte 46 * Opcode Map in the Intel IA32 ISA Reference (page A-6 in my copy). The 47 * decoding loops then traverse out through the other tables as necessary to 48 * decode a given instruction. 49 * 50 * The behavior of this file can be controlled by one of the following flags: 51 * 52 * DIS_TEXT Include text for disassembly 53 * DIS_MEM Include memory-size calculations 54 * 55 * Either or both of these can be defined. 56 * 57 * This file is not, and will never be, cstyled. If anything, the tables should 58 * be taken out another tab stop or two so nothing overlaps. 59 */ 60 61 /* 62 * These functions must be provided for the consumer to do disassembly. 63 */ 64 #ifdef DIS_TEXT 65 extern char *strncpy(char *, const char *, size_t); 66 extern size_t strlen(const char *); 67 extern int strcmp(const char *, const char *); 68 extern int strncmp(const char *, const char *, size_t); 69 extern size_t strlcat(char *, const char *, size_t); 70 #endif 71 72 73 #define TERM 0 /* used to indicate that the 'indirect' */ 74 /* field terminates - no pointer. */ 75 76 /* Used to decode instructions. */ 77 typedef struct instable { 78 struct instable *it_indirect; /* for decode op codes */ 79 uchar_t it_adrmode; 80 #ifdef DIS_TEXT 81 char it_name[NCPS]; 82 uint_t it_suffix:1; /* mnem + "w", "l", or "d" */ 83 #endif 84 #ifdef DIS_MEM 85 uint_t it_size:16; 86 #endif 87 uint_t it_invalid64:1; /* opcode invalid in amd64 */ 88 uint_t it_always64:1; /* 64 bit when in 64 bit mode */ 89 uint_t it_invalid32:1; /* invalid in IA32 */ 90 uint_t it_stackop:1; /* push/pop stack operation */ 91 uint_t it_vexwoxmm:1; /* VEX instructions that don't use XMM/YMM */ 92 uint_t it_avxsuf:2; /* AVX2/AVX512 suffix rqd. */ 93 uint_t it_vexopmask:1; /* VEX inst. that use opmask */ 94 } instable_t; 95 96 /* 97 * Instruction formats. 98 */ 99 enum { 100 UNKNOWN, 101 MRw, 102 IMlw, 103 IMw, 104 IR, 105 OA, 106 AO, 107 MS, 108 SM, 109 Mv, 110 Mw, 111 M, /* register or memory */ 112 MG9, /* register or memory in group 9 (prefix optional) */ 113 Mb, /* register or memory, always byte sized */ 114 MO, /* memory only (no registers) */ 115 PREF, 116 SWAPGS_RDTSCP, 117 MONITOR_MWAIT, 118 R, 119 RA, 120 SEG, 121 MR, 122 RM, 123 RM_66r, /* RM, but with a required 0x66 prefix */ 124 IA, 125 MA, 126 SD, 127 AD, 128 SA, 129 D, 130 INM, 131 SO, 132 BD, 133 I, 134 P, 135 V, 136 DSHIFT, /* for double shift that has an 8-bit immediate */ 137 U, 138 OVERRIDE, 139 NORM, /* instructions w/o ModR/M byte, no memory access */ 140 IMPLMEM, /* instructions w/o ModR/M byte, implicit mem access */ 141 O, /* for call */ 142 JTAB, /* jump table */ 143 IMUL, /* for 186 iimul instr */ 144 CBW, /* so data16 can be evaluated for cbw and variants */ 145 MvI, /* for 186 logicals */ 146 ENTER, /* for 186 enter instr */ 147 RMw, /* for 286 arpl instr */ 148 Ib, /* for push immediate byte */ 149 F, /* for 287 instructions */ 150 FF, /* for 287 instructions */ 151 FFC, /* for 287 instructions */ 152 DM, /* 16-bit data */ 153 AM, /* 16-bit addr */ 154 LSEG, /* for 3-bit seg reg encoding */ 155 MIb, /* for 386 logicals */ 156 SREG, /* for 386 special registers */ 157 PREFIX, /* a REP instruction prefix */ 158 LOCK, /* a LOCK instruction prefix */ 159 INT3, /* The int 3 instruction, which has a fake operand */ 160 INTx, /* The normal int instruction, with explicit int num */ 161 DSHIFTcl, /* for double shift that implicitly uses %cl */ 162 CWD, /* so data16 can be evaluated for cwd and variants */ 163 RET, /* single immediate 16-bit operand */ 164 MOVZ, /* for movs and movz, with different size operands */ 165 CRC32, /* for crc32, with different size operands */ 166 XADDB, /* for xaddb */ 167 MOVSXZ, /* AMD64 mov sign extend 32 to 64 bit instruction */ 168 MOVBE, /* movbe instruction */ 169 170 /* 171 * MMX/SIMD addressing modes. 172 */ 173 174 MMO, /* Prefixable MMX/SIMD-Int mm/mem -> mm */ 175 MMOIMPL, /* Prefixable MMX/SIMD-Int mm -> mm (mem) */ 176 MMO3P, /* Prefixable MMX/SIMD-Int mm -> r32,imm8 */ 177 MMOM3, /* Prefixable MMX/SIMD-Int mm -> r32 */ 178 MMOS, /* Prefixable MMX/SIMD-Int mm -> mm/mem */ 179 MMOMS, /* Prefixable MMX/SIMD-Int mm -> mem */ 180 MMOPM, /* MMX/SIMD-Int mm/mem -> mm,imm8 */ 181 MMOPM_66o, /* MMX/SIMD-Int 0x66 optional mm/mem -> mm,imm8 */ 182 MMOPRM, /* Prefixable MMX/SIMD-Int r32/mem -> mm,imm8 */ 183 MMOSH, /* Prefixable MMX mm,imm8 */ 184 MM, /* MMX/SIMD-Int mm/mem -> mm */ 185 MMS, /* MMX/SIMD-Int mm -> mm/mem */ 186 MMSH, /* MMX mm,imm8 */ 187 XMMO, /* Prefixable SIMD xmm/mem -> xmm */ 188 XMMOS, /* Prefixable SIMD xmm -> xmm/mem */ 189 XMMOPM, /* Prefixable SIMD xmm/mem w/to xmm,imm8 */ 190 XMMOMX, /* Prefixable SIMD mm/mem -> xmm */ 191 XMMOX3, /* Prefixable SIMD xmm -> r32 */ 192 XMMOXMM, /* Prefixable SIMD xmm/mem -> mm */ 193 XMMOM, /* Prefixable SIMD xmm -> mem */ 194 XMMOMS, /* Prefixable SIMD mem -> xmm */ 195 XMM, /* SIMD xmm/mem -> xmm */ 196 XMM_66r, /* SIMD 0x66 prefix required xmm/mem -> xmm */ 197 XMM_66o, /* SIMD 0x66 prefix optional xmm/mem -> xmm */ 198 XMMXIMPL, /* SIMD xmm -> xmm (mem) */ 199 XMM3P, /* SIMD xmm -> r32,imm8 */ 200 XMM3PM_66r, /* SIMD 0x66 prefix required xmm -> r32/mem,imm8 */ 201 XMMP, /* SIMD xmm/mem w/to xmm,imm8 */ 202 XMMP_66o, /* SIMD 0x66 prefix optional xmm/mem w/to xmm,imm8 */ 203 XMMP_66r, /* SIMD 0x66 prefix required xmm/mem w/to xmm,imm8 */ 204 XMMPRM, /* SIMD r32/mem -> xmm,imm8 */ 205 XMMPRM_66r, /* SIMD 0x66 prefix required r32/mem -> xmm,imm8 */ 206 XMMS, /* SIMD xmm -> xmm/mem */ 207 XMMM, /* SIMD mem -> xmm */ 208 XMMM_66r, /* SIMD 0x66 prefix required mem -> xmm */ 209 XMMMS, /* SIMD xmm -> mem */ 210 XMM3MX, /* SIMD r32/mem -> xmm */ 211 XMM3MXS, /* SIMD xmm -> r32/mem */ 212 XMMSH, /* SIMD xmm,imm8 */ 213 XMMXM3, /* SIMD xmm/mem -> r32 */ 214 XMMX3, /* SIMD xmm -> r32 */ 215 XMMXMM, /* SIMD xmm/mem -> mm */ 216 XMMMX, /* SIMD mm -> xmm */ 217 XMMXM, /* SIMD xmm -> mm */ 218 XMMX2I, /* SIMD xmm -> xmm, imm, imm */ 219 XMM2I, /* SIMD xmm, imm, imm */ 220 XMMFENCE, /* SIMD lfence or mfence */ 221 XMMSFNC, /* SIMD sfence (none or mem) */ 222 FSGS, /* FSGSBASE if reg */ 223 XGETBV_XSETBV, 224 VEX_NONE, /* VEX no operand */ 225 VEX_MO, /* VEX mod_rm -> implicit reg */ 226 VEX_RMrX, /* VEX VEX.vvvv, mod_rm -> mod_reg */ 227 VEX_VRMrX, /* VEX mod_rm, VEX.vvvv -> mod_rm */ 228 VEX_RRX, /* VEX VEX.vvvv, mod_reg -> mod_rm */ 229 VEX_RMRX, /* VEX VEX.vvvv, mod_rm, imm8[7:4] -> mod_reg */ 230 VEX_MX, /* VEX mod_rm -> mod_reg */ 231 VEX_MXI, /* VEX mod_rm, imm8 -> mod_reg */ 232 VEX_XXI, /* VEX mod_rm, imm8 -> VEX.vvvv */ 233 VEX_MR, /* VEX mod_rm -> mod_reg */ 234 VEX_RRI, /* VEX mod_reg, mod_rm -> implicit(eflags/r32) */ 235 VEX_RX, /* VEX mod_reg -> mod_rm */ 236 VEX_KRR, /* VEX mod_rm -> mod_reg */ 237 VEX_KMR, /* VEX mod_reg -> mod_rm */ 238 VEX_KRM, /* VEX mod_rm -> mod_reg */ 239 VEX_RR, /* VEX mod_rm -> mod_reg */ 240 VEX_RRi, /* VEX mod_rm, imm8 -> mod_reg */ 241 VEX_RM, /* VEX mod_reg -> mod_rm */ 242 VEX_RIM, /* VEX mod_reg, imm8 -> mod_rm */ 243 VEX_RRM, /* VEX VEX.vvvv, mod_reg -> mod_rm */ 244 VEX_RMX, /* VEX VEX.vvvv, mod_rm -> mod_reg */ 245 VEX_SbVM, /* VEX SIB, VEX.vvvv -> mod_rm */ 246 VMx, /* vmcall/vmlaunch/vmresume/vmxoff */ 247 VMxo, /* VMx instruction with optional prefix */ 248 SVM, /* AMD SVM instructions */ 249 BLS, /* BLSR, BLSMSK, BLSI */ 250 FMA, /* FMA instructions, all VEX_RMrX */ 251 ADX, /* ADX instructions, support REX.w, mod_rm->mod_reg */ 252 EVEX_RX, /* EVEX mod_reg -> mod_rm */ 253 EVEX_MX, /* EVEX mod_rm -> mod_reg */ 254 EVEX_RMrX, /* EVEX EVEX.vvvv, mod_rm -> mod_reg */ 255 EVEX_RMRX /* EVEX EVEX.vvvv, mod_rm, imm8 -> mod_reg */ 256 }; 257 258 /* 259 * VEX prefixes 260 */ 261 #define VEX_2bytes 0xC5 /* the first byte of two-byte form */ 262 #define VEX_3bytes 0xC4 /* the first byte of three-byte form */ 263 264 #define FILL 0x90 /* Fill byte used for alignment (nop) */ 265 266 /* 267 ** Register numbers for the i386 268 */ 269 #define EAX_REGNO 0 270 #define ECX_REGNO 1 271 #define EDX_REGNO 2 272 #define EBX_REGNO 3 273 #define ESP_REGNO 4 274 #define EBP_REGNO 5 275 #define ESI_REGNO 6 276 #define EDI_REGNO 7 277 278 /* 279 * modes for immediate values 280 */ 281 #define MODE_NONE 0 282 #define MODE_IPREL 1 /* signed IP relative value */ 283 #define MODE_SIGNED 2 /* sign extended immediate */ 284 #define MODE_IMPLIED 3 /* constant value implied from opcode */ 285 #define MODE_OFFSET 4 /* offset part of an address */ 286 #define MODE_RIPREL 5 /* like IPREL, but from %rip (amd64) */ 287 288 /* 289 * The letters used in these macros are: 290 * IND - indirect to another to another table 291 * "T" - means to Terminate indirections (this is the final opcode) 292 * "S" - means "operand length suffix required" 293 * "Sa" - means AVX2 suffix (q/d) required 294 * "Sq" - means AVX512 suffix (q/d) required 295 * "Sd" - means AVX512 suffix (d/s) required 296 * "NS" - means "no suffix" which is the operand length suffix of the opcode 297 * "Z" - means instruction size arg required 298 * "u" - means the opcode is invalid in IA32 but valid in amd64 299 * "x" - means the opcode is invalid in amd64, but not IA32 300 * "y" - means the operand size is always 64 bits in 64 bit mode 301 * "p" - means push/pop stack operation 302 * "vr" - means VEX instruction that operates on normal registers, not fpu 303 * "vo" - means VEX instruction that operates on opmask registers, not fpu 304 */ 305 306 #define AVS2 (uint_t)1 /* it_avxsuf: AVX2 q/d suffix handling */ 307 #define AVS5Q (uint_t)2 /* it_avxsuf: AVX512 q/d suffix handling */ 308 #define AVS5D (uint_t)3 /* it_avxsuf: AVX512 d/s suffix handling */ 309 310 #if defined(DIS_TEXT) && defined(DIS_MEM) 311 #define IND(table) {(instable_t *)table, 0, "", 0, 0, 0, 0, 0, 0} 312 #define INDx(table) {(instable_t *)table, 0, "", 0, 0, 1, 0, 0, 0} 313 #define TNS(name, amode) {TERM, amode, name, 0, 0, 0, 0, 0, 0} 314 #define TNSu(name, amode) {TERM, amode, name, 0, 0, 0, 0, 1, 0} 315 #define TNSx(name, amode) {TERM, amode, name, 0, 0, 1, 0, 0, 0} 316 #define TNSy(name, amode) {TERM, amode, name, 0, 0, 0, 1, 0, 0} 317 #define TNSyp(name, amode) {TERM, amode, name, 0, 0, 0, 1, 0, 1} 318 #define TNSZ(name, amode, sz) {TERM, amode, name, 0, sz, 0, 0, 0, 0} 319 #define TNSZy(name, amode, sz) {TERM, amode, name, 0, sz, 0, 1, 0, 0} 320 #define TNSZvr(name, amode, sz) {TERM, amode, name, 0, sz, 0, 0, 0, 0, 1} 321 #define TSvo(name, amode) {TERM, amode, name, 1, 0, 0, 0, 0, 0, 0, 0, 1} 322 #define TS(name, amode) {TERM, amode, name, 1, 0, 0, 0, 0, 0} 323 #define TSx(name, amode) {TERM, amode, name, 1, 0, 1, 0, 0, 0} 324 #define TSy(name, amode) {TERM, amode, name, 1, 0, 0, 1, 0, 0} 325 #define TSp(name, amode) {TERM, amode, name, 1, 0, 0, 0, 0, 1} 326 #define TSZ(name, amode, sz) {TERM, amode, name, 1, sz, 0, 0, 0, 0} 327 #define TSaZ(name, amode, sz) {TERM, amode, name, 1, sz, 0, 0, 0, 0, 0, AVS2} 328 #define TSq(name, amode) {TERM, amode, name, 0, 0, 0, 0, 0, 0, 0, AVS5Q} 329 #define TSd(name, amode) {TERM, amode, name, 0, 0, 0, 0, 0, 0, 0, AVS5D} 330 #define TSZx(name, amode, sz) {TERM, amode, name, 1, sz, 1, 0, 0, 0} 331 #define TSZy(name, amode, sz) {TERM, amode, name, 1, sz, 0, 1, 0, 0} 332 #define INVALID {TERM, UNKNOWN, "", 0, 0, 0, 0, 0} 333 #elif defined(DIS_TEXT) 334 #define IND(table) {(instable_t *)table, 0, "", 0, 0, 0, 0, 0} 335 #define INDx(table) {(instable_t *)table, 0, "", 0, 1, 0, 0, 0} 336 #define TNS(name, amode) {TERM, amode, name, 0, 0, 0, 0, 0} 337 #define TNSu(name, amode) {TERM, amode, name, 0, 0, 0, 1, 0} 338 #define TNSx(name, amode) {TERM, amode, name, 0, 1, 0, 0, 0} 339 #define TNSy(name, amode) {TERM, amode, name, 0, 0, 1, 0, 0} 340 #define TNSyp(name, amode) {TERM, amode, name, 0, 0, 1, 0, 1} 341 #define TNSZ(name, amode, sz) {TERM, amode, name, 0, 0, 0, 0, 0} 342 #define TNSZy(name, amode, sz) {TERM, amode, name, 0, 0, 1, 0, 0} 343 #define TNSZvr(name, amode, sz) {TERM, amode, name, 0, 0, 0, 0, 0, 1} 344 #define TSvo(name, amode) {TERM, amode, name, 1, 0, 0, 0, 0, 0, 0, 1} 345 #define TS(name, amode) {TERM, amode, name, 1, 0, 0, 0, 0} 346 #define TSx(name, amode) {TERM, amode, name, 1, 1, 0, 0, 0} 347 #define TSy(name, amode) {TERM, amode, name, 1, 0, 1, 0, 0} 348 #define TSp(name, amode) {TERM, amode, name, 1, 0, 0, 0, 1} 349 #define TSZ(name, amode, sz) {TERM, amode, name, 1, 0, 0, 0, 0} 350 #define TSaZ(name, amode, sz) {TERM, amode, name, 1, 0, 0, 0, 0, 0, AVS2} 351 #define TSq(name, amode) {TERM, amode, name, 0, 0, 0, 0, 0, 0, AVS5Q} 352 #define TSZx(name, amode, sz) {TERM, amode, name, 1, 1, 0, 0, 0} 353 #define TSZy(name, amode, sz) {TERM, amode, name, 1, 0, 1, 0, 0} 354 #define INVALID {TERM, UNKNOWN, "", 0, 0, 0, 0, 0} 355 #elif defined(DIS_MEM) 356 #define IND(table) {(instable_t *)table, 0, 0, 0, 0, 0, 0} 357 #define INDx(table) {(instable_t *)table, 0, 0, 1, 0, 0, 0} 358 #define TNS(name, amode) {TERM, amode, 0, 0, 0, 0, 0} 359 #define TNSu(name, amode) {TERM, amode, 0, 0, 0, 1, 0} 360 #define TNSy(name, amode) {TERM, amode, 0, 0, 1, 0, 0} 361 #define TNSyp(name, amode) {TERM, amode, 0, 0, 1, 0, 1} 362 #define TNSx(name, amode) {TERM, amode, 0, 1, 0, 0, 0} 363 #define TNSZ(name, amode, sz) {TERM, amode, sz, 0, 0, 0, 0} 364 #define TNSZy(name, amode, sz) {TERM, amode, sz, 0, 1, 0, 0} 365 #define TNSZvr(name, amode, sz) {TERM, amode, sz, 0, 0, 0, 0, 1} 366 #define TSvo(name, amode) {TERM, amode, 0, 0, 0, 0, 0, 0, 0, 1} 367 #define TS(name, amode) {TERM, amode, 0, 0, 0, 0, 0} 368 #define TSx(name, amode) {TERM, amode, 0, 1, 0, 0, 0} 369 #define TSy(name, amode) {TERM, amode, 0, 0, 1, 0, 0} 370 #define TSp(name, amode) {TERM, amode, 0, 0, 0, 0, 1} 371 #define TSZ(name, amode, sz) {TERM, amode, sz, 0, 0, 0, 0} 372 #define TSaZ(name, amode, sz) {TERM, amode, sz, 0, 0, 0, 0, 0, AVS2} 373 #define TSq(name, amode) {TERM, amode, 0, 0, 0, 0, 0, 0, AVS5Q} 374 #define TSZx(name, amode, sz) {TERM, amode, sz, 1, 0, 0, 0} 375 #define TSZy(name, amode, sz) {TERM, amode, sz, 0, 1, 0, 0} 376 #define INVALID {TERM, UNKNOWN, 0, 0, 0, 0, 0} 377 #else 378 #define IND(table) {(instable_t *)table, 0, 0, 0, 0, 0} 379 #define INDx(table) {(instable_t *)table, 0, 1, 0, 0, 0} 380 #define TNS(name, amode) {TERM, amode, 0, 0, 0, 0} 381 #define TNSu(name, amode) {TERM, amode, 0, 0, 1, 0} 382 #define TNSy(name, amode) {TERM, amode, 0, 1, 0, 0} 383 #define TNSyp(name, amode) {TERM, amode, 0, 1, 0, 1} 384 #define TNSx(name, amode) {TERM, amode, 1, 0, 0, 0} 385 #define TNSZ(name, amode, sz) {TERM, amode, 0, 0, 0, 0} 386 #define TNSZy(name, amode, sz) {TERM, amode, 0, 1, 0, 0} 387 #define TNSZvr(name, amode, sz) {TERM, amode, 0, 0, 0, 0, 1} 388 #define TSvo(name, amode) {TERM, amode, 0, 0, 0, 0, 0, 0, 1} 389 #define TS(name, amode) {TERM, amode, 0, 0, 0, 0} 390 #define TSx(name, amode) {TERM, amode, 1, 0, 0, 0} 391 #define TSy(name, amode) {TERM, amode, 0, 1, 0, 0} 392 #define TSp(name, amode) {TERM, amode, 0, 0, 0, 1} 393 #define TSZ(name, amode, sz) {TERM, amode, 0, 0, 0, 0} 394 #define TSaZ(name, amode, sz) {TERM, amode, 0, 0, 0, 0, 0, AVS2} 395 #define TSq(name, amode) {TERM, amode, 0, 0, 0, 0, 0, AVS5Q} 396 #define TSd(name, amode) {TERM, amode, 0, 0, 0, 0, 0, AVS5D} 397 #define TSZx(name, amode, sz) {TERM, amode, 1, 0, 0, 0} 398 #define TSZy(name, amode, sz) {TERM, amode, 0, 1, 0, 0} 399 #define INVALID {TERM, UNKNOWN, 0, 0, 0, 0} 400 #endif 401 402 #ifdef DIS_TEXT 403 /* 404 * this decodes the r_m field for mode's 0, 1, 2 in 16 bit mode 405 */ 406 const char *const dis_addr16[3][8] = { 407 "(%bx,%si)", "(%bx,%di)", "(%bp,%si)", "(%bp,%di)", "(%si)", "(%di)", "", 408 "(%bx)", 409 "(%bx,%si)", "(%bx,%di)", "(%bp,%si)", "(%bp,%di)", "(%si)", "(%di", "(%bp)", 410 "(%bx)", 411 "(%bx,%si)", "(%bx,%di)", "(%bp,%si)", "(%bp,%di)", "(%si)", "(%di)", "(%bp)", 412 "(%bx)", 413 }; 414 415 416 /* 417 * This decodes 32 bit addressing mode r_m field for modes 0, 1, 2 418 */ 419 const char *const dis_addr32_mode0[16] = { 420 "(%eax)", "(%ecx)", "(%edx)", "(%ebx)", "", "", "(%esi)", "(%edi)", 421 "(%r8d)", "(%r9d)", "(%r10d)", "(%r11d)", "", "", "(%r14d)", "(%r15d)" 422 }; 423 424 const char *const dis_addr32_mode12[16] = { 425 "(%eax)", "(%ecx)", "(%edx)", "(%ebx)", "", "(%ebp)", "(%esi)", "(%edi)", 426 "(%r8d)", "(%r9d)", "(%r10d)", "(%r11d)", "", "(%r13d)", "(%r14d)", "(%r15d)" 427 }; 428 429 /* 430 * This decodes 64 bit addressing mode r_m field for modes 0, 1, 2 431 */ 432 const char *const dis_addr64_mode0[16] = { 433 "(%rax)", "(%rcx)", "(%rdx)", "(%rbx)", "", "(%rip)", "(%rsi)", "(%rdi)", 434 "(%r8)", "(%r9)", "(%r10)", "(%r11)", "(%r12)", "(%rip)", "(%r14)", "(%r15)" 435 }; 436 const char *const dis_addr64_mode12[16] = { 437 "(%rax)", "(%rcx)", "(%rdx)", "(%rbx)", "", "(%rbp)", "(%rsi)", "(%rdi)", 438 "(%r8)", "(%r9)", "(%r10)", "(%r11)", "(%r12)", "(%r13)", "(%r14)", "(%r15)" 439 }; 440 441 /* 442 * decode for scale from SIB byte 443 */ 444 const char *const dis_scale_factor[4] = { ")", ",2)", ",4)", ",8)" }; 445 446 /* 447 * decode for scale from VSIB byte, note that we always include the scale factor 448 * to match gas. 449 */ 450 const char *const dis_vscale_factor[4] = { ",1)", ",2)", ",4)", ",8)" }; 451 452 /* 453 * register decoding for normal references to registers (ie. not addressing) 454 */ 455 const char *const dis_REG8[16] = { 456 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh", 457 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b" 458 }; 459 460 const char *const dis_REG8_REX[16] = { 461 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil", 462 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b" 463 }; 464 465 const char *const dis_REG16[16] = { 466 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di", 467 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w" 468 }; 469 470 const char *const dis_REG32[16] = { 471 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi", 472 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d" 473 }; 474 475 const char *const dis_REG64[16] = { 476 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi", 477 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15" 478 }; 479 480 const char *const dis_DEBUGREG[16] = { 481 "%db0", "%db1", "%db2", "%db3", "%db4", "%db5", "%db6", "%db7", 482 "%db8", "%db9", "%db10", "%db11", "%db12", "%db13", "%db14", "%db15" 483 }; 484 485 const char *const dis_CONTROLREG[16] = { 486 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5?", "%cr6?", "%cr7?", 487 "%cr8", "%cr9?", "%cr10?", "%cr11?", "%cr12?", "%cr13?", "%cr14?", "%cr15?" 488 }; 489 490 const char *const dis_TESTREG[16] = { 491 "%tr0?", "%tr1?", "%tr2?", "%tr3", "%tr4", "%tr5", "%tr6", "%tr7", 492 "%tr0?", "%tr1?", "%tr2?", "%tr3", "%tr4", "%tr5", "%tr6", "%tr7" 493 }; 494 495 const char *const dis_MMREG[16] = { 496 "%mm0", "%mm1", "%mm2", "%mm3", "%mm4", "%mm5", "%mm6", "%mm7", 497 "%mm0", "%mm1", "%mm2", "%mm3", "%mm4", "%mm5", "%mm6", "%mm7" 498 }; 499 500 const char *const dis_XMMREG[32] = { 501 "%xmm0", "%xmm1", "%xmm2", "%xmm3", 502 "%xmm4", "%xmm5", "%xmm6", "%xmm7", 503 "%xmm8", "%xmm9", "%xmm10", "%xmm11", 504 "%xmm12", "%xmm13", "%xmm14", "%xmm15", 505 "%xmm16", "%xmm17", "%xmm18", "%xmm19", 506 "%xmm20", "%xmm21", "%xmm22", "%xmm23", 507 "%xmm24", "%xmm25", "%xmm26", "%xmm27", 508 "%xmm28", "%xmm29", "%xmm30", "%xmm31", 509 }; 510 511 const char *const dis_YMMREG[32] = { 512 "%ymm0", "%ymm1", "%ymm2", "%ymm3", 513 "%ymm4", "%ymm5", "%ymm6", "%ymm7", 514 "%ymm8", "%ymm9", "%ymm10", "%ymm11", 515 "%ymm12", "%ymm13", "%ymm14", "%ymm15", 516 "%ymm16", "%ymm17", "%ymm18", "%ymm19", 517 "%ymm20", "%ymm21", "%ymm22", "%ymm23", 518 "%ymm24", "%ymm25", "%ymm26", "%ymm27", 519 "%ymm28", "%ymm29", "%ymm30", "%ymm31", 520 }; 521 522 const char *const dis_ZMMREG[32] = { 523 "%zmm0", "%zmm1", "%zmm2", "%zmm3", 524 "%zmm4", "%zmm5", "%zmm6", "%zmm7", 525 "%zmm8", "%zmm9", "%zmm10", "%zmm11", 526 "%zmm12", "%zmm13", "%zmm14", "%zmm15", 527 "%zmm16", "%zmm17", "%zmm18", "%zmm19", 528 "%zmm20", "%zmm21", "%zmm22", "%zmm23", 529 "%zmm24", "%zmm25", "%zmm26", "%zmm27", 530 "%zmm28", "%zmm29", "%zmm30", "%zmm31", 531 }; 532 533 const char *const dis_KOPMASKREG[8] = { 534 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7" 535 }; 536 537 const char *const dis_SEGREG[16] = { 538 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "<reserved>", "<reserved>", 539 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "<reserved>", "<reserved>" 540 }; 541 542 /* 543 * SIMD predicate suffixes 544 */ 545 const char *const dis_PREDSUFFIX[8] = { 546 "eq", "lt", "le", "unord", "neq", "nlt", "nle", "ord" 547 }; 548 549 const char *const dis_AVXvgrp7[3][8] = { 550 /*0 1 2 3 4 5 6 7*/ 551 /*71*/ {"", "", "vpsrlw", "", "vpsraw", "", "vpsllw", ""}, 552 /*72*/ {"", "", "vpsrld", "", "vpsrad", "", "vpslld", ""}, 553 /*73*/ {"", "", "vpsrlq", "vpsrldq", "", "", "vpsllq", "vpslldq"} 554 }; 555 556 #endif /* DIS_TEXT */ 557 558 /* 559 * "decode table" for 64 bit mode MOVSXD instruction (opcode 0x63) 560 */ 561 const instable_t dis_opMOVSLD = TNS("movslq",MOVSXZ); 562 563 /* 564 * "decode table" for pause and clflush instructions 565 */ 566 const instable_t dis_opPause = TNS("pause", NORM); 567 568 /* 569 * "decode table" for wbnoinvd instruction 570 */ 571 const instable_t dis_opWbnoinvd = TNS("wbnoinvd", NORM); 572 573 /* 574 * Decode table for 0x0F00 opcodes 575 */ 576 const instable_t dis_op0F00[8] = { 577 578 /* [0] */ TNS("sldt",M), TNS("str",M), TNSy("lldt",M), TNSy("ltr",M), 579 /* [4] */ TNSZ("verr",M,2), TNSZ("verw",M,2), INVALID, INVALID, 580 }; 581 582 583 /* 584 * Decode table for 0x0F01 opcodes 585 */ 586 const instable_t dis_op0F01[8] = { 587 588 /* [0] */ TNSZ("sgdt",VMx,6), TNSZ("sidt",MONITOR_MWAIT,6), TNSZ("lgdt",XGETBV_XSETBV,6), TNSZ("lidt",SVM,6), 589 /* [4] */ TNSZ("smsw",M,2), INVALID, TNSZ("lmsw",M,2), TNS("invlpg",SWAPGS_RDTSCP), 590 }; 591 592 /* 593 * Decode table for 0x0F18 opcodes -- SIMD prefetch 594 */ 595 const instable_t dis_op0F18[8] = { 596 597 /* [0] */ TNS("prefetchnta",PREF),TNS("prefetcht0",PREF), TNS("prefetcht1",PREF), TNS("prefetcht2",PREF), 598 /* [4] */ INVALID, INVALID, INVALID, INVALID, 599 }; 600 601 /* 602 * Decode table for 0x0FAE opcodes -- SIMD state save/restore 603 */ 604 const instable_t dis_op0FAE[8] = { 605 /* [0] */ TNSZ("fxsave",FSGS,512),TNSZ("fxrstor",FSGS,512),TNS("ldmxcsr",FSGS), TNS("stmxcsr",FSGS), 606 /* [4] */ TNSZ("xsave",M,512), TNS("lfence",XMMFENCE), TNS("mfence",XMMFENCE), TNS("sfence",XMMSFNC), 607 }; 608 609 /* 610 * Decode table for 0xF30FAE opcodes -- FSGSBASE 611 */ 612 const instable_t dis_opF30FAE[8] = { 613 /* [0] */ TNSx("rdfsbase",FSGS), TNSx("rdgsbase",FSGS), TNSx("wrfsbase",FSGS), TNSx("wrgsbase",FSGS), 614 /* [4] */ INVALID, INVALID, INVALID, INVALID, 615 }; 616 617 /* 618 * Decode table for 0x0FBA opcodes 619 */ 620 621 const instable_t dis_op0FBA[8] = { 622 623 /* [0] */ INVALID, INVALID, INVALID, INVALID, 624 /* [4] */ TS("bt",MIb), TS("bts",MIb), TS("btr",MIb), TS("btc",MIb), 625 }; 626 627 /* 628 * Decode table for 0x0FC7 opcode (group 9) 629 */ 630 631 const instable_t dis_op0FC7[8] = { 632 633 /* [0] */ INVALID, TNS("cmpxchg8b",M), INVALID, TNS("xrstors",MG9), 634 /* [4] */ TNS("xsavec",MG9), TNS("xsaves",MG9), TNS("vmptrld",MG9), TNS("vmptrst",MG9), 635 }; 636 637 /* 638 * Decode table for 0x0FC7 opcode (group 9) mode 3 639 */ 640 641 const instable_t dis_op0FC7m3[8] = { 642 643 /* [0] */ INVALID, INVALID, INVALID, INVALID, 644 /* [4] */ INVALID, INVALID, TNS("rdrand",MG9), TNS("rdseed", MG9), 645 }; 646 647 /* 648 * Decode table for 0x0FC7 opcode with 0x66 prefix 649 */ 650 651 const instable_t dis_op660FC7[8] = { 652 653 /* [0] */ INVALID, INVALID, INVALID, INVALID, 654 /* [4] */ INVALID, INVALID, TNS("vmclear",M), INVALID, 655 }; 656 657 /* 658 * Decode table for 0x0FC7 opcode with 0xF3 prefix 659 */ 660 661 const instable_t dis_opF30FC7[8] = { 662 663 /* [0] */ INVALID, INVALID, INVALID, INVALID, 664 /* [4] */ INVALID, INVALID, TNS("vmxon",M), INVALID, 665 }; 666 667 /* 668 * Decode table for 0x0FC8 opcode -- 486 bswap instruction 669 * 670 *bit pattern: 0000 1111 1100 1reg 671 */ 672 const instable_t dis_op0FC8[4] = { 673 /* [0] */ TNS("bswap",R), INVALID, INVALID, INVALID, 674 }; 675 676 /* 677 * Decode table for 0x0F71, 0x0F72, and 0x0F73 opcodes -- MMX instructions 678 */ 679 const instable_t dis_op0F7123[4][8] = { 680 { 681 /* [70].0 */ INVALID, INVALID, INVALID, INVALID, 682 /* .4 */ INVALID, INVALID, INVALID, INVALID, 683 }, { 684 /* [71].0 */ INVALID, INVALID, TNS("psrlw",MMOSH), INVALID, 685 /* .4 */ TNS("psraw",MMOSH), INVALID, TNS("psllw",MMOSH), INVALID, 686 }, { 687 /* [72].0 */ INVALID, INVALID, TNS("psrld",MMOSH), INVALID, 688 /* .4 */ TNS("psrad",MMOSH), INVALID, TNS("pslld",MMOSH), INVALID, 689 }, { 690 /* [73].0 */ INVALID, INVALID, TNS("psrlq",MMOSH), TNS("INVALID",MMOSH), 691 /* .4 */ INVALID, INVALID, TNS("psllq",MMOSH), TNS("INVALID",MMOSH), 692 } }; 693 694 /* 695 * Decode table for SIMD extensions to above 0x0F71-0x0F73 opcodes. 696 */ 697 const instable_t dis_opSIMD7123[32] = { 698 /* [70].0 */ INVALID, INVALID, INVALID, INVALID, 699 /* .4 */ INVALID, INVALID, INVALID, INVALID, 700 701 /* [71].0 */ INVALID, INVALID, TNS("psrlw",XMMSH), INVALID, 702 /* .4 */ TNS("psraw",XMMSH), INVALID, TNS("psllw",XMMSH), INVALID, 703 704 /* [72].0 */ INVALID, INVALID, TNS("psrld",XMMSH), INVALID, 705 /* .4 */ TNS("psrad",XMMSH), INVALID, TNS("pslld",XMMSH), INVALID, 706 707 /* [73].0 */ INVALID, INVALID, TNS("psrlq",XMMSH), TNS("psrldq",XMMSH), 708 /* .4 */ INVALID, INVALID, TNS("psllq",XMMSH), TNS("pslldq",XMMSH), 709 }; 710 711 /* 712 * SIMD instructions have been wedged into the existing IA32 instruction 713 * set through the use of prefixes. That is, while 0xf0 0x58 may be 714 * addps, 0xf3 0xf0 0x58 (literally, repz addps) is a completely different 715 * instruction - addss. At present, three prefixes have been coopted in 716 * this manner - address size (0x66), repnz (0xf2) and repz (0xf3). The 717 * following tables are used to provide the prefixed instruction names. 718 * The arrays are sparse, but they're fast. 719 */ 720 721 /* 722 * Decode table for SIMD instructions with the address size (0x66) prefix. 723 */ 724 const instable_t dis_opSIMDdata16[256] = { 725 /* [00] */ INVALID, INVALID, INVALID, INVALID, 726 /* [04] */ INVALID, INVALID, INVALID, INVALID, 727 /* [08] */ INVALID, INVALID, INVALID, INVALID, 728 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 729 730 /* [10] */ TNSZ("movupd",XMM,16), TNSZ("movupd",XMMS,16), TNSZ("movlpd",XMMM,8), TNSZ("movlpd",XMMMS,8), 731 /* [14] */ TNSZ("unpcklpd",XMM,16),TNSZ("unpckhpd",XMM,16),TNSZ("movhpd",XMMM,8), TNSZ("movhpd",XMMMS,8), 732 /* [18] */ INVALID, INVALID, INVALID, INVALID, 733 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 734 735 /* [20] */ INVALID, INVALID, INVALID, INVALID, 736 /* [24] */ INVALID, INVALID, INVALID, INVALID, 737 /* [28] */ TNSZ("movapd",XMM,16), TNSZ("movapd",XMMS,16), TNSZ("cvtpi2pd",XMMOMX,8),TNSZ("movntpd",XMMOMS,16), 738 /* [2C] */ TNSZ("cvttpd2pi",XMMXMM,16),TNSZ("cvtpd2pi",XMMXMM,16),TNSZ("ucomisd",XMM,8),TNSZ("comisd",XMM,8), 739 740 /* [30] */ INVALID, INVALID, INVALID, INVALID, 741 /* [34] */ INVALID, INVALID, INVALID, INVALID, 742 /* [38] */ INVALID, INVALID, INVALID, INVALID, 743 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 744 745 /* [40] */ INVALID, INVALID, INVALID, INVALID, 746 /* [44] */ INVALID, INVALID, INVALID, INVALID, 747 /* [48] */ INVALID, INVALID, INVALID, INVALID, 748 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 749 750 /* [50] */ TNS("movmskpd",XMMOX3), TNSZ("sqrtpd",XMM,16), INVALID, INVALID, 751 /* [54] */ TNSZ("andpd",XMM,16), TNSZ("andnpd",XMM,16), TNSZ("orpd",XMM,16), TNSZ("xorpd",XMM,16), 752 /* [58] */ TNSZ("addpd",XMM,16), TNSZ("mulpd",XMM,16), TNSZ("cvtpd2ps",XMM,16),TNSZ("cvtps2dq",XMM,16), 753 /* [5C] */ TNSZ("subpd",XMM,16), TNSZ("minpd",XMM,16), TNSZ("divpd",XMM,16), TNSZ("maxpd",XMM,16), 754 755 /* [60] */ TNSZ("punpcklbw",XMM,16),TNSZ("punpcklwd",XMM,16),TNSZ("punpckldq",XMM,16),TNSZ("packsswb",XMM,16), 756 /* [64] */ TNSZ("pcmpgtb",XMM,16), TNSZ("pcmpgtw",XMM,16), TNSZ("pcmpgtd",XMM,16), TNSZ("packuswb",XMM,16), 757 /* [68] */ TNSZ("punpckhbw",XMM,16),TNSZ("punpckhwd",XMM,16),TNSZ("punpckhdq",XMM,16),TNSZ("packssdw",XMM,16), 758 /* [6C] */ TNSZ("punpcklqdq",XMM,16),TNSZ("punpckhqdq",XMM,16),TNSZ("movd",XMM3MX,4),TNSZ("movdqa",XMM,16), 759 760 /* [70] */ TNSZ("pshufd",XMMP,16), INVALID, INVALID, INVALID, 761 /* [74] */ TNSZ("pcmpeqb",XMM,16), TNSZ("pcmpeqw",XMM,16), TNSZ("pcmpeqd",XMM,16), INVALID, 762 /* [78] */ TNSZ("extrq",XMM2I,16), TNSZ("extrq",XMM,16), INVALID, INVALID, 763 /* [7C] */ TNSZ("haddpd",XMM,16), TNSZ("hsubpd",XMM,16), TNSZ("movd",XMM3MXS,4), TNSZ("movdqa",XMMS,16), 764 765 /* [80] */ INVALID, INVALID, INVALID, INVALID, 766 /* [84] */ INVALID, INVALID, INVALID, INVALID, 767 /* [88] */ INVALID, INVALID, INVALID, INVALID, 768 /* [8C] */ INVALID, INVALID, INVALID, INVALID, 769 770 /* [90] */ INVALID, INVALID, INVALID, INVALID, 771 /* [94] */ INVALID, INVALID, INVALID, INVALID, 772 /* [98] */ INVALID, INVALID, INVALID, INVALID, 773 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 774 775 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 776 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 777 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 778 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 779 780 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 781 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 782 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 783 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 784 785 /* [C0] */ INVALID, INVALID, TNSZ("cmppd",XMMP,16), INVALID, 786 /* [C4] */ TNSZ("pinsrw",XMMPRM,2),TNS("pextrw",XMM3P), TNSZ("shufpd",XMMP,16), INVALID, 787 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 788 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 789 790 /* [D0] */ TNSZ("addsubpd",XMM,16),TNSZ("psrlw",XMM,16), TNSZ("psrld",XMM,16), TNSZ("psrlq",XMM,16), 791 /* [D4] */ TNSZ("paddq",XMM,16), TNSZ("pmullw",XMM,16), TNSZ("movq",XMMS,8), TNS("pmovmskb",XMMX3), 792 /* [D8] */ TNSZ("psubusb",XMM,16), TNSZ("psubusw",XMM,16), TNSZ("pminub",XMM,16), TNSZ("pand",XMM,16), 793 /* [DC] */ TNSZ("paddusb",XMM,16), TNSZ("paddusw",XMM,16), TNSZ("pmaxub",XMM,16), TNSZ("pandn",XMM,16), 794 795 /* [E0] */ TNSZ("pavgb",XMM,16), TNSZ("psraw",XMM,16), TNSZ("psrad",XMM,16), TNSZ("pavgw",XMM,16), 796 /* [E4] */ TNSZ("pmulhuw",XMM,16), TNSZ("pmulhw",XMM,16), TNSZ("cvttpd2dq",XMM,16),TNSZ("movntdq",XMMS,16), 797 /* [E8] */ TNSZ("psubsb",XMM,16), TNSZ("psubsw",XMM,16), TNSZ("pminsw",XMM,16), TNSZ("por",XMM,16), 798 /* [EC] */ TNSZ("paddsb",XMM,16), TNSZ("paddsw",XMM,16), TNSZ("pmaxsw",XMM,16), TNSZ("pxor",XMM,16), 799 800 /* [F0] */ INVALID, TNSZ("psllw",XMM,16), TNSZ("pslld",XMM,16), TNSZ("psllq",XMM,16), 801 /* [F4] */ TNSZ("pmuludq",XMM,16), TNSZ("pmaddwd",XMM,16), TNSZ("psadbw",XMM,16), TNSZ("maskmovdqu", XMMXIMPL,16), 802 /* [F8] */ TNSZ("psubb",XMM,16), TNSZ("psubw",XMM,16), TNSZ("psubd",XMM,16), TNSZ("psubq",XMM,16), 803 /* [FC] */ TNSZ("paddb",XMM,16), TNSZ("paddw",XMM,16), TNSZ("paddd",XMM,16), INVALID, 804 }; 805 806 const instable_t dis_opAVX660F[256] = { 807 /* [00] */ INVALID, INVALID, INVALID, INVALID, 808 /* [04] */ INVALID, INVALID, INVALID, INVALID, 809 /* [08] */ INVALID, INVALID, INVALID, INVALID, 810 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 811 812 /* [10] */ TNSZ("vmovupd",VEX_MX,16), TNSZ("vmovupd",VEX_RX,16), TNSZ("vmovlpd",VEX_RMrX,8), TNSZ("vmovlpd",VEX_RM,8), 813 /* [14] */ TNSZ("vunpcklpd",VEX_RMrX,16),TNSZ("vunpckhpd",VEX_RMrX,16),TNSZ("vmovhpd",VEX_RMrX,8), TNSZ("vmovhpd",VEX_RM,8), 814 /* [18] */ INVALID, INVALID, INVALID, INVALID, 815 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 816 817 /* [20] */ INVALID, INVALID, INVALID, INVALID, 818 /* [24] */ INVALID, INVALID, INVALID, INVALID, 819 /* [28] */ TNSZ("vmovapd",VEX_MX,16), TNSZ("vmovapd",VEX_RX,16), INVALID, TNSZ("vmovntpd",VEX_RM,16), 820 /* [2C] */ INVALID, INVALID, TNSZ("vucomisd",VEX_MX,8),TNSZ("vcomisd",VEX_MX,8), 821 822 /* [30] */ INVALID, INVALID, INVALID, INVALID, 823 /* [34] */ INVALID, INVALID, INVALID, INVALID, 824 /* [38] */ INVALID, INVALID, INVALID, INVALID, 825 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 826 827 /* [40] */ INVALID, TSvo("kand",VEX_RMX), TSvo("kandn",VEX_RMX), INVALID, 828 /* [44] */ TSvo("knot",VEX_MX), TSvo("kor",VEX_RMX), TSvo("kxnor",VEX_RMX), TSvo("kxor",VEX_RMX), 829 /* [48] */ INVALID, INVALID, TSvo("kadd",VEX_RMX), TSvo("kunpck",VEX_RMX), 830 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 831 832 /* [50] */ TNS("vmovmskpd",VEX_MR), TNSZ("vsqrtpd",VEX_MX,16), INVALID, INVALID, 833 /* [54] */ TNSZ("vandpd",VEX_RMrX,16), TNSZ("vandnpd",VEX_RMrX,16), TNSZ("vorpd",VEX_RMrX,16), TNSZ("vxorpd",VEX_RMrX,16), 834 /* [58] */ TNSZ("vaddpd",VEX_RMrX,16), TNSZ("vmulpd",VEX_RMrX,16), TNSZ("vcvtpd2ps",VEX_MX,16),TNSZ("vcvtps2dq",VEX_MX,16), 835 /* [5C] */ TNSZ("vsubpd",VEX_RMrX,16), TNSZ("vminpd",VEX_RMrX,16), TNSZ("vdivpd",VEX_RMrX,16), TNSZ("vmaxpd",VEX_RMrX,16), 836 837 /* [60] */ TNSZ("vpunpcklbw",VEX_RMrX,16),TNSZ("vpunpcklwd",VEX_RMrX,16),TNSZ("vpunpckldq",VEX_RMrX,16),TNSZ("vpacksswb",VEX_RMrX,16), 838 /* [64] */ TNSZ("vpcmpgtb",VEX_RMrX,16), TNSZ("vpcmpgtw",VEX_RMrX,16), TNSZ("vpcmpgtd",VEX_RMrX,16), TNSZ("vpackuswb",VEX_RMrX,16), 839 /* [68] */ TNSZ("vpunpckhbw",VEX_RMrX,16),TNSZ("vpunpckhwd",VEX_RMrX,16),TNSZ("vpunpckhdq",VEX_RMrX,16),TNSZ("vpackssdw",VEX_RMrX,16), 840 /* [6C] */ TNSZ("vpunpcklqdq",VEX_RMrX,16),TNSZ("vpunpckhqdq",VEX_RMrX,16),TNSZ("vmovd",VEX_MX,4),TNSZ("vmovdqa",VEX_MX,16), 841 842 /* [70] */ TNSZ("vpshufd",VEX_MXI,16), TNSZ("vgrp71",VEX_XXI,16), TNSZ("vgrp72",VEX_XXI,16), TNSZ("vgrp73",VEX_XXI,16), 843 /* [74] */ TNSZ("vpcmpeqb",VEX_RMrX,16), TNSZ("vpcmpeqw",VEX_RMrX,16), TNSZ("vpcmpeqd",VEX_RMrX,16), INVALID, 844 /* [78] */ INVALID, INVALID, INVALID, INVALID, 845 /* [7C] */ TNSZ("vhaddpd",VEX_RMrX,16), TNSZ("vhsubpd",VEX_RMrX,16), TNSZ("vmovd",VEX_RR,4), TNSZ("vmovdqa",VEX_RX,16), 846 847 /* [80] */ INVALID, INVALID, INVALID, INVALID, 848 /* [84] */ INVALID, INVALID, INVALID, INVALID, 849 /* [88] */ INVALID, INVALID, INVALID, INVALID, 850 /* [8C] */ INVALID, INVALID, INVALID, INVALID, 851 852 /* [90] */ TSvo("kmov",VEX_KRM), TSvo("kmov",VEX_KMR), TSvo("kmov",VEX_KRR), TSvo("kmov",VEX_MR), 853 /* [94] */ INVALID, INVALID, INVALID, INVALID, 854 /* [98] */ TSvo("kortest",VEX_MX), TSvo("ktest",VEX_MX), INVALID, INVALID, 855 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 856 857 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 858 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 859 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 860 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 861 862 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 863 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 864 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 865 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 866 867 /* [C0] */ INVALID, INVALID, TNSZ("vcmppd",VEX_RMRX,16), INVALID, 868 /* [C4] */ TNSZ("vpinsrw",VEX_RMRX,2),TNS("vpextrw",VEX_MR), TNSZ("vshufpd",VEX_RMRX,16), INVALID, 869 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 870 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 871 872 /* [D0] */ TNSZ("vaddsubpd",VEX_RMrX,16),TNSZ("vpsrlw",VEX_RMrX,16), TNSZ("vpsrld",VEX_RMrX,16), TNSZ("vpsrlq",VEX_RMrX,16), 873 /* [D4] */ TNSZ("vpaddq",VEX_RMrX,16), TNSZ("vpmullw",VEX_RMrX,16), TNSZ("vmovq",VEX_RX,8), TNS("vpmovmskb",VEX_MR), 874 /* [D8] */ TNSZ("vpsubusb",VEX_RMrX,16), TNSZ("vpsubusw",VEX_RMrX,16), TNSZ("vpminub",VEX_RMrX,16), TNSZ("vpand",VEX_RMrX,16), 875 /* [DC] */ TNSZ("vpaddusb",VEX_RMrX,16), TNSZ("vpaddusw",VEX_RMrX,16), TNSZ("vpmaxub",VEX_RMrX,16), TNSZ("vpandn",VEX_RMrX,16), 876 877 /* [E0] */ TNSZ("vpavgb",VEX_RMrX,16), TNSZ("vpsraw",VEX_RMrX,16), TNSZ("vpsrad",VEX_RMrX,16), TNSZ("vpavgw",VEX_RMrX,16), 878 /* [E4] */ TNSZ("vpmulhuw",VEX_RMrX,16), TNSZ("vpmulhw",VEX_RMrX,16), TNSZ("vcvttpd2dq",VEX_MX,16),TNSZ("vmovntdq",VEX_RM,16), 879 /* [E8] */ TNSZ("vpsubsb",VEX_RMrX,16), TNSZ("vpsubsw",VEX_RMrX,16), TNSZ("vpminsw",VEX_RMrX,16), TNSZ("vpor",VEX_RMrX,16), 880 /* [EC] */ TNSZ("vpaddsb",VEX_RMrX,16), TNSZ("vpaddsw",VEX_RMrX,16), TNSZ("vpmaxsw",VEX_RMrX,16), TNSZ("vpxor",VEX_RMrX,16), 881 882 /* [F0] */ INVALID, TNSZ("vpsllw",VEX_RMrX,16), TNSZ("vpslld",VEX_RMrX,16), TNSZ("vpsllq",VEX_RMrX,16), 883 /* [F4] */ TNSZ("vpmuludq",VEX_RMrX,16), TNSZ("vpmaddwd",VEX_RMrX,16), TNSZ("vpsadbw",VEX_RMrX,16), TNS("vmaskmovdqu",VEX_MX), 884 /* [F8] */ TNSZ("vpsubb",VEX_RMrX,16), TNSZ("vpsubw",VEX_RMrX,16), TNSZ("vpsubd",VEX_RMrX,16), TNSZ("vpsubq",VEX_RMrX,16), 885 /* [FC] */ TNSZ("vpaddb",VEX_RMrX,16), TNSZ("vpaddw",VEX_RMrX,16), TNSZ("vpaddd",VEX_RMrX,16), INVALID, 886 }; 887 888 /* 889 * Decode table for SIMD instructions with the repnz (0xf2) prefix. 890 */ 891 const instable_t dis_opSIMDrepnz[256] = { 892 /* [00] */ INVALID, INVALID, INVALID, INVALID, 893 /* [04] */ INVALID, INVALID, INVALID, INVALID, 894 /* [08] */ INVALID, INVALID, INVALID, INVALID, 895 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 896 897 /* [10] */ TNSZ("movsd",XMM,8), TNSZ("movsd",XMMS,8), TNSZ("movddup",XMM,8), INVALID, 898 /* [14] */ INVALID, INVALID, INVALID, INVALID, 899 /* [18] */ INVALID, INVALID, INVALID, INVALID, 900 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 901 902 /* [20] */ INVALID, INVALID, INVALID, INVALID, 903 /* [24] */ INVALID, INVALID, INVALID, INVALID, 904 /* [28] */ INVALID, INVALID, TNSZ("cvtsi2sd",XMM3MX,4),TNSZ("movntsd",XMMMS,8), 905 /* [2C] */ TNSZ("cvttsd2si",XMMXM3,8),TNSZ("cvtsd2si",XMMXM3,8),INVALID, INVALID, 906 907 /* [30] */ INVALID, INVALID, INVALID, INVALID, 908 /* [34] */ INVALID, INVALID, INVALID, INVALID, 909 /* [38] */ INVALID, INVALID, INVALID, INVALID, 910 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 911 912 /* [40] */ INVALID, INVALID, INVALID, INVALID, 913 /* [44] */ INVALID, INVALID, INVALID, INVALID, 914 /* [48] */ INVALID, INVALID, INVALID, INVALID, 915 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 916 917 /* [50] */ INVALID, TNSZ("sqrtsd",XMM,8), INVALID, INVALID, 918 /* [54] */ INVALID, INVALID, INVALID, INVALID, 919 /* [58] */ TNSZ("addsd",XMM,8), TNSZ("mulsd",XMM,8), TNSZ("cvtsd2ss",XMM,8), INVALID, 920 /* [5C] */ TNSZ("subsd",XMM,8), TNSZ("minsd",XMM,8), TNSZ("divsd",XMM,8), TNSZ("maxsd",XMM,8), 921 922 /* [60] */ INVALID, INVALID, INVALID, INVALID, 923 /* [64] */ INVALID, INVALID, INVALID, INVALID, 924 /* [68] */ INVALID, INVALID, INVALID, INVALID, 925 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 926 927 /* [70] */ TNSZ("pshuflw",XMMP,16),INVALID, INVALID, INVALID, 928 /* [74] */ INVALID, INVALID, INVALID, INVALID, 929 /* [78] */ TNSZ("insertq",XMMX2I,16),TNSZ("insertq",XMM,8),INVALID, INVALID, 930 /* [7C] */ TNSZ("haddps",XMM,16), TNSZ("hsubps",XMM,16), INVALID, INVALID, 931 932 /* [80] */ INVALID, INVALID, INVALID, INVALID, 933 /* [84] */ INVALID, INVALID, INVALID, INVALID, 934 /* [88] */ INVALID, INVALID, INVALID, INVALID, 935 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 936 937 /* [90] */ INVALID, INVALID, INVALID, INVALID, 938 /* [94] */ INVALID, INVALID, INVALID, INVALID, 939 /* [98] */ INVALID, INVALID, INVALID, INVALID, 940 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 941 942 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 943 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 944 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 945 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 946 947 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 948 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 949 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 950 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 951 952 /* [C0] */ INVALID, INVALID, TNSZ("cmpsd",XMMP,8), INVALID, 953 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 954 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 955 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 956 957 /* [D0] */ TNSZ("addsubps",XMM,16),INVALID, INVALID, INVALID, 958 /* [D4] */ INVALID, INVALID, TNS("movdq2q",XMMXM), INVALID, 959 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 960 /* [DC] */ INVALID, INVALID, INVALID, INVALID, 961 962 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 963 /* [E4] */ INVALID, INVALID, TNSZ("cvtpd2dq",XMM,16),INVALID, 964 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 965 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 966 967 /* [F0] */ TNS("lddqu",XMMM), INVALID, INVALID, INVALID, 968 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 969 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 970 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 971 }; 972 973 const instable_t dis_opAVXF20F[256] = { 974 /* [00] */ INVALID, INVALID, INVALID, INVALID, 975 /* [04] */ INVALID, INVALID, INVALID, INVALID, 976 /* [08] */ INVALID, INVALID, INVALID, INVALID, 977 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 978 979 /* [10] */ TNSZ("vmovsd",VEX_RMrX,8), TNSZ("vmovsd",VEX_RRX,8), TNSZ("vmovddup",VEX_MX,8), INVALID, 980 /* [14] */ INVALID, INVALID, INVALID, INVALID, 981 /* [18] */ INVALID, INVALID, INVALID, INVALID, 982 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 983 984 /* [20] */ INVALID, INVALID, INVALID, INVALID, 985 /* [24] */ INVALID, INVALID, INVALID, INVALID, 986 /* [28] */ INVALID, INVALID, TNSZ("vcvtsi2sd",VEX_RMrX,4),INVALID, 987 /* [2C] */ TNSZ("vcvttsd2si",VEX_MR,8),TNSZ("vcvtsd2si",VEX_MR,8),INVALID, INVALID, 988 989 /* [30] */ INVALID, INVALID, INVALID, INVALID, 990 /* [34] */ INVALID, INVALID, INVALID, INVALID, 991 /* [38] */ INVALID, INVALID, INVALID, INVALID, 992 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 993 994 /* [40] */ INVALID, INVALID, INVALID, INVALID, 995 /* [44] */ INVALID, INVALID, INVALID, INVALID, 996 /* [48] */ INVALID, INVALID, INVALID, INVALID, 997 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 998 999 /* [50] */ INVALID, TNSZ("vsqrtsd",VEX_RMrX,8), INVALID, INVALID, 1000 /* [54] */ INVALID, INVALID, INVALID, INVALID, 1001 /* [58] */ TNSZ("vaddsd",VEX_RMrX,8), TNSZ("vmulsd",VEX_RMrX,8), TNSZ("vcvtsd2ss",VEX_RMrX,8), INVALID, 1002 /* [5C] */ TNSZ("vsubsd",VEX_RMrX,8), TNSZ("vminsd",VEX_RMrX,8), TNSZ("vdivsd",VEX_RMrX,8), TNSZ("vmaxsd",VEX_RMrX,8), 1003 1004 /* [60] */ INVALID, INVALID, INVALID, INVALID, 1005 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1006 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1007 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 1008 1009 /* [70] */ TNSZ("vpshuflw",VEX_MXI,16),INVALID, INVALID, INVALID, 1010 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1011 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1012 /* [7C] */ TNSZ("vhaddps",VEX_RMrX,8), TNSZ("vhsubps",VEX_RMrX,8), INVALID, INVALID, 1013 1014 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1015 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1016 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1017 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1018 1019 /* [90] */ INVALID, INVALID, TSvo("kmov",VEX_KRR), TSvo("kmov",VEX_MR), 1020 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1021 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1022 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1023 1024 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1025 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1026 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1027 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1028 1029 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1030 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1031 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 1032 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 1033 1034 /* [C0] */ INVALID, INVALID, TNSZ("vcmpsd",VEX_RMRX,8), INVALID, 1035 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1036 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1037 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1038 1039 /* [D0] */ TNSZ("vaddsubps",VEX_RMrX,8), INVALID, INVALID, INVALID, 1040 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1041 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 1042 /* [DC] */ INVALID, INVALID, INVALID, INVALID, 1043 1044 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1045 /* [E4] */ INVALID, INVALID, TNSZ("vcvtpd2dq",VEX_MX,16),INVALID, 1046 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1047 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1048 1049 /* [F0] */ TNSZ("vlddqu",VEX_MX,16), INVALID, INVALID, INVALID, 1050 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 1051 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1052 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1053 }; 1054 1055 const instable_t dis_opAVXF20F3A[256] = { 1056 /* [00] */ INVALID, INVALID, INVALID, INVALID, 1057 /* [04] */ INVALID, INVALID, INVALID, INVALID, 1058 /* [08] */ INVALID, INVALID, INVALID, INVALID, 1059 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1060 1061 /* [10] */ INVALID, INVALID, INVALID, INVALID, 1062 /* [14] */ INVALID, INVALID, INVALID, INVALID, 1063 /* [18] */ INVALID, INVALID, INVALID, INVALID, 1064 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 1065 1066 /* [20] */ INVALID, INVALID, INVALID, INVALID, 1067 /* [24] */ INVALID, INVALID, INVALID, INVALID, 1068 /* [28] */ INVALID, INVALID, INVALID, INVALID, 1069 /* [2C] */ INVALID, INVALID, INVALID, INVALID, 1070 1071 /* [30] */ INVALID, INVALID, INVALID, INVALID, 1072 /* [34] */ INVALID, INVALID, INVALID, INVALID, 1073 /* [38] */ INVALID, INVALID, INVALID, INVALID, 1074 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 1075 1076 /* [40] */ INVALID, INVALID, INVALID, INVALID, 1077 /* [44] */ INVALID, INVALID, INVALID, INVALID, 1078 /* [48] */ INVALID, INVALID, INVALID, INVALID, 1079 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 1080 1081 /* [50] */ INVALID, INVALID, INVALID, INVALID, 1082 /* [54] */ INVALID, INVALID, INVALID, INVALID, 1083 /* [58] */ INVALID, INVALID, INVALID, INVALID, 1084 /* [5C] */ INVALID, INVALID, INVALID, INVALID, 1085 1086 /* [60] */ INVALID, INVALID, INVALID, INVALID, 1087 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1088 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1089 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 1090 1091 /* [70] */ INVALID, INVALID, INVALID, INVALID, 1092 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1093 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1094 /* [7C] */ INVALID, INVALID, INVALID, INVALID, 1095 1096 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1097 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1098 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1099 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1100 1101 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1102 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1103 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1104 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1105 1106 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1107 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1108 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1109 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1110 1111 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1112 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1113 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 1114 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 1115 1116 /* [C0] */ INVALID, INVALID, INVALID, INVALID, 1117 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1118 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1119 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1120 1121 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1122 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1123 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 1124 /* [DC] */ INVALID, INVALID, INVALID, INVALID, 1125 1126 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1127 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 1128 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1129 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1130 1131 /* [F0] */ TNSZvr("rorx",VEX_MXI,6),INVALID, INVALID, INVALID, 1132 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 1133 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1134 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1135 }; 1136 1137 const instable_t dis_opAVXF20F38[256] = { 1138 /* [00] */ INVALID, INVALID, INVALID, INVALID, 1139 /* [04] */ INVALID, INVALID, INVALID, INVALID, 1140 /* [08] */ INVALID, INVALID, INVALID, INVALID, 1141 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1142 1143 /* [10] */ INVALID, INVALID, INVALID, INVALID, 1144 /* [14] */ INVALID, INVALID, INVALID, INVALID, 1145 /* [18] */ INVALID, INVALID, INVALID, INVALID, 1146 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 1147 1148 /* [20] */ INVALID, INVALID, INVALID, INVALID, 1149 /* [24] */ INVALID, INVALID, INVALID, INVALID, 1150 /* [28] */ INVALID, INVALID, INVALID, INVALID, 1151 /* [2C] */ INVALID, INVALID, INVALID, INVALID, 1152 1153 /* [30] */ INVALID, INVALID, INVALID, INVALID, 1154 /* [34] */ INVALID, INVALID, INVALID, INVALID, 1155 /* [38] */ INVALID, INVALID, INVALID, INVALID, 1156 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 1157 1158 /* [40] */ INVALID, INVALID, INVALID, INVALID, 1159 /* [44] */ INVALID, INVALID, INVALID, INVALID, 1160 /* [48] */ INVALID, INVALID, INVALID, INVALID, 1161 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 1162 1163 /* [50] */ INVALID, INVALID, INVALID, INVALID, 1164 /* [54] */ INVALID, INVALID, INVALID, INVALID, 1165 /* [58] */ INVALID, INVALID, INVALID, INVALID, 1166 /* [5C] */ INVALID, INVALID, INVALID, INVALID, 1167 1168 /* [60] */ INVALID, INVALID, INVALID, INVALID, 1169 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1170 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1171 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 1172 1173 /* [70] */ INVALID, INVALID, INVALID, INVALID, 1174 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1175 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1176 /* [7C] */ INVALID, INVALID, INVALID, INVALID, 1177 1178 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1179 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1180 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1181 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1182 1183 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1184 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1185 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1186 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1187 1188 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1189 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1190 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1191 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1192 1193 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1194 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1195 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 1196 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 1197 1198 /* [C0] */ INVALID, INVALID, INVALID, INVALID, 1199 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1200 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1201 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1202 1203 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1204 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1205 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 1206 /* [DC] */ INVALID, INVALID, INVALID, INVALID, 1207 1208 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1209 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 1210 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1211 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1212 1213 /* [F0] */ INVALID, INVALID, INVALID, INVALID, 1214 /* [F4] */ INVALID, TNSZvr("pdep",VEX_RMrX,5),TNSZvr("mulx",VEX_RMrX,5),TNSZvr("shrx",VEX_VRMrX,5), 1215 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1216 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1217 }; 1218 1219 const instable_t dis_opAVXF30F38[256] = { 1220 /* [00] */ INVALID, INVALID, INVALID, INVALID, 1221 /* [04] */ INVALID, INVALID, INVALID, INVALID, 1222 /* [08] */ INVALID, INVALID, INVALID, INVALID, 1223 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1224 1225 /* [10] */ INVALID, INVALID, INVALID, INVALID, 1226 /* [14] */ INVALID, INVALID, INVALID, INVALID, 1227 /* [18] */ INVALID, INVALID, INVALID, INVALID, 1228 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 1229 1230 /* [20] */ INVALID, INVALID, INVALID, INVALID, 1231 /* [24] */ INVALID, INVALID, INVALID, INVALID, 1232 /* [28] */ INVALID, INVALID, INVALID, INVALID, 1233 /* [2C] */ INVALID, INVALID, INVALID, INVALID, 1234 1235 /* [30] */ INVALID, INVALID, INVALID, INVALID, 1236 /* [34] */ INVALID, INVALID, INVALID, INVALID, 1237 /* [38] */ INVALID, INVALID, INVALID, INVALID, 1238 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 1239 1240 /* [40] */ INVALID, INVALID, INVALID, INVALID, 1241 /* [44] */ INVALID, INVALID, INVALID, INVALID, 1242 /* [48] */ INVALID, INVALID, INVALID, INVALID, 1243 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 1244 1245 /* [50] */ INVALID, INVALID, INVALID, INVALID, 1246 /* [54] */ INVALID, INVALID, INVALID, INVALID, 1247 /* [58] */ INVALID, INVALID, INVALID, INVALID, 1248 /* [5C] */ INVALID, INVALID, INVALID, INVALID, 1249 1250 /* [60] */ INVALID, INVALID, INVALID, INVALID, 1251 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1252 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1253 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 1254 1255 /* [70] */ INVALID, INVALID, INVALID, INVALID, 1256 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1257 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1258 /* [7C] */ INVALID, INVALID, INVALID, INVALID, 1259 1260 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1261 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1262 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1263 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1264 1265 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1266 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1267 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1268 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1269 1270 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1271 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1272 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1273 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1274 1275 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1276 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1277 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 1278 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 1279 1280 /* [C0] */ INVALID, INVALID, INVALID, INVALID, 1281 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1282 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1283 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1284 1285 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1286 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1287 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 1288 /* [DC] */ INVALID, INVALID, INVALID, INVALID, 1289 1290 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1291 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 1292 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1293 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1294 1295 /* [F0] */ INVALID, INVALID, INVALID, INVALID, 1296 /* [F4] */ INVALID, TNSZvr("pext",VEX_RMrX,5),INVALID, TNSZvr("sarx",VEX_VRMrX,5), 1297 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1298 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1299 }; 1300 /* 1301 * Decode table for SIMD instructions with the repz (0xf3) prefix. 1302 */ 1303 const instable_t dis_opSIMDrepz[256] = { 1304 /* [00] */ INVALID, INVALID, INVALID, INVALID, 1305 /* [04] */ INVALID, INVALID, INVALID, INVALID, 1306 /* [08] */ INVALID, INVALID, INVALID, INVALID, 1307 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1308 1309 /* [10] */ TNSZ("movss",XMM,4), TNSZ("movss",XMMS,4), TNSZ("movsldup",XMM,16),INVALID, 1310 /* [14] */ INVALID, INVALID, TNSZ("movshdup",XMM,16),INVALID, 1311 /* [18] */ INVALID, INVALID, INVALID, INVALID, 1312 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 1313 1314 /* [20] */ INVALID, INVALID, INVALID, INVALID, 1315 /* [24] */ INVALID, INVALID, INVALID, INVALID, 1316 /* [28] */ INVALID, INVALID, TNSZ("cvtsi2ss",XMM3MX,4),TNSZ("movntss",XMMMS,4), 1317 /* [2C] */ TNSZ("cvttss2si",XMMXM3,4),TNSZ("cvtss2si",XMMXM3,4),INVALID, INVALID, 1318 1319 /* [30] */ INVALID, INVALID, INVALID, INVALID, 1320 /* [34] */ INVALID, INVALID, INVALID, INVALID, 1321 /* [38] */ INVALID, INVALID, INVALID, INVALID, 1322 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 1323 1324 /* [40] */ INVALID, INVALID, INVALID, INVALID, 1325 /* [44] */ INVALID, INVALID, INVALID, INVALID, 1326 /* [48] */ INVALID, INVALID, INVALID, INVALID, 1327 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 1328 1329 /* [50] */ INVALID, TNSZ("sqrtss",XMM,4), TNSZ("rsqrtss",XMM,4), TNSZ("rcpss",XMM,4), 1330 /* [54] */ INVALID, INVALID, INVALID, INVALID, 1331 /* [58] */ TNSZ("addss",XMM,4), TNSZ("mulss",XMM,4), TNSZ("cvtss2sd",XMM,4), TNSZ("cvttps2dq",XMM,16), 1332 /* [5C] */ TNSZ("subss",XMM,4), TNSZ("minss",XMM,4), TNSZ("divss",XMM,4), TNSZ("maxss",XMM,4), 1333 1334 /* [60] */ INVALID, INVALID, INVALID, INVALID, 1335 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1336 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1337 /* [6C] */ INVALID, INVALID, INVALID, TNSZ("movdqu",XMM,16), 1338 1339 /* [70] */ TNSZ("pshufhw",XMMP,16),INVALID, INVALID, INVALID, 1340 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1341 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1342 /* [7C] */ INVALID, INVALID, TNSZ("movq",XMM,8), TNSZ("movdqu",XMMS,16), 1343 1344 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1345 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1346 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1347 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1348 1349 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1350 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1351 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1352 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1353 1354 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1355 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1356 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1357 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1358 1359 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1360 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1361 /* [B8] */ TS("popcnt",MRw), INVALID, INVALID, INVALID, 1362 /* [BC] */ TNSZ("tzcnt",MRw,5), TS("lzcnt",MRw), INVALID, INVALID, 1363 1364 /* [C0] */ INVALID, INVALID, TNSZ("cmpss",XMMP,4), INVALID, 1365 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1366 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1367 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1368 1369 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1370 /* [D4] */ INVALID, INVALID, TNS("movq2dq",XMMMX), INVALID, 1371 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 1372 /* [DC] */ INVALID, INVALID, INVALID, INVALID, 1373 1374 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1375 /* [E4] */ INVALID, INVALID, TNSZ("cvtdq2pd",XMM,8), INVALID, 1376 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1377 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1378 1379 /* [F0] */ INVALID, INVALID, INVALID, INVALID, 1380 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 1381 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1382 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1383 }; 1384 1385 const instable_t dis_opAVXF30F[256] = { 1386 /* [00] */ INVALID, INVALID, INVALID, INVALID, 1387 /* [04] */ INVALID, INVALID, INVALID, INVALID, 1388 /* [08] */ INVALID, INVALID, INVALID, INVALID, 1389 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1390 1391 /* [10] */ TNSZ("vmovss",VEX_RMrX,4), TNSZ("vmovss",VEX_RRX,4), TNSZ("vmovsldup",VEX_MX,4), INVALID, 1392 /* [14] */ INVALID, INVALID, TNSZ("vmovshdup",VEX_MX,4), INVALID, 1393 /* [18] */ INVALID, INVALID, INVALID, INVALID, 1394 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 1395 1396 /* [20] */ INVALID, INVALID, INVALID, INVALID, 1397 /* [24] */ INVALID, INVALID, INVALID, INVALID, 1398 /* [28] */ INVALID, INVALID, TNSZ("vcvtsi2ss",VEX_RMrX,4),INVALID, 1399 /* [2C] */ TNSZ("vcvttss2si",VEX_MR,4),TNSZ("vcvtss2si",VEX_MR,4),INVALID, INVALID, 1400 1401 /* [30] */ INVALID, INVALID, INVALID, INVALID, 1402 /* [34] */ INVALID, INVALID, INVALID, INVALID, 1403 /* [38] */ INVALID, INVALID, INVALID, INVALID, 1404 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 1405 1406 /* [40] */ INVALID, INVALID, INVALID, INVALID, 1407 /* [44] */ INVALID, INVALID, INVALID, INVALID, 1408 /* [48] */ INVALID, INVALID, INVALID, INVALID, 1409 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 1410 1411 /* [50] */ INVALID, TNSZ("vsqrtss",VEX_RMrX,4), TNSZ("vrsqrtss",VEX_RMrX,4), TNSZ("vrcpss",VEX_RMrX,4), 1412 /* [54] */ INVALID, INVALID, INVALID, INVALID, 1413 /* [58] */ TNSZ("vaddss",VEX_RMrX,4), TNSZ("vmulss",VEX_RMrX,4), TNSZ("vcvtss2sd",VEX_RMrX,4), TNSZ("vcvttps2dq",VEX_MX,16), 1414 /* [5C] */ TNSZ("vsubss",VEX_RMrX,4), TNSZ("vminss",VEX_RMrX,4), TNSZ("vdivss",VEX_RMrX,4), TNSZ("vmaxss",VEX_RMrX,4), 1415 1416 /* [60] */ INVALID, INVALID, INVALID, INVALID, 1417 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1418 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1419 /* [6C] */ INVALID, INVALID, INVALID, TNSZ("vmovdqu",VEX_MX,16), 1420 1421 /* [70] */ TNSZ("vpshufhw",VEX_MXI,16),INVALID, INVALID, INVALID, 1422 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1423 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1424 /* [7C] */ INVALID, INVALID, TNSZ("vmovq",VEX_MX,8), TNSZ("vmovdqu",VEX_RX,16), 1425 1426 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1427 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1428 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1429 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1430 1431 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1432 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1433 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1434 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1435 1436 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1437 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1438 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1439 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1440 1441 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1442 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1443 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 1444 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 1445 1446 /* [C0] */ INVALID, INVALID, TNSZ("vcmpss",VEX_RMRX,4), INVALID, 1447 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1448 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1449 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1450 1451 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1452 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1453 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 1454 /* [DC] */ INVALID, INVALID, INVALID, INVALID, 1455 1456 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1457 /* [E4] */ INVALID, INVALID, TNSZ("vcvtdq2pd",VEX_MX,8), INVALID, 1458 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1459 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1460 1461 /* [F0] */ INVALID, INVALID, INVALID, INVALID, 1462 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 1463 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1464 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1465 }; 1466 1467 /* 1468 * Table for instructions with an EVEX prefix followed by 0F. 1469 */ 1470 const instable_t dis_opEVEX0F[256] = { 1471 /* [00] */ INVALID, INVALID, INVALID, INVALID, 1472 /* [04] */ INVALID, INVALID, INVALID, INVALID, 1473 /* [08] */ INVALID, INVALID, INVALID, INVALID, 1474 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1475 1476 /* [10] */ TNS("vmovups",EVEX_MX), TNS("vmovups",EVEX_RX), INVALID, INVALID, 1477 /* [14] */ INVALID, INVALID, INVALID, INVALID, 1478 /* [18] */ INVALID, INVALID, INVALID, INVALID, 1479 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 1480 1481 /* [20] */ INVALID, INVALID, INVALID, INVALID, 1482 /* [24] */ INVALID, INVALID, INVALID, INVALID, 1483 /* [28] */ TNS("vmovaps",EVEX_MX), TNS("vmovaps",EVEX_RX), INVALID, INVALID, 1484 /* [2C] */ INVALID, INVALID, INVALID, INVALID, 1485 1486 /* [30] */ INVALID, INVALID, INVALID, INVALID, 1487 /* [34] */ INVALID, INVALID, INVALID, INVALID, 1488 /* [38] */ INVALID, INVALID, INVALID, INVALID, 1489 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 1490 1491 /* [40] */ INVALID, INVALID, INVALID, INVALID, 1492 /* [44] */ INVALID, INVALID, INVALID, INVALID, 1493 /* [48] */ INVALID, INVALID, INVALID, INVALID, 1494 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 1495 1496 /* [50] */ INVALID, INVALID, INVALID, INVALID, 1497 /* [54] */ TNS("vandps",EVEX_RMrX),TNS("vandnps",EVEX_RMrX),TNS("vorps",EVEX_RMrX),TNS("vxorps",EVEX_RMrX), 1498 /* [58] */ INVALID, INVALID, INVALID, INVALID, 1499 /* [5C] */ INVALID, INVALID, INVALID, INVALID, 1500 1501 /* [60] */ INVALID, INVALID, INVALID, INVALID, 1502 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1503 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1504 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 1505 1506 /* [70] */ INVALID, INVALID, INVALID, INVALID, 1507 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1508 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1509 /* [7C] */ INVALID, INVALID, INVALID, INVALID, 1510 1511 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1512 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1513 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1514 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1515 1516 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1517 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1518 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1519 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1520 1521 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1522 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1523 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1524 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1525 1526 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1527 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1528 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 1529 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 1530 1531 /* [C0] */ INVALID, INVALID, INVALID, INVALID, 1532 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1533 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1534 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1535 1536 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1537 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1538 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 1539 /* [DC] */ INVALID, INVALID, INVALID, INVALID, 1540 1541 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1542 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 1543 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1544 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1545 1546 /* [F0] */ INVALID, INVALID, INVALID, INVALID, 1547 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 1548 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1549 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1550 }; 1551 1552 /* 1553 * Decode tables for EVEX 66 0F 1554 */ 1555 const instable_t dis_opEVEX660F[256] = { 1556 /* [00] */ INVALID, INVALID, INVALID, INVALID, 1557 /* [04] */ INVALID, INVALID, INVALID, INVALID, 1558 /* [08] */ INVALID, INVALID, INVALID, INVALID, 1559 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1560 1561 /* [10] */ TNS("vmovupd",EVEX_MX), TNS("vmovupd",EVEX_RX), INVALID, INVALID, 1562 /* [14] */ INVALID, INVALID, INVALID, INVALID, 1563 /* [18] */ INVALID, INVALID, INVALID, INVALID, 1564 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 1565 1566 /* [20] */ INVALID, INVALID, INVALID, INVALID, 1567 /* [24] */ INVALID, INVALID, INVALID, INVALID, 1568 /* [28] */ TNS("vmovapd",EVEX_MX), TNS("vmovapd",EVEX_RX), INVALID, INVALID, 1569 /* [2C] */ INVALID, INVALID, INVALID, INVALID, 1570 1571 /* [30] */ INVALID, INVALID, INVALID, INVALID, 1572 /* [34] */ INVALID, INVALID, INVALID, INVALID, 1573 /* [38] */ INVALID, INVALID, INVALID, INVALID, 1574 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 1575 1576 /* [40] */ INVALID, INVALID, INVALID, INVALID, 1577 /* [44] */ INVALID, INVALID, INVALID, INVALID, 1578 /* [48] */ INVALID, INVALID, INVALID, INVALID, 1579 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 1580 1581 /* [50] */ INVALID, INVALID, INVALID, INVALID, 1582 /* [54] */ TNS("vandpd",EVEX_RMrX),TNS("vandnpd",EVEX_RMrX),TNS("vorpd",EVEX_RMrX),TNS("vxorpd",EVEX_RMrX), 1583 /* [58] */ INVALID, INVALID, INVALID, INVALID, 1584 /* [5C] */ INVALID, INVALID, INVALID, INVALID, 1585 1586 /* [60] */ INVALID, INVALID, INVALID, INVALID, 1587 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1588 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1589 /* [6C] */ INVALID, INVALID, INVALID, TNS("vmovdqa",EVEX_MX), 1590 1591 /* [70] */ INVALID, INVALID, INVALID, INVALID, 1592 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1593 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1594 /* [7C] */ INVALID, INVALID, INVALID, TNS("vmovdqa",EVEX_RX), 1595 1596 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1597 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1598 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1599 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1600 1601 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1602 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1603 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1604 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1605 1606 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1607 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1608 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1609 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1610 1611 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1612 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1613 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 1614 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 1615 1616 /* [C0] */ INVALID, INVALID, INVALID, INVALID, 1617 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1618 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1619 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1620 1621 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1622 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1623 /* [D8] */ INVALID, INVALID, INVALID, TSq("vpand",EVEX_RMrX), 1624 /* [DC] */ INVALID, INVALID, INVALID, TSq("vpandn",EVEX_RMrX), 1625 1626 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1627 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 1628 /* [E8] */ INVALID, INVALID, INVALID, TSq("vpor",EVEX_RMrX), 1629 /* [EC] */ INVALID, INVALID, INVALID, TSq("vpxor",EVEX_RMrX), 1630 1631 /* [F0] */ INVALID, INVALID, INVALID, INVALID, 1632 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 1633 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1634 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1635 }; 1636 1637 const instable_t dis_opEVEX660F38[256] = { 1638 /* [00] */ INVALID, INVALID, INVALID, INVALID, 1639 /* [04] */ INVALID, INVALID, INVALID, INVALID, 1640 /* [08] */ INVALID, INVALID, INVALID, INVALID, 1641 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1642 1643 /* [10] */ INVALID, INVALID, INVALID, INVALID, 1644 /* [14] */ INVALID, INVALID, INVALID, INVALID, 1645 /* [18] */ INVALID, INVALID, INVALID, INVALID, 1646 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 1647 1648 /* [20] */ INVALID, INVALID, INVALID, INVALID, 1649 /* [24] */ INVALID, INVALID, INVALID, INVALID, 1650 /* [28] */ INVALID, INVALID, INVALID, INVALID, 1651 /* [2C] */ INVALID, INVALID, INVALID, INVALID, 1652 1653 /* [30] */ INVALID, INVALID, INVALID, INVALID, 1654 /* [34] */ INVALID, INVALID, INVALID, INVALID, 1655 /* [38] */ INVALID, INVALID, INVALID, INVALID, 1656 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 1657 1658 /* [40] */ INVALID, INVALID, INVALID, INVALID, 1659 /* [44] */ INVALID, INVALID, INVALID, INVALID, 1660 /* [48] */ INVALID, INVALID, INVALID, INVALID, 1661 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 1662 1663 /* [50] */ TNSZ("vpdpbusd",EVEX_RMrX,16),TNSZ("vpdpbusds",EVEX_RMrX,16),TNSZ("vpdpwssd",EVEX_RMrX,16),TNSZ("vpdpwssds",EVEX_RMrX,16), 1664 /* [54] */ INVALID, INVALID, INVALID, INVALID, 1665 /* [58] */ INVALID, INVALID, INVALID, INVALID, 1666 /* [5C] */ INVALID, INVALID, INVALID, INVALID, 1667 1668 /* [60] */ INVALID, INVALID, INVALID, INVALID, 1669 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1670 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1671 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 1672 1673 /* [70] */ INVALID, INVALID, INVALID, INVALID, 1674 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1675 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1676 /* [7C] */ INVALID, INVALID, INVALID, INVALID, 1677 1678 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1679 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1680 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1681 /* [8C] */ INVALID, INVALID, INVALID, INVALID, 1682 1683 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1684 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1685 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1686 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1687 1688 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1689 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1690 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1691 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1692 1693 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1694 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1695 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 1696 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 1697 1698 /* [C0] */ INVALID, INVALID, INVALID, INVALID, 1699 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1700 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1701 /* [CC] */ INVALID, INVALID, INVALID, TNS("vgf2p8mulb",EVEX_RMrX), 1702 1703 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1704 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1705 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 1706 /* [DC] */ TNSZ("vaesenc",EVEX_RMrX,16),TNSZ("vaesenclast",EVEX_RMrX,16),TNSZ("vaesdec",EVEX_RMrX,16),TNSZ("vaesdeclast",EVEX_RMrX,16), 1707 1708 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1709 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 1710 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1711 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1712 1713 /* [F0] */ INVALID, INVALID, INVALID, INVALID, 1714 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 1715 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1716 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1717 }; 1718 1719 const instable_t dis_opEVEX660F3A[256] = { 1720 /* [00] */ INVALID, INVALID, INVALID, INVALID, 1721 /* [04] */ INVALID, INVALID, INVALID, INVALID, 1722 /* [08] */ INVALID, INVALID, INVALID, INVALID, 1723 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1724 1725 /* [10] */ INVALID, INVALID, INVALID, INVALID, 1726 /* [14] */ INVALID, INVALID, INVALID, INVALID, 1727 /* [18] */ INVALID, INVALID, INVALID, INVALID, 1728 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 1729 1730 /* [20] */ INVALID, INVALID, INVALID, INVALID, 1731 /* [24] */ INVALID, INVALID, INVALID, INVALID, 1732 /* [28] */ INVALID, INVALID, INVALID, INVALID, 1733 /* [2C] */ INVALID, INVALID, INVALID, INVALID, 1734 1735 /* [30] */ INVALID, INVALID, INVALID, INVALID, 1736 /* [34] */ INVALID, INVALID, INVALID, INVALID, 1737 /* [38] */ INVALID, INVALID, INVALID, INVALID, 1738 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 1739 1740 /* [40] */ INVALID, INVALID, INVALID, INVALID, 1741 /* [44] */ TNSZ("vpclmulqdq",EVEX_RMRX,16),INVALID, INVALID, INVALID, 1742 /* [48] */ INVALID, INVALID, INVALID, INVALID, 1743 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 1744 1745 /* [50] */ INVALID, INVALID, INVALID, INVALID, 1746 /* [54] */ INVALID, INVALID, INVALID, INVALID, 1747 /* [58] */ INVALID, INVALID, INVALID, INVALID, 1748 /* [5C] */ INVALID, INVALID, INVALID, INVALID, 1749 1750 /* [60] */ INVALID, INVALID, INVALID, INVALID, 1751 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1752 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1753 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 1754 1755 /* [70] */ INVALID, INVALID, INVALID, INVALID, 1756 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1757 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1758 /* [7C] */ INVALID, INVALID, INVALID, INVALID, 1759 1760 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1761 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1762 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1763 /* [8C] */ INVALID, INVALID, INVALID, INVALID, 1764 1765 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1766 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1767 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1768 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1769 1770 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1771 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1772 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1773 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1774 1775 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1776 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1777 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 1778 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 1779 1780 /* [C0] */ INVALID, INVALID, INVALID, INVALID, 1781 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1782 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1783 /* [CC] */ INVALID, INVALID, TNS("vgf2p8affineqb",EVEX_RMRX),TNS("vgf2p8affineinvqb",EVEX_RMRX), 1784 1785 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1786 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1787 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 1788 /* [DC] */ INVALID, INVALID, INVALID, INVALID, 1789 1790 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1791 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 1792 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1793 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1794 1795 /* [F0] */ INVALID, INVALID, INVALID, INVALID, 1796 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 1797 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1798 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1799 }; 1800 1801 1802 const instable_t dis_opEVEXF20F[256] = { 1803 /* [00] */ INVALID, INVALID, INVALID, INVALID, 1804 /* [04] */ INVALID, INVALID, INVALID, INVALID, 1805 /* [08] */ INVALID, INVALID, INVALID, INVALID, 1806 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1807 1808 /* [10] */ INVALID, INVALID, INVALID, INVALID, 1809 /* [14] */ INVALID, INVALID, INVALID, INVALID, 1810 /* [18] */ INVALID, INVALID, INVALID, INVALID, 1811 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 1812 1813 /* [20] */ INVALID, INVALID, INVALID, INVALID, 1814 /* [24] */ INVALID, INVALID, INVALID, INVALID, 1815 /* [28] */ INVALID, INVALID, INVALID, INVALID, 1816 /* [2C] */ INVALID, INVALID, INVALID, INVALID, 1817 1818 /* [30] */ INVALID, INVALID, INVALID, INVALID, 1819 /* [34] */ INVALID, INVALID, INVALID, INVALID, 1820 /* [38] */ INVALID, INVALID, INVALID, INVALID, 1821 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 1822 1823 /* [40] */ INVALID, INVALID, INVALID, INVALID, 1824 /* [44] */ INVALID, INVALID, INVALID, INVALID, 1825 /* [48] */ INVALID, INVALID, INVALID, INVALID, 1826 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 1827 1828 /* [50] */ INVALID, INVALID, INVALID, INVALID, 1829 /* [54] */ INVALID, INVALID, INVALID, INVALID, 1830 /* [58] */ INVALID, INVALID, INVALID, INVALID, 1831 /* [5C] */ INVALID, INVALID, INVALID, INVALID, 1832 1833 /* [60] */ INVALID, INVALID, INVALID, INVALID, 1834 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1835 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1836 /* [6C] */ INVALID, INVALID, INVALID, TNS("vmovdqu",EVEX_MX), 1837 1838 /* [70] */ INVALID, INVALID, INVALID, INVALID, 1839 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1840 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1841 /* [7C] */ INVALID, INVALID, INVALID, TNS("vmovdqu",EVEX_RX), 1842 1843 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1844 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1845 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1846 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1847 1848 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1849 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1850 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1851 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1852 1853 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1854 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1855 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1856 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1857 1858 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1859 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1860 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 1861 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 1862 1863 /* [C0] */ INVALID, INVALID, INVALID, INVALID, 1864 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1865 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1866 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1867 1868 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1869 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1870 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 1871 /* [DC] */ INVALID, INVALID, INVALID, INVALID, 1872 1873 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1874 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 1875 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1876 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1877 1878 /* [F0] */ INVALID, INVALID, INVALID, INVALID, 1879 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 1880 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1881 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1882 }; 1883 1884 const instable_t dis_opEVEXF30F[256] = { 1885 /* [00] */ INVALID, INVALID, INVALID, INVALID, 1886 /* [04] */ INVALID, INVALID, INVALID, INVALID, 1887 /* [08] */ INVALID, INVALID, INVALID, INVALID, 1888 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1889 1890 /* [10] */ INVALID, INVALID, INVALID, INVALID, 1891 /* [14] */ INVALID, INVALID, INVALID, INVALID, 1892 /* [18] */ INVALID, INVALID, INVALID, INVALID, 1893 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 1894 1895 /* [20] */ INVALID, INVALID, INVALID, INVALID, 1896 /* [24] */ INVALID, INVALID, INVALID, INVALID, 1897 /* [28] */ INVALID, INVALID, INVALID, INVALID, 1898 /* [2C] */ INVALID, INVALID, INVALID, INVALID, 1899 1900 /* [30] */ INVALID, INVALID, INVALID, INVALID, 1901 /* [34] */ INVALID, INVALID, INVALID, INVALID, 1902 /* [38] */ INVALID, INVALID, INVALID, INVALID, 1903 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 1904 1905 /* [40] */ INVALID, INVALID, INVALID, INVALID, 1906 /* [44] */ INVALID, INVALID, INVALID, INVALID, 1907 /* [48] */ INVALID, INVALID, INVALID, INVALID, 1908 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 1909 1910 /* [50] */ INVALID, INVALID, INVALID, INVALID, 1911 /* [54] */ INVALID, INVALID, INVALID, INVALID, 1912 /* [58] */ INVALID, INVALID, INVALID, INVALID, 1913 /* [5C] */ INVALID, INVALID, INVALID, INVALID, 1914 1915 /* [60] */ INVALID, INVALID, INVALID, INVALID, 1916 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1917 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1918 /* [6C] */ INVALID, INVALID, INVALID, TNS("vmovdqu",EVEX_MX), 1919 1920 /* [70] */ INVALID, INVALID, INVALID, INVALID, 1921 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1922 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1923 /* [7C] */ INVALID, INVALID, INVALID, TNS("vmovdqu",EVEX_RX), 1924 1925 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1926 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1927 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1928 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1929 1930 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1931 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1932 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1933 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1934 1935 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1936 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1937 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1938 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1939 1940 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1941 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1942 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 1943 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 1944 1945 /* [C0] */ INVALID, INVALID, INVALID, INVALID, 1946 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1947 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1948 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1949 1950 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1951 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1952 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 1953 /* [DC] */ INVALID, INVALID, INVALID, INVALID, 1954 1955 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1956 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 1957 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1958 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1959 1960 /* [F0] */ INVALID, INVALID, INVALID, INVALID, 1961 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 1962 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1963 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1964 }; 1965 /* 1966 * The following two tables are used to encode crc32 and movbe 1967 * since they share the same opcodes. 1968 */ 1969 const instable_t dis_op0F38F0[2] = { 1970 /* [00] */ TNS("crc32b",CRC32), 1971 TS("movbe",MOVBE), 1972 }; 1973 1974 const instable_t dis_op0F38F1[2] = { 1975 /* [00] */ TS("crc32",CRC32), 1976 TS("movbe",MOVBE), 1977 }; 1978 1979 /* 1980 * The following table is used to distinguish between adox and adcx which share 1981 * the same opcodes. 1982 */ 1983 const instable_t dis_op0F38F6[2] = { 1984 /* [00] */ TNS("adcx",ADX), 1985 TNS("adox",ADX), 1986 }; 1987 1988 const instable_t dis_op0F38[256] = { 1989 /* [00] */ TNSZ("pshufb",XMM_66o,16),TNSZ("phaddw",XMM_66o,16),TNSZ("phaddd",XMM_66o,16),TNSZ("phaddsw",XMM_66o,16), 1990 /* [04] */ TNSZ("pmaddubsw",XMM_66o,16),TNSZ("phsubw",XMM_66o,16), TNSZ("phsubd",XMM_66o,16),TNSZ("phsubsw",XMM_66o,16), 1991 /* [08] */ TNSZ("psignb",XMM_66o,16),TNSZ("psignw",XMM_66o,16),TNSZ("psignd",XMM_66o,16),TNSZ("pmulhrsw",XMM_66o,16), 1992 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1993 1994 /* [10] */ TNSZ("pblendvb",XMM_66r,16),INVALID, INVALID, INVALID, 1995 /* [14] */ TNSZ("blendvps",XMM_66r,16),TNSZ("blendvpd",XMM_66r,16),INVALID, TNSZ("ptest",XMM_66r,16), 1996 /* [18] */ INVALID, INVALID, INVALID, INVALID, 1997 /* [1C] */ TNSZ("pabsb",XMM_66o,16),TNSZ("pabsw",XMM_66o,16),TNSZ("pabsd",XMM_66o,16),INVALID, 1998 1999 /* [20] */ TNSZ("pmovsxbw",XMM_66r,16),TNSZ("pmovsxbd",XMM_66r,16),TNSZ("pmovsxbq",XMM_66r,16),TNSZ("pmovsxwd",XMM_66r,16), 2000 /* [24] */ TNSZ("pmovsxwq",XMM_66r,16),TNSZ("pmovsxdq",XMM_66r,16),INVALID, INVALID, 2001 /* [28] */ TNSZ("pmuldq",XMM_66r,16),TNSZ("pcmpeqq",XMM_66r,16),TNSZ("movntdqa",XMMM_66r,16),TNSZ("packusdw",XMM_66r,16), 2002 /* [2C] */ INVALID, INVALID, INVALID, INVALID, 2003 2004 /* [30] */ TNSZ("pmovzxbw",XMM_66r,16),TNSZ("pmovzxbd",XMM_66r,16),TNSZ("pmovzxbq",XMM_66r,16),TNSZ("pmovzxwd",XMM_66r,16), 2005 /* [34] */ TNSZ("pmovzxwq",XMM_66r,16),TNSZ("pmovzxdq",XMM_66r,16),INVALID, TNSZ("pcmpgtq",XMM_66r,16), 2006 /* [38] */ TNSZ("pminsb",XMM_66r,16),TNSZ("pminsd",XMM_66r,16),TNSZ("pminuw",XMM_66r,16),TNSZ("pminud",XMM_66r,16), 2007 /* [3C] */ TNSZ("pmaxsb",XMM_66r,16),TNSZ("pmaxsd",XMM_66r,16),TNSZ("pmaxuw",XMM_66r,16),TNSZ("pmaxud",XMM_66r,16), 2008 2009 /* [40] */ TNSZ("pmulld",XMM_66r,16),TNSZ("phminposuw",XMM_66r,16),INVALID, INVALID, 2010 /* [44] */ INVALID, INVALID, INVALID, INVALID, 2011 /* [48] */ INVALID, INVALID, INVALID, INVALID, 2012 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 2013 2014 /* [50] */ INVALID, INVALID, INVALID, INVALID, 2015 /* [54] */ INVALID, INVALID, INVALID, INVALID, 2016 /* [58] */ INVALID, INVALID, INVALID, INVALID, 2017 /* [5C] */ INVALID, INVALID, INVALID, INVALID, 2018 2019 /* [60] */ INVALID, INVALID, INVALID, INVALID, 2020 /* [64] */ INVALID, INVALID, INVALID, INVALID, 2021 /* [68] */ INVALID, INVALID, INVALID, INVALID, 2022 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 2023 2024 /* [70] */ INVALID, INVALID, INVALID, INVALID, 2025 /* [74] */ INVALID, INVALID, INVALID, INVALID, 2026 /* [78] */ INVALID, INVALID, INVALID, INVALID, 2027 /* [7C] */ INVALID, INVALID, INVALID, INVALID, 2028 2029 /* [80] */ TNSy("invept", RM_66r), TNSy("invvpid", RM_66r),TNSy("invpcid", RM_66r),INVALID, 2030 /* [84] */ INVALID, INVALID, INVALID, INVALID, 2031 /* [88] */ INVALID, INVALID, INVALID, INVALID, 2032 /* [8C] */ INVALID, INVALID, INVALID, INVALID, 2033 2034 /* [90] */ INVALID, INVALID, INVALID, INVALID, 2035 /* [94] */ INVALID, INVALID, INVALID, INVALID, 2036 /* [98] */ INVALID, INVALID, INVALID, INVALID, 2037 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 2038 2039 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 2040 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 2041 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 2042 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 2043 2044 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 2045 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 2046 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 2047 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 2048 2049 /* [C0] */ INVALID, INVALID, INVALID, INVALID, 2050 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 2051 /* [C8] */ TNSZ("sha1nexte",XMM,16),TNSZ("sha1msg1",XMM,16),TNSZ("sha1msg2",XMM,16),TNSZ("sha256rnds2",XMM,16), 2052 /* [CC] */ TNSZ("sha256msg1",XMM,16),TNSZ("sha256msg2",XMM,16),INVALID, TNS("gf2p8mulb",XMM_66r), 2053 2054 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 2055 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 2056 /* [D8] */ INVALID, INVALID, INVALID, TNSZ("aesimc",XMM_66r,16), 2057 /* [DC] */ TNSZ("aesenc",XMM_66r,16),TNSZ("aesenclast",XMM_66r,16),TNSZ("aesdec",XMM_66r,16),TNSZ("aesdeclast",XMM_66r,16), 2058 2059 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 2060 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 2061 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 2062 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 2063 /* [F0] */ IND(dis_op0F38F0), IND(dis_op0F38F1), INVALID, INVALID, 2064 /* [F4] */ INVALID, INVALID, IND(dis_op0F38F6), INVALID, 2065 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 2066 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 2067 }; 2068 2069 const instable_t dis_opAVX660F38[256] = { 2070 /* [00] */ TNSZ("vpshufb",VEX_RMrX,16),TNSZ("vphaddw",VEX_RMrX,16),TNSZ("vphaddd",VEX_RMrX,16),TNSZ("vphaddsw",VEX_RMrX,16), 2071 /* [04] */ TNSZ("vpmaddubsw",VEX_RMrX,16),TNSZ("vphsubw",VEX_RMrX,16), TNSZ("vphsubd",VEX_RMrX,16),TNSZ("vphsubsw",VEX_RMrX,16), 2072 /* [08] */ TNSZ("vpsignb",VEX_RMrX,16),TNSZ("vpsignw",VEX_RMrX,16),TNSZ("vpsignd",VEX_RMrX,16),TNSZ("vpmulhrsw",VEX_RMrX,16), 2073 /* [0C] */ TNSZ("vpermilps",VEX_RMrX,8),TNSZ("vpermilpd",VEX_RMrX,16),TNSZ("vtestps",VEX_RRI,8), TNSZ("vtestpd",VEX_RRI,16), 2074 2075 /* [10] */ INVALID, INVALID, INVALID, TNSZ("vcvtph2ps",VEX_MX,16), 2076 /* [14] */ INVALID, INVALID, TNSZ("vpermps",VEX_RMrX,16),TNSZ("vptest",VEX_RRI,16), 2077 /* [18] */ TNSZ("vbroadcastss",VEX_MX,4),TNSZ("vbroadcastsd",VEX_MX,8),TNSZ("vbroadcastf128",VEX_MX,16),INVALID, 2078 /* [1C] */ TNSZ("vpabsb",VEX_MX,16),TNSZ("vpabsw",VEX_MX,16),TNSZ("vpabsd",VEX_MX,16),INVALID, 2079 2080 /* [20] */ TNSZ("vpmovsxbw",VEX_MX,16),TNSZ("vpmovsxbd",VEX_MX,16),TNSZ("vpmovsxbq",VEX_MX,16),TNSZ("vpmovsxwd",VEX_MX,16), 2081 /* [24] */ TNSZ("vpmovsxwq",VEX_MX,16),TNSZ("vpmovsxdq",VEX_MX,16),INVALID, INVALID, 2082 /* [28] */ TNSZ("vpmuldq",VEX_RMrX,16),TNSZ("vpcmpeqq",VEX_RMrX,16),TNSZ("vmovntdqa",VEX_MX,16),TNSZ("vpackusdw",VEX_RMrX,16), 2083 /* [2C] */ TNSZ("vmaskmovps",VEX_RMrX,8),TNSZ("vmaskmovpd",VEX_RMrX,16),TNSZ("vmaskmovps",VEX_RRM,8),TNSZ("vmaskmovpd",VEX_RRM,16), 2084 2085 /* [30] */ TNSZ("vpmovzxbw",VEX_MX,16),TNSZ("vpmovzxbd",VEX_MX,16),TNSZ("vpmovzxbq",VEX_MX,16),TNSZ("vpmovzxwd",VEX_MX,16), 2086 /* [34] */ TNSZ("vpmovzxwq",VEX_MX,16),TNSZ("vpmovzxdq",VEX_MX,16),TNSZ("vpermd",VEX_RMrX,16),TNSZ("vpcmpgtq",VEX_RMrX,16), 2087 /* [38] */ TNSZ("vpminsb",VEX_RMrX,16),TNSZ("vpminsd",VEX_RMrX,16),TNSZ("vpminuw",VEX_RMrX,16),TNSZ("vpminud",VEX_RMrX,16), 2088 /* [3C] */ TNSZ("vpmaxsb",VEX_RMrX,16),TNSZ("vpmaxsd",VEX_RMrX,16),TNSZ("vpmaxuw",VEX_RMrX,16),TNSZ("vpmaxud",VEX_RMrX,16), 2089 2090 /* [40] */ TNSZ("vpmulld",VEX_RMrX,16),TNSZ("vphminposuw",VEX_MX,16),INVALID, INVALID, 2091 /* [44] */ INVALID, TSaZ("vpsrlv",VEX_RMrX,16),TNSZ("vpsravd",VEX_RMrX,16),TSaZ("vpsllv",VEX_RMrX,16), 2092 /* [48] */ INVALID, INVALID, INVALID, INVALID, 2093 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 2094 2095 /* [50] */ INVALID, INVALID, INVALID, INVALID, 2096 /* [54] */ INVALID, INVALID, INVALID, INVALID, 2097 /* [58] */ TNSZ("vpbroadcastd",VEX_MX,16),TNSZ("vpbroadcastq",VEX_MX,16),TNSZ("vbroadcasti128",VEX_MX,16),INVALID, 2098 /* [5C] */ INVALID, INVALID, INVALID, INVALID, 2099 2100 /* [60] */ INVALID, INVALID, INVALID, INVALID, 2101 /* [64] */ INVALID, INVALID, INVALID, INVALID, 2102 /* [68] */ INVALID, INVALID, INVALID, INVALID, 2103 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 2104 2105 /* [70] */ INVALID, INVALID, INVALID, INVALID, 2106 /* [74] */ INVALID, INVALID, INVALID, INVALID, 2107 /* [78] */ TNSZ("vpbroadcastb",VEX_MX,16),TNSZ("vpbroadcastw",VEX_MX,16),INVALID, INVALID, 2108 /* [7C] */ INVALID, INVALID, INVALID, INVALID, 2109 2110 /* [80] */ INVALID, INVALID, INVALID, INVALID, 2111 /* [84] */ INVALID, INVALID, INVALID, INVALID, 2112 /* [88] */ INVALID, INVALID, INVALID, INVALID, 2113 /* [8C] */ TSaZ("vpmaskmov",VEX_RMrX,16),INVALID, TSaZ("vpmaskmov",VEX_RRM,16),INVALID, 2114 2115 /* [90] */ TNSZ("vpgatherd",VEX_SbVM,16),TNSZ("vpgatherq",VEX_SbVM,16),TNSZ("vgatherdp",VEX_SbVM,16),TNSZ("vgatherqp",VEX_SbVM,16), 2116 /* [94] */ INVALID, INVALID, TNSZ("vfmaddsub132p",FMA,16),TNSZ("vfmsubadd132p",FMA,16), 2117 /* [98] */ TNSZ("vfmadd132p",FMA,16),TNSZ("vfmadd132s",FMA,16),TNSZ("vfmsub132p",FMA,16),TNSZ("vfmsub132s",FMA,16), 2118 /* [9C] */ TNSZ("vfnmadd132p",FMA,16),TNSZ("vfnmadd132s",FMA,16),TNSZ("vfnmsub132p",FMA,16),TNSZ("vfnmsub132s",FMA,16), 2119 2120 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 2121 /* [A4] */ INVALID, INVALID, TNSZ("vfmaddsub213p",FMA,16),TNSZ("vfmsubadd213p",FMA,16), 2122 /* [A8] */ TNSZ("vfmadd213p",FMA,16),TNSZ("vfmadd213s",FMA,16),TNSZ("vfmsub213p",FMA,16),TNSZ("vfmsub213s",FMA,16), 2123 /* [AC] */ TNSZ("vfnmadd213p",FMA,16),TNSZ("vfnmadd213s",FMA,16),TNSZ("vfnmsub213p",FMA,16),TNSZ("vfnmsub213s",FMA,16), 2124 2125 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 2126 /* [B4] */ INVALID, INVALID, TNSZ("vfmaddsub231p",FMA,16),TNSZ("vfmsubadd231p",FMA,16), 2127 /* [B8] */ TNSZ("vfmadd231p",FMA,16),TNSZ("vfmadd231s",FMA,16),TNSZ("vfmsub231p",FMA,16),TNSZ("vfmsub231s",FMA,16), 2128 /* [BC] */ TNSZ("vfnmadd231p",FMA,16),TNSZ("vfnmadd231s",FMA,16),TNSZ("vfnmsub231p",FMA,16),TNSZ("vfnmsub231s",FMA,16), 2129 2130 /* [C0] */ INVALID, INVALID, INVALID, INVALID, 2131 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 2132 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 2133 /* [CC] */ INVALID, INVALID, INVALID, TNS("vgf2p8mulb",VEX_RMrX), 2134 2135 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 2136 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 2137 /* [D8] */ INVALID, INVALID, INVALID, TNSZ("vaesimc",VEX_MX,16), 2138 /* [DC] */ TNSZ("vaesenc",VEX_RMrX,16),TNSZ("vaesenclast",VEX_RMrX,16),TNSZ("vaesdec",VEX_RMrX,16),TNSZ("vaesdeclast",VEX_RMrX,16), 2139 2140 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 2141 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 2142 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 2143 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 2144 /* [F0] */ IND(dis_op0F38F0), IND(dis_op0F38F1), INVALID, INVALID, 2145 /* [F4] */ INVALID, INVALID, INVALID, TNSZvr("shlx",VEX_VRMrX,5), 2146 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 2147 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 2148 }; 2149 2150 const instable_t dis_op0F3A[256] = { 2151 /* [00] */ INVALID, INVALID, INVALID, INVALID, 2152 /* [04] */ INVALID, INVALID, INVALID, INVALID, 2153 /* [08] */ TNSZ("roundps",XMMP_66r,16),TNSZ("roundpd",XMMP_66r,16),TNSZ("roundss",XMMP_66r,16),TNSZ("roundsd",XMMP_66r,16), 2154 /* [0C] */ TNSZ("blendps",XMMP_66r,16),TNSZ("blendpd",XMMP_66r,16),TNSZ("pblendw",XMMP_66r,16),TNSZ("palignr",XMMP_66o,16), 2155 2156 /* [10] */ INVALID, INVALID, INVALID, INVALID, 2157 /* [14] */ TNSZ("pextrb",XMM3PM_66r,8),TNSZ("pextrw",XMM3PM_66r,16),TSZ("pextr",XMM3PM_66r,16),TNSZ("extractps",XMM3PM_66r,16), 2158 /* [18] */ INVALID, INVALID, INVALID, INVALID, 2159 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 2160 2161 /* [20] */ TNSZ("pinsrb",XMMPRM_66r,8),TNSZ("insertps",XMMP_66r,16),TSZ("pinsr",XMMPRM_66r,16),INVALID, 2162 /* [24] */ INVALID, INVALID, INVALID, INVALID, 2163 /* [28] */ INVALID, INVALID, INVALID, INVALID, 2164 /* [2C] */ INVALID, INVALID, INVALID, INVALID, 2165 2166 /* [30] */ INVALID, INVALID, INVALID, INVALID, 2167 /* [34] */ INVALID, INVALID, INVALID, INVALID, 2168 /* [38] */ INVALID, INVALID, INVALID, INVALID, 2169 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 2170 2171 /* [40] */ TNSZ("dpps",XMMP_66r,16),TNSZ("dppd",XMMP_66r,16),TNSZ("mpsadbw",XMMP_66r,16),INVALID, 2172 /* [44] */ TNSZ("pclmulqdq",XMMP_66r,16),INVALID, INVALID, INVALID, 2173 /* [48] */ INVALID, INVALID, INVALID, INVALID, 2174 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 2175 2176 /* [50] */ INVALID, INVALID, INVALID, INVALID, 2177 /* [54] */ INVALID, INVALID, INVALID, INVALID, 2178 /* [58] */ INVALID, INVALID, INVALID, INVALID, 2179 /* [5C] */ INVALID, INVALID, INVALID, INVALID, 2180 2181 /* [60] */ TNSZ("pcmpestrm",XMMP_66r,16),TNSZ("pcmpestri",XMMP_66r,16),TNSZ("pcmpistrm",XMMP_66r,16),TNSZ("pcmpistri",XMMP_66r,16), 2182 /* [64] */ INVALID, INVALID, INVALID, INVALID, 2183 /* [68] */ INVALID, INVALID, INVALID, INVALID, 2184 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 2185 2186 /* [70] */ INVALID, INVALID, INVALID, INVALID, 2187 /* [74] */ INVALID, INVALID, INVALID, INVALID, 2188 /* [78] */ INVALID, INVALID, INVALID, INVALID, 2189 /* [7C] */ INVALID, INVALID, INVALID, INVALID, 2190 2191 /* [80] */ INVALID, INVALID, INVALID, INVALID, 2192 /* [84] */ INVALID, INVALID, INVALID, INVALID, 2193 /* [88] */ INVALID, INVALID, INVALID, INVALID, 2194 /* [8C] */ INVALID, INVALID, INVALID, INVALID, 2195 2196 /* [90] */ INVALID, INVALID, INVALID, INVALID, 2197 /* [94] */ INVALID, INVALID, INVALID, INVALID, 2198 /* [98] */ INVALID, INVALID, INVALID, INVALID, 2199 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 2200 2201 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 2202 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 2203 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 2204 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 2205 2206 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 2207 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 2208 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 2209 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 2210 2211 /* [C0] */ INVALID, INVALID, INVALID, INVALID, 2212 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 2213 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 2214 /* [CC] */ TNSZ("sha1rnds4",XMMP,16),INVALID, TNS("gf2p8affineqb",XMMP_66r),TNS("gf2p8affineinvqb",XMMP_66r), 2215 2216 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 2217 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 2218 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 2219 /* [DC] */ INVALID, INVALID, INVALID, TNSZ("aeskeygenassist",XMMP_66r,16), 2220 2221 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 2222 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 2223 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 2224 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 2225 2226 /* [F0] */ INVALID, INVALID, INVALID, INVALID, 2227 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 2228 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 2229 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 2230 }; 2231 2232 const instable_t dis_opAVX660F3A[256] = { 2233 /* [00] */ TNSZ("vpermq",VEX_MXI,16),TNSZ("vpermpd",VEX_MXI,16),TNSZ("vpblendd",VEX_RMRX,16),INVALID, 2234 /* [04] */ TNSZ("vpermilps",VEX_MXI,8),TNSZ("vpermilpd",VEX_MXI,16),TNSZ("vperm2f128",VEX_RMRX,16),INVALID, 2235 /* [08] */ TNSZ("vroundps",VEX_MXI,16),TNSZ("vroundpd",VEX_MXI,16),TNSZ("vroundss",VEX_RMRX,16),TNSZ("vroundsd",VEX_RMRX,16), 2236 /* [0C] */ TNSZ("vblendps",VEX_RMRX,16),TNSZ("vblendpd",VEX_RMRX,16),TNSZ("vpblendw",VEX_RMRX,16),TNSZ("vpalignr",VEX_RMRX,16), 2237 2238 /* [10] */ INVALID, INVALID, INVALID, INVALID, 2239 /* [14] */ TNSZ("vpextrb",VEX_RRi,8),TNSZ("vpextrw",VEX_RRi,16),TNSZ("vpextrd",VEX_RRi,16),TNSZ("vextractps",VEX_RM,16), 2240 /* [18] */ TNSZ("vinsertf128",VEX_RMRX,16),TNSZ("vextractf128",VEX_RX,16),INVALID, INVALID, 2241 /* [1C] */ INVALID, TNSZ("vcvtps2ph",VEX_RX,16), INVALID, INVALID, 2242 2243 /* [20] */ TNSZ("vpinsrb",VEX_RMRX,8),TNSZ("vinsertps",VEX_RMRX,16),TNSZ("vpinsrd",VEX_RMRX,16),INVALID, 2244 /* [24] */ INVALID, INVALID, INVALID, INVALID, 2245 /* [28] */ INVALID, INVALID, INVALID, INVALID, 2246 /* [2C] */ INVALID, INVALID, INVALID, INVALID, 2247 2248 /* [30] */ TSvo("kshiftr",VEX_MXI), TSvo("kshiftr",VEX_MXI), TSvo("kshiftl",VEX_MXI), TSvo("kshiftl",VEX_MXI), 2249 /* [34] */ INVALID, INVALID, INVALID, INVALID, 2250 /* [38] */ TNSZ("vinserti128",VEX_RMRX,16),TNSZ("vextracti128",VEX_RIM,16),INVALID, INVALID, 2251 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 2252 2253 /* [40] */ TNSZ("vdpps",VEX_RMRX,16),TNSZ("vdppd",VEX_RMRX,16),TNSZ("vmpsadbw",VEX_RMRX,16),INVALID, 2254 /* [44] */ TNSZ("vpclmulqdq",VEX_RMRX,16),INVALID, TNSZ("vperm2i128",VEX_RMRX,16),INVALID, 2255 /* [48] */ INVALID, INVALID, TNSZ("vblendvps",VEX_RMRX,8), TNSZ("vblendvpd",VEX_RMRX,16), 2256 /* [4C] */ TNSZ("vpblendvb",VEX_RMRX,16),INVALID, INVALID, INVALID, 2257 2258 /* [50] */ INVALID, INVALID, INVALID, INVALID, 2259 /* [54] */ INVALID, INVALID, INVALID, INVALID, 2260 /* [58] */ INVALID, INVALID, INVALID, INVALID, 2261 /* [5C] */ INVALID, INVALID, INVALID, INVALID, 2262 2263 /* [60] */ TNSZ("vpcmpestrm",VEX_MXI,16),TNSZ("vpcmpestri",VEX_MXI,16),TNSZ("vpcmpistrm",VEX_MXI,16),TNSZ("vpcmpistri",VEX_MXI,16), 2264 /* [64] */ INVALID, INVALID, INVALID, INVALID, 2265 /* [68] */ INVALID, INVALID, INVALID, INVALID, 2266 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 2267 2268 /* [70] */ INVALID, INVALID, INVALID, INVALID, 2269 /* [74] */ INVALID, INVALID, INVALID, INVALID, 2270 /* [78] */ INVALID, INVALID, INVALID, INVALID, 2271 /* [7C] */ INVALID, INVALID, INVALID, INVALID, 2272 2273 /* [80] */ INVALID, INVALID, INVALID, INVALID, 2274 /* [84] */ INVALID, INVALID, INVALID, INVALID, 2275 /* [88] */ INVALID, INVALID, INVALID, INVALID, 2276 /* [8C] */ INVALID, INVALID, INVALID, INVALID, 2277 2278 /* [90] */ INVALID, INVALID, INVALID, INVALID, 2279 /* [94] */ INVALID, INVALID, INVALID, INVALID, 2280 /* [98] */ INVALID, INVALID, INVALID, INVALID, 2281 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 2282 2283 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 2284 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 2285 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 2286 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 2287 2288 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 2289 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 2290 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 2291 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 2292 2293 /* [C0] */ INVALID, INVALID, INVALID, INVALID, 2294 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 2295 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 2296 /* [CC] */ INVALID, INVALID, TNS("vgf2p8affineqb",VEX_RMRX),TNS("vgf2p8affineinvqb",VEX_RMRX), 2297 2298 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 2299 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 2300 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 2301 /* [DC] */ INVALID, INVALID, INVALID, TNSZ("vaeskeygenassist",VEX_MXI,16), 2302 2303 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 2304 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 2305 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 2306 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 2307 2308 /* [F0] */ INVALID, INVALID, INVALID, INVALID, 2309 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 2310 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 2311 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 2312 }; 2313 2314 /* 2315 * Decode table for 0x0F0D which uses the first byte of the mod_rm to 2316 * indicate a sub-code. 2317 */ 2318 const instable_t dis_op0F0D[8] = { 2319 /* [00] */ INVALID, TNS("prefetchw",PREF), TNS("prefetchwt1",PREF),INVALID, 2320 /* [04] */ INVALID, INVALID, INVALID, INVALID, 2321 }; 2322 2323 /* 2324 * Decode table for 0x0F opcodes 2325 */ 2326 2327 const instable_t dis_op0F[16][16] = { 2328 { 2329 /* [00] */ IND(dis_op0F00), IND(dis_op0F01), TNS("lar",MR), TNS("lsl",MR), 2330 /* [04] */ INVALID, TNS("syscall",NORM), TNS("clts",NORM), TNS("sysret",NORM), 2331 /* [08] */ TNS("invd",NORM), TNS("wbinvd",NORM), INVALID, TNS("ud2",NORM), 2332 /* [0C] */ INVALID, IND(dis_op0F0D), INVALID, INVALID, 2333 }, { 2334 /* [10] */ TNSZ("movups",XMMO,16), TNSZ("movups",XMMOS,16),TNSZ("movlps",XMMO,8), TNSZ("movlps",XMMOS,8), 2335 /* [14] */ TNSZ("unpcklps",XMMO,16),TNSZ("unpckhps",XMMO,16),TNSZ("movhps",XMMOM,8),TNSZ("movhps",XMMOMS,8), 2336 /* [18] */ IND(dis_op0F18), INVALID, INVALID, INVALID, 2337 /* [1C] */ INVALID, INVALID, INVALID, TS("nop",Mw), 2338 }, { 2339 /* [20] */ TSy("mov",SREG), TSy("mov",SREG), TSy("mov",SREG), TSy("mov",SREG), 2340 /* [24] */ TSx("mov",SREG), INVALID, TSx("mov",SREG), INVALID, 2341 /* [28] */ TNSZ("movaps",XMMO,16), TNSZ("movaps",XMMOS,16),TNSZ("cvtpi2ps",XMMOMX,8),TNSZ("movntps",XMMOS,16), 2342 /* [2C] */ TNSZ("cvttps2pi",XMMOXMM,8),TNSZ("cvtps2pi",XMMOXMM,8),TNSZ("ucomiss",XMMO,4),TNSZ("comiss",XMMO,4), 2343 }, { 2344 /* [30] */ TNS("wrmsr",NORM), TNS("rdtsc",NORM), TNS("rdmsr",NORM), TNS("rdpmc",NORM), 2345 /* [34] */ TNS("sysenter",NORM), TNS("sysexit",NORM), INVALID, INVALID, 2346 /* [38] */ INVALID, INVALID, INVALID, INVALID, 2347 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 2348 }, { 2349 /* [40] */ TS("cmovx.o",MR), TS("cmovx.no",MR), TS("cmovx.b",MR), TS("cmovx.ae",MR), 2350 /* [44] */ TS("cmovx.e",MR), TS("cmovx.ne",MR), TS("cmovx.be",MR), TS("cmovx.a",MR), 2351 /* [48] */ TS("cmovx.s",MR), TS("cmovx.ns",MR), TS("cmovx.pe",MR), TS("cmovx.po",MR), 2352 /* [4C] */ TS("cmovx.l",MR), TS("cmovx.ge",MR), TS("cmovx.le",MR), TS("cmovx.g",MR), 2353 }, { 2354 /* [50] */ TNS("movmskps",XMMOX3), TNSZ("sqrtps",XMMO,16), TNSZ("rsqrtps",XMMO,16),TNSZ("rcpps",XMMO,16), 2355 /* [54] */ TNSZ("andps",XMMO,16), TNSZ("andnps",XMMO,16), TNSZ("orps",XMMO,16), TNSZ("xorps",XMMO,16), 2356 /* [58] */ TNSZ("addps",XMMO,16), TNSZ("mulps",XMMO,16), TNSZ("cvtps2pd",XMMO,8),TNSZ("cvtdq2ps",XMMO,16), 2357 /* [5C] */ TNSZ("subps",XMMO,16), TNSZ("minps",XMMO,16), TNSZ("divps",XMMO,16), TNSZ("maxps",XMMO,16), 2358 }, { 2359 /* [60] */ TNSZ("punpcklbw",MMO,4),TNSZ("punpcklwd",MMO,4),TNSZ("punpckldq",MMO,4),TNSZ("packsswb",MMO,8), 2360 /* [64] */ TNSZ("pcmpgtb",MMO,8), TNSZ("pcmpgtw",MMO,8), TNSZ("pcmpgtd",MMO,8), TNSZ("packuswb",MMO,8), 2361 /* [68] */ TNSZ("punpckhbw",MMO,8),TNSZ("punpckhwd",MMO,8),TNSZ("punpckhdq",MMO,8),TNSZ("packssdw",MMO,8), 2362 /* [6C] */ TNSZ("INVALID",MMO,0), TNSZ("INVALID",MMO,0), TNSZ("movd",MMO,4), TNSZ("movq",MMO,8), 2363 }, { 2364 /* [70] */ TNSZ("pshufw",MMOPM,8), TNS("psrXXX",MR), TNS("psrXXX",MR), TNS("psrXXX",MR), 2365 /* [74] */ TNSZ("pcmpeqb",MMO,8), TNSZ("pcmpeqw",MMO,8), TNSZ("pcmpeqd",MMO,8), TNS("emms",NORM), 2366 /* [78] */ TNSy("vmread",RM), TNSy("vmwrite",MR), INVALID, INVALID, 2367 /* [7C] */ INVALID, INVALID, TNSZ("movd",MMOS,4), TNSZ("movq",MMOS,8), 2368 }, { 2369 /* [80] */ TNS("jo",D), TNS("jno",D), TNS("jb",D), TNS("jae",D), 2370 /* [84] */ TNS("je",D), TNS("jne",D), TNS("jbe",D), TNS("ja",D), 2371 /* [88] */ TNS("js",D), TNS("jns",D), TNS("jp",D), TNS("jnp",D), 2372 /* [8C] */ TNS("jl",D), TNS("jge",D), TNS("jle",D), TNS("jg",D), 2373 }, { 2374 /* [90] */ TNS("seto",Mb), TNS("setno",Mb), TNS("setb",Mb), TNS("setae",Mb), 2375 /* [94] */ TNS("sete",Mb), TNS("setne",Mb), TNS("setbe",Mb), TNS("seta",Mb), 2376 /* [98] */ TNS("sets",Mb), TNS("setns",Mb), TNS("setp",Mb), TNS("setnp",Mb), 2377 /* [9C] */ TNS("setl",Mb), TNS("setge",Mb), TNS("setle",Mb), TNS("setg",Mb), 2378 }, { 2379 /* [A0] */ TSp("push",LSEG), TSp("pop",LSEG), TNS("cpuid",NORM), TS("bt",RMw), 2380 /* [A4] */ TS("shld",DSHIFT), TS("shld",DSHIFTcl), INVALID, INVALID, 2381 /* [A8] */ TSp("push",LSEG), TSp("pop",LSEG), TNS("rsm",NORM), TS("bts",RMw), 2382 /* [AC] */ TS("shrd",DSHIFT), TS("shrd",DSHIFTcl), IND(dis_op0FAE), TS("imul",MRw), 2383 }, { 2384 /* [B0] */ TNS("cmpxchgb",RMw), TS("cmpxchg",RMw), TS("lss",MR), TS("btr",RMw), 2385 /* [B4] */ TS("lfs",MR), TS("lgs",MR), TS("movzb",MOVZ), TNS("movzwl",MOVZ), 2386 /* [B8] */ TNS("INVALID",MRw), INVALID, IND(dis_op0FBA), TS("btc",RMw), 2387 /* [BC] */ TS("bsf",MRw), TS("bsr",MRw), TS("movsb",MOVZ), TNS("movswl",MOVZ), 2388 }, { 2389 /* [C0] */ TNS("xaddb",XADDB), TS("xadd",RMw), TNSZ("cmpps",XMMOPM,16),TNS("movnti",RM), 2390 /* [C4] */ TNSZ("pinsrw",MMOPRM,2),TNS("pextrw",MMO3P), TNSZ("shufps",XMMOPM,16),IND(dis_op0FC7), 2391 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 2392 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 2393 }, { 2394 /* [D0] */ INVALID, TNSZ("psrlw",MMO,8), TNSZ("psrld",MMO,8), TNSZ("psrlq",MMO,8), 2395 /* [D4] */ TNSZ("paddq",MMO,8), TNSZ("pmullw",MMO,8), TNSZ("INVALID",MMO,0), TNS("pmovmskb",MMOM3), 2396 /* [D8] */ TNSZ("psubusb",MMO,8), TNSZ("psubusw",MMO,8), TNSZ("pminub",MMO,8), TNSZ("pand",MMO,8), 2397 /* [DC] */ TNSZ("paddusb",MMO,8), TNSZ("paddusw",MMO,8), TNSZ("pmaxub",MMO,8), TNSZ("pandn",MMO,8), 2398 }, { 2399 /* [E0] */ TNSZ("pavgb",MMO,8), TNSZ("psraw",MMO,8), TNSZ("psrad",MMO,8), TNSZ("pavgw",MMO,8), 2400 /* [E4] */ TNSZ("pmulhuw",MMO,8), TNSZ("pmulhw",MMO,8), TNS("INVALID",XMMO), TNSZ("movntq",MMOMS,8), 2401 /* [E8] */ TNSZ("psubsb",MMO,8), TNSZ("psubsw",MMO,8), TNSZ("pminsw",MMO,8), TNSZ("por",MMO,8), 2402 /* [EC] */ TNSZ("paddsb",MMO,8), TNSZ("paddsw",MMO,8), TNSZ("pmaxsw",MMO,8), TNSZ("pxor",MMO,8), 2403 }, { 2404 /* [F0] */ INVALID, TNSZ("psllw",MMO,8), TNSZ("pslld",MMO,8), TNSZ("psllq",MMO,8), 2405 /* [F4] */ TNSZ("pmuludq",MMO,8), TNSZ("pmaddwd",MMO,8), TNSZ("psadbw",MMO,8), TNSZ("maskmovq",MMOIMPL,8), 2406 /* [F8] */ TNSZ("psubb",MMO,8), TNSZ("psubw",MMO,8), TNSZ("psubd",MMO,8), TNSZ("psubq",MMO,8), 2407 /* [FC] */ TNSZ("paddb",MMO,8), TNSZ("paddw",MMO,8), TNSZ("paddd",MMO,8), INVALID, 2408 } }; 2409 2410 const instable_t dis_opAVX0F[16][16] = { 2411 { 2412 /* [00] */ INVALID, INVALID, INVALID, INVALID, 2413 /* [04] */ INVALID, INVALID, INVALID, INVALID, 2414 /* [08] */ INVALID, INVALID, INVALID, INVALID, 2415 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 2416 }, { 2417 /* [10] */ TNSZ("vmovups",VEX_MX,16), TNSZ("vmovups",VEX_RM,16),TNSZ("vmovlps",VEX_RMrX,8), TNSZ("vmovlps",VEX_RM,8), 2418 /* [14] */ TNSZ("vunpcklps",VEX_RMrX,16),TNSZ("vunpckhps",VEX_RMrX,16),TNSZ("vmovhps",VEX_RMrX,8),TNSZ("vmovhps",VEX_RM,8), 2419 /* [18] */ INVALID, INVALID, INVALID, INVALID, 2420 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 2421 }, { 2422 /* [20] */ INVALID, INVALID, INVALID, INVALID, 2423 /* [24] */ INVALID, INVALID, INVALID, INVALID, 2424 /* [28] */ TNSZ("vmovaps",VEX_MX,16), TNSZ("vmovaps",VEX_RX,16),INVALID, TNSZ("vmovntps",VEX_RM,16), 2425 /* [2C] */ INVALID, INVALID, TNSZ("vucomiss",VEX_MX,4),TNSZ("vcomiss",VEX_MX,4), 2426 }, { 2427 /* [30] */ INVALID, INVALID, INVALID, INVALID, 2428 /* [34] */ INVALID, INVALID, INVALID, INVALID, 2429 /* [38] */ INVALID, INVALID, INVALID, INVALID, 2430 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 2431 }, { 2432 /* [40] */ INVALID, TSvo("kand",VEX_RMX), TSvo("kandn",VEX_RMX), INVALID, 2433 /* [44] */ TSvo("knot",VEX_MX), TSvo("kor",VEX_RMX), TSvo("kxnor",VEX_RMX), TSvo("kxor",VEX_RMX), 2434 /* [48] */ INVALID, INVALID, TSvo("kadd",VEX_RMX), TSvo("kunpck",VEX_RMX), 2435 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 2436 }, { 2437 /* [50] */ TNS("vmovmskps",VEX_MR), TNSZ("vsqrtps",VEX_MX,16), TNSZ("vrsqrtps",VEX_MX,16),TNSZ("vrcpps",VEX_MX,16), 2438 /* [54] */ TNSZ("vandps",VEX_RMrX,16), TNSZ("vandnps",VEX_RMrX,16), TNSZ("vorps",VEX_RMrX,16), TNSZ("vxorps",VEX_RMrX,16), 2439 /* [58] */ TNSZ("vaddps",VEX_RMrX,16), TNSZ("vmulps",VEX_RMrX,16), TNSZ("vcvtps2pd",VEX_MX,8),TNSZ("vcvtdq2ps",VEX_MX,16), 2440 /* [5C] */ TNSZ("vsubps",VEX_RMrX,16), TNSZ("vminps",VEX_RMrX,16), TNSZ("vdivps",VEX_RMrX,16), TNSZ("vmaxps",VEX_RMrX,16), 2441 }, { 2442 /* [60] */ INVALID, INVALID, INVALID, INVALID, 2443 /* [64] */ INVALID, INVALID, INVALID, INVALID, 2444 /* [68] */ INVALID, INVALID, INVALID, INVALID, 2445 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 2446 }, { 2447 /* [70] */ INVALID, INVALID, INVALID, INVALID, 2448 /* [74] */ INVALID, INVALID, INVALID, TNS("vzeroupper", VEX_NONE), 2449 /* [78] */ INVALID, INVALID, INVALID, INVALID, 2450 /* [7C] */ INVALID, INVALID, INVALID, INVALID, 2451 }, { 2452 /* [80] */ INVALID, INVALID, INVALID, INVALID, 2453 /* [84] */ INVALID, INVALID, INVALID, INVALID, 2454 /* [88] */ INVALID, INVALID, INVALID, INVALID, 2455 /* [8C] */ INVALID, INVALID, INVALID, INVALID, 2456 }, { 2457 /* [90] */ TSvo("kmov",VEX_KRM), TSvo("kmov",VEX_KMR), TSvo("kmov",VEX_KRR), TSvo("kmov",VEX_MR), 2458 /* [94] */ INVALID, INVALID, INVALID, INVALID, 2459 /* [98] */ TSvo("kortest",VEX_MX), TSvo("ktest",VEX_MX), INVALID, INVALID, 2460 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 2461 }, { 2462 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 2463 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 2464 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 2465 /* [AC] */ INVALID, INVALID, TNSZ("vldmxcsr",VEX_MO,2), INVALID, 2466 }, { 2467 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 2468 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 2469 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 2470 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 2471 }, { 2472 /* [C0] */ INVALID, INVALID, TNSZ("vcmpps",VEX_RMRX,16),INVALID, 2473 /* [C4] */ INVALID, INVALID, TNSZ("vshufps",VEX_RMRX,16),INVALID, 2474 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 2475 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 2476 }, { 2477 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 2478 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 2479 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 2480 /* [DC] */ INVALID, INVALID, INVALID, INVALID, 2481 }, { 2482 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 2483 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 2484 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 2485 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 2486 }, { 2487 /* [F0] */ INVALID, INVALID, TNSZvr("andn",VEX_RMrX,5),TNSZvr("bls",BLS,5), 2488 /* [F4] */ INVALID, TNSZvr("bzhi",VEX_VRMrX,5),INVALID, TNSZvr("bextr",VEX_VRMrX,5), 2489 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 2490 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 2491 } }; 2492 2493 /* 2494 * Decode table for 0x80 opcodes 2495 */ 2496 2497 const instable_t dis_op80[8] = { 2498 2499 /* [0] */ TNS("addb",IMlw), TNS("orb",IMw), TNS("adcb",IMlw), TNS("sbbb",IMlw), 2500 /* [4] */ TNS("andb",IMw), TNS("subb",IMlw), TNS("xorb",IMw), TNS("cmpb",IMlw), 2501 }; 2502 2503 2504 /* 2505 * Decode table for 0x81 opcodes. 2506 */ 2507 2508 const instable_t dis_op81[8] = { 2509 2510 /* [0] */ TS("add",IMlw), TS("or",IMw), TS("adc",IMlw), TS("sbb",IMlw), 2511 /* [4] */ TS("and",IMw), TS("sub",IMlw), TS("xor",IMw), TS("cmp",IMlw), 2512 }; 2513 2514 2515 /* 2516 * Decode table for 0x82 opcodes. 2517 */ 2518 2519 const instable_t dis_op82[8] = { 2520 2521 /* [0] */ TNSx("addb",IMlw), TNSx("orb",IMlw), TNSx("adcb",IMlw), TNSx("sbbb",IMlw), 2522 /* [4] */ TNSx("andb",IMlw), TNSx("subb",IMlw), TNSx("xorb",IMlw), TNSx("cmpb",IMlw), 2523 }; 2524 /* 2525 * Decode table for 0x83 opcodes. 2526 */ 2527 2528 const instable_t dis_op83[8] = { 2529 2530 /* [0] */ TS("add",IMlw), TS("or",IMlw), TS("adc",IMlw), TS("sbb",IMlw), 2531 /* [4] */ TS("and",IMlw), TS("sub",IMlw), TS("xor",IMlw), TS("cmp",IMlw), 2532 }; 2533 2534 /* 2535 * Decode table for 0xC0 opcodes. 2536 */ 2537 2538 const instable_t dis_opC0[8] = { 2539 2540 /* [0] */ TNS("rolb",MvI), TNS("rorb",MvI), TNS("rclb",MvI), TNS("rcrb",MvI), 2541 /* [4] */ TNS("shlb",MvI), TNS("shrb",MvI), INVALID, TNS("sarb",MvI), 2542 }; 2543 2544 /* 2545 * Decode table for 0xD0 opcodes. 2546 */ 2547 2548 const instable_t dis_opD0[8] = { 2549 2550 /* [0] */ TNS("rolb",Mv), TNS("rorb",Mv), TNS("rclb",Mv), TNS("rcrb",Mv), 2551 /* [4] */ TNS("shlb",Mv), TNS("shrb",Mv), TNS("salb",Mv), TNS("sarb",Mv), 2552 }; 2553 2554 /* 2555 * Decode table for 0xC1 opcodes. 2556 * 186 instruction set 2557 */ 2558 2559 const instable_t dis_opC1[8] = { 2560 2561 /* [0] */ TS("rol",MvI), TS("ror",MvI), TS("rcl",MvI), TS("rcr",MvI), 2562 /* [4] */ TS("shl",MvI), TS("shr",MvI), TS("sal",MvI), TS("sar",MvI), 2563 }; 2564 2565 /* 2566 * Decode table for 0xD1 opcodes. 2567 */ 2568 2569 const instable_t dis_opD1[8] = { 2570 2571 /* [0] */ TS("rol",Mv), TS("ror",Mv), TS("rcl",Mv), TS("rcr",Mv), 2572 /* [4] */ TS("shl",Mv), TS("shr",Mv), TS("sal",Mv), TS("sar",Mv), 2573 }; 2574 2575 2576 /* 2577 * Decode table for 0xD2 opcodes. 2578 */ 2579 2580 const instable_t dis_opD2[8] = { 2581 2582 /* [0] */ TNS("rolb",Mv), TNS("rorb",Mv), TNS("rclb",Mv), TNS("rcrb",Mv), 2583 /* [4] */ TNS("shlb",Mv), TNS("shrb",Mv), TNS("salb",Mv), TNS("sarb",Mv), 2584 }; 2585 /* 2586 * Decode table for 0xD3 opcodes. 2587 */ 2588 2589 const instable_t dis_opD3[8] = { 2590 2591 /* [0] */ TS("rol",Mv), TS("ror",Mv), TS("rcl",Mv), TS("rcr",Mv), 2592 /* [4] */ TS("shl",Mv), TS("shr",Mv), TS("salb",Mv), TS("sar",Mv), 2593 }; 2594 2595 2596 /* 2597 * Decode table for 0xF6 opcodes. 2598 */ 2599 2600 const instable_t dis_opF6[8] = { 2601 2602 /* [0] */ TNS("testb",IMw), TNS("testb",IMw), TNS("notb",Mw), TNS("negb",Mw), 2603 /* [4] */ TNS("mulb",MA), TNS("imulb",MA), TNS("divb",MA), TNS("idivb",MA), 2604 }; 2605 2606 2607 /* 2608 * Decode table for 0xF7 opcodes. 2609 */ 2610 2611 const instable_t dis_opF7[8] = { 2612 2613 /* [0] */ TS("test",IMw), TS("test",IMw), TS("not",Mw), TS("neg",Mw), 2614 /* [4] */ TS("mul",MA), TS("imul",MA), TS("div",MA), TS("idiv",MA), 2615 }; 2616 2617 2618 /* 2619 * Decode table for 0xFE opcodes. 2620 */ 2621 2622 const instable_t dis_opFE[8] = { 2623 2624 /* [0] */ TNS("incb",Mw), TNS("decb",Mw), INVALID, INVALID, 2625 /* [4] */ INVALID, INVALID, INVALID, INVALID, 2626 }; 2627 /* 2628 * Decode table for 0xFF opcodes. 2629 */ 2630 2631 const instable_t dis_opFF[8] = { 2632 2633 /* [0] */ TS("inc",Mw), TS("dec",Mw), TNSyp("call",INM), TNS("lcall",INM), 2634 /* [4] */ TNSy("jmp",INM), TNS("ljmp",INM), TSp("push",M), INVALID, 2635 }; 2636 2637 /* for 287 instructions, which are a mess to decode */ 2638 2639 const instable_t dis_opFP1n2[8][8] = { 2640 { 2641 /* bit pattern: 1101 1xxx MODxx xR/M */ 2642 /* [0,0] */ TNS("fadds",M), TNS("fmuls",M), TNS("fcoms",M), TNS("fcomps",M), 2643 /* [0,4] */ TNS("fsubs",M), TNS("fsubrs",M), TNS("fdivs",M), TNS("fdivrs",M), 2644 }, { 2645 /* [1,0] */ TNS("flds",M), INVALID, TNS("fsts",M), TNS("fstps",M), 2646 /* [1,4] */ TNSZ("fldenv",M,28), TNSZ("fldcw",M,2), TNSZ("fnstenv",M,28), TNSZ("fnstcw",M,2), 2647 }, { 2648 /* [2,0] */ TNS("fiaddl",M), TNS("fimull",M), TNS("ficoml",M), TNS("ficompl",M), 2649 /* [2,4] */ TNS("fisubl",M), TNS("fisubrl",M), TNS("fidivl",M), TNS("fidivrl",M), 2650 }, { 2651 /* [3,0] */ TNS("fildl",M), TNSZ("tisttpl",M,4), TNS("fistl",M), TNS("fistpl",M), 2652 /* [3,4] */ INVALID, TNSZ("fldt",M,10), INVALID, TNSZ("fstpt",M,10), 2653 }, { 2654 /* [4,0] */ TNSZ("faddl",M,8), TNSZ("fmull",M,8), TNSZ("fcoml",M,8), TNSZ("fcompl",M,8), 2655 /* [4,1] */ TNSZ("fsubl",M,8), TNSZ("fsubrl",M,8), TNSZ("fdivl",M,8), TNSZ("fdivrl",M,8), 2656 }, { 2657 /* [5,0] */ TNSZ("fldl",M,8), TNSZ("fisttpll",M,8), TNSZ("fstl",M,8), TNSZ("fstpl",M,8), 2658 /* [5,4] */ TNSZ("frstor",M,108), INVALID, TNSZ("fnsave",M,108), TNSZ("fnstsw",M,2), 2659 }, { 2660 /* [6,0] */ TNSZ("fiadd",M,2), TNSZ("fimul",M,2), TNSZ("ficom",M,2), TNSZ("ficomp",M,2), 2661 /* [6,4] */ TNSZ("fisub",M,2), TNSZ("fisubr",M,2), TNSZ("fidiv",M,2), TNSZ("fidivr",M,2), 2662 }, { 2663 /* [7,0] */ TNSZ("fild",M,2), TNSZ("fisttp",M,2), TNSZ("fist",M,2), TNSZ("fistp",M,2), 2664 /* [7,4] */ TNSZ("fbld",M,10), TNSZ("fildll",M,8), TNSZ("fbstp",M,10), TNSZ("fistpll",M,8), 2665 } }; 2666 2667 const instable_t dis_opFP3[8][8] = { 2668 { 2669 /* bit pattern: 1101 1xxx 11xx xREG */ 2670 /* [0,0] */ TNS("fadd",FF), TNS("fmul",FF), TNS("fcom",F), TNS("fcomp",F), 2671 /* [0,4] */ TNS("fsub",FF), TNS("fsubr",FF), TNS("fdiv",FF), TNS("fdivr",FF), 2672 }, { 2673 /* [1,0] */ TNS("fld",F), TNS("fxch",F), TNS("fnop",NORM), TNS("fstp",F), 2674 /* [1,4] */ INVALID, INVALID, INVALID, INVALID, 2675 }, { 2676 /* [2,0] */ INVALID, INVALID, INVALID, INVALID, 2677 /* [2,4] */ INVALID, TNS("fucompp",NORM), INVALID, INVALID, 2678 }, { 2679 /* [3,0] */ INVALID, INVALID, INVALID, INVALID, 2680 /* [3,4] */ INVALID, INVALID, INVALID, INVALID, 2681 }, { 2682 /* [4,0] */ TNS("fadd",FF), TNS("fmul",FF), TNS("fcom",F), TNS("fcomp",F), 2683 /* [4,4] */ TNS("fsub",FF), TNS("fsubr",FF), TNS("fdiv",FF), TNS("fdivr",FF), 2684 }, { 2685 /* [5,0] */ TNS("ffree",F), TNS("fxch",F), TNS("fst",F), TNS("fstp",F), 2686 /* [5,4] */ TNS("fucom",F), TNS("fucomp",F), INVALID, INVALID, 2687 }, { 2688 /* [6,0] */ TNS("faddp",FF), TNS("fmulp",FF), TNS("fcomp",F), TNS("fcompp",NORM), 2689 /* [6,4] */ TNS("fsubp",FF), TNS("fsubrp",FF), TNS("fdivp",FF), TNS("fdivrp",FF), 2690 }, { 2691 /* [7,0] */ TNS("ffreep",F), TNS("fxch",F), TNS("fstp",F), TNS("fstp",F), 2692 /* [7,4] */ TNS("fnstsw",M), TNS("fucomip",FFC), TNS("fcomip",FFC), INVALID, 2693 } }; 2694 2695 const instable_t dis_opFP4[4][8] = { 2696 { 2697 /* bit pattern: 1101 1001 111x xxxx */ 2698 /* [0,0] */ TNS("fchs",NORM), TNS("fabs",NORM), INVALID, INVALID, 2699 /* [0,4] */ TNS("ftst",NORM), TNS("fxam",NORM), TNS("ftstp",NORM), INVALID, 2700 }, { 2701 /* [1,0] */ TNS("fld1",NORM), TNS("fldl2t",NORM), TNS("fldl2e",NORM), TNS("fldpi",NORM), 2702 /* [1,4] */ TNS("fldlg2",NORM), TNS("fldln2",NORM), TNS("fldz",NORM), INVALID, 2703 }, { 2704 /* [2,0] */ TNS("f2xm1",NORM), TNS("fyl2x",NORM), TNS("fptan",NORM), TNS("fpatan",NORM), 2705 /* [2,4] */ TNS("fxtract",NORM), TNS("fprem1",NORM), TNS("fdecstp",NORM), TNS("fincstp",NORM), 2706 }, { 2707 /* [3,0] */ TNS("fprem",NORM), TNS("fyl2xp1",NORM), TNS("fsqrt",NORM), TNS("fsincos",NORM), 2708 /* [3,4] */ TNS("frndint",NORM), TNS("fscale",NORM), TNS("fsin",NORM), TNS("fcos",NORM), 2709 } }; 2710 2711 const instable_t dis_opFP5[8] = { 2712 /* bit pattern: 1101 1011 111x xxxx */ 2713 /* [0] */ TNS("feni",NORM), TNS("fdisi",NORM), TNS("fnclex",NORM), TNS("fninit",NORM), 2714 /* [4] */ TNS("fsetpm",NORM), TNS("frstpm",NORM), INVALID, INVALID, 2715 }; 2716 2717 const instable_t dis_opFP6[8] = { 2718 /* bit pattern: 1101 1011 11yy yxxx */ 2719 /* [00] */ TNS("fcmov.nb",FF), TNS("fcmov.ne",FF), TNS("fcmov.nbe",FF), TNS("fcmov.nu",FF), 2720 /* [04] */ INVALID, TNS("fucomi",F), TNS("fcomi",F), INVALID, 2721 }; 2722 2723 const instable_t dis_opFP7[8] = { 2724 /* bit pattern: 1101 1010 11yy yxxx */ 2725 /* [00] */ TNS("fcmov.b",FF), TNS("fcmov.e",FF), TNS("fcmov.be",FF), TNS("fcmov.u",FF), 2726 /* [04] */ INVALID, INVALID, INVALID, INVALID, 2727 }; 2728 2729 /* 2730 * Main decode table for the op codes. The first two nibbles 2731 * will be used as an index into the table. If there is a 2732 * a need to further decode an instruction, the array to be 2733 * referenced is indicated with the other two entries being 2734 * empty. 2735 */ 2736 2737 const instable_t dis_distable[16][16] = { 2738 { 2739 /* [0,0] */ TNS("addb",RMw), TS("add",RMw), TNS("addb",MRw), TS("add",MRw), 2740 /* [0,4] */ TNS("addb",IA), TS("add",IA), TSx("push",SEG), TSx("pop",SEG), 2741 /* [0,8] */ TNS("orb",RMw), TS("or",RMw), TNS("orb",MRw), TS("or",MRw), 2742 /* [0,C] */ TNS("orb",IA), TS("or",IA), TSx("push",SEG), IND(dis_op0F), 2743 }, { 2744 /* [1,0] */ TNS("adcb",RMw), TS("adc",RMw), TNS("adcb",MRw), TS("adc",MRw), 2745 /* [1,4] */ TNS("adcb",IA), TS("adc",IA), TSx("push",SEG), TSx("pop",SEG), 2746 /* [1,8] */ TNS("sbbb",RMw), TS("sbb",RMw), TNS("sbbb",MRw), TS("sbb",MRw), 2747 /* [1,C] */ TNS("sbbb",IA), TS("sbb",IA), TSx("push",SEG), TSx("pop",SEG), 2748 }, { 2749 /* [2,0] */ TNS("andb",RMw), TS("and",RMw), TNS("andb",MRw), TS("and",MRw), 2750 /* [2,4] */ TNS("andb",IA), TS("and",IA), TNSx("%es:",OVERRIDE), TNSx("daa",NORM), 2751 /* [2,8] */ TNS("subb",RMw), TS("sub",RMw), TNS("subb",MRw), TS("sub",MRw), 2752 /* [2,C] */ TNS("subb",IA), TS("sub",IA), TNS("%cs:",OVERRIDE), TNSx("das",NORM), 2753 }, { 2754 /* [3,0] */ TNS("xorb",RMw), TS("xor",RMw), TNS("xorb",MRw), TS("xor",MRw), 2755 /* [3,4] */ TNS("xorb",IA), TS("xor",IA), TNSx("%ss:",OVERRIDE), TNSx("aaa",NORM), 2756 /* [3,8] */ TNS("cmpb",RMw), TS("cmp",RMw), TNS("cmpb",MRw), TS("cmp",MRw), 2757 /* [3,C] */ TNS("cmpb",IA), TS("cmp",IA), TNSx("%ds:",OVERRIDE), TNSx("aas",NORM), 2758 }, { 2759 /* [4,0] */ TSx("inc",R), TSx("inc",R), TSx("inc",R), TSx("inc",R), 2760 /* [4,4] */ TSx("inc",R), TSx("inc",R), TSx("inc",R), TSx("inc",R), 2761 /* [4,8] */ TSx("dec",R), TSx("dec",R), TSx("dec",R), TSx("dec",R), 2762 /* [4,C] */ TSx("dec",R), TSx("dec",R), TSx("dec",R), TSx("dec",R), 2763 }, { 2764 /* [5,0] */ TSp("push",R), TSp("push",R), TSp("push",R), TSp("push",R), 2765 /* [5,4] */ TSp("push",R), TSp("push",R), TSp("push",R), TSp("push",R), 2766 /* [5,8] */ TSp("pop",R), TSp("pop",R), TSp("pop",R), TSp("pop",R), 2767 /* [5,C] */ TSp("pop",R), TSp("pop",R), TSp("pop",R), TSp("pop",R), 2768 }, { 2769 /* [6,0] */ TSZx("pusha",IMPLMEM,28),TSZx("popa",IMPLMEM,28), TSx("bound",RM), TNS("arpl",RMw), 2770 /* [6,4] */ TNS("%fs:",OVERRIDE), TNS("%gs:",OVERRIDE), TNS("data16",DM), TNS("addr16",AM), 2771 /* [6,8] */ TSp("push",I), TS("imul",IMUL), TSp("push",Ib), TS("imul",IMUL), 2772 /* [6,C] */ TNSZ("insb",IMPLMEM,1), TSZ("ins",IMPLMEM,4), TNSZ("outsb",IMPLMEM,1),TSZ("outs",IMPLMEM,4), 2773 }, { 2774 /* [7,0] */ TNSy("jo",BD), TNSy("jno",BD), TNSy("jb",BD), TNSy("jae",BD), 2775 /* [7,4] */ TNSy("je",BD), TNSy("jne",BD), TNSy("jbe",BD), TNSy("ja",BD), 2776 /* [7,8] */ TNSy("js",BD), TNSy("jns",BD), TNSy("jp",BD), TNSy("jnp",BD), 2777 /* [7,C] */ TNSy("jl",BD), TNSy("jge",BD), TNSy("jle",BD), TNSy("jg",BD), 2778 }, { 2779 /* [8,0] */ IND(dis_op80), IND(dis_op81), INDx(dis_op82), IND(dis_op83), 2780 /* [8,4] */ TNS("testb",RMw), TS("test",RMw), TNS("xchgb",RMw), TS("xchg",RMw), 2781 /* [8,8] */ TNS("movb",RMw), TS("mov",RMw), TNS("movb",MRw), TS("mov",MRw), 2782 /* [8,C] */ TNS("movw",SM), TS("lea",MR), TNS("movw",MS), TSp("pop",M), 2783 }, { 2784 /* [9,0] */ TNS("nop",NORM), TS("xchg",RA), TS("xchg",RA), TS("xchg",RA), 2785 /* [9,4] */ TS("xchg",RA), TS("xchg",RA), TS("xchg",RA), TS("xchg",RA), 2786 /* [9,8] */ TNS("cXtX",CBW), TNS("cXtX",CWD), TNSx("lcall",SO), TNS("fwait",NORM), 2787 /* [9,C] */ TSZy("pushf",IMPLMEM,4),TSZy("popf",IMPLMEM,4), TNS("sahf",NORM), TNS("lahf",NORM), 2788 }, { 2789 /* [A,0] */ TNS("movb",OA), TS("mov",OA), TNS("movb",AO), TS("mov",AO), 2790 /* [A,4] */ TNSZ("movsb",SD,1), TS("movs",SD), TNSZ("cmpsb",SD,1), TS("cmps",SD), 2791 /* [A,8] */ TNS("testb",IA), TS("test",IA), TNS("stosb",AD), TS("stos",AD), 2792 /* [A,C] */ TNS("lodsb",SA), TS("lods",SA), TNS("scasb",AD), TS("scas",AD), 2793 }, { 2794 /* [B,0] */ TNS("movb",IR), TNS("movb",IR), TNS("movb",IR), TNS("movb",IR), 2795 /* [B,4] */ TNS("movb",IR), TNS("movb",IR), TNS("movb",IR), TNS("movb",IR), 2796 /* [B,8] */ TS("mov",IR), TS("mov",IR), TS("mov",IR), TS("mov",IR), 2797 /* [B,C] */ TS("mov",IR), TS("mov",IR), TS("mov",IR), TS("mov",IR), 2798 }, { 2799 /* [C,0] */ IND(dis_opC0), IND(dis_opC1), TNSyp("ret",RET), TNSyp("ret",NORM), 2800 /* [C,4] */ TNSx("les",MR), TNSx("lds",MR), TNS("movb",IMw), TS("mov",IMw), 2801 /* [C,8] */ TNSyp("enter",ENTER), TNSyp("leave",NORM), TNS("lret",RET), TNS("lret",NORM), 2802 /* [C,C] */ TNS("int",INT3), TNS("int",INTx), TNSx("into",NORM), TNS("iret",NORM), 2803 }, { 2804 /* [D,0] */ IND(dis_opD0), IND(dis_opD1), IND(dis_opD2), IND(dis_opD3), 2805 /* [D,4] */ TNSx("aam",U), TNSx("aad",U), TNSx("falc",NORM), TNSZ("xlat",IMPLMEM,1), 2806 2807 /* 287 instructions. Note that although the indirect field */ 2808 /* indicates opFP1n2 for further decoding, this is not necessarily */ 2809 /* the case since the opFP arrays are not partitioned according to key1 */ 2810 /* and key2. opFP1n2 is given only to indicate that we haven't */ 2811 /* finished decoding the instruction. */ 2812 /* [D,8] */ IND(dis_opFP1n2), IND(dis_opFP1n2), IND(dis_opFP1n2), IND(dis_opFP1n2), 2813 /* [D,C] */ IND(dis_opFP1n2), IND(dis_opFP1n2), IND(dis_opFP1n2), IND(dis_opFP1n2), 2814 }, { 2815 /* [E,0] */ TNSy("loopnz",BD), TNSy("loopz",BD), TNSy("loop",BD), TNSy("jcxz",BD), 2816 /* [E,4] */ TNS("inb",P), TS("in",P), TNS("outb",P), TS("out",P), 2817 /* [E,8] */ TNSyp("call",D), TNSy("jmp",D), TNSx("ljmp",SO), TNSy("jmp",BD), 2818 /* [E,C] */ TNS("inb",V), TS("in",V), TNS("outb",V), TS("out",V), 2819 }, { 2820 /* [F,0] */ TNS("lock",LOCK), TNS("icebp", NORM), TNS("repnz",PREFIX), TNS("repz",PREFIX), 2821 /* [F,4] */ TNS("hlt",NORM), TNS("cmc",NORM), IND(dis_opF6), IND(dis_opF7), 2822 /* [F,8] */ TNS("clc",NORM), TNS("stc",NORM), TNS("cli",NORM), TNS("sti",NORM), 2823 /* [F,C] */ TNS("cld",NORM), TNS("std",NORM), IND(dis_opFE), IND(dis_opFF), 2824 } }; 2825 2826 /* END CSTYLED */ 2827 2828 /* 2829 * common functions to decode and disassemble an x86 or amd64 instruction 2830 */ 2831 2832 /* 2833 * These are the individual fields of a REX prefix. Note that a REX 2834 * prefix with none of these set is still needed to: 2835 * - use the MOVSXD (sign extend 32 to 64 bits) instruction 2836 * - access the %sil, %dil, %bpl, %spl registers 2837 */ 2838 #define REX_W 0x08 /* 64 bit operand size when set */ 2839 #define REX_R 0x04 /* high order bit extension of ModRM reg field */ 2840 #define REX_X 0x02 /* high order bit extension of SIB index field */ 2841 #define REX_B 0x01 /* extends ModRM r_m, SIB base, or opcode reg */ 2842 2843 /* 2844 * These are the individual fields of a VEX/EVEX prefix. 2845 */ 2846 #define VEX_R 0x08 /* REX.R in 1's complement form */ 2847 #define VEX_X 0x04 /* REX.X in 1's complement form */ 2848 #define VEX_B 0x02 /* REX.B in 1's complement form */ 2849 2850 /* Additional EVEX prefix definitions */ 2851 #define EVEX_R 0x01 /* REX.R' in 1's complement form */ 2852 #define EVEX_OPREG_MASK 0x7 /* bit mask for selecting opmask register number */ 2853 #define EVEX_ZERO_MASK 0x80 /* bit mask for selecting zeroing */ 2854 2855 /* Vector Length, 0: scalar or 128-bit vector, 1: 256-bit vector */ 2856 #define VEX_L 0x04 2857 /* Vector Length, 0: scalar or 128-bit vector, 1: 256-bit vector, 2: 512-bit */ 2858 #define EVEX_L 0x06 /* bit mask for EVEX.L'L vector length/RC */ 2859 #define VEX_W 0x08 /* opcode specific, use like REX.W */ 2860 #define VEX_m 0x1F /* VEX m-mmmm field */ 2861 #define EVEX_m 0x3 /* EVEX mm field */ 2862 #define VEX_v 0x78 /* VEX/EVEX register specifier */ 2863 #define VEX_p 0x03 /* VEX pp field, opcode extension */ 2864 2865 /* VEX m-mmmm field, only used by three bytes prefix */ 2866 #define VEX_m_0F 0x01 /* implied 0F leading opcode byte */ 2867 #define VEX_m_0F38 0x02 /* implied 0F 38 leading opcode byte */ 2868 #define VEX_m_0F3A 0x03 /* implied 0F 3A leading opcode byte */ 2869 2870 /* VEX pp field, providing equivalent functionality of a SIMD prefix */ 2871 #define VEX_p_66 0x01 2872 #define VEX_p_F3 0x02 2873 #define VEX_p_F2 0x03 2874 2875 /* 2876 * Even in 64 bit mode, usually only 4 byte immediate operands are supported. 2877 */ 2878 static int isize[] = {1, 2, 4, 4}; 2879 static int isize64[] = {1, 2, 4, 8}; 2880 2881 /* 2882 * Just a bunch of useful macros. 2883 */ 2884 #define WBIT(x) (x & 0x1) /* to get w bit */ 2885 #define REGNO(x) (x & 0x7) /* to get 3 bit register */ 2886 #define VBIT(x) ((x)>>1 & 0x1) /* to get 'v' bit */ 2887 #define OPSIZE(osize, wbit) ((wbit) ? isize[osize] : 1) 2888 #define OPSIZE64(osize, wbit) ((wbit) ? isize64[osize] : 1) 2889 2890 #define REG_ONLY 3 /* mode to indicate a register operand (not memory) */ 2891 2892 #define BYTE_OPND 0 /* w-bit value indicating byte register */ 2893 #define LONG_OPND 1 /* w-bit value indicating opnd_size register */ 2894 #define MM_OPND 2 /* "value" used to indicate a mmx reg */ 2895 #define XMM_OPND 3 /* "value" used to indicate a xmm reg */ 2896 #define SEG_OPND 4 /* "value" used to indicate a segment reg */ 2897 #define CONTROL_OPND 5 /* "value" used to indicate a control reg */ 2898 #define DEBUG_OPND 6 /* "value" used to indicate a debug reg */ 2899 #define TEST_OPND 7 /* "value" used to indicate a test reg */ 2900 #define WORD_OPND 8 /* w-bit value indicating word size reg */ 2901 #define YMM_OPND 9 /* "value" used to indicate a ymm reg */ 2902 #define KOPMASK_OPND 10 /* "value" used to indicate an opmask reg */ 2903 #define ZMM_OPND 11 /* "value" used to indicate a zmm reg */ 2904 2905 /* 2906 * The AVX2 gather instructions are a bit of a mess. While there's a pattern, 2907 * there's not really a consistent scheme that we can use to know what the mode 2908 * is supposed to be for a given type. Various instructions, like VPGATHERDD, 2909 * always match the value of VEX_L. Other instructions like VPGATHERDQ, have 2910 * some registers match VEX_L, but the VSIB is always XMM. 2911 * 2912 * The simplest way to deal with this is to just define a table based on the 2913 * instruction opcodes, which are 0x90-0x93, so we subtract 0x90 to index into 2914 * them. 2915 * 2916 * We further have to subdivide this based on the value of VEX_W and the value 2917 * of VEX_L. The array is constructed to be indexed as: 2918 * [opcode - 0x90][VEX_W][VEX_L]. 2919 */ 2920 /* w = 0, 0x90 */ 2921 typedef struct dis_gather_regs { 2922 uint_t dgr_arg0; /* src reg */ 2923 uint_t dgr_arg1; /* vsib reg */ 2924 uint_t dgr_arg2; /* dst reg */ 2925 char *dgr_suffix; /* suffix to append */ 2926 } dis_gather_regs_t; 2927 2928 static dis_gather_regs_t dis_vgather[4][2][2] = { 2929 { 2930 /* op 0x90, W.0 */ 2931 { 2932 { XMM_OPND, XMM_OPND, XMM_OPND, "d" }, 2933 { YMM_OPND, YMM_OPND, YMM_OPND, "d" } 2934 }, 2935 /* op 0x90, W.1 */ 2936 { 2937 { XMM_OPND, XMM_OPND, XMM_OPND, "q" }, 2938 { YMM_OPND, XMM_OPND, YMM_OPND, "q" } 2939 } 2940 }, 2941 { 2942 /* op 0x91, W.0 */ 2943 { 2944 { XMM_OPND, XMM_OPND, XMM_OPND, "d" }, 2945 { XMM_OPND, YMM_OPND, XMM_OPND, "d" }, 2946 }, 2947 /* op 0x91, W.1 */ 2948 { 2949 { XMM_OPND, XMM_OPND, XMM_OPND, "q" }, 2950 { YMM_OPND, YMM_OPND, YMM_OPND, "q" }, 2951 } 2952 }, 2953 { 2954 /* op 0x92, W.0 */ 2955 { 2956 { XMM_OPND, XMM_OPND, XMM_OPND, "s" }, 2957 { YMM_OPND, YMM_OPND, YMM_OPND, "s" } 2958 }, 2959 /* op 0x92, W.1 */ 2960 { 2961 { XMM_OPND, XMM_OPND, XMM_OPND, "d" }, 2962 { YMM_OPND, XMM_OPND, YMM_OPND, "d" } 2963 } 2964 }, 2965 { 2966 /* op 0x93, W.0 */ 2967 { 2968 { XMM_OPND, XMM_OPND, XMM_OPND, "s" }, 2969 { XMM_OPND, YMM_OPND, XMM_OPND, "s" } 2970 }, 2971 /* op 0x93, W.1 */ 2972 { 2973 { XMM_OPND, XMM_OPND, XMM_OPND, "d" }, 2974 { YMM_OPND, YMM_OPND, YMM_OPND, "d" } 2975 } 2976 } 2977 }; 2978 2979 /* 2980 * Get the next byte and separate the op code into the high and low nibbles. 2981 */ 2982 static int 2983 dtrace_get_opcode(dis86_t *x, uint_t *high, uint_t *low) 2984 { 2985 int byte; 2986 2987 /* 2988 * x86 instructions have a maximum length of 15 bytes. Bail out if 2989 * we try to read more. 2990 */ 2991 if (x->d86_len >= 15) 2992 return (x->d86_error = 1); 2993 2994 if (x->d86_error) 2995 return (1); 2996 byte = x->d86_get_byte(x->d86_data); 2997 if (byte < 0) 2998 return (x->d86_error = 1); 2999 x->d86_bytes[x->d86_len++] = byte; 3000 *low = byte & 0xf; /* ----xxxx low 4 bits */ 3001 *high = byte >> 4 & 0xf; /* xxxx---- bits 7 to 4 */ 3002 return (0); 3003 } 3004 3005 /* 3006 * Get and decode an SIB (scaled index base) byte 3007 */ 3008 static void 3009 dtrace_get_SIB(dis86_t *x, uint_t *ss, uint_t *index, uint_t *base) 3010 { 3011 int byte; 3012 3013 if (x->d86_error) 3014 return; 3015 3016 byte = x->d86_get_byte(x->d86_data); 3017 if (byte < 0) { 3018 x->d86_error = 1; 3019 return; 3020 } 3021 x->d86_bytes[x->d86_len++] = byte; 3022 3023 *base = byte & 0x7; 3024 *index = (byte >> 3) & 0x7; 3025 *ss = (byte >> 6) & 0x3; 3026 } 3027 3028 /* 3029 * Get the byte following the op code and separate it into the 3030 * mode, register, and r/m fields. 3031 */ 3032 static void 3033 dtrace_get_modrm(dis86_t *x, uint_t *mode, uint_t *reg, uint_t *r_m) 3034 { 3035 if (x->d86_got_modrm == 0) { 3036 if (x->d86_rmindex == -1) 3037 x->d86_rmindex = x->d86_len; 3038 dtrace_get_SIB(x, mode, reg, r_m); 3039 x->d86_got_modrm = 1; 3040 } 3041 } 3042 3043 /* 3044 * Adjust register selection based on any REX prefix bits present. 3045 */ 3046 /*ARGSUSED*/ 3047 static void 3048 dtrace_rex_adjust(uint_t rex_prefix, uint_t mode, uint_t *reg, uint_t *r_m) 3049 { 3050 if (reg != NULL && r_m == NULL) { 3051 if (rex_prefix & REX_B) 3052 *reg += 8; 3053 } else { 3054 if (reg != NULL && (REX_R & rex_prefix) != 0) 3055 *reg += 8; 3056 if (r_m != NULL && (REX_B & rex_prefix) != 0) 3057 *r_m += 8; 3058 } 3059 } 3060 3061 /* 3062 * Adjust register selection based on any VEX prefix bits present. 3063 * Notes: VEX.R, VEX.X and VEX.B use the inverted form compared with REX prefix 3064 */ 3065 /*ARGSUSED*/ 3066 static void 3067 dtrace_vex_adjust(uint_t vex_byte1, uint_t mode, uint_t *reg, uint_t *r_m) 3068 { 3069 if (reg != NULL && r_m == NULL) { 3070 if (!(vex_byte1 & VEX_B)) 3071 *reg += 8; 3072 } else { 3073 if (reg != NULL && ((VEX_R & vex_byte1) == 0)) 3074 *reg += 8; 3075 if (r_m != NULL && ((VEX_B & vex_byte1) == 0)) 3076 *r_m += 8; 3077 } 3078 } 3079 3080 /* 3081 * Adjust the instruction mnemonic with the appropriate suffix. 3082 */ 3083 /* ARGSUSED */ 3084 static void 3085 dtrace_evex_mnem_adjust(dis86_t *x, const instable_t *dp, uint_t vex_W, 3086 uint_t evex_byte2) 3087 { 3088 #ifdef DIS_TEXT 3089 if (dp == &dis_opEVEX660F[0x7f] || /* vmovdqa */ 3090 dp == &dis_opEVEX660F[0x6f]) { 3091 (void) strlcat(x->d86_mnem, vex_W != 0 ? "64" : "32", 3092 OPLEN); 3093 } 3094 3095 if (dp == &dis_opEVEXF20F[0x7f] || /* vmovdqu */ 3096 dp == &dis_opEVEXF20F[0x6f] || 3097 dp == &dis_opEVEXF30F[0x7f] || 3098 dp == &dis_opEVEXF30F[0x6f]) { 3099 switch (evex_byte2 & 0x81) { 3100 case 0x0: 3101 (void) strlcat(x->d86_mnem, "32", OPLEN); 3102 break; 3103 case 0x1: 3104 (void) strlcat(x->d86_mnem, "8", OPLEN); 3105 break; 3106 case 0x80: 3107 (void) strlcat(x->d86_mnem, "64", OPLEN); 3108 break; 3109 case 0x81: 3110 (void) strlcat(x->d86_mnem, "16", OPLEN); 3111 break; 3112 } 3113 } 3114 3115 if (dp->it_avxsuf == AVS5Q) { 3116 (void) strlcat(x->d86_mnem, vex_W != 0 ? "q" : "d", 3117 OPLEN); 3118 } 3119 #endif 3120 } 3121 3122 /* 3123 * The following three functions adjust the register selection based on any 3124 * EVEX prefix bits present. See Intel 64 and IA-32 Architectures Software 3125 * Developer’s Manual Volume 2 (IASDv2), section 2.6.1 Table 2-30 and 3126 * section 2.6.2 Table 2-31. 3127 */ 3128 static void 3129 dtrace_evex_adjust_reg(uint_t evex_byte1, uint_t *reg) 3130 { 3131 if (reg != NULL) { 3132 if ((VEX_R & evex_byte1) == 0) { 3133 *reg += 8; 3134 } 3135 if ((EVEX_R & evex_byte1) == 0) { 3136 *reg += 16; 3137 } 3138 } 3139 } 3140 3141 static void 3142 dtrace_evex_adjust_rm(uint_t evex_byte1, uint_t *r_m) 3143 { 3144 if (r_m != NULL) { 3145 if ((VEX_B & evex_byte1) == 0) { 3146 *r_m += 8; 3147 } 3148 if ((VEX_X & evex_byte1) == 0) { 3149 *r_m += 16; 3150 } 3151 } 3152 } 3153 3154 /* 3155 * Use evex_L to set wbit. See IASDv2 Section 2.6.10 and Table 2-36. 3156 */ 3157 static void 3158 dtrace_evex_adjust_reg_name(uint_t evex_L, uint_t *wbitp) 3159 { 3160 switch (evex_L) { 3161 case 0x0: 3162 *wbitp = XMM_OPND; 3163 break; 3164 case 0x1: 3165 *wbitp = YMM_OPND; 3166 break; 3167 case 0x2: 3168 *wbitp = ZMM_OPND; 3169 break; 3170 } 3171 } 3172 3173 /* 3174 * Adjust operand value for disp8*N immediate. See IASDv2 Section 2.6.5. 3175 * This currently only handles a subset of the possibilities. 3176 */ 3177 static void 3178 dtrace_evex_adjust_disp8_n(dis86_t *x, int opindex, uint_t L, uint_t modrm) 3179 { 3180 d86opnd_t *opnd = &x->d86_opnd[opindex]; 3181 3182 if (x->d86_error) 3183 return; 3184 3185 /* Check disp8 bit in the ModR/M byte */ 3186 if ((modrm & 0x80) == 0x80) 3187 return; 3188 3189 /* use evex_L to adjust the value */ 3190 switch (L) { 3191 case 0x0: 3192 opnd->d86_value *= 16; 3193 break; 3194 case 0x1: 3195 opnd->d86_value *= 32; 3196 break; 3197 case 0x2: 3198 opnd->d86_value *= 64; 3199 break; 3200 } 3201 } 3202 3203 /* 3204 * Adjust target for opmask and zeroing. See IASDv2 Section 2.6.1 Table 2-30. 3205 */ 3206 /* ARGSUSED */ 3207 static void 3208 dtrace_evex_adjust_z_opmask(dis86_t *x, uint_t tgtop, uint_t evex_byte3) 3209 { 3210 #ifdef DIS_TEXT 3211 char *opnd = x->d86_opnd[tgtop].d86_opnd; 3212 int opmask_reg = evex_byte3 & EVEX_OPREG_MASK; 3213 #endif 3214 if (x->d86_error) 3215 return; 3216 3217 #ifdef DIS_TEXT 3218 if (opmask_reg != 0) { 3219 /* Append the opmask register to operand 1 */ 3220 (void) strlcat(opnd, "{", OPLEN); 3221 (void) strlcat(opnd, dis_KOPMASKREG[opmask_reg], OPLEN); 3222 (void) strlcat(opnd, "}", OPLEN); 3223 } 3224 if ((evex_byte3 & EVEX_ZERO_MASK) != 0) { 3225 /* Append the 'zeroing' modifier to operand 1 */ 3226 (void) strlcat(opnd, "{z}", OPLEN); 3227 } 3228 #endif /* DIS_TEXT */ 3229 } 3230 3231 /* 3232 * Get an immediate operand of the given size, with sign extension. 3233 */ 3234 static void 3235 dtrace_imm_opnd(dis86_t *x, int wbit, int size, int opindex) 3236 { 3237 int i; 3238 int byte; 3239 int valsize; 3240 3241 if (x->d86_numopnds < opindex + 1) 3242 x->d86_numopnds = opindex + 1; 3243 3244 switch (wbit) { 3245 case BYTE_OPND: 3246 valsize = 1; 3247 break; 3248 case LONG_OPND: 3249 if (x->d86_opnd_size == SIZE16) 3250 valsize = 2; 3251 else if (x->d86_opnd_size == SIZE32) 3252 valsize = 4; 3253 else 3254 valsize = 8; 3255 break; 3256 case MM_OPND: 3257 case XMM_OPND: 3258 case YMM_OPND: 3259 case ZMM_OPND: 3260 case SEG_OPND: 3261 case CONTROL_OPND: 3262 case DEBUG_OPND: 3263 case TEST_OPND: 3264 valsize = size; 3265 break; 3266 case WORD_OPND: 3267 valsize = 2; 3268 break; 3269 } 3270 if (valsize < size) 3271 valsize = size; 3272 3273 if (x->d86_error) 3274 return; 3275 x->d86_opnd[opindex].d86_value = 0; 3276 for (i = 0; i < size; ++i) { 3277 byte = x->d86_get_byte(x->d86_data); 3278 if (byte < 0) { 3279 x->d86_error = 1; 3280 return; 3281 } 3282 x->d86_bytes[x->d86_len++] = byte; 3283 x->d86_opnd[opindex].d86_value |= (uint64_t)byte << (i * 8); 3284 } 3285 /* Do sign extension */ 3286 if (x->d86_bytes[x->d86_len - 1] & 0x80) { 3287 for (; i < sizeof (uint64_t); i++) 3288 x->d86_opnd[opindex].d86_value |= 3289 (uint64_t)0xff << (i * 8); 3290 } 3291 #ifdef DIS_TEXT 3292 x->d86_opnd[opindex].d86_mode = MODE_SIGNED; 3293 x->d86_opnd[opindex].d86_value_size = valsize; 3294 x->d86_imm_bytes += size; 3295 #endif 3296 } 3297 3298 /* 3299 * Get an ip relative operand of the given size, with sign extension. 3300 */ 3301 static void 3302 dtrace_disp_opnd(dis86_t *x, int wbit, int size, int opindex) 3303 { 3304 dtrace_imm_opnd(x, wbit, size, opindex); 3305 #ifdef DIS_TEXT 3306 x->d86_opnd[opindex].d86_mode = MODE_IPREL; 3307 #endif 3308 } 3309 3310 /* 3311 * Check to see if there is a segment override prefix pending. 3312 * If so, print it in the current 'operand' location and set 3313 * the override flag back to false. 3314 */ 3315 /*ARGSUSED*/ 3316 static void 3317 dtrace_check_override(dis86_t *x, int opindex) 3318 { 3319 #ifdef DIS_TEXT 3320 if (x->d86_seg_prefix) { 3321 (void) strlcat(x->d86_opnd[opindex].d86_prefix, 3322 x->d86_seg_prefix, PFIXLEN); 3323 } 3324 #endif 3325 x->d86_seg_prefix = NULL; 3326 } 3327 3328 3329 /* 3330 * Process a single instruction Register or Memory operand. 3331 * 3332 * mode = addressing mode from ModRM byte 3333 * r_m = r_m (or reg if mode == 3) field from ModRM byte 3334 * wbit = indicates which register (8bit, 16bit, ... MMX, etc.) set to use. 3335 * o = index of operand that we are processing (0, 1 or 2) 3336 * 3337 * the value of reg or r_m must have already been adjusted for any REX prefix. 3338 */ 3339 /*ARGSUSED*/ 3340 static void 3341 dtrace_get_operand(dis86_t *x, uint_t mode, uint_t r_m, int wbit, int opindex) 3342 { 3343 int have_SIB = 0; /* flag presence of scale-index-byte */ 3344 uint_t ss; /* scale-factor from opcode */ 3345 uint_t index; /* index register number */ 3346 uint_t base; /* base register number */ 3347 int dispsize; /* size of displacement in bytes */ 3348 #ifdef DIS_TEXT 3349 char *opnd = x->d86_opnd[opindex].d86_opnd; 3350 #endif 3351 3352 if (x->d86_numopnds < opindex + 1) 3353 x->d86_numopnds = opindex + 1; 3354 3355 if (x->d86_error) 3356 return; 3357 3358 /* 3359 * first handle a simple register 3360 */ 3361 if (mode == REG_ONLY) { 3362 #ifdef DIS_TEXT 3363 switch (wbit) { 3364 case MM_OPND: 3365 (void) strlcat(opnd, dis_MMREG[r_m], OPLEN); 3366 break; 3367 case XMM_OPND: 3368 (void) strlcat(opnd, dis_XMMREG[r_m], OPLEN); 3369 break; 3370 case YMM_OPND: 3371 (void) strlcat(opnd, dis_YMMREG[r_m], OPLEN); 3372 break; 3373 case ZMM_OPND: 3374 (void) strlcat(opnd, dis_ZMMREG[r_m], OPLEN); 3375 break; 3376 case KOPMASK_OPND: 3377 (void) strlcat(opnd, dis_KOPMASKREG[r_m], OPLEN); 3378 break; 3379 case SEG_OPND: 3380 (void) strlcat(opnd, dis_SEGREG[r_m], OPLEN); 3381 break; 3382 case CONTROL_OPND: 3383 (void) strlcat(opnd, dis_CONTROLREG[r_m], OPLEN); 3384 break; 3385 case DEBUG_OPND: 3386 (void) strlcat(opnd, dis_DEBUGREG[r_m], OPLEN); 3387 break; 3388 case TEST_OPND: 3389 (void) strlcat(opnd, dis_TESTREG[r_m], OPLEN); 3390 break; 3391 case BYTE_OPND: 3392 if (x->d86_rex_prefix == 0) 3393 (void) strlcat(opnd, dis_REG8[r_m], OPLEN); 3394 else 3395 (void) strlcat(opnd, dis_REG8_REX[r_m], OPLEN); 3396 break; 3397 case WORD_OPND: 3398 (void) strlcat(opnd, dis_REG16[r_m], OPLEN); 3399 break; 3400 case LONG_OPND: 3401 if (x->d86_opnd_size == SIZE16) 3402 (void) strlcat(opnd, dis_REG16[r_m], OPLEN); 3403 else if (x->d86_opnd_size == SIZE32) 3404 (void) strlcat(opnd, dis_REG32[r_m], OPLEN); 3405 else 3406 (void) strlcat(opnd, dis_REG64[r_m], OPLEN); 3407 break; 3408 } 3409 #endif /* DIS_TEXT */ 3410 return; 3411 } 3412 3413 /* 3414 * if symbolic representation, skip override prefix, if any 3415 */ 3416 dtrace_check_override(x, opindex); 3417 3418 /* 3419 * Handle 16 bit memory references first, since they decode 3420 * the mode values more simply. 3421 * mode 1 is r_m + 8 bit displacement 3422 * mode 2 is r_m + 16 bit displacement 3423 * mode 0 is just r_m, unless r_m is 6 which is 16 bit disp 3424 */ 3425 if (x->d86_addr_size == SIZE16) { 3426 if ((mode == 0 && r_m == 6) || mode == 2) 3427 dtrace_imm_opnd(x, WORD_OPND, 2, opindex); 3428 else if (mode == 1) 3429 dtrace_imm_opnd(x, BYTE_OPND, 1, opindex); 3430 #ifdef DIS_TEXT 3431 if (mode == 0 && r_m == 6) 3432 x->d86_opnd[opindex].d86_mode = MODE_SIGNED; 3433 else if (mode == 0) 3434 x->d86_opnd[opindex].d86_mode = MODE_NONE; 3435 else 3436 x->d86_opnd[opindex].d86_mode = MODE_OFFSET; 3437 (void) strlcat(opnd, dis_addr16[mode][r_m], OPLEN); 3438 #endif 3439 return; 3440 } 3441 3442 /* 3443 * 32 and 64 bit addressing modes are more complex since they can 3444 * involve an SIB (scaled index and base) byte to decode. When using VEX 3445 * and EVEX encodings, the r_m indicator for a SIB may be offset by 8 3446 * and 24 (8 + 16) respectively. 3447 */ 3448 if (r_m == ESP_REGNO || r_m == ESP_REGNO + 8 || r_m == ESP_REGNO + 24) { 3449 have_SIB = 1; 3450 dtrace_get_SIB(x, &ss, &index, &base); 3451 if (x->d86_error) 3452 return; 3453 if (base != 5 || mode != 0) 3454 if (x->d86_rex_prefix & REX_B) 3455 base += 8; 3456 if (x->d86_rex_prefix & REX_X) 3457 index += 8; 3458 } else { 3459 base = r_m; 3460 } 3461 3462 /* 3463 * Compute the displacement size and get its bytes 3464 */ 3465 dispsize = 0; 3466 3467 if (mode == 1) 3468 dispsize = 1; 3469 else if (mode == 2) 3470 dispsize = 4; 3471 else if ((r_m & 7) == EBP_REGNO || 3472 (have_SIB && (base & 7) == EBP_REGNO)) 3473 dispsize = 4; 3474 3475 if (dispsize > 0) { 3476 dtrace_imm_opnd(x, dispsize == 4 ? LONG_OPND : BYTE_OPND, 3477 dispsize, opindex); 3478 if (x->d86_error) 3479 return; 3480 } 3481 3482 #ifdef DIS_TEXT 3483 if (dispsize > 0) 3484 x->d86_opnd[opindex].d86_mode = MODE_OFFSET; 3485 3486 if (have_SIB == 0) { 3487 if (x->d86_mode == SIZE32) { 3488 if (mode == 0) 3489 (void) strlcat(opnd, dis_addr32_mode0[r_m], 3490 OPLEN); 3491 else 3492 (void) strlcat(opnd, dis_addr32_mode12[r_m], 3493 OPLEN); 3494 } else { 3495 if (mode == 0) { 3496 (void) strlcat(opnd, dis_addr64_mode0[r_m], 3497 OPLEN); 3498 if (r_m == 5) { 3499 x->d86_opnd[opindex].d86_mode = 3500 MODE_RIPREL; 3501 } 3502 } else { 3503 (void) strlcat(opnd, dis_addr64_mode12[r_m], 3504 OPLEN); 3505 } 3506 } 3507 } else { 3508 uint_t need_paren = 0; 3509 char **regs; 3510 char **bregs; 3511 const char *const *sf; 3512 if (x->d86_mode == SIZE32) /* NOTE this is not addr_size! */ 3513 regs = (char **)dis_REG32; 3514 else 3515 regs = (char **)dis_REG64; 3516 3517 if (x->d86_vsib != 0) { 3518 if (wbit == YMM_OPND) { /* NOTE this is not addr_size */ 3519 bregs = (char **)dis_YMMREG; 3520 } else if (wbit == XMM_OPND) { 3521 bregs = (char **)dis_XMMREG; 3522 } else { 3523 bregs = (char **)dis_ZMMREG; 3524 } 3525 sf = dis_vscale_factor; 3526 } else { 3527 bregs = regs; 3528 sf = dis_scale_factor; 3529 } 3530 3531 /* 3532 * print the base (if any) 3533 */ 3534 if (base == EBP_REGNO && mode == 0) { 3535 if (index != ESP_REGNO || x->d86_vsib != 0) { 3536 (void) strlcat(opnd, "(", OPLEN); 3537 need_paren = 1; 3538 } 3539 } else { 3540 (void) strlcat(opnd, "(", OPLEN); 3541 (void) strlcat(opnd, regs[base], OPLEN); 3542 need_paren = 1; 3543 } 3544 3545 /* 3546 * print the index (if any) 3547 */ 3548 if (index != ESP_REGNO || x->d86_vsib) { 3549 (void) strlcat(opnd, ",", OPLEN); 3550 (void) strlcat(opnd, bregs[index], OPLEN); 3551 (void) strlcat(opnd, sf[ss], OPLEN); 3552 } else 3553 if (need_paren) 3554 (void) strlcat(opnd, ")", OPLEN); 3555 } 3556 #endif 3557 } 3558 3559 /* 3560 * Operand sequence for standard instruction involving one register 3561 * and one register/memory operand. 3562 * wbit indicates a byte(0) or opnd_size(1) operation 3563 * vbit indicates direction (0 for "opcode r,r_m") or (1 for "opcode r_m, r") 3564 */ 3565 #define STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, vbit) { \ 3566 dtrace_get_modrm(x, &mode, ®, &r_m); \ 3567 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); \ 3568 dtrace_get_operand(x, mode, r_m, wbit, vbit); \ 3569 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1 - vbit); \ 3570 } 3571 3572 /* 3573 * Similar to above, but allows for the two operands to be of different 3574 * classes (ie. wbit). 3575 * wbit is for the r_m operand 3576 * w2 is for the reg operand 3577 */ 3578 #define MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, w2, vbit) { \ 3579 dtrace_get_modrm(x, &mode, ®, &r_m); \ 3580 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); \ 3581 dtrace_get_operand(x, mode, r_m, wbit, vbit); \ 3582 dtrace_get_operand(x, REG_ONLY, reg, w2, 1 - vbit); \ 3583 } 3584 3585 /* 3586 * Similar, but for 2 operands plus an immediate. 3587 * vbit indicates direction 3588 * 0 for "opcode imm, r, r_m" or 3589 * 1 for "opcode imm, r_m, r" 3590 */ 3591 #define THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, w2, immsize, vbit) { \ 3592 dtrace_get_modrm(x, &mode, ®, &r_m); \ 3593 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); \ 3594 dtrace_get_operand(x, mode, r_m, wbit, 2-vbit); \ 3595 dtrace_get_operand(x, REG_ONLY, reg, w2, 1+vbit); \ 3596 dtrace_imm_opnd(x, wbit, immsize, 0); \ 3597 } 3598 3599 /* 3600 * Similar, but for 2 operands plus two immediates. 3601 */ 3602 #define FOUROPERAND(x, mode, reg, r_m, rex_prefix, wbit, w2, immsize) { \ 3603 dtrace_get_modrm(x, &mode, ®, &r_m); \ 3604 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); \ 3605 dtrace_get_operand(x, mode, r_m, wbit, 2); \ 3606 dtrace_get_operand(x, REG_ONLY, reg, w2, 3); \ 3607 dtrace_imm_opnd(x, wbit, immsize, 1); \ 3608 dtrace_imm_opnd(x, wbit, immsize, 0); \ 3609 } 3610 3611 /* 3612 * 1 operands plus two immediates. 3613 */ 3614 #define ONEOPERAND_TWOIMM(x, mode, reg, r_m, rex_prefix, wbit, immsize) { \ 3615 dtrace_get_modrm(x, &mode, ®, &r_m); \ 3616 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); \ 3617 dtrace_get_operand(x, mode, r_m, wbit, 2); \ 3618 dtrace_imm_opnd(x, wbit, immsize, 1); \ 3619 dtrace_imm_opnd(x, wbit, immsize, 0); \ 3620 } 3621 3622 /* 3623 * Dissassemble a single x86 or amd64 instruction. 3624 * 3625 * Mode determines the default operating mode (SIZE16, SIZE32 or SIZE64) 3626 * for interpreting instructions. 3627 * 3628 * returns non-zero for bad opcode 3629 */ 3630 int 3631 dtrace_disx86(dis86_t *x, uint_t cpu_mode) 3632 { 3633 const instable_t *dp; /* decode table being used */ 3634 #ifdef DIS_TEXT 3635 uint_t i; 3636 #endif 3637 #ifdef DIS_MEM 3638 uint_t nomem = 0; 3639 #define NOMEM (nomem = 1) 3640 #else 3641 #define NOMEM /* nothing */ 3642 #endif 3643 uint_t opnd_size; /* SIZE16, SIZE32 or SIZE64 */ 3644 uint_t addr_size; /* SIZE16, SIZE32 or SIZE64 */ 3645 uint_t wbit; /* opcode wbit, 0 is 8 bit, !0 for opnd_size */ 3646 uint_t w2; /* wbit value for second operand */ 3647 uint_t vbit; 3648 uint_t mode = 0; /* mode value from ModRM byte */ 3649 uint_t reg; /* reg value from ModRM byte */ 3650 uint_t r_m; /* r_m value from ModRM byte */ 3651 3652 uint_t opcode1; /* high nibble of 1st byte */ 3653 uint_t opcode2; /* low nibble of 1st byte */ 3654 uint_t opcode3; /* extra opcode bits usually from ModRM byte */ 3655 uint_t opcode4; /* high nibble of 2nd byte */ 3656 uint_t opcode5; /* low nibble of 2nd byte */ 3657 uint_t opcode6; /* high nibble of 3rd byte */ 3658 uint_t opcode7; /* low nibble of 3rd byte */ 3659 uint_t opcode8; /* high nibble of 4th byte */ 3660 uint_t opcode9; /* low nibble of 4th byte */ 3661 uint_t opcode_bytes = 1; 3662 3663 /* 3664 * legacy prefixes come in 5 flavors, you should have only one of each 3665 */ 3666 uint_t opnd_size_prefix = 0; 3667 uint_t addr_size_prefix = 0; 3668 uint_t segment_prefix = 0; 3669 uint_t lock_prefix = 0; 3670 uint_t rep_prefix = 0; 3671 uint_t rex_prefix = 0; /* amd64 register extension prefix */ 3672 3673 /* 3674 * Intel VEX instruction encoding prefix and fields 3675 */ 3676 3677 /* 0xC4 means 3 bytes prefix, 0xC5 means 2 bytes prefix */ 3678 uint_t vex_prefix = 0; 3679 3680 /* 3681 * VEX prefix byte 1, includes vex.r, vex.x and vex.b 3682 * (for 3 bytes prefix) 3683 */ 3684 uint_t vex_byte1 = 0; 3685 3686 /* 3687 * EVEX prefix byte 1 includes vex.r, vex.x, vex.b and evex.r. 3688 */ 3689 uint_t evex_byte1 = 0; 3690 uint_t evex_byte2 = 0; 3691 uint_t evex_byte3 = 0; 3692 3693 /* 3694 * For 32-bit mode, it should prefetch the next byte to 3695 * distinguish between AVX and les/lds 3696 */ 3697 uint_t vex_prefetch = 0; 3698 3699 uint_t vex_m = 0; 3700 uint_t vex_v = 0; 3701 uint_t vex_p = 0; 3702 uint_t vex_R = 1; 3703 uint_t vex_X = 1; 3704 uint_t vex_B = 1; 3705 uint_t vex_W = 0; 3706 uint_t vex_L = 0; 3707 uint_t evex_L = 0; 3708 uint_t evex_modrm = 0; 3709 uint_t evex_prefix = 0; 3710 dis_gather_regs_t *vreg; 3711 3712 #ifdef DIS_TEXT 3713 /* Instruction name for BLS* family of instructions */ 3714 char *blsinstr; 3715 #endif 3716 3717 size_t off; 3718 3719 instable_t dp_mmx; 3720 3721 x->d86_len = 0; 3722 x->d86_rmindex = -1; 3723 x->d86_error = 0; 3724 #ifdef DIS_TEXT 3725 x->d86_numopnds = 0; 3726 x->d86_seg_prefix = NULL; 3727 x->d86_mnem[0] = 0; 3728 for (i = 0; i < 4; ++i) { 3729 x->d86_opnd[i].d86_opnd[0] = 0; 3730 x->d86_opnd[i].d86_prefix[0] = 0; 3731 x->d86_opnd[i].d86_value_size = 0; 3732 x->d86_opnd[i].d86_value = 0; 3733 x->d86_opnd[i].d86_mode = MODE_NONE; 3734 } 3735 #endif 3736 x->d86_rex_prefix = 0; 3737 x->d86_got_modrm = 0; 3738 x->d86_memsize = 0; 3739 x->d86_vsib = 0; 3740 3741 if (cpu_mode == SIZE16) { 3742 opnd_size = SIZE16; 3743 addr_size = SIZE16; 3744 } else if (cpu_mode == SIZE32) { 3745 opnd_size = SIZE32; 3746 addr_size = SIZE32; 3747 } else { 3748 opnd_size = SIZE32; 3749 addr_size = SIZE64; 3750 } 3751 3752 /* 3753 * Get one opcode byte and check for zero padding that follows 3754 * jump tables. 3755 */ 3756 if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0) 3757 goto error; 3758 3759 if (opcode1 == 0 && opcode2 == 0 && 3760 x->d86_check_func != NULL && x->d86_check_func(x->d86_data)) { 3761 #ifdef DIS_TEXT 3762 (void) strncpy(x->d86_mnem, ".byte\t0", OPLEN); 3763 #endif 3764 goto done; 3765 } 3766 3767 /* 3768 * Gather up legacy x86 prefix bytes. 3769 */ 3770 for (;;) { 3771 uint_t *which_prefix = NULL; 3772 3773 dp = (instable_t *)&dis_distable[opcode1][opcode2]; 3774 3775 switch (dp->it_adrmode) { 3776 case PREFIX: 3777 which_prefix = &rep_prefix; 3778 break; 3779 case LOCK: 3780 which_prefix = &lock_prefix; 3781 break; 3782 case OVERRIDE: 3783 which_prefix = &segment_prefix; 3784 #ifdef DIS_TEXT 3785 x->d86_seg_prefix = (char *)dp->it_name; 3786 #endif 3787 if (dp->it_invalid64 && cpu_mode == SIZE64) 3788 goto error; 3789 break; 3790 case AM: 3791 which_prefix = &addr_size_prefix; 3792 break; 3793 case DM: 3794 which_prefix = &opnd_size_prefix; 3795 break; 3796 } 3797 if (which_prefix == NULL) 3798 break; 3799 *which_prefix = (opcode1 << 4) | opcode2; 3800 if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0) 3801 goto error; 3802 } 3803 3804 /* 3805 * Handle amd64 mode PREFIX values. 3806 * Some of the segment prefixes are no-ops. (only FS/GS actually work) 3807 * We might have a REX prefix (opcodes 0x40-0x4f) 3808 */ 3809 if (cpu_mode == SIZE64) { 3810 if (segment_prefix != 0x64 && segment_prefix != 0x65) 3811 segment_prefix = 0; 3812 3813 if (opcode1 == 0x4) { 3814 rex_prefix = (opcode1 << 4) | opcode2; 3815 if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0) 3816 goto error; 3817 dp = (instable_t *)&dis_distable[opcode1][opcode2]; 3818 } else if (opcode1 == 0xC && 3819 (opcode2 == 0x4 || opcode2 == 0x5)) { 3820 /* AVX instructions */ 3821 vex_prefix = (opcode1 << 4) | opcode2; 3822 x->d86_rex_prefix = 0x40; 3823 } 3824 } else if (opcode1 == 0xC && (opcode2 == 0x4 || opcode2 == 0x5)) { 3825 /* LDS, LES or AVX */ 3826 dtrace_get_modrm(x, &mode, ®, &r_m); 3827 vex_prefetch = 1; 3828 3829 if (mode == REG_ONLY) { 3830 /* AVX */ 3831 vex_prefix = (opcode1 << 4) | opcode2; 3832 x->d86_rex_prefix = 0x40; 3833 opcode3 = (((mode << 3) | reg)>>1) & 0x0F; 3834 opcode4 = ((reg << 3) | r_m) & 0x0F; 3835 } 3836 } 3837 3838 /* 3839 * The EVEX prefix and "bound" instruction share the same first byte. 3840 * "bound" is only valid for 32-bit. For 64-bit this byte begins the 3841 * EVEX prefix and the 2nd byte must have bits 2 & 3 set to 0. 3842 */ 3843 if (opcode1 == 0x6 && opcode2 == 0x2) { 3844 evex_prefix = 0x62; 3845 3846 /* 3847 * An EVEX prefix is 4 bytes long, get the next 3 bytes. 3848 */ 3849 if (dtrace_get_opcode(x, &opcode4, &opcode5) != 0) 3850 goto error; 3851 3852 if (addr_size == SIZE32 && (opcode4 & 0xf) == 0) { 3853 /* 3854 * Upper bits in 2nd byte == 0 is 'bound' instn. 3855 * 3856 * We've already read the byte so perform the 3857 * equivalent of dtrace_get_modrm on the byte and set 3858 * the flag to indicate we've already read it. 3859 */ 3860 char b = (opcode4 << 4) | opcode5; 3861 3862 r_m = b & 0x7; 3863 reg = (b >> 3) & 0x7; 3864 mode = (b >> 6) & 0x3; 3865 vex_prefetch = 1; 3866 goto not_avx512; 3867 } 3868 3869 /* check for correct bits being 0 in 2nd byte */ 3870 if ((opcode5 & 0xc) != 0) 3871 goto error; 3872 3873 if (dtrace_get_opcode(x, &opcode6, &opcode7) != 0) 3874 goto error; 3875 /* check for correct bit being 1 in 3rd byte */ 3876 if ((opcode7 & 0x4) == 0) 3877 goto error; 3878 3879 if (dtrace_get_opcode(x, &opcode8, &opcode9) != 0) 3880 goto error; 3881 3882 /* Reuse opcode1 & opcode2 to get the real opcode now */ 3883 if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0) 3884 goto error; 3885 3886 /* 3887 * We only use the high nibble from the 2nd byte of the prefix 3888 * and save it in the low bits of evex_byte1. This is because 3889 * two of the bits in opcode5 are constant 0 (checked above), 3890 * and the other two bits are captured in vex_m. Also, the VEX 3891 * constants we check in evex_byte1 are against the low bits. 3892 */ 3893 evex_byte1 = opcode4; 3894 evex_byte2 = (opcode6 << 4) | opcode7; 3895 evex_byte3 = (opcode8 << 4) | opcode9; 3896 3897 vex_m = opcode5 & EVEX_m; 3898 vex_v = (((opcode6 << 4) | opcode7) & VEX_v) >> 3; 3899 vex_W = (opcode6 & VEX_W) >> 3; 3900 vex_p = opcode7 & VEX_p; 3901 3902 /* 3903 * Store the corresponding prefix information for later use when 3904 * calculating the SIB. 3905 */ 3906 if ((evex_byte1 & VEX_R) == 0) 3907 x->d86_rex_prefix |= REX_R; 3908 if ((evex_byte1 & VEX_X) == 0) 3909 x->d86_rex_prefix |= REX_X; 3910 if ((evex_byte1 & VEX_B) == 0) 3911 x->d86_rex_prefix |= REX_B; 3912 3913 /* Currently only 3 valid values for evex L'L: 00, 01, 10 */ 3914 evex_L = (opcode8 & EVEX_L) >> 1; 3915 3916 switch (vex_p) { 3917 case VEX_p_66: 3918 switch (vex_m) { 3919 case VEX_m_0F: 3920 dp = &dis_opEVEX660F[(opcode1 << 4) | opcode2]; 3921 break; 3922 case VEX_m_0F38: 3923 dp = &dis_opEVEX660F38[(opcode1 << 4) | 3924 opcode2]; 3925 break; 3926 case VEX_m_0F3A: 3927 dp = &dis_opEVEX660F3A[(opcode1 << 4) | 3928 opcode2]; 3929 break; 3930 default: 3931 goto error; 3932 } 3933 break; 3934 case VEX_p_F3: 3935 switch (vex_m) { 3936 case VEX_m_0F: 3937 dp = &dis_opEVEXF30F[(opcode1 << 4) | opcode2]; 3938 break; 3939 default: 3940 goto error; 3941 } 3942 break; 3943 case VEX_p_F2: 3944 switch (vex_m) { 3945 case VEX_m_0F: 3946 dp = &dis_opEVEXF20F[(opcode1 << 4) | opcode2]; 3947 break; 3948 default: 3949 goto error; 3950 } 3951 break; 3952 default: 3953 dp = &dis_opEVEX0F[(opcode1 << 4) | opcode2]; 3954 break; 3955 } 3956 } 3957 not_avx512: 3958 3959 if (vex_prefix == VEX_2bytes) { 3960 if (!vex_prefetch) { 3961 if (dtrace_get_opcode(x, &opcode3, &opcode4) != 0) 3962 goto error; 3963 } 3964 vex_R = ((opcode3 & VEX_R) & 0x0F) >> 3; 3965 vex_L = ((opcode4 & VEX_L) & 0x0F) >> 2; 3966 vex_v = (((opcode3 << 4) | opcode4) & VEX_v) >> 3; 3967 vex_p = opcode4 & VEX_p; 3968 /* 3969 * The vex.x and vex.b bits are not defined in two bytes 3970 * mode vex prefix, their default values are 1 3971 */ 3972 vex_byte1 = (opcode3 & VEX_R) | VEX_X | VEX_B; 3973 3974 if (vex_R == 0) 3975 x->d86_rex_prefix |= REX_R; 3976 3977 if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0) 3978 goto error; 3979 3980 switch (vex_p) { 3981 case VEX_p_66: 3982 dp = (instable_t *) 3983 &dis_opAVX660F[(opcode1 << 4) | opcode2]; 3984 break; 3985 case VEX_p_F3: 3986 dp = (instable_t *) 3987 &dis_opAVXF30F[(opcode1 << 4) | opcode2]; 3988 break; 3989 case VEX_p_F2: 3990 dp = (instable_t *) 3991 &dis_opAVXF20F [(opcode1 << 4) | opcode2]; 3992 break; 3993 default: 3994 dp = (instable_t *) 3995 &dis_opAVX0F[opcode1][opcode2]; 3996 3997 } 3998 3999 } else if (vex_prefix == VEX_3bytes) { 4000 if (!vex_prefetch) { 4001 if (dtrace_get_opcode(x, &opcode3, &opcode4) != 0) 4002 goto error; 4003 } 4004 vex_R = (opcode3 & VEX_R) >> 3; 4005 vex_X = (opcode3 & VEX_X) >> 2; 4006 vex_B = (opcode3 & VEX_B) >> 1; 4007 vex_m = (((opcode3 << 4) | opcode4) & VEX_m); 4008 vex_byte1 = opcode3 & (VEX_R | VEX_X | VEX_B); 4009 4010 if (vex_R == 0) 4011 x->d86_rex_prefix |= REX_R; 4012 if (vex_X == 0) 4013 x->d86_rex_prefix |= REX_X; 4014 if (vex_B == 0) 4015 x->d86_rex_prefix |= REX_B; 4016 4017 if (dtrace_get_opcode(x, &opcode5, &opcode6) != 0) 4018 goto error; 4019 vex_W = (opcode5 & VEX_W) >> 3; 4020 vex_L = (opcode6 & VEX_L) >> 2; 4021 vex_v = (((opcode5 << 4) | opcode6) & VEX_v) >> 3; 4022 vex_p = opcode6 & VEX_p; 4023 4024 if (vex_W) 4025 x->d86_rex_prefix |= REX_W; 4026 4027 /* Only these three vex_m values valid; others are reserved */ 4028 if ((vex_m != VEX_m_0F) && (vex_m != VEX_m_0F38) && 4029 (vex_m != VEX_m_0F3A)) 4030 goto error; 4031 4032 if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0) 4033 goto error; 4034 4035 switch (vex_p) { 4036 case VEX_p_66: 4037 if (vex_m == VEX_m_0F) { 4038 dp = (instable_t *) 4039 &dis_opAVX660F 4040 [(opcode1 << 4) | opcode2]; 4041 } else if (vex_m == VEX_m_0F38) { 4042 dp = (instable_t *) 4043 &dis_opAVX660F38 4044 [(opcode1 << 4) | opcode2]; 4045 } else if (vex_m == VEX_m_0F3A) { 4046 dp = (instable_t *) 4047 &dis_opAVX660F3A 4048 [(opcode1 << 4) | opcode2]; 4049 } else { 4050 goto error; 4051 } 4052 break; 4053 case VEX_p_F3: 4054 if (vex_m == VEX_m_0F) { 4055 dp = (instable_t *) 4056 &dis_opAVXF30F 4057 [(opcode1 << 4) | opcode2]; 4058 } else if (vex_m == VEX_m_0F38) { 4059 dp = (instable_t *) 4060 &dis_opAVXF30F38 4061 [(opcode1 << 4) | opcode2]; 4062 } else { 4063 goto error; 4064 } 4065 break; 4066 case VEX_p_F2: 4067 if (vex_m == VEX_m_0F) { 4068 dp = (instable_t *) 4069 &dis_opAVXF20F 4070 [(opcode1 << 4) | opcode2]; 4071 } else if (vex_m == VEX_m_0F3A) { 4072 dp = (instable_t *) 4073 &dis_opAVXF20F3A 4074 [(opcode1 << 4) | opcode2]; 4075 } else if (vex_m == VEX_m_0F38) { 4076 dp = (instable_t *) 4077 &dis_opAVXF20F38 4078 [(opcode1 << 4) | opcode2]; 4079 } else { 4080 goto error; 4081 } 4082 break; 4083 default: 4084 dp = (instable_t *) 4085 &dis_opAVX0F[opcode1][opcode2]; 4086 4087 } 4088 } 4089 if (vex_prefix) { 4090 if (dp->it_vexwoxmm) { 4091 wbit = LONG_OPND; 4092 } else if (dp->it_vexopmask) { 4093 wbit = KOPMASK_OPND; 4094 } else { 4095 if (vex_L) { 4096 wbit = YMM_OPND; 4097 } else { 4098 wbit = XMM_OPND; 4099 } 4100 } 4101 } 4102 4103 /* 4104 * Deal with selection of operand and address size now. 4105 * Note that the REX.W bit being set causes opnd_size_prefix to be 4106 * ignored. 4107 */ 4108 if (cpu_mode == SIZE64) { 4109 if ((rex_prefix & REX_W) || vex_W) 4110 opnd_size = SIZE64; 4111 else if (opnd_size_prefix) 4112 opnd_size = SIZE16; 4113 4114 if (addr_size_prefix) 4115 addr_size = SIZE32; 4116 } else if (cpu_mode == SIZE32) { 4117 if (opnd_size_prefix) 4118 opnd_size = SIZE16; 4119 if (addr_size_prefix) 4120 addr_size = SIZE16; 4121 } else { 4122 if (opnd_size_prefix) 4123 opnd_size = SIZE32; 4124 if (addr_size_prefix) 4125 addr_size = SIZE32; 4126 } 4127 /* 4128 * The pause instruction - a repz'd nop. This doesn't fit 4129 * with any of the other prefix goop added for SSE, so we'll 4130 * special-case it here. 4131 */ 4132 if (rep_prefix == 0xf3 && opcode1 == 0x9 && opcode2 == 0x0) { 4133 rep_prefix = 0; 4134 dp = (instable_t *)&dis_opPause; 4135 } 4136 4137 /* 4138 * Some 386 instructions have 2 bytes of opcode before the mod_r/m 4139 * byte so we may need to perform a table indirection. 4140 */ 4141 if (dp->it_indirect == (instable_t *)dis_op0F) { 4142 if (dtrace_get_opcode(x, &opcode4, &opcode5) != 0) 4143 goto error; 4144 opcode_bytes = 2; 4145 if (opcode4 == 0x7 && opcode5 >= 0x1 && opcode5 <= 0x3) { 4146 uint_t subcode; 4147 4148 if (dtrace_get_opcode(x, &opcode6, &opcode7) != 0) 4149 goto error; 4150 opcode_bytes = 3; 4151 subcode = ((opcode6 & 0x3) << 1) | 4152 ((opcode7 & 0x8) >> 3); 4153 dp = (instable_t *)&dis_op0F7123[opcode5][subcode]; 4154 } else if ((opcode4 == 0xc) && (opcode5 >= 0x8)) { 4155 dp = (instable_t *)&dis_op0FC8[0]; 4156 } else if ((opcode4 == 0x3) && (opcode5 == 0xA)) { 4157 opcode_bytes = 3; 4158 if (dtrace_get_opcode(x, &opcode6, &opcode7) != 0) 4159 goto error; 4160 if (opnd_size == SIZE16) 4161 opnd_size = SIZE32; 4162 4163 dp = (instable_t *)&dis_op0F3A[(opcode6<<4)|opcode7]; 4164 #ifdef DIS_TEXT 4165 if (strcmp(dp->it_name, "INVALID") == 0) 4166 goto error; 4167 #endif 4168 switch (dp->it_adrmode) { 4169 case XMMP: 4170 break; 4171 case XMMP_66r: 4172 case XMMPRM_66r: 4173 case XMM3PM_66r: 4174 if (opnd_size_prefix == 0) { 4175 goto error; 4176 } 4177 4178 break; 4179 case XMMP_66o: 4180 if (opnd_size_prefix == 0) { 4181 /* SSSE3 MMX instructions */ 4182 dp_mmx = *dp; 4183 dp_mmx.it_adrmode = MMOPM_66o; 4184 #ifdef DIS_MEM 4185 dp_mmx.it_size = 8; 4186 #endif 4187 dp = &dp_mmx; 4188 } 4189 break; 4190 default: 4191 goto error; 4192 } 4193 } else if ((opcode4 == 0x3) && (opcode5 == 0x8)) { 4194 opcode_bytes = 3; 4195 if (dtrace_get_opcode(x, &opcode6, &opcode7) != 0) 4196 goto error; 4197 dp = (instable_t *)&dis_op0F38[(opcode6<<4)|opcode7]; 4198 4199 /* 4200 * Both crc32 and movbe have the same 3rd opcode 4201 * byte of either 0xF0 or 0xF1, so we use another 4202 * indirection to distinguish between the two. 4203 */ 4204 if (dp->it_indirect == (instable_t *)dis_op0F38F0 || 4205 dp->it_indirect == (instable_t *)dis_op0F38F1) { 4206 4207 dp = dp->it_indirect; 4208 if (rep_prefix != 0xF2) { 4209 /* It is movbe */ 4210 dp++; 4211 } 4212 } 4213 4214 /* 4215 * The adx family of instructions (adcx and adox) 4216 * continue the classic Intel tradition of abusing 4217 * arbitrary prefixes without actually meaning the 4218 * prefix bit. Therefore, if we find either the 4219 * opnd_size_prefix or rep_prefix we end up zeroing it 4220 * out after making our determination so as to ensure 4221 * that we don't get confused and accidentally print 4222 * repz prefixes and the like on these instructions. 4223 * 4224 * In addition, these instructions are actually much 4225 * closer to AVX instructions in semantics. Importantly, 4226 * they always default to having 32-bit operands. 4227 * However, if the CPU is in 64-bit mode, then and only 4228 * then, does it use REX.w promotes things to 64-bits 4229 * and REX.r allows 64-bit mode to use register r8-r15. 4230 */ 4231 if (dp->it_indirect == (instable_t *)dis_op0F38F6) { 4232 dp = dp->it_indirect; 4233 if (opnd_size_prefix == 0 && 4234 rep_prefix == 0xf3) { 4235 /* It is adox */ 4236 dp++; 4237 } else if (opnd_size_prefix != 0x66 && 4238 rep_prefix != 0) { 4239 /* It isn't adcx */ 4240 goto error; 4241 } 4242 opnd_size_prefix = 0; 4243 rep_prefix = 0; 4244 opnd_size = SIZE32; 4245 if (rex_prefix & REX_W) 4246 opnd_size = SIZE64; 4247 } 4248 4249 #ifdef DIS_TEXT 4250 if (strcmp(dp->it_name, "INVALID") == 0) 4251 goto error; 4252 #endif 4253 switch (dp->it_adrmode) { 4254 case ADX: 4255 case XMM: 4256 break; 4257 case RM_66r: 4258 case XMM_66r: 4259 case XMMM_66r: 4260 if (opnd_size_prefix == 0) { 4261 goto error; 4262 } 4263 break; 4264 case XMM_66o: 4265 if (opnd_size_prefix == 0) { 4266 /* SSSE3 MMX instructions */ 4267 dp_mmx = *dp; 4268 dp_mmx.it_adrmode = MM; 4269 #ifdef DIS_MEM 4270 dp_mmx.it_size = 8; 4271 #endif 4272 dp = &dp_mmx; 4273 } 4274 break; 4275 case CRC32: 4276 if (rep_prefix != 0xF2) { 4277 goto error; 4278 } 4279 rep_prefix = 0; 4280 break; 4281 case MOVBE: 4282 if (rep_prefix != 0x0) { 4283 goto error; 4284 } 4285 break; 4286 default: 4287 goto error; 4288 } 4289 } else if (rep_prefix == 0xf3 && opcode4 == 0 && opcode5 == 9) { 4290 rep_prefix = 0; 4291 dp = (instable_t *)&dis_opWbnoinvd; 4292 } else { 4293 dp = (instable_t *)&dis_op0F[opcode4][opcode5]; 4294 } 4295 } 4296 4297 /* 4298 * If still not at a TERM decode entry, then a ModRM byte 4299 * exists and its fields further decode the instruction. 4300 */ 4301 x->d86_got_modrm = 0; 4302 if (dp->it_indirect != TERM) { 4303 dtrace_get_modrm(x, &mode, &opcode3, &r_m); 4304 if (x->d86_error) 4305 goto error; 4306 reg = opcode3; 4307 4308 /* 4309 * decode 287 instructions (D8-DF) from opcodeN 4310 */ 4311 if (opcode1 == 0xD && opcode2 >= 0x8) { 4312 if (opcode2 == 0xB && mode == 0x3 && opcode3 == 4) 4313 dp = (instable_t *)&dis_opFP5[r_m]; 4314 else if (opcode2 == 0xA && mode == 0x3 && opcode3 < 4) 4315 dp = (instable_t *)&dis_opFP7[opcode3]; 4316 else if (opcode2 == 0xB && mode == 0x3) 4317 dp = (instable_t *)&dis_opFP6[opcode3]; 4318 else if (opcode2 == 0x9 && mode == 0x3 && opcode3 >= 4) 4319 dp = (instable_t *)&dis_opFP4[opcode3 - 4][r_m]; 4320 else if (mode == 0x3) 4321 dp = (instable_t *) 4322 &dis_opFP3[opcode2 - 8][opcode3]; 4323 else 4324 dp = (instable_t *) 4325 &dis_opFP1n2[opcode2 - 8][opcode3]; 4326 } else { 4327 dp = (instable_t *)dp->it_indirect + opcode3; 4328 } 4329 } 4330 4331 /* 4332 * In amd64 bit mode, ARPL opcode is changed to MOVSXD 4333 * (sign extend 32bit to 64 bit) 4334 */ 4335 if ((vex_prefix == 0) && cpu_mode == SIZE64 && 4336 opcode1 == 0x6 && opcode2 == 0x3) 4337 dp = (instable_t *)&dis_opMOVSLD; 4338 4339 /* 4340 * at this point we should have a correct (or invalid) opcode 4341 */ 4342 if (cpu_mode == SIZE64 && dp->it_invalid64 || 4343 cpu_mode != SIZE64 && dp->it_invalid32) 4344 goto error; 4345 if (dp->it_indirect != TERM) 4346 goto error; 4347 4348 /* 4349 * Deal with MMX/SSE opcodes which are changed by prefixes. Note, we do 4350 * need to include UNKNOWN below, as we may have instructions that 4351 * actually have a prefix, but don't exist in any other form. 4352 */ 4353 switch (dp->it_adrmode) { 4354 case UNKNOWN: 4355 case MMO: 4356 case MMOIMPL: 4357 case MMO3P: 4358 case MMOM3: 4359 case MMOMS: 4360 case MMOPM: 4361 case MMOPRM: 4362 case MMOS: 4363 case XMMO: 4364 case XMMOM: 4365 case XMMOMS: 4366 case XMMOPM: 4367 case XMMOS: 4368 case XMMOMX: 4369 case XMMOX3: 4370 case XMMOXMM: 4371 /* 4372 * This is horrible. Some SIMD instructions take the 4373 * form 0x0F 0x?? ..., which is easily decoded using the 4374 * existing tables. Other SIMD instructions use various 4375 * prefix bytes to overload existing instructions. For 4376 * Example, addps is F0, 58, whereas addss is F3 (repz), 4377 * F0, 58. Presumably someone got a raise for this. 4378 * 4379 * If we see one of the instructions which can be 4380 * modified in this way (if we've got one of the SIMDO* 4381 * address modes), we'll check to see if the last prefix 4382 * was a repz. If it was, we strip the prefix from the 4383 * mnemonic, and we indirect using the dis_opSIMDrepz 4384 * table. 4385 */ 4386 4387 /* 4388 * Calculate our offset in dis_op0F 4389 */ 4390 if ((uintptr_t)dp - (uintptr_t)dis_op0F > sizeof (dis_op0F)) 4391 goto error; 4392 4393 off = ((uintptr_t)dp - (uintptr_t)dis_op0F) / 4394 sizeof (instable_t); 4395 4396 /* 4397 * Rewrite if this instruction used one of the magic prefixes. 4398 */ 4399 if (rep_prefix) { 4400 if (rep_prefix == 0xf2) 4401 dp = (instable_t *)&dis_opSIMDrepnz[off]; 4402 else 4403 dp = (instable_t *)&dis_opSIMDrepz[off]; 4404 rep_prefix = 0; 4405 } else if (opnd_size_prefix) { 4406 dp = (instable_t *)&dis_opSIMDdata16[off]; 4407 opnd_size_prefix = 0; 4408 if (opnd_size == SIZE16) 4409 opnd_size = SIZE32; 4410 } 4411 break; 4412 4413 case MG9: 4414 /* 4415 * More horribleness: the group 9 (0xF0 0xC7) instructions are 4416 * allowed an optional prefix of 0x66 or 0xF3. This is similar 4417 * to the SIMD business described above, but with a different 4418 * addressing mode (and an indirect table), so we deal with it 4419 * separately (if similarly). 4420 * 4421 * Intel further complicated this with the release of Ivy Bridge 4422 * where they overloaded these instructions based on the ModR/M 4423 * bytes. The VMX instructions have a mode of 0 since they are 4424 * memory instructions but rdrand instructions have a mode of 4425 * 0b11 (REG_ONLY) because they only operate on registers. While 4426 * there are different prefix formats, for now it is sufficient 4427 * to use a single different table. 4428 */ 4429 4430 /* 4431 * Calculate our offset in dis_op0FC7 (the group 9 table) 4432 */ 4433 if ((uintptr_t)dp - (uintptr_t)dis_op0FC7 > sizeof (dis_op0FC7)) 4434 goto error; 4435 4436 off = ((uintptr_t)dp - (uintptr_t)dis_op0FC7) / 4437 sizeof (instable_t); 4438 4439 /* 4440 * If we have a mode of 0b11 then we have to rewrite this. 4441 */ 4442 dtrace_get_modrm(x, &mode, ®, &r_m); 4443 if (mode == REG_ONLY) { 4444 dp = (instable_t *)&dis_op0FC7m3[off]; 4445 break; 4446 } 4447 4448 /* 4449 * Rewrite if this instruction used one of the magic prefixes. 4450 */ 4451 if (rep_prefix) { 4452 if (rep_prefix == 0xf3) 4453 dp = (instable_t *)&dis_opF30FC7[off]; 4454 else 4455 goto error; 4456 rep_prefix = 0; 4457 } else if (opnd_size_prefix) { 4458 dp = (instable_t *)&dis_op660FC7[off]; 4459 opnd_size_prefix = 0; 4460 if (opnd_size == SIZE16) 4461 opnd_size = SIZE32; 4462 } else if (reg == 4 || reg == 5) { 4463 /* 4464 * We have xsavec (4) or xsaves (5), so rewrite. 4465 */ 4466 dp = (instable_t *)&dis_op0FC7[reg]; 4467 break; 4468 } 4469 break; 4470 4471 4472 case MMOSH: 4473 /* 4474 * As with the "normal" SIMD instructions, the MMX 4475 * shuffle instructions are overloaded. These 4476 * instructions, however, are special in that they use 4477 * an extra byte, and thus an extra table. As of this 4478 * writing, they only use the opnd_size prefix. 4479 */ 4480 4481 /* 4482 * Calculate our offset in dis_op0F7123 4483 */ 4484 if ((uintptr_t)dp - (uintptr_t)dis_op0F7123 > 4485 sizeof (dis_op0F7123)) 4486 goto error; 4487 4488 if (opnd_size_prefix) { 4489 off = ((uintptr_t)dp - (uintptr_t)dis_op0F7123) / 4490 sizeof (instable_t); 4491 dp = (instable_t *)&dis_opSIMD7123[off]; 4492 opnd_size_prefix = 0; 4493 if (opnd_size == SIZE16) 4494 opnd_size = SIZE32; 4495 } 4496 break; 4497 case MRw: 4498 if (rep_prefix) { 4499 if (rep_prefix == 0xf3) { 4500 4501 /* 4502 * Calculate our offset in dis_op0F 4503 */ 4504 if ((uintptr_t)dp - (uintptr_t)dis_op0F > 4505 sizeof (dis_op0F)) 4506 goto error; 4507 4508 off = ((uintptr_t)dp - (uintptr_t)dis_op0F) / 4509 sizeof (instable_t); 4510 4511 dp = (instable_t *)&dis_opSIMDrepz[off]; 4512 rep_prefix = 0; 4513 } else { 4514 goto error; 4515 } 4516 } 4517 break; 4518 case FSGS: 4519 if (rep_prefix == 0xf3) { 4520 if ((uintptr_t)dp - (uintptr_t)dis_op0FAE > 4521 sizeof (dis_op0FAE)) 4522 goto error; 4523 4524 off = ((uintptr_t)dp - (uintptr_t)dis_op0FAE) / 4525 sizeof (instable_t); 4526 dp = (instable_t *)&dis_opF30FAE[off]; 4527 rep_prefix = 0; 4528 } else if (rep_prefix != 0x00) { 4529 goto error; 4530 } 4531 } 4532 4533 /* 4534 * In 64 bit mode, some opcodes automatically use opnd_size == SIZE64. 4535 */ 4536 if (cpu_mode == SIZE64) 4537 if (dp->it_always64 || (opnd_size == SIZE32 && dp->it_stackop)) 4538 opnd_size = SIZE64; 4539 4540 #ifdef DIS_TEXT 4541 /* 4542 * At this point most instructions can format the opcode mnemonic 4543 * including the prefixes. 4544 */ 4545 if (lock_prefix) 4546 (void) strlcat(x->d86_mnem, "lock ", OPLEN); 4547 4548 if (rep_prefix == 0xf2) 4549 (void) strlcat(x->d86_mnem, "repnz ", OPLEN); 4550 else if (rep_prefix == 0xf3) 4551 (void) strlcat(x->d86_mnem, "repz ", OPLEN); 4552 4553 if (cpu_mode == SIZE64 && addr_size_prefix) 4554 (void) strlcat(x->d86_mnem, "addr32 ", OPLEN); 4555 4556 if (dp->it_adrmode != CBW && 4557 dp->it_adrmode != CWD && 4558 dp->it_adrmode != XMMSFNC) { 4559 if (strcmp(dp->it_name, "INVALID") == 0) 4560 goto error; 4561 (void) strlcat(x->d86_mnem, dp->it_name, OPLEN); 4562 if (dp->it_avxsuf == AVS2 && dp->it_suffix) { 4563 (void) strlcat(x->d86_mnem, vex_W != 0 ? "q" : "d", 4564 OPLEN); 4565 } else if (dp->it_vexopmask && dp->it_suffix) { 4566 /* opmask instructions */ 4567 4568 if (opcode1 == 4 && opcode2 == 0xb) { 4569 /* It's a kunpck. */ 4570 if (vex_prefix == VEX_2bytes) { 4571 (void) strlcat(x->d86_mnem, 4572 vex_p == 0 ? "wd" : "bw", OPLEN); 4573 } else { 4574 /* vex_prefix == VEX_3bytes */ 4575 (void) strlcat(x->d86_mnem, 4576 "dq", OPLEN); 4577 } 4578 } else if (opcode1 == 3) { 4579 /* It's a kshift[l|r]. */ 4580 if (vex_W == 0) { 4581 (void) strlcat(x->d86_mnem, 4582 opcode2 == 2 || 4583 opcode2 == 0 ? 4584 "b" : "d", OPLEN); 4585 } else { 4586 /* W == 1 */ 4587 (void) strlcat(x->d86_mnem, 4588 opcode2 == 3 || opcode2 == 1 ? 4589 "q" : "w", OPLEN); 4590 } 4591 } else { 4592 /* if (vex_prefix == VEX_2bytes) { */ 4593 if ((cpu_mode == SIZE64 && opnd_size == 2) || 4594 vex_prefix == VEX_2bytes) { 4595 (void) strlcat(x->d86_mnem, 4596 vex_p == 0 ? "w" : 4597 vex_p == 1 ? "b" : "d", 4598 OPLEN); 4599 } else { 4600 /* vex_prefix == VEX_3bytes */ 4601 (void) strlcat(x->d86_mnem, 4602 vex_p == 1 ? "d" : "q", OPLEN); 4603 } 4604 } 4605 } else if (dp->it_suffix) { 4606 char *types[] = {"", "w", "l", "q"}; 4607 if (opcode_bytes == 2 && opcode4 == 4) { 4608 /* It's a cmovx.yy. Replace the suffix x */ 4609 for (i = 5; i < OPLEN; i++) { 4610 if (x->d86_mnem[i] == '.') 4611 break; 4612 } 4613 x->d86_mnem[i - 1] = *types[opnd_size]; 4614 } else if ((opnd_size == 2) && (opcode_bytes == 3) && 4615 ((opcode6 == 1 && opcode7 == 6) || 4616 (opcode6 == 2 && opcode7 == 2))) { 4617 /* 4618 * To handle PINSRD and PEXTRD 4619 */ 4620 (void) strlcat(x->d86_mnem, "d", OPLEN); 4621 } else if (dp != &dis_distable[0x6][0x2]) { 4622 /* bound instructions (0x62) have no suffix */ 4623 (void) strlcat(x->d86_mnem, types[opnd_size], 4624 OPLEN); 4625 } 4626 } 4627 } 4628 #endif 4629 4630 /* 4631 * Process operands based on the addressing modes. 4632 */ 4633 x->d86_mode = cpu_mode; 4634 /* 4635 * In vex mode the rex_prefix has no meaning 4636 */ 4637 if (!vex_prefix && evex_prefix == 0) 4638 x->d86_rex_prefix = rex_prefix; 4639 x->d86_opnd_size = opnd_size; 4640 x->d86_addr_size = addr_size; 4641 vbit = 0; /* initialize for mem/reg -> reg */ 4642 switch (dp->it_adrmode) { 4643 /* 4644 * amd64 instruction to sign extend 32 bit reg/mem operands 4645 * into 64 bit register values 4646 */ 4647 case MOVSXZ: 4648 #ifdef DIS_TEXT 4649 if (rex_prefix == 0) 4650 (void) strncpy(x->d86_mnem, "movzld", OPLEN); 4651 #endif 4652 dtrace_get_modrm(x, &mode, ®, &r_m); 4653 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 4654 x->d86_opnd_size = SIZE64; 4655 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1); 4656 x->d86_opnd_size = opnd_size = SIZE32; 4657 wbit = LONG_OPND; 4658 dtrace_get_operand(x, mode, r_m, wbit, 0); 4659 break; 4660 4661 /* 4662 * movsbl movsbw movsbq (0x0FBE) or movswl movswq (0x0FBF) 4663 * movzbl movzbw movzbq (0x0FB6) or movzwl movzwq (0x0FB7) 4664 * wbit lives in 2nd byte, note that operands 4665 * are different sized 4666 */ 4667 case MOVZ: 4668 if (rex_prefix & REX_W) { 4669 /* target register size = 64 bit */ 4670 x->d86_mnem[5] = 'q'; 4671 } 4672 dtrace_get_modrm(x, &mode, ®, &r_m); 4673 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 4674 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1); 4675 x->d86_opnd_size = opnd_size = SIZE16; 4676 wbit = WBIT(opcode5); 4677 dtrace_get_operand(x, mode, r_m, wbit, 0); 4678 break; 4679 case CRC32: 4680 opnd_size = SIZE32; 4681 if (rex_prefix & REX_W) 4682 opnd_size = SIZE64; 4683 x->d86_opnd_size = opnd_size; 4684 4685 dtrace_get_modrm(x, &mode, ®, &r_m); 4686 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 4687 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1); 4688 wbit = WBIT(opcode7); 4689 if (opnd_size_prefix) 4690 x->d86_opnd_size = opnd_size = SIZE16; 4691 dtrace_get_operand(x, mode, r_m, wbit, 0); 4692 break; 4693 case MOVBE: 4694 opnd_size = SIZE32; 4695 if (rex_prefix & REX_W) 4696 opnd_size = SIZE64; 4697 x->d86_opnd_size = opnd_size; 4698 4699 dtrace_get_modrm(x, &mode, ®, &r_m); 4700 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 4701 wbit = WBIT(opcode7); 4702 if (opnd_size_prefix) 4703 x->d86_opnd_size = opnd_size = SIZE16; 4704 if (wbit) { 4705 /* reg -> mem */ 4706 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 0); 4707 dtrace_get_operand(x, mode, r_m, wbit, 1); 4708 } else { 4709 /* mem -> reg */ 4710 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1); 4711 dtrace_get_operand(x, mode, r_m, wbit, 0); 4712 } 4713 break; 4714 4715 /* 4716 * imul instruction, with either 8-bit or longer immediate 4717 * opcode 0x6B for byte, sign-extended displacement, 0x69 for word(s) 4718 */ 4719 case IMUL: 4720 wbit = LONG_OPND; 4721 THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, LONG_OPND, 4722 OPSIZE(opnd_size, opcode2 == 0x9), 1); 4723 break; 4724 4725 /* memory or register operand to register, with 'w' bit */ 4726 case MRw: 4727 case ADX: 4728 wbit = WBIT(opcode2); 4729 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 0); 4730 break; 4731 4732 /* register to memory or register operand, with 'w' bit */ 4733 /* arpl happens to fit here also because it is odd */ 4734 case RMw: 4735 if (opcode_bytes == 2) 4736 wbit = WBIT(opcode5); 4737 else 4738 wbit = WBIT(opcode2); 4739 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 1); 4740 break; 4741 4742 /* xaddb instruction */ 4743 case XADDB: 4744 wbit = 0; 4745 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 1); 4746 break; 4747 4748 /* MMX register to memory or register operand */ 4749 case MMS: 4750 case MMOS: 4751 #ifdef DIS_TEXT 4752 wbit = strcmp(dp->it_name, "movd") ? MM_OPND : LONG_OPND; 4753 #else 4754 wbit = LONG_OPND; 4755 #endif 4756 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, MM_OPND, 1); 4757 break; 4758 4759 /* MMX register to memory */ 4760 case MMOMS: 4761 dtrace_get_modrm(x, &mode, ®, &r_m); 4762 if (mode == REG_ONLY) 4763 goto error; 4764 wbit = MM_OPND; 4765 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, MM_OPND, 1); 4766 break; 4767 4768 /* Double shift. Has immediate operand specifying the shift. */ 4769 case DSHIFT: 4770 wbit = LONG_OPND; 4771 dtrace_get_modrm(x, &mode, ®, &r_m); 4772 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 4773 dtrace_get_operand(x, mode, r_m, wbit, 2); 4774 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1); 4775 dtrace_imm_opnd(x, wbit, 1, 0); 4776 break; 4777 4778 /* 4779 * Double shift. With no immediate operand, specifies using %cl. 4780 */ 4781 case DSHIFTcl: 4782 wbit = LONG_OPND; 4783 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 1); 4784 break; 4785 4786 /* immediate to memory or register operand */ 4787 case IMlw: 4788 wbit = WBIT(opcode2); 4789 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 4790 dtrace_get_operand(x, mode, r_m, wbit, 1); 4791 /* 4792 * Have long immediate for opcode 0x81, but not 0x80 nor 0x83 4793 */ 4794 dtrace_imm_opnd(x, wbit, OPSIZE(opnd_size, opcode2 == 1), 0); 4795 break; 4796 4797 /* immediate to memory or register operand with the */ 4798 /* 'w' bit present */ 4799 case IMw: 4800 wbit = WBIT(opcode2); 4801 dtrace_get_modrm(x, &mode, ®, &r_m); 4802 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 4803 dtrace_get_operand(x, mode, r_m, wbit, 1); 4804 dtrace_imm_opnd(x, wbit, OPSIZE(opnd_size, wbit), 0); 4805 break; 4806 4807 /* immediate to register with register in low 3 bits */ 4808 /* of op code */ 4809 case IR: 4810 /* w-bit here (with regs) is bit 3 */ 4811 wbit = opcode2 >>3 & 0x1; 4812 reg = REGNO(opcode2); 4813 dtrace_rex_adjust(rex_prefix, mode, ®, NULL); 4814 mode = REG_ONLY; 4815 r_m = reg; 4816 dtrace_get_operand(x, mode, r_m, wbit, 1); 4817 dtrace_imm_opnd(x, wbit, OPSIZE64(opnd_size, wbit), 0); 4818 break; 4819 4820 /* MMX immediate shift of register */ 4821 case MMSH: 4822 case MMOSH: 4823 wbit = MM_OPND; 4824 goto mm_shift; /* in next case */ 4825 4826 /* SIMD immediate shift of register */ 4827 case XMMSH: 4828 wbit = XMM_OPND; 4829 mm_shift: 4830 reg = REGNO(opcode7); 4831 dtrace_rex_adjust(rex_prefix, mode, ®, NULL); 4832 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 4833 dtrace_imm_opnd(x, wbit, 1, 0); 4834 NOMEM; 4835 break; 4836 4837 /* accumulator to memory operand */ 4838 case AO: 4839 vbit = 1; 4840 /*FALLTHROUGH*/ 4841 4842 /* memory operand to accumulator */ 4843 case OA: 4844 wbit = WBIT(opcode2); 4845 dtrace_get_operand(x, REG_ONLY, EAX_REGNO, wbit, 1 - vbit); 4846 dtrace_imm_opnd(x, wbit, OPSIZE64(addr_size, LONG_OPND), vbit); 4847 #ifdef DIS_TEXT 4848 x->d86_opnd[vbit].d86_mode = MODE_OFFSET; 4849 #endif 4850 break; 4851 4852 4853 /* segment register to memory or register operand */ 4854 case SM: 4855 vbit = 1; 4856 /*FALLTHROUGH*/ 4857 4858 /* memory or register operand to segment register */ 4859 case MS: 4860 dtrace_get_modrm(x, &mode, ®, &r_m); 4861 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 4862 dtrace_get_operand(x, mode, r_m, LONG_OPND, vbit); 4863 dtrace_get_operand(x, REG_ONLY, reg, SEG_OPND, 1 - vbit); 4864 break; 4865 4866 /* 4867 * rotate or shift instructions, which may shift by 1 or 4868 * consult the cl register, depending on the 'v' bit 4869 */ 4870 case Mv: 4871 vbit = VBIT(opcode2); 4872 wbit = WBIT(opcode2); 4873 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 4874 dtrace_get_operand(x, mode, r_m, wbit, 1); 4875 #ifdef DIS_TEXT 4876 if (vbit) { 4877 (void) strlcat(x->d86_opnd[0].d86_opnd, "%cl", OPLEN); 4878 } else { 4879 x->d86_opnd[0].d86_mode = MODE_SIGNED; 4880 x->d86_opnd[0].d86_value_size = 1; 4881 x->d86_opnd[0].d86_value = 1; 4882 } 4883 #endif 4884 break; 4885 /* 4886 * immediate rotate or shift instructions 4887 */ 4888 case MvI: 4889 wbit = WBIT(opcode2); 4890 normal_imm_mem: 4891 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 4892 dtrace_get_operand(x, mode, r_m, wbit, 1); 4893 dtrace_imm_opnd(x, wbit, 1, 0); 4894 break; 4895 4896 /* bit test instructions */ 4897 case MIb: 4898 wbit = LONG_OPND; 4899 goto normal_imm_mem; 4900 4901 /* single memory or register operand with 'w' bit present */ 4902 case Mw: 4903 wbit = WBIT(opcode2); 4904 just_mem: 4905 dtrace_get_modrm(x, &mode, ®, &r_m); 4906 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 4907 dtrace_get_operand(x, mode, r_m, wbit, 0); 4908 break; 4909 4910 case SWAPGS_RDTSCP: 4911 if (cpu_mode == SIZE64 && mode == 3 && r_m == 0) { 4912 #ifdef DIS_TEXT 4913 (void) strncpy(x->d86_mnem, "swapgs", OPLEN); 4914 #endif 4915 NOMEM; 4916 break; 4917 } else if (mode == 3 && r_m == 1) { 4918 #ifdef DIS_TEXT 4919 (void) strncpy(x->d86_mnem, "rdtscp", OPLEN); 4920 #endif 4921 NOMEM; 4922 break; 4923 } else if (mode == 3 && r_m == 2) { 4924 #ifdef DIS_TEXT 4925 (void) strncpy(x->d86_mnem, "monitorx", OPLEN); 4926 #endif 4927 NOMEM; 4928 break; 4929 } else if (mode == 3 && r_m == 3) { 4930 #ifdef DIS_TEXT 4931 (void) strncpy(x->d86_mnem, "mwaitx", OPLEN); 4932 #endif 4933 NOMEM; 4934 break; 4935 } else if (mode == 3 && r_m == 4) { 4936 #ifdef DIS_TEXT 4937 (void) strncpy(x->d86_mnem, "clzero", OPLEN); 4938 #endif 4939 NOMEM; 4940 break; 4941 } 4942 4943 /*FALLTHROUGH*/ 4944 4945 /* prefetch instruction - memory operand, but no memory acess */ 4946 case PREF: 4947 NOMEM; 4948 /*FALLTHROUGH*/ 4949 4950 /* single memory or register operand */ 4951 case M: 4952 case MG9: 4953 wbit = LONG_OPND; 4954 goto just_mem; 4955 4956 /* single memory or register byte operand */ 4957 case Mb: 4958 wbit = BYTE_OPND; 4959 goto just_mem; 4960 4961 case VMx: 4962 if (mode == 3) { 4963 #ifdef DIS_TEXT 4964 char *vminstr; 4965 4966 switch (r_m) { 4967 case 1: 4968 vminstr = "vmcall"; 4969 break; 4970 case 2: 4971 vminstr = "vmlaunch"; 4972 break; 4973 case 3: 4974 vminstr = "vmresume"; 4975 break; 4976 case 4: 4977 vminstr = "vmxoff"; 4978 break; 4979 default: 4980 goto error; 4981 } 4982 4983 (void) strncpy(x->d86_mnem, vminstr, OPLEN); 4984 #else 4985 if (r_m < 1 || r_m > 4) 4986 goto error; 4987 #endif 4988 4989 NOMEM; 4990 break; 4991 } 4992 /*FALLTHROUGH*/ 4993 case SVM: 4994 if (mode == 3) { 4995 #ifdef DIS_TEXT 4996 char *vinstr; 4997 4998 switch (r_m) { 4999 case 0: 5000 vinstr = "vmrun"; 5001 break; 5002 case 1: 5003 vinstr = "vmmcall"; 5004 break; 5005 case 2: 5006 vinstr = "vmload"; 5007 break; 5008 case 3: 5009 vinstr = "vmsave"; 5010 break; 5011 case 4: 5012 vinstr = "stgi"; 5013 break; 5014 case 5: 5015 vinstr = "clgi"; 5016 break; 5017 case 6: 5018 vinstr = "skinit"; 5019 break; 5020 case 7: 5021 vinstr = "invlpga"; 5022 break; 5023 } 5024 5025 (void) strncpy(x->d86_mnem, vinstr, OPLEN); 5026 #endif 5027 NOMEM; 5028 break; 5029 } 5030 /*FALLTHROUGH*/ 5031 case MONITOR_MWAIT: 5032 if (mode == 3) { 5033 if (r_m == 0) { 5034 #ifdef DIS_TEXT 5035 (void) strncpy(x->d86_mnem, "monitor", OPLEN); 5036 #endif 5037 NOMEM; 5038 break; 5039 } else if (r_m == 1) { 5040 #ifdef DIS_TEXT 5041 (void) strncpy(x->d86_mnem, "mwait", OPLEN); 5042 #endif 5043 NOMEM; 5044 break; 5045 } else if (r_m == 2) { 5046 #ifdef DIS_TEXT 5047 (void) strncpy(x->d86_mnem, "clac", OPLEN); 5048 #endif 5049 NOMEM; 5050 break; 5051 } else if (r_m == 3) { 5052 #ifdef DIS_TEXT 5053 (void) strncpy(x->d86_mnem, "stac", OPLEN); 5054 #endif 5055 NOMEM; 5056 break; 5057 } else { 5058 goto error; 5059 } 5060 } 5061 /*FALLTHROUGH*/ 5062 case XGETBV_XSETBV: 5063 if (mode == 3) { 5064 if (r_m == 0) { 5065 #ifdef DIS_TEXT 5066 (void) strncpy(x->d86_mnem, "xgetbv", OPLEN); 5067 #endif 5068 NOMEM; 5069 break; 5070 } else if (r_m == 1) { 5071 #ifdef DIS_TEXT 5072 (void) strncpy(x->d86_mnem, "xsetbv", OPLEN); 5073 #endif 5074 NOMEM; 5075 break; 5076 } else { 5077 goto error; 5078 } 5079 5080 } 5081 /*FALLTHROUGH*/ 5082 case MO: 5083 /* Similar to M, but only memory (no direct registers) */ 5084 wbit = LONG_OPND; 5085 dtrace_get_modrm(x, &mode, ®, &r_m); 5086 if (mode == 3) 5087 goto error; 5088 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 5089 dtrace_get_operand(x, mode, r_m, wbit, 0); 5090 break; 5091 5092 /* move special register to register or reverse if vbit */ 5093 case SREG: 5094 switch (opcode5) { 5095 5096 case 2: 5097 vbit = 1; 5098 /*FALLTHROUGH*/ 5099 case 0: 5100 wbit = CONTROL_OPND; 5101 break; 5102 5103 case 3: 5104 vbit = 1; 5105 /*FALLTHROUGH*/ 5106 case 1: 5107 wbit = DEBUG_OPND; 5108 break; 5109 5110 case 6: 5111 vbit = 1; 5112 /*FALLTHROUGH*/ 5113 case 4: 5114 wbit = TEST_OPND; 5115 break; 5116 5117 } 5118 dtrace_get_modrm(x, &mode, ®, &r_m); 5119 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 5120 dtrace_get_operand(x, REG_ONLY, reg, wbit, vbit); 5121 dtrace_get_operand(x, REG_ONLY, r_m, LONG_OPND, 1 - vbit); 5122 NOMEM; 5123 break; 5124 5125 /* 5126 * single register operand with register in the low 3 5127 * bits of op code 5128 */ 5129 case R: 5130 if (opcode_bytes == 2) 5131 reg = REGNO(opcode5); 5132 else 5133 reg = REGNO(opcode2); 5134 dtrace_rex_adjust(rex_prefix, mode, ®, NULL); 5135 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 0); 5136 NOMEM; 5137 break; 5138 5139 /* 5140 * register to accumulator with register in the low 3 5141 * bits of op code, xchg instructions 5142 */ 5143 case RA: 5144 NOMEM; 5145 reg = REGNO(opcode2); 5146 dtrace_rex_adjust(rex_prefix, mode, ®, NULL); 5147 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 0); 5148 dtrace_get_operand(x, REG_ONLY, EAX_REGNO, LONG_OPND, 1); 5149 break; 5150 5151 /* 5152 * single segment register operand, with register in 5153 * bits 3-4 of op code byte 5154 */ 5155 case SEG: 5156 NOMEM; 5157 reg = (x->d86_bytes[x->d86_len - 1] >> 3) & 0x3; 5158 dtrace_get_operand(x, REG_ONLY, reg, SEG_OPND, 0); 5159 break; 5160 5161 /* 5162 * single segment register operand, with register in 5163 * bits 3-5 of op code 5164 */ 5165 case LSEG: 5166 NOMEM; 5167 /* long seg reg from opcode */ 5168 reg = (x->d86_bytes[x->d86_len - 1] >> 3) & 0x7; 5169 dtrace_get_operand(x, REG_ONLY, reg, SEG_OPND, 0); 5170 break; 5171 5172 /* memory or register operand to register */ 5173 case MR: 5174 if (vex_prefetch) 5175 x->d86_got_modrm = 1; 5176 wbit = LONG_OPND; 5177 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 0); 5178 break; 5179 5180 case RM: 5181 case RM_66r: 5182 if (vex_prefetch) 5183 x->d86_got_modrm = 1; 5184 wbit = LONG_OPND; 5185 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 1); 5186 break; 5187 5188 /* MMX/SIMD-Int memory or mm reg to mm reg */ 5189 case MM: 5190 case MMO: 5191 #ifdef DIS_TEXT 5192 wbit = strcmp(dp->it_name, "movd") ? MM_OPND : LONG_OPND; 5193 #else 5194 wbit = LONG_OPND; 5195 #endif 5196 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, MM_OPND, 0); 5197 break; 5198 5199 case MMOIMPL: 5200 #ifdef DIS_TEXT 5201 wbit = strcmp(dp->it_name, "movd") ? MM_OPND : LONG_OPND; 5202 #else 5203 wbit = LONG_OPND; 5204 #endif 5205 dtrace_get_modrm(x, &mode, ®, &r_m); 5206 if (mode != REG_ONLY) 5207 goto error; 5208 5209 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 5210 dtrace_get_operand(x, mode, r_m, wbit, 0); 5211 dtrace_get_operand(x, REG_ONLY, reg, MM_OPND, 1); 5212 mode = 0; /* change for memory access size... */ 5213 break; 5214 5215 /* MMX/SIMD-Int and SIMD-FP predicated mm reg to r32 */ 5216 case MMO3P: 5217 wbit = MM_OPND; 5218 goto xmm3p; 5219 case XMM3P: 5220 wbit = XMM_OPND; 5221 xmm3p: 5222 dtrace_get_modrm(x, &mode, ®, &r_m); 5223 if (mode != REG_ONLY) 5224 goto error; 5225 5226 THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, LONG_OPND, 1, 5227 1); 5228 NOMEM; 5229 break; 5230 5231 case XMM3PM_66r: 5232 THREEOPERAND(x, mode, reg, r_m, rex_prefix, LONG_OPND, XMM_OPND, 5233 1, 0); 5234 break; 5235 5236 /* MMX/SIMD-Int predicated r32/mem to mm reg */ 5237 case MMOPRM: 5238 wbit = LONG_OPND; 5239 w2 = MM_OPND; 5240 goto xmmprm; 5241 case XMMPRM: 5242 case XMMPRM_66r: 5243 wbit = LONG_OPND; 5244 w2 = XMM_OPND; 5245 xmmprm: 5246 THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, w2, 1, 1); 5247 break; 5248 5249 /* MMX/SIMD-Int predicated mm/mem to mm reg */ 5250 case MMOPM: 5251 case MMOPM_66o: 5252 wbit = w2 = MM_OPND; 5253 goto xmmprm; 5254 5255 /* MMX/SIMD-Int mm reg to r32 */ 5256 case MMOM3: 5257 NOMEM; 5258 dtrace_get_modrm(x, &mode, ®, &r_m); 5259 if (mode != REG_ONLY) 5260 goto error; 5261 wbit = MM_OPND; 5262 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, LONG_OPND, 0); 5263 break; 5264 5265 /* SIMD memory or xmm reg operand to xmm reg */ 5266 case XMM: 5267 case XMM_66o: 5268 case XMM_66r: 5269 case XMMO: 5270 case XMMXIMPL: 5271 wbit = XMM_OPND; 5272 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 0); 5273 5274 if (dp->it_adrmode == XMMXIMPL && mode != REG_ONLY) 5275 goto error; 5276 5277 #ifdef DIS_TEXT 5278 /* 5279 * movlps and movhlps share opcodes. They differ in the 5280 * addressing modes allowed for their operands. 5281 * movhps and movlhps behave similarly. 5282 */ 5283 if (mode == REG_ONLY) { 5284 if (strcmp(dp->it_name, "movlps") == 0) 5285 (void) strncpy(x->d86_mnem, "movhlps", OPLEN); 5286 else if (strcmp(dp->it_name, "movhps") == 0) 5287 (void) strncpy(x->d86_mnem, "movlhps", OPLEN); 5288 } 5289 #endif 5290 if (dp->it_adrmode == XMMXIMPL) 5291 mode = 0; /* change for memory access size... */ 5292 break; 5293 5294 /* SIMD xmm reg to memory or xmm reg */ 5295 case XMMS: 5296 case XMMOS: 5297 case XMMMS: 5298 case XMMOMS: 5299 dtrace_get_modrm(x, &mode, ®, &r_m); 5300 #ifdef DIS_TEXT 5301 if ((strcmp(dp->it_name, "movlps") == 0 || 5302 strcmp(dp->it_name, "movhps") == 0 || 5303 strcmp(dp->it_name, "movntps") == 0) && 5304 mode == REG_ONLY) 5305 goto error; 5306 #endif 5307 wbit = XMM_OPND; 5308 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 1); 5309 break; 5310 5311 /* SIMD memory to xmm reg */ 5312 case XMMM: 5313 case XMMM_66r: 5314 case XMMOM: 5315 wbit = XMM_OPND; 5316 dtrace_get_modrm(x, &mode, ®, &r_m); 5317 #ifdef DIS_TEXT 5318 if (mode == REG_ONLY) { 5319 if (strcmp(dp->it_name, "movhps") == 0) 5320 (void) strncpy(x->d86_mnem, "movlhps", OPLEN); 5321 else 5322 goto error; 5323 } 5324 #endif 5325 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 0); 5326 break; 5327 5328 /* SIMD memory or r32 to xmm reg */ 5329 case XMM3MX: 5330 wbit = LONG_OPND; 5331 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 0); 5332 break; 5333 5334 case XMM3MXS: 5335 wbit = LONG_OPND; 5336 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 1); 5337 break; 5338 5339 /* SIMD memory or mm reg to xmm reg */ 5340 case XMMOMX: 5341 /* SIMD mm to xmm */ 5342 case XMMMX: 5343 wbit = MM_OPND; 5344 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 0); 5345 break; 5346 5347 /* SIMD memory or xmm reg to mm reg */ 5348 case XMMXMM: 5349 case XMMOXMM: 5350 case XMMXM: 5351 wbit = XMM_OPND; 5352 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, MM_OPND, 0); 5353 break; 5354 5355 5356 /* SIMD memory or xmm reg to r32 */ 5357 case XMMXM3: 5358 wbit = XMM_OPND; 5359 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, LONG_OPND, 0); 5360 break; 5361 5362 /* SIMD xmm to r32 */ 5363 case XMMX3: 5364 case XMMOX3: 5365 dtrace_get_modrm(x, &mode, ®, &r_m); 5366 if (mode != REG_ONLY) 5367 goto error; 5368 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 5369 dtrace_get_operand(x, mode, r_m, XMM_OPND, 0); 5370 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1); 5371 NOMEM; 5372 break; 5373 5374 /* SIMD predicated memory or xmm reg with/to xmm reg */ 5375 case XMMP: 5376 case XMMP_66r: 5377 case XMMP_66o: 5378 case XMMOPM: 5379 wbit = XMM_OPND; 5380 THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 1, 5381 1); 5382 5383 #ifdef DIS_TEXT 5384 /* 5385 * cmpps and cmpss vary their instruction name based 5386 * on the value of imm8. Other XMMP instructions, 5387 * such as shufps, require explicit specification of 5388 * the predicate. 5389 */ 5390 if (dp->it_name[0] == 'c' && 5391 dp->it_name[1] == 'm' && 5392 dp->it_name[2] == 'p' && 5393 strlen(dp->it_name) == 5) { 5394 uchar_t pred = x->d86_opnd[0].d86_value & 0xff; 5395 5396 if (pred >= (sizeof (dis_PREDSUFFIX) / sizeof (char *))) 5397 goto error; 5398 5399 (void) strncpy(x->d86_mnem, "cmp", OPLEN); 5400 (void) strlcat(x->d86_mnem, dis_PREDSUFFIX[pred], 5401 OPLEN); 5402 (void) strlcat(x->d86_mnem, 5403 dp->it_name + strlen(dp->it_name) - 2, 5404 OPLEN); 5405 x->d86_opnd[0] = x->d86_opnd[1]; 5406 x->d86_opnd[1] = x->d86_opnd[2]; 5407 x->d86_numopnds = 2; 5408 } 5409 5410 /* 5411 * The pclmulqdq instruction has a series of alternate names for 5412 * various encodings of the immediate byte. As such, if we 5413 * happen to find it and the immediate value matches, we'll 5414 * rewrite the mnemonic. 5415 */ 5416 if (strcmp(dp->it_name, "pclmulqdq") == 0) { 5417 boolean_t changed = B_TRUE; 5418 switch (x->d86_opnd[0].d86_value) { 5419 case 0x00: 5420 (void) strncpy(x->d86_mnem, "pclmullqlqdq", 5421 OPLEN); 5422 break; 5423 case 0x01: 5424 (void) strncpy(x->d86_mnem, "pclmulhqlqdq", 5425 OPLEN); 5426 break; 5427 case 0x10: 5428 (void) strncpy(x->d86_mnem, "pclmullqhqdq", 5429 OPLEN); 5430 break; 5431 case 0x11: 5432 (void) strncpy(x->d86_mnem, "pclmulhqhqdq", 5433 OPLEN); 5434 break; 5435 default: 5436 changed = B_FALSE; 5437 break; 5438 } 5439 5440 if (changed == B_TRUE) { 5441 x->d86_opnd[0].d86_value_size = 0; 5442 x->d86_opnd[0] = x->d86_opnd[1]; 5443 x->d86_opnd[1] = x->d86_opnd[2]; 5444 x->d86_numopnds = 2; 5445 } 5446 } 5447 #endif 5448 break; 5449 5450 case XMMX2I: 5451 FOUROPERAND(x, mode, reg, r_m, rex_prefix, XMM_OPND, XMM_OPND, 5452 1); 5453 NOMEM; 5454 break; 5455 5456 case XMM2I: 5457 ONEOPERAND_TWOIMM(x, mode, reg, r_m, rex_prefix, XMM_OPND, 1); 5458 NOMEM; 5459 break; 5460 5461 /* immediate operand to accumulator */ 5462 case IA: 5463 wbit = WBIT(opcode2); 5464 dtrace_get_operand(x, REG_ONLY, EAX_REGNO, wbit, 1); 5465 dtrace_imm_opnd(x, wbit, OPSIZE(opnd_size, wbit), 0); 5466 NOMEM; 5467 break; 5468 5469 /* memory or register operand to accumulator */ 5470 case MA: 5471 wbit = WBIT(opcode2); 5472 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 5473 dtrace_get_operand(x, mode, r_m, wbit, 0); 5474 break; 5475 5476 /* si register to di register used to reference memory */ 5477 case SD: 5478 #ifdef DIS_TEXT 5479 dtrace_check_override(x, 0); 5480 x->d86_numopnds = 2; 5481 if (addr_size == SIZE64) { 5482 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%rsi)", 5483 OPLEN); 5484 (void) strlcat(x->d86_opnd[1].d86_opnd, "(%rdi)", 5485 OPLEN); 5486 } else if (addr_size == SIZE32) { 5487 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%esi)", 5488 OPLEN); 5489 (void) strlcat(x->d86_opnd[1].d86_opnd, "(%edi)", 5490 OPLEN); 5491 } else { 5492 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%si)", 5493 OPLEN); 5494 (void) strlcat(x->d86_opnd[1].d86_opnd, "(%di)", 5495 OPLEN); 5496 } 5497 #endif 5498 wbit = LONG_OPND; 5499 break; 5500 5501 /* accumulator to di register */ 5502 case AD: 5503 wbit = WBIT(opcode2); 5504 #ifdef DIS_TEXT 5505 dtrace_check_override(x, 1); 5506 x->d86_numopnds = 2; 5507 dtrace_get_operand(x, REG_ONLY, EAX_REGNO, wbit, 0); 5508 if (addr_size == SIZE64) 5509 (void) strlcat(x->d86_opnd[1].d86_opnd, "(%rdi)", 5510 OPLEN); 5511 else if (addr_size == SIZE32) 5512 (void) strlcat(x->d86_opnd[1].d86_opnd, "(%edi)", 5513 OPLEN); 5514 else 5515 (void) strlcat(x->d86_opnd[1].d86_opnd, "(%di)", 5516 OPLEN); 5517 #endif 5518 break; 5519 5520 /* si register to accumulator */ 5521 case SA: 5522 wbit = WBIT(opcode2); 5523 #ifdef DIS_TEXT 5524 dtrace_check_override(x, 0); 5525 x->d86_numopnds = 2; 5526 if (addr_size == SIZE64) 5527 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%rsi)", 5528 OPLEN); 5529 else if (addr_size == SIZE32) 5530 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%esi)", 5531 OPLEN); 5532 else 5533 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%si)", 5534 OPLEN); 5535 dtrace_get_operand(x, REG_ONLY, EAX_REGNO, wbit, 1); 5536 #endif 5537 break; 5538 5539 /* 5540 * single operand, a 16/32 bit displacement 5541 */ 5542 case D: 5543 wbit = LONG_OPND; 5544 dtrace_disp_opnd(x, wbit, OPSIZE(opnd_size, LONG_OPND), 0); 5545 NOMEM; 5546 break; 5547 5548 /* jmp/call indirect to memory or register operand */ 5549 case INM: 5550 #ifdef DIS_TEXT 5551 (void) strlcat(x->d86_opnd[0].d86_prefix, "*", OPLEN); 5552 #endif 5553 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 5554 dtrace_get_operand(x, mode, r_m, LONG_OPND, 0); 5555 wbit = LONG_OPND; 5556 break; 5557 5558 /* 5559 * for long jumps and long calls -- a new code segment 5560 * register and an offset in IP -- stored in object 5561 * code in reverse order. Note - not valid in amd64 5562 */ 5563 case SO: 5564 dtrace_check_override(x, 1); 5565 wbit = LONG_OPND; 5566 dtrace_imm_opnd(x, wbit, OPSIZE(opnd_size, LONG_OPND), 1); 5567 #ifdef DIS_TEXT 5568 x->d86_opnd[1].d86_mode = MODE_SIGNED; 5569 #endif 5570 /* will now get segment operand */ 5571 dtrace_imm_opnd(x, wbit, 2, 0); 5572 break; 5573 5574 /* 5575 * jmp/call. single operand, 8 bit displacement. 5576 * added to current EIP in 'compofff' 5577 */ 5578 case BD: 5579 dtrace_disp_opnd(x, BYTE_OPND, 1, 0); 5580 NOMEM; 5581 break; 5582 5583 /* single 32/16 bit immediate operand */ 5584 case I: 5585 wbit = LONG_OPND; 5586 dtrace_imm_opnd(x, wbit, OPSIZE(opnd_size, LONG_OPND), 0); 5587 break; 5588 5589 /* single 8 bit immediate operand */ 5590 case Ib: 5591 wbit = LONG_OPND; 5592 dtrace_imm_opnd(x, wbit, 1, 0); 5593 break; 5594 5595 case ENTER: 5596 wbit = LONG_OPND; 5597 dtrace_imm_opnd(x, wbit, 2, 0); 5598 dtrace_imm_opnd(x, wbit, 1, 1); 5599 switch (opnd_size) { 5600 case SIZE64: 5601 x->d86_memsize = (x->d86_opnd[1].d86_value + 1) * 8; 5602 break; 5603 case SIZE32: 5604 x->d86_memsize = (x->d86_opnd[1].d86_value + 1) * 4; 5605 break; 5606 case SIZE16: 5607 x->d86_memsize = (x->d86_opnd[1].d86_value + 1) * 2; 5608 break; 5609 } 5610 5611 break; 5612 5613 /* 16-bit immediate operand */ 5614 case RET: 5615 wbit = LONG_OPND; 5616 dtrace_imm_opnd(x, wbit, 2, 0); 5617 break; 5618 5619 /* single 8 bit port operand */ 5620 case P: 5621 dtrace_check_override(x, 0); 5622 dtrace_imm_opnd(x, BYTE_OPND, 1, 0); 5623 NOMEM; 5624 break; 5625 5626 /* single operand, dx register (variable port instruction) */ 5627 case V: 5628 x->d86_numopnds = 1; 5629 dtrace_check_override(x, 0); 5630 #ifdef DIS_TEXT 5631 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%dx)", OPLEN); 5632 #endif 5633 NOMEM; 5634 break; 5635 5636 /* 5637 * The int instruction, which has two forms: 5638 * int 3 (breakpoint) or 5639 * int n, where n is indicated in the subsequent 5640 * byte (format Ib). The int 3 instruction (opcode 0xCC), 5641 * where, although the 3 looks like an operand, 5642 * it is implied by the opcode. It must be converted 5643 * to the correct base and output. 5644 */ 5645 case INT3: 5646 #ifdef DIS_TEXT 5647 x->d86_numopnds = 1; 5648 x->d86_opnd[0].d86_mode = MODE_SIGNED; 5649 x->d86_opnd[0].d86_value_size = 1; 5650 x->d86_opnd[0].d86_value = 3; 5651 #endif 5652 NOMEM; 5653 break; 5654 5655 /* single 8 bit immediate operand */ 5656 case INTx: 5657 dtrace_imm_opnd(x, BYTE_OPND, 1, 0); 5658 NOMEM; 5659 break; 5660 5661 /* an unused byte must be discarded */ 5662 case U: 5663 if (x->d86_get_byte(x->d86_data) < 0) 5664 goto error; 5665 x->d86_len++; 5666 NOMEM; 5667 break; 5668 5669 case CBW: 5670 #ifdef DIS_TEXT 5671 if (opnd_size == SIZE16) 5672 (void) strlcat(x->d86_mnem, "cbtw", OPLEN); 5673 else if (opnd_size == SIZE32) 5674 (void) strlcat(x->d86_mnem, "cwtl", OPLEN); 5675 else 5676 (void) strlcat(x->d86_mnem, "cltq", OPLEN); 5677 #endif 5678 wbit = LONG_OPND; 5679 NOMEM; 5680 break; 5681 5682 case CWD: 5683 #ifdef DIS_TEXT 5684 if (opnd_size == SIZE16) 5685 (void) strlcat(x->d86_mnem, "cwtd", OPLEN); 5686 else if (opnd_size == SIZE32) 5687 (void) strlcat(x->d86_mnem, "cltd", OPLEN); 5688 else 5689 (void) strlcat(x->d86_mnem, "cqtd", OPLEN); 5690 #endif 5691 wbit = LONG_OPND; 5692 NOMEM; 5693 break; 5694 5695 case XMMSFNC: 5696 /* 5697 * sfence is sfence if mode is REG_ONLY. If mode isn't 5698 * REG_ONLY, mnemonic should be 'clflush'. 5699 */ 5700 dtrace_get_modrm(x, &mode, ®, &r_m); 5701 5702 /* sfence doesn't take operands */ 5703 if (mode != REG_ONLY) { 5704 if (opnd_size_prefix == 0x66) { 5705 #ifdef DIS_TEXT 5706 (void) strlcat(x->d86_mnem, "clflushopt", 5707 OPLEN); 5708 #endif 5709 } else if (opnd_size_prefix == 0) { 5710 #ifdef DIS_TEXT 5711 (void) strlcat(x->d86_mnem, "clflush", OPLEN); 5712 #endif 5713 } else { 5714 /* Unknown instruction */ 5715 goto error; 5716 } 5717 5718 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 5719 dtrace_get_operand(x, mode, r_m, BYTE_OPND, 0); 5720 NOMEM; 5721 #ifdef DIS_TEXT 5722 } else { 5723 (void) strlcat(x->d86_mnem, "sfence", OPLEN); 5724 #endif 5725 } 5726 break; 5727 5728 case FSGS: 5729 /* 5730 * The FSGSBASE instructions are taken only when the mode is set 5731 * to registers. They share opcodes with instructions like 5732 * fxrstor, stmxcsr, etc. We handle the repz prefix earlier. 5733 */ 5734 wbit = WBIT(opcode2); 5735 dtrace_get_modrm(x, &mode, ®, &r_m); 5736 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 5737 dtrace_get_operand(x, mode, r_m, wbit, 0); 5738 if (mode == REG_ONLY) { 5739 NOMEM; 5740 } 5741 break; 5742 5743 /* 5744 * no disassembly, the mnemonic was all there was so go on 5745 */ 5746 case NORM: 5747 if (dp->it_invalid32 && cpu_mode != SIZE64) 5748 goto error; 5749 NOMEM; 5750 /*FALLTHROUGH*/ 5751 case IMPLMEM: 5752 break; 5753 5754 case XMMFENCE: 5755 /* 5756 * XRSTOR, XSAVEOPT and LFENCE share the same opcode but 5757 * differ in mode and reg. 5758 */ 5759 dtrace_get_modrm(x, &mode, ®, &r_m); 5760 5761 if (mode == REG_ONLY) { 5762 /* 5763 * Only the following exact byte sequences are allowed: 5764 * 5765 * 0f ae e8 lfence 5766 * 0f ae f0 mfence 5767 */ 5768 if ((uint8_t)x->d86_bytes[x->d86_len - 1] != 0xe8 && 5769 (uint8_t)x->d86_bytes[x->d86_len - 1] != 0xf0) 5770 goto error; 5771 } else { 5772 #ifdef DIS_TEXT 5773 if (reg == 5) { 5774 (void) strncpy(x->d86_mnem, "xrstor", OPLEN); 5775 } else if (reg == 6) { 5776 if (opnd_size_prefix == 0x66) { 5777 (void) strncpy(x->d86_mnem, "clwb", 5778 OPLEN); 5779 } else if (opnd_size_prefix == 0x00) { 5780 (void) strncpy(x->d86_mnem, "xsaveopt", 5781 OPLEN); 5782 } else { 5783 goto error; 5784 } 5785 } else { 5786 goto error; 5787 } 5788 #endif 5789 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 5790 dtrace_get_operand(x, mode, r_m, BYTE_OPND, 0); 5791 } 5792 break; 5793 5794 /* float reg */ 5795 case F: 5796 #ifdef DIS_TEXT 5797 x->d86_numopnds = 1; 5798 (void) strlcat(x->d86_opnd[0].d86_opnd, "%st(X)", OPLEN); 5799 x->d86_opnd[0].d86_opnd[4] = r_m + '0'; 5800 #endif 5801 NOMEM; 5802 break; 5803 5804 /* float reg to float reg, with ret bit present */ 5805 case FF: 5806 vbit = opcode2 >> 2 & 0x1; /* vbit = 1: st -> st(i) */ 5807 /*FALLTHROUGH*/ 5808 case FFC: /* case for vbit always = 0 */ 5809 #ifdef DIS_TEXT 5810 x->d86_numopnds = 2; 5811 (void) strlcat(x->d86_opnd[1 - vbit].d86_opnd, "%st", OPLEN); 5812 (void) strlcat(x->d86_opnd[vbit].d86_opnd, "%st(X)", OPLEN); 5813 x->d86_opnd[vbit].d86_opnd[4] = r_m + '0'; 5814 #endif 5815 NOMEM; 5816 break; 5817 5818 /* AVX instructions */ 5819 case VEX_MO: 5820 /* op(ModR/M.r/m) */ 5821 x->d86_numopnds = 1; 5822 dtrace_get_modrm(x, &mode, ®, &r_m); 5823 #ifdef DIS_TEXT 5824 if ((dp == &dis_opAVX0F[0xA][0xE]) && (reg == 3)) 5825 (void) strncpy(x->d86_mnem, "vstmxcsr", OPLEN); 5826 #endif 5827 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5828 dtrace_get_operand(x, mode, r_m, wbit, 0); 5829 break; 5830 case VEX_RMrX: 5831 case FMA: 5832 /* ModR/M.reg := op(VEX.vvvv, ModR/M.r/m) */ 5833 x->d86_numopnds = 3; 5834 dtrace_get_modrm(x, &mode, ®, &r_m); 5835 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5836 5837 /* 5838 * In classic Intel fashion, the opcodes for all of the FMA 5839 * instructions all have two possible mnemonics which vary by 5840 * one letter, which is selected based on the value of the wbit. 5841 * When wbit is one, they have the 'd' suffix and when 'wbit' is 5842 * 0, they have the 's' suffix. Otherwise, the FMA instructions 5843 * are all a standard VEX_RMrX. 5844 */ 5845 #ifdef DIS_TEXT 5846 if (dp->it_adrmode == FMA) { 5847 size_t len = strlen(dp->it_name); 5848 (void) strncpy(x->d86_mnem, dp->it_name, OPLEN); 5849 if (len + 1 < OPLEN) { 5850 (void) strncpy(x->d86_mnem + len, 5851 vex_W != 0 ? "d" : "s", OPLEN - len); 5852 } 5853 } 5854 #endif 5855 5856 if (mode != REG_ONLY) { 5857 if ((dp == &dis_opAVXF20F[0x10]) || 5858 (dp == &dis_opAVXF30F[0x10])) { 5859 /* vmovsd <m64>, <xmm> */ 5860 /* or vmovss <m64>, <xmm> */ 5861 x->d86_numopnds = 2; 5862 goto L_VEX_MX; 5863 } 5864 } 5865 5866 dtrace_get_operand(x, REG_ONLY, reg, wbit, 2); 5867 /* 5868 * VEX prefix uses the 1's complement form to encode the 5869 * XMM/YMM regs 5870 */ 5871 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 1); 5872 5873 if ((dp == &dis_opAVXF20F[0x2A]) || 5874 (dp == &dis_opAVXF30F[0x2A])) { 5875 /* 5876 * vcvtsi2si </r,m>, <xmm>, <xmm> or vcvtsi2ss </r,m>, 5877 * <xmm>, <xmm> 5878 */ 5879 wbit = LONG_OPND; 5880 } 5881 #ifdef DIS_TEXT 5882 else if ((mode == REG_ONLY) && 5883 (dp == &dis_opAVX0F[0x1][0x6])) { /* vmovlhps */ 5884 (void) strncpy(x->d86_mnem, "vmovlhps", OPLEN); 5885 } else if ((mode == REG_ONLY) && 5886 (dp == &dis_opAVX0F[0x1][0x2])) { /* vmovhlps */ 5887 (void) strncpy(x->d86_mnem, "vmovhlps", OPLEN); 5888 } 5889 #endif 5890 dtrace_get_operand(x, mode, r_m, wbit, 0); 5891 5892 break; 5893 5894 case VEX_VRMrX: 5895 /* ModR/M.reg := op(MODR/M.r/m, VEX.vvvv) */ 5896 x->d86_numopnds = 3; 5897 dtrace_get_modrm(x, &mode, ®, &r_m); 5898 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5899 5900 dtrace_get_operand(x, REG_ONLY, reg, wbit, 2); 5901 /* 5902 * VEX prefix uses the 1's complement form to encode the 5903 * XMM/YMM regs 5904 */ 5905 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 0); 5906 5907 dtrace_get_operand(x, mode, r_m, wbit, 1); 5908 break; 5909 5910 case VEX_SbVM: 5911 /* ModR/M.reg := op(MODR/M.r/m, VSIB, VEX.vvvv) */ 5912 x->d86_numopnds = 3; 5913 x->d86_vsib = 1; 5914 5915 /* 5916 * All instructions that use VSIB are currently a mess. See the 5917 * comment around the dis_gather_regs_t structure definition. 5918 */ 5919 5920 vreg = &dis_vgather[opcode2][vex_W][vex_L]; 5921 5922 #ifdef DIS_TEXT 5923 (void) strncpy(x->d86_mnem, dp->it_name, OPLEN); 5924 (void) strlcat(x->d86_mnem + strlen(dp->it_name), 5925 vreg->dgr_suffix, OPLEN - strlen(dp->it_name)); 5926 #endif 5927 5928 dtrace_get_modrm(x, &mode, ®, &r_m); 5929 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5930 5931 dtrace_get_operand(x, REG_ONLY, reg, vreg->dgr_arg2, 2); 5932 /* 5933 * VEX prefix uses the 1's complement form to encode the 5934 * XMM/YMM regs 5935 */ 5936 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), vreg->dgr_arg0, 5937 0); 5938 dtrace_get_operand(x, mode, r_m, vreg->dgr_arg1, 1); 5939 break; 5940 5941 case VEX_RRX: 5942 /* ModR/M.rm := op(VEX.vvvv, ModR/M.reg) */ 5943 x->d86_numopnds = 3; 5944 5945 dtrace_get_modrm(x, &mode, ®, &r_m); 5946 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5947 5948 if (mode != REG_ONLY) { 5949 if ((dp == &dis_opAVXF20F[0x11]) || 5950 (dp == &dis_opAVXF30F[0x11])) { 5951 /* vmovsd <xmm>, <m64> */ 5952 /* or vmovss <xmm>, <m64> */ 5953 x->d86_numopnds = 2; 5954 goto L_VEX_RM; 5955 } 5956 } 5957 5958 dtrace_get_operand(x, mode, r_m, wbit, 2); 5959 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 1); 5960 dtrace_get_operand(x, REG_ONLY, reg, wbit, 0); 5961 break; 5962 5963 case VEX_RMRX: 5964 /* ModR/M.reg := op(VEX.vvvv, ModR/M.r_m, imm8[7:4]) */ 5965 x->d86_numopnds = 4; 5966 5967 dtrace_get_modrm(x, &mode, ®, &r_m); 5968 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5969 dtrace_get_operand(x, REG_ONLY, reg, wbit, 3); 5970 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 2); 5971 if (dp == &dis_opAVX660F3A[0x18]) { 5972 /* vinsertf128 <imm8>, <xmm>, <ymm>, <ymm> */ 5973 dtrace_get_operand(x, mode, r_m, XMM_OPND, 1); 5974 } else if ((dp == &dis_opAVX660F3A[0x20]) || 5975 (dp == & dis_opAVX660F[0xC4])) { 5976 /* vpinsrb <imm8>, <reg/mm>, <xmm>, <xmm> */ 5977 /* or vpinsrw <imm8>, <reg/mm>, <xmm>, <xmm> */ 5978 dtrace_get_operand(x, mode, r_m, LONG_OPND, 1); 5979 } else if (dp == &dis_opAVX660F3A[0x22]) { 5980 /* vpinsrd/q <imm8>, <reg/mm>, <xmm>, <xmm> */ 5981 #ifdef DIS_TEXT 5982 if (vex_W) 5983 x->d86_mnem[6] = 'q'; 5984 #endif 5985 dtrace_get_operand(x, mode, r_m, LONG_OPND, 1); 5986 } else { 5987 dtrace_get_operand(x, mode, r_m, wbit, 1); 5988 } 5989 5990 /* one byte immediate number */ 5991 dtrace_imm_opnd(x, wbit, 1, 0); 5992 5993 /* vblendvpd, vblendvps, vblendvb use the imm encode the regs */ 5994 if ((dp == &dis_opAVX660F3A[0x4A]) || 5995 (dp == &dis_opAVX660F3A[0x4B]) || 5996 (dp == &dis_opAVX660F3A[0x4C])) { 5997 #ifdef DIS_TEXT 5998 int regnum = (x->d86_opnd[0].d86_value & 0xF0) >> 4; 5999 #endif 6000 x->d86_opnd[0].d86_mode = MODE_NONE; 6001 #ifdef DIS_TEXT 6002 if (vex_L) 6003 (void) strncpy(x->d86_opnd[0].d86_opnd, 6004 dis_YMMREG[regnum], OPLEN); 6005 else 6006 (void) strncpy(x->d86_opnd[0].d86_opnd, 6007 dis_XMMREG[regnum], OPLEN); 6008 #endif 6009 } 6010 break; 6011 6012 case VEX_MX: 6013 /* ModR/M.reg := op(ModR/M.rm) */ 6014 x->d86_numopnds = 2; 6015 6016 dtrace_get_modrm(x, &mode, ®, &r_m); 6017 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 6018 L_VEX_MX: 6019 6020 if ((dp == &dis_opAVXF20F[0xE6]) || 6021 (dp == &dis_opAVX660F[0x5A]) || 6022 (dp == &dis_opAVX660F[0xE6])) { 6023 /* vcvtpd2dq <ymm>, <xmm> */ 6024 /* or vcvtpd2ps <ymm>, <xmm> */ 6025 /* or vcvttpd2dq <ymm>, <xmm> */ 6026 dtrace_get_operand(x, REG_ONLY, reg, XMM_OPND, 1); 6027 dtrace_get_operand(x, mode, r_m, wbit, 0); 6028 } else if ((dp == &dis_opAVXF30F[0xE6]) || 6029 (dp == &dis_opAVX0F[0x5][0xA]) || 6030 (dp == &dis_opAVX660F38[0x13]) || 6031 (dp == &dis_opAVX660F38[0x18]) || 6032 (dp == &dis_opAVX660F38[0x19]) || 6033 (dp == &dis_opAVX660F38[0x58]) || 6034 (dp == &dis_opAVX660F38[0x78]) || 6035 (dp == &dis_opAVX660F38[0x79]) || 6036 (dp == &dis_opAVX660F38[0x59])) { 6037 /* vcvtdq2pd <xmm>, <ymm> */ 6038 /* or vcvtps2pd <xmm>, <ymm> */ 6039 /* or vcvtph2ps <xmm>, <ymm> */ 6040 /* or vbroadcasts* <xmm>, <ymm> */ 6041 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 6042 dtrace_get_operand(x, mode, r_m, XMM_OPND, 0); 6043 } else if (dp == &dis_opAVX660F[0x6E]) { 6044 /* vmovd/q <reg/mem 32/64>, <xmm> */ 6045 #ifdef DIS_TEXT 6046 if (vex_W) 6047 x->d86_mnem[4] = 'q'; 6048 #endif 6049 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 6050 dtrace_get_operand(x, mode, r_m, LONG_OPND, 0); 6051 } else { 6052 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 6053 dtrace_get_operand(x, mode, r_m, wbit, 0); 6054 } 6055 6056 break; 6057 6058 case VEX_MXI: 6059 /* ModR/M.reg := op(ModR/M.rm, imm8) */ 6060 x->d86_numopnds = 3; 6061 6062 dtrace_get_modrm(x, &mode, ®, &r_m); 6063 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 6064 6065 dtrace_get_operand(x, REG_ONLY, reg, wbit, 2); 6066 dtrace_get_operand(x, mode, r_m, wbit, 1); 6067 6068 /* one byte immediate number */ 6069 dtrace_imm_opnd(x, wbit, 1, 0); 6070 break; 6071 6072 case VEX_XXI: 6073 /* VEX.vvvv := op(ModR/M.rm, imm8) */ 6074 x->d86_numopnds = 3; 6075 6076 dtrace_get_modrm(x, &mode, ®, &r_m); 6077 #ifdef DIS_TEXT 6078 (void) strncpy(x->d86_mnem, dis_AVXvgrp7[opcode2 - 1][reg], 6079 OPLEN); 6080 #endif 6081 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 6082 6083 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 2); 6084 dtrace_get_operand(x, REG_ONLY, r_m, wbit, 1); 6085 6086 /* one byte immediate number */ 6087 dtrace_imm_opnd(x, wbit, 1, 0); 6088 break; 6089 6090 case VEX_MR: 6091 /* ModR/M.reg (reg32/64) := op(ModR/M.rm) */ 6092 if (dp == &dis_opAVX660F[0xC5]) { 6093 /* vpextrw <imm8>, <xmm>, <reg> */ 6094 x->d86_numopnds = 2; 6095 vbit = 2; 6096 } else { 6097 x->d86_numopnds = 2; 6098 vbit = 1; 6099 } 6100 6101 dtrace_get_modrm(x, &mode, ®, &r_m); 6102 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 6103 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, vbit); 6104 dtrace_get_operand(x, mode, r_m, wbit, vbit - 1); 6105 6106 if (vbit == 2) 6107 dtrace_imm_opnd(x, wbit, 1, 0); 6108 6109 break; 6110 6111 case VEX_KMR: 6112 /* opmask: mod_rm := %k */ 6113 x->d86_numopnds = 2; 6114 dtrace_get_modrm(x, &mode, ®, &r_m); 6115 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 6116 dtrace_get_operand(x, mode, r_m, LONG_OPND, 1); 6117 dtrace_get_operand(x, REG_ONLY, reg, wbit, 0); 6118 break; 6119 6120 case VEX_KRM: 6121 /* opmask: mod_reg := mod_rm */ 6122 x->d86_numopnds = 2; 6123 dtrace_get_modrm(x, &mode, ®, &r_m); 6124 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 6125 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 6126 if (mode == REG_ONLY) { 6127 dtrace_get_operand(x, mode, r_m, KOPMASK_OPND, 0); 6128 } else { 6129 dtrace_get_operand(x, mode, r_m, LONG_OPND, 0); 6130 } 6131 break; 6132 6133 case VEX_KRR: 6134 /* opmask: mod_reg := mod_rm */ 6135 x->d86_numopnds = 2; 6136 dtrace_get_modrm(x, &mode, ®, &r_m); 6137 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 6138 dtrace_get_operand(x, mode, reg, wbit, 1); 6139 dtrace_get_operand(x, REG_ONLY, r_m, LONG_OPND, 0); 6140 break; 6141 6142 case VEX_RRI: 6143 /* implicit(eflags/r32) := op(ModR/M.reg, ModR/M.rm) */ 6144 x->d86_numopnds = 2; 6145 6146 dtrace_get_modrm(x, &mode, ®, &r_m); 6147 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 6148 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 6149 dtrace_get_operand(x, mode, r_m, wbit, 0); 6150 break; 6151 6152 case VEX_RX: 6153 /* ModR/M.rm := op(ModR/M.reg) */ 6154 /* vextractf128 || vcvtps2ph */ 6155 if (dp == &dis_opAVX660F3A[0x19] || 6156 dp == &dis_opAVX660F3A[0x1d]) { 6157 x->d86_numopnds = 3; 6158 6159 dtrace_get_modrm(x, &mode, ®, &r_m); 6160 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 6161 6162 dtrace_get_operand(x, mode, r_m, XMM_OPND, 2); 6163 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 6164 6165 /* one byte immediate number */ 6166 dtrace_imm_opnd(x, wbit, 1, 0); 6167 break; 6168 } 6169 6170 x->d86_numopnds = 2; 6171 6172 dtrace_get_modrm(x, &mode, ®, &r_m); 6173 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 6174 dtrace_get_operand(x, mode, r_m, wbit, 1); 6175 dtrace_get_operand(x, REG_ONLY, reg, wbit, 0); 6176 break; 6177 6178 case VEX_RR: 6179 /* ModR/M.rm := op(ModR/M.reg) */ 6180 x->d86_numopnds = 2; 6181 6182 dtrace_get_modrm(x, &mode, ®, &r_m); 6183 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 6184 6185 if (dp == &dis_opAVX660F[0x7E]) { 6186 /* vmovd/q <reg/mem 32/64>, <xmm> */ 6187 #ifdef DIS_TEXT 6188 if (vex_W) 6189 x->d86_mnem[4] = 'q'; 6190 #endif 6191 dtrace_get_operand(x, mode, r_m, LONG_OPND, 1); 6192 } else 6193 dtrace_get_operand(x, mode, r_m, wbit, 1); 6194 6195 dtrace_get_operand(x, REG_ONLY, reg, wbit, 0); 6196 break; 6197 6198 case VEX_RRi: 6199 /* ModR/M.rm := op(ModR/M.reg, imm) */ 6200 x->d86_numopnds = 3; 6201 6202 dtrace_get_modrm(x, &mode, ®, &r_m); 6203 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 6204 6205 #ifdef DIS_TEXT 6206 if (dp == &dis_opAVX660F3A[0x16]) { 6207 /* vpextrd/q <imm>, <xmm>, <reg/mem 32/64> */ 6208 if (vex_W) 6209 x->d86_mnem[6] = 'q'; 6210 } 6211 #endif 6212 dtrace_get_operand(x, mode, r_m, LONG_OPND, 2); 6213 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 6214 6215 /* one byte immediate number */ 6216 dtrace_imm_opnd(x, wbit, 1, 0); 6217 break; 6218 case VEX_RIM: 6219 /* ModR/M.rm := op(ModR/M.reg, imm) */ 6220 x->d86_numopnds = 3; 6221 6222 dtrace_get_modrm(x, &mode, ®, &r_m); 6223 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 6224 6225 dtrace_get_operand(x, mode, r_m, XMM_OPND, 2); 6226 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 6227 /* one byte immediate number */ 6228 dtrace_imm_opnd(x, wbit, 1, 0); 6229 break; 6230 6231 case VEX_RM: 6232 /* ModR/M.rm := op(ModR/M.reg) */ 6233 if (dp == &dis_opAVX660F3A[0x17]) { /* vextractps */ 6234 x->d86_numopnds = 3; 6235 6236 dtrace_get_modrm(x, &mode, ®, &r_m); 6237 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 6238 6239 dtrace_get_operand(x, mode, r_m, LONG_OPND, 2); 6240 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 6241 /* one byte immediate number */ 6242 dtrace_imm_opnd(x, wbit, 1, 0); 6243 break; 6244 } 6245 x->d86_numopnds = 2; 6246 6247 dtrace_get_modrm(x, &mode, ®, &r_m); 6248 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 6249 L_VEX_RM: 6250 vbit = 1; 6251 dtrace_get_operand(x, mode, r_m, wbit, vbit); 6252 dtrace_get_operand(x, REG_ONLY, reg, wbit, vbit - 1); 6253 6254 break; 6255 6256 case VEX_RRM: 6257 /* ModR/M.rm := op(VEX.vvvv, ModR/M.reg) */ 6258 x->d86_numopnds = 3; 6259 6260 dtrace_get_modrm(x, &mode, ®, &r_m); 6261 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 6262 dtrace_get_operand(x, mode, r_m, wbit, 2); 6263 /* VEX use the 1's complement form encode the XMM/YMM regs */ 6264 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 1); 6265 dtrace_get_operand(x, REG_ONLY, reg, wbit, 0); 6266 break; 6267 6268 case VEX_RMX: 6269 /* ModR/M.reg := op(VEX.vvvv, ModR/M.rm) */ 6270 x->d86_numopnds = 3; 6271 6272 dtrace_get_modrm(x, &mode, ®, &r_m); 6273 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 6274 dtrace_get_operand(x, REG_ONLY, reg, wbit, 2); 6275 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 1); 6276 dtrace_get_operand(x, REG_ONLY, r_m, wbit, 0); 6277 break; 6278 6279 case VEX_NONE: 6280 #ifdef DIS_TEXT 6281 if (vex_L) 6282 (void) strncpy(x->d86_mnem, "vzeroall", OPLEN); 6283 #endif 6284 break; 6285 case BLS: { 6286 6287 /* 6288 * The BLS instructions are VEX instructions that are based on 6289 * VEX.0F38.F3; however, they are considered special group 17 6290 * and like everything else, they use the bits in 3-5 of the 6291 * MOD R/M to determine the sub instruction. Unlike many others 6292 * like the VMX instructions, these are valid both for memory 6293 * and register forms. 6294 */ 6295 6296 dtrace_get_modrm(x, &mode, ®, &r_m); 6297 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 6298 6299 switch (reg) { 6300 case 1: 6301 #ifdef DIS_TEXT 6302 blsinstr = "blsr"; 6303 #endif 6304 break; 6305 case 2: 6306 #ifdef DIS_TEXT 6307 blsinstr = "blsmsk"; 6308 #endif 6309 break; 6310 case 3: 6311 #ifdef DIS_TEXT 6312 blsinstr = "blsi"; 6313 #endif 6314 break; 6315 default: 6316 goto error; 6317 } 6318 6319 x->d86_numopnds = 2; 6320 #ifdef DIS_TEXT 6321 (void) strncpy(x->d86_mnem, blsinstr, OPLEN); 6322 #endif 6323 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 1); 6324 dtrace_get_operand(x, mode, r_m, wbit, 0); 6325 break; 6326 } 6327 case EVEX_MX: 6328 /* ModR/M.reg := op(ModR/M.rm) */ 6329 x->d86_numopnds = 2; 6330 dtrace_evex_mnem_adjust(x, dp, vex_W, evex_byte2); 6331 dtrace_get_modrm(x, &mode, ®, &r_m); 6332 evex_modrm = x->d86_bytes[x->d86_len - 1] & 0xff; 6333 dtrace_evex_adjust_reg(evex_byte1, ®); 6334 dtrace_evex_adjust_rm(evex_byte1, &r_m); 6335 dtrace_evex_adjust_reg_name(evex_L, &wbit); 6336 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 6337 dtrace_evex_adjust_z_opmask(x, 1, evex_byte3); 6338 dtrace_get_operand(x, mode, r_m, wbit, 0); 6339 dtrace_evex_adjust_disp8_n(x, 0, evex_L, evex_modrm); 6340 break; 6341 case EVEX_RX: 6342 /* ModR/M.rm := op(ModR/M.reg) */ 6343 x->d86_numopnds = 2; 6344 dtrace_evex_mnem_adjust(x, dp, vex_W, evex_byte2); 6345 dtrace_get_modrm(x, &mode, ®, &r_m); 6346 evex_modrm = x->d86_bytes[x->d86_len - 1] & 0xff; 6347 dtrace_evex_adjust_reg(evex_byte1, ®); 6348 dtrace_evex_adjust_rm(evex_byte1, &r_m); 6349 dtrace_evex_adjust_reg_name(evex_L, &wbit); 6350 dtrace_get_operand(x, mode, r_m, wbit, 1); 6351 dtrace_evex_adjust_disp8_n(x, 1, evex_L, evex_modrm); 6352 dtrace_evex_adjust_z_opmask(x, 1, evex_byte3); 6353 dtrace_get_operand(x, REG_ONLY, reg, wbit, 0); 6354 break; 6355 case EVEX_RMrX: 6356 /* ModR/M.reg := op(EVEX.vvvv, ModR/M.r/m) */ 6357 x->d86_numopnds = 3; 6358 dtrace_evex_mnem_adjust(x, dp, vex_W, evex_byte2); 6359 dtrace_get_modrm(x, &mode, ®, &r_m); 6360 evex_modrm = x->d86_bytes[x->d86_len - 1] & 0xff; 6361 dtrace_evex_adjust_reg(evex_byte1, ®); 6362 dtrace_evex_adjust_rm(evex_byte1, &r_m); 6363 dtrace_evex_adjust_reg_name(evex_L, &wbit); 6364 dtrace_get_operand(x, REG_ONLY, reg, wbit, 2); 6365 /* 6366 * EVEX.vvvv is the same as VEX.vvvv (ones complement of the 6367 * register specifier). The EVEX prefix handling uses the vex_v 6368 * variable for these bits. 6369 */ 6370 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 1); 6371 dtrace_get_operand(x, mode, r_m, wbit, 0); 6372 dtrace_evex_adjust_disp8_n(x, 0, evex_L, evex_modrm); 6373 dtrace_evex_adjust_z_opmask(x, 2, evex_byte3); 6374 break; 6375 case EVEX_RMRX: 6376 /* ModR/M.reg := op(EVEX.vvvv, ModR/M.r_m, imm8) */ 6377 x->d86_numopnds = 4; 6378 6379 dtrace_evex_mnem_adjust(x, dp, vex_W, evex_byte2); 6380 dtrace_get_modrm(x, &mode, ®, &r_m); 6381 evex_modrm = x->d86_bytes[x->d86_len - 1] & 0xff; 6382 dtrace_evex_adjust_reg(evex_byte1, ®); 6383 dtrace_evex_adjust_rm(evex_byte1, &r_m); 6384 dtrace_evex_adjust_reg_name(evex_L, &wbit); 6385 dtrace_get_operand(x, REG_ONLY, reg, wbit, 3); 6386 /* 6387 * EVEX.vvvv is the same as VEX.vvvv (ones complement of the 6388 * register specifier). The EVEX prefix handling uses the vex_v 6389 * variable for these bits. 6390 */ 6391 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 2); 6392 dtrace_get_operand(x, mode, r_m, wbit, 1); 6393 dtrace_evex_adjust_disp8_n(x, 0, evex_L, evex_modrm); 6394 dtrace_evex_adjust_z_opmask(x, 3, evex_byte3); 6395 6396 dtrace_imm_opnd(x, wbit, 1, 0); 6397 break; 6398 /* an invalid op code */ 6399 case AM: 6400 case DM: 6401 case OVERRIDE: 6402 case PREFIX: 6403 case UNKNOWN: 6404 NOMEM; 6405 default: 6406 goto error; 6407 } /* end switch */ 6408 if (x->d86_error) 6409 goto error; 6410 6411 done: 6412 #ifdef DIS_MEM 6413 /* 6414 * compute the size of any memory accessed by the instruction 6415 */ 6416 if (x->d86_memsize != 0) { 6417 return (0); 6418 } else if (dp->it_stackop) { 6419 switch (opnd_size) { 6420 case SIZE16: 6421 x->d86_memsize = 2; 6422 break; 6423 case SIZE32: 6424 x->d86_memsize = 4; 6425 break; 6426 case SIZE64: 6427 x->d86_memsize = 8; 6428 break; 6429 } 6430 } else if (nomem || mode == REG_ONLY) { 6431 x->d86_memsize = 0; 6432 6433 } else if (dp->it_size != 0) { 6434 /* 6435 * In 64 bit mode descriptor table entries 6436 * go up to 10 bytes and popf/pushf are always 8 bytes 6437 */ 6438 if (x->d86_mode == SIZE64 && dp->it_size == 6) 6439 x->d86_memsize = 10; 6440 else if (x->d86_mode == SIZE64 && opcode1 == 0x9 && 6441 (opcode2 == 0xc || opcode2 == 0xd)) 6442 x->d86_memsize = 8; 6443 else 6444 x->d86_memsize = dp->it_size; 6445 6446 } else if (wbit == 0) { 6447 x->d86_memsize = 1; 6448 6449 } else if (wbit == LONG_OPND) { 6450 if (opnd_size == SIZE64) 6451 x->d86_memsize = 8; 6452 else if (opnd_size == SIZE32) 6453 x->d86_memsize = 4; 6454 else 6455 x->d86_memsize = 2; 6456 6457 } else if (wbit == SEG_OPND) { 6458 x->d86_memsize = 4; 6459 6460 } else { 6461 x->d86_memsize = 8; 6462 } 6463 #endif 6464 return (0); 6465 6466 error: 6467 #ifdef DIS_TEXT 6468 (void) strlcat(x->d86_mnem, "undef", OPLEN); 6469 #endif 6470 return (1); 6471 } 6472 6473 #ifdef DIS_TEXT 6474 6475 /* 6476 * Some instructions should have immediate operands printed 6477 * as unsigned integers. We compare against this table. 6478 */ 6479 static char *unsigned_ops[] = { 6480 "or", "and", "xor", "test", "in", "out", "lcall", "ljmp", 6481 "rcr", "rcl", "ror", "rol", "shl", "shr", "sal", "psr", "psl", 6482 0 6483 }; 6484 6485 6486 static int 6487 isunsigned_op(char *opcode) 6488 { 6489 char *where; 6490 int i; 6491 int is_unsigned = 0; 6492 6493 /* 6494 * Work back to start of last mnemonic, since we may have 6495 * prefixes on some opcodes. 6496 */ 6497 where = opcode + strlen(opcode) - 1; 6498 while (where > opcode && *where != ' ') 6499 --where; 6500 if (*where == ' ') 6501 ++where; 6502 6503 for (i = 0; unsigned_ops[i]; ++i) { 6504 if (strncmp(where, unsigned_ops[i], 6505 strlen(unsigned_ops[i]))) 6506 continue; 6507 is_unsigned = 1; 6508 break; 6509 } 6510 return (is_unsigned); 6511 } 6512 6513 /* 6514 * Print a numeric immediate into end of buf, maximum length buflen. 6515 * The immediate may be an address or a displacement. Mask is set 6516 * for address size. If the immediate is a "small negative", or 6517 * if it's a negative displacement of any magnitude, print as -<absval>. 6518 * Respect the "octal" flag. "Small negative" is defined as "in the 6519 * interval [NEG_LIMIT, 0)". 6520 * 6521 * Also, "isunsigned_op()" instructions never print negatives. 6522 * 6523 * Return whether we decided to print a negative value or not. 6524 */ 6525 6526 #define NEG_LIMIT -255 6527 enum {IMM, DISP}; 6528 enum {POS, TRY_NEG}; 6529 6530 static int 6531 print_imm(dis86_t *dis, uint64_t usv, uint64_t mask, char *buf, 6532 size_t buflen, int disp, int try_neg) 6533 { 6534 int curlen; 6535 int64_t sv = (int64_t)usv; 6536 int octal = dis->d86_flags & DIS_F_OCTAL; 6537 6538 curlen = strlen(buf); 6539 6540 if (try_neg == TRY_NEG && sv < 0 && 6541 (disp || sv >= NEG_LIMIT) && 6542 !isunsigned_op(dis->d86_mnem)) { 6543 dis->d86_sprintf_func(buf + curlen, buflen - curlen, 6544 octal ? "-0%llo" : "-0x%llx", (-sv) & mask); 6545 return (1); 6546 } else { 6547 if (disp == DISP) 6548 dis->d86_sprintf_func(buf + curlen, buflen - curlen, 6549 octal ? "+0%llo" : "+0x%llx", usv & mask); 6550 else 6551 dis->d86_sprintf_func(buf + curlen, buflen - curlen, 6552 octal ? "0%llo" : "0x%llx", usv & mask); 6553 return (0); 6554 6555 } 6556 } 6557 6558 6559 static int 6560 log2(int size) 6561 { 6562 switch (size) { 6563 case 1: return (0); 6564 case 2: return (1); 6565 case 4: return (2); 6566 case 8: return (3); 6567 } 6568 return (0); 6569 } 6570 6571 /* ARGSUSED */ 6572 void 6573 dtrace_disx86_str(dis86_t *dis, uint_t mode, uint64_t pc, char *buf, 6574 size_t buflen) 6575 { 6576 uint64_t reltgt = 0; 6577 uint64_t tgt = 0; 6578 int curlen; 6579 int (*lookup)(void *, uint64_t, char *, size_t); 6580 int i; 6581 int64_t sv; 6582 uint64_t usv, mask, save_mask, save_usv; 6583 static uint64_t masks[] = 6584 {0xffU, 0xffffU, 0xffffffffU, 0xffffffffffffffffULL}; 6585 save_usv = 0; 6586 6587 dis->d86_sprintf_func(buf, buflen, "%-6s ", dis->d86_mnem); 6588 6589 /* 6590 * For PC-relative jumps, the pc is really the next pc after executing 6591 * this instruction, so increment it appropriately. 6592 */ 6593 pc += dis->d86_len; 6594 6595 for (i = 0; i < dis->d86_numopnds; i++) { 6596 d86opnd_t *op = &dis->d86_opnd[i]; 6597 6598 if (i != 0) 6599 (void) strlcat(buf, ",", buflen); 6600 6601 (void) strlcat(buf, op->d86_prefix, buflen); 6602 6603 /* 6604 * sv is for the signed, possibly-truncated immediate or 6605 * displacement; usv retains the original size and 6606 * unsignedness for symbol lookup. 6607 */ 6608 6609 sv = usv = op->d86_value; 6610 6611 /* 6612 * About masks: for immediates that represent 6613 * addresses, the appropriate display size is 6614 * the effective address size of the instruction. 6615 * This includes MODE_OFFSET, MODE_IPREL, and 6616 * MODE_RIPREL. Immediates that are simply 6617 * immediate values should display in the operand's 6618 * size, however, since they don't represent addresses. 6619 */ 6620 6621 /* d86_addr_size is SIZEnn, which is log2(real size) */ 6622 mask = masks[dis->d86_addr_size]; 6623 6624 /* d86_value_size and d86_imm_bytes are in bytes */ 6625 if (op->d86_mode == MODE_SIGNED || 6626 op->d86_mode == MODE_IMPLIED) 6627 mask = masks[log2(op->d86_value_size)]; 6628 6629 switch (op->d86_mode) { 6630 6631 case MODE_NONE: 6632 6633 (void) strlcat(buf, op->d86_opnd, buflen); 6634 break; 6635 6636 case MODE_SIGNED: 6637 case MODE_IMPLIED: 6638 case MODE_OFFSET: 6639 6640 tgt = usv; 6641 6642 if (dis->d86_seg_prefix) 6643 (void) strlcat(buf, dis->d86_seg_prefix, 6644 buflen); 6645 6646 if (op->d86_mode == MODE_SIGNED || 6647 op->d86_mode == MODE_IMPLIED) { 6648 (void) strlcat(buf, "$", buflen); 6649 } 6650 6651 if (print_imm(dis, usv, mask, buf, buflen, 6652 IMM, TRY_NEG) && 6653 (op->d86_mode == MODE_SIGNED || 6654 op->d86_mode == MODE_IMPLIED)) { 6655 6656 /* 6657 * We printed a negative value for an 6658 * immediate that wasn't a 6659 * displacement. Note that fact so we can 6660 * print the positive value as an 6661 * annotation. 6662 */ 6663 6664 save_usv = usv; 6665 save_mask = mask; 6666 } 6667 (void) strlcat(buf, op->d86_opnd, buflen); 6668 break; 6669 6670 case MODE_IPREL: 6671 case MODE_RIPREL: 6672 6673 reltgt = pc + sv; 6674 6675 switch (mode) { 6676 case SIZE16: 6677 reltgt = (uint16_t)reltgt; 6678 break; 6679 case SIZE32: 6680 reltgt = (uint32_t)reltgt; 6681 break; 6682 } 6683 6684 (void) print_imm(dis, usv, mask, buf, buflen, 6685 DISP, TRY_NEG); 6686 6687 if (op->d86_mode == MODE_RIPREL) 6688 (void) strlcat(buf, "(%rip)", buflen); 6689 break; 6690 } 6691 } 6692 6693 /* 6694 * The symbol lookups may result in false positives, 6695 * particularly on object files, where small numbers may match 6696 * the 0-relative non-relocated addresses of symbols. 6697 */ 6698 6699 lookup = dis->d86_sym_lookup; 6700 if (tgt != 0) { 6701 if ((dis->d86_flags & DIS_F_NOIMMSYM) == 0 && 6702 lookup(dis->d86_data, tgt, NULL, 0) == 0) { 6703 (void) strlcat(buf, "\t<", buflen); 6704 curlen = strlen(buf); 6705 lookup(dis->d86_data, tgt, buf + curlen, 6706 buflen - curlen); 6707 (void) strlcat(buf, ">", buflen); 6708 } 6709 6710 /* 6711 * If we printed a negative immediate above, print the 6712 * positive in case our heuristic was unhelpful 6713 */ 6714 if (save_usv) { 6715 (void) strlcat(buf, "\t<", buflen); 6716 (void) print_imm(dis, save_usv, save_mask, buf, buflen, 6717 IMM, POS); 6718 (void) strlcat(buf, ">", buflen); 6719 } 6720 } 6721 6722 if (reltgt != 0) { 6723 /* Print symbol or effective address for reltgt */ 6724 6725 (void) strlcat(buf, "\t<", buflen); 6726 curlen = strlen(buf); 6727 lookup(dis->d86_data, reltgt, buf + curlen, 6728 buflen - curlen); 6729 (void) strlcat(buf, ">", buflen); 6730 } 6731 } 6732 6733 #endif /* DIS_TEXT */ 6734