1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 * 22 * $FreeBSD$ 23 */ 24/* 25 * Copyright 2004 Sun Microsystems, Inc. All rights reserved. 26 * Use is subject to license terms. 27 */ 28 29#define _ASM 30#define _LOCORE 31#define LOCORE 32 33#include <sys/cpuvar_defs.h> 34#include <sys/dtrace.h> 35 36#include <machine/armreg.h> 37#include <machine/asm.h> 38 39#include "assym.s" 40 41/* 42void dtrace_membar_producer(void) 43*/ 44ENTRY(dtrace_membar_producer) 45 RET 46END(dtrace_membar_producer) 47 48/* 49void dtrace_membar_consumer(void) 50*/ 51ENTRY(dtrace_membar_consumer) 52 RET 53END(dtrace_membar_consumer) 54 55/* 56dtrace_icookie_t dtrace_interrupt_disable(void) 57*/ 58ENTRY(dtrace_interrupt_disable) 59 mrs r0, cpsr 60 mov r1, r0 61 orr r1, r1, #(PSR_I | PSR_F) 62 msr cpsr_c, r1 63 RET 64END(dtrace_interrupt_disable) 65 66/* 67void dtrace_interrupt_enable(dtrace_icookie_t cookie) 68*/ 69ENTRY(dtrace_interrupt_enable) 70 and r0, r0, #(PSR_I | PSR_F) 71 mrs r1, cpsr 72 bic r1, r1, #(PSR_I | PSR_F) 73 orr r1, r1, r0 74 msr cpsr_c, r1 75 RET 76END(dtrace_interrupt_enable) 77/* 78uint8_t 79dtrace_fuword8_nocheck(void *addr) 80*/ 81ENTRY(dtrace_fuword8_nocheck) 82 ldrb r3, [r0] 83 mov r0, r3 84 RET 85END(dtrace_fuword8_nocheck) 86 87/* 88uint16_t 89dtrace_fuword16_nocheck(void *addr) 90*/ 91ENTRY(dtrace_fuword16_nocheck) 92 ldrh r3, [r0] 93 mov r0, r3 94 RET 95END(dtrace_fuword16_nocheck) 96 97/* 98uint32_t 99dtrace_fuword32_nocheck(void *addr) 100*/ 101ENTRY(dtrace_fuword32_nocheck) 102 ldr r3, [r0] 103 mov r0, r3 104 RET 105END(dtrace_fuword32_nocheck) 106 107/* 108uint64_t 109dtrace_fuword64_nocheck(void *addr) 110*/ 111ENTRY(dtrace_fuword64_nocheck) 112 ldm r0, {r2, r3} 113 114 mov r0, r2 115 mov r1, r3 116#if defined(__BIG_ENDIAN__) 117/* big endian */ 118 mov r0, r3 119 mov r1, r2 120#else 121/* little endian */ 122 mov r0, r2 123 mov r1, r3 124 125#endif 126 RET 127END(dtrace_fuword64_nocheck) 128 129/* 130void 131dtrace_copy(uintptr_t uaddr, uintptr_t kaddr, size_t size) 132*/ 133ENTRY(dtrace_copy) 134 stmfd sp!, {r4-r5} /* stack is 8 byte aligned */ 135 teq r2, #0x00000000 136 mov r5, #0x00000000 137 beq 2f 138 1391: ldrb r4, [r0], #0x0001 140 add r5, r5, #0x00000001 141 strb r4, [r1], #0x0001 142 teqne r5, r2 143 bne 1b 144 1452: ldmfd sp!, {r4-r5} /* stack is 8 byte aligned */ 146 RET 147END(dtrace_copy) 148 149/* 150void 151dtrace_copystr(uintptr_t uaddr, uintptr_t kaddr, size_t size, 152 volatile uint16_t *flags) 153XXX: Check for flags? 154*/ 155ENTRY(dtrace_copystr) 156 stmfd sp!, {r4-r5} /* stack is 8 byte aligned */ 157 teq r2, #0x00000000 158 mov r5, #0x00000000 159 beq 2f 160 1611: ldrb r4, [r0], #0x0001 162 add r5, r5, #0x00000001 163 teq r4, #0x00000000 164 strb r4, [r1], #0x0001 165 teqne r5, r2 166 bne 1b 167 1682: ldmfd sp!, {r4-r5} /* stack is 8 byte aligned */ 169 RET 170END(dtrace_copystr) 171 172/* 173void 174vpanic(const char *format, va_list alist) 175*/ 176ENTRY(vpanic) /* Initial stack layout: */ 177vpanic_common: 178 RET 179END(vpanic) 180 181/* 182void 183dtrace_vpanic(const char *format, va_list alist) 184*/ 185ENTRY(dtrace_vpanic) /* Initial stack layout: */ 186 b vpanic 187 RET 188END(dtrace_vpanic) /* Initial stack layout: */ 189 190/* 191uintptr_t 192dtrace_caller(int aframes) 193*/ 194ENTRY(dtrace_caller) 195 mov r0, #-1 196 RET 197END(dtrace_caller) 198 199/* 200uint32_t 201dtrace_cas32(uint32_t *target, uint32_t cmp, uint32_t new) 202 203void * 204dtrace_casptr(volatile void *target, volatile void *cmp, volatile void *new) 205*/ 206ENTRY(dtrace_cas32) 207EENTRY(dtrace_casptr) 2081: ldrex r3, [r0] /* Load target */ 209 cmp r3, r1 /* Check if *target == cmp */ 210 bne 2f /* No, return */ 211 strex ip, r2, [r0] /* Store new to target */ 212 cmp ip, #0 /* Did the store succeed? */ 213 bne 1b /* No, try again */ 2142: mov r0, r3 /* Return the value loaded from target */ 215 RET 216EEND(dtrace_casptr) 217END(dtrace_cas32) 218