1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22/* 23 * Copyright 2004 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27#define _ASM 28#define _LOCORE 29 30#include <sys/cpuvar_defs.h> 31#include <sys/dtrace.h> 32 33#include <machine/asm.h> 34#include <machine/armreg.h> 35 36#include "assym.inc" 37 38/* 39void dtrace_membar_producer(void) 40*/ 41ENTRY(dtrace_membar_producer) 42 RET 43END(dtrace_membar_producer) 44 45/* 46void dtrace_membar_consumer(void) 47*/ 48ENTRY(dtrace_membar_consumer) 49 RET 50END(dtrace_membar_consumer) 51 52/* 53dtrace_icookie_t dtrace_interrupt_disable(void) 54*/ 55ENTRY(dtrace_interrupt_disable) 56 mrs r0, cpsr 57 mov r1, r0 58 orr r1, r1, #(PSR_I | PSR_F) 59 msr cpsr_c, r1 60 RET 61END(dtrace_interrupt_disable) 62 63/* 64void dtrace_interrupt_enable(dtrace_icookie_t cookie) 65*/ 66ENTRY(dtrace_interrupt_enable) 67 and r0, r0, #(PSR_I | PSR_F) 68 mrs r1, cpsr 69 bic r1, r1, #(PSR_I | PSR_F) 70 orr r1, r1, r0 71 msr cpsr_c, r1 72 RET 73END(dtrace_interrupt_enable) 74/* 75uint8_t 76dtrace_fuword8_nocheck(void *addr) 77*/ 78ENTRY(dtrace_fuword8_nocheck) 79 ldrb r3, [r0] 80 mov r0, r3 81 RET 82END(dtrace_fuword8_nocheck) 83 84/* 85uint16_t 86dtrace_fuword16_nocheck(void *addr) 87*/ 88ENTRY(dtrace_fuword16_nocheck) 89 ldrh r3, [r0] 90 mov r0, r3 91 RET 92END(dtrace_fuword16_nocheck) 93 94/* 95uint32_t 96dtrace_fuword32_nocheck(void *addr) 97*/ 98ENTRY(dtrace_fuword32_nocheck) 99 ldr r3, [r0] 100 mov r0, r3 101 RET 102END(dtrace_fuword32_nocheck) 103 104/* 105uint64_t 106dtrace_fuword64_nocheck(void *addr) 107*/ 108ENTRY(dtrace_fuword64_nocheck) 109 ldm r0, {r2, r3} 110 111 mov r0, r2 112 mov r1, r3 113#if defined(__BIG_ENDIAN__) 114/* big endian */ 115 mov r0, r3 116 mov r1, r2 117#else 118/* little endian */ 119 mov r0, r2 120 mov r1, r3 121 122#endif 123 RET 124END(dtrace_fuword64_nocheck) 125 126/* 127void 128dtrace_copy(uintptr_t uaddr, uintptr_t kaddr, size_t size) 129*/ 130ENTRY(dtrace_copy) 131 stmfd sp!, {r4-r5} /* stack is 8 byte aligned */ 132 teq r2, #0x00000000 133 mov r5, #0x00000000 134 beq 2f 135 1361: ldrb r4, [r0], #0x0001 137 add r5, r5, #0x00000001 138 strb r4, [r1], #0x0001 139 teqne r5, r2 140 bne 1b 141 1422: ldmfd sp!, {r4-r5} /* stack is 8 byte aligned */ 143 RET 144END(dtrace_copy) 145 146/* 147void 148dtrace_copystr(uintptr_t uaddr, uintptr_t kaddr, size_t size, 149 volatile uint16_t *flags) 150XXX: Check for flags? 151*/ 152ENTRY(dtrace_copystr) 153 stmfd sp!, {r4-r5} /* stack is 8 byte aligned */ 154 teq r2, #0x00000000 155 mov r5, #0x00000000 156 beq 2f 157 1581: ldrb r4, [r0], #0x0001 159 add r5, r5, #0x00000001 160 teq r4, #0x00000000 161 strb r4, [r1], #0x0001 162 teqne r5, r2 163 bne 1b 164 1652: ldmfd sp!, {r4-r5} /* stack is 8 byte aligned */ 166 RET 167END(dtrace_copystr) 168 169/* 170uintptr_t 171dtrace_caller(int aframes) 172*/ 173ENTRY(dtrace_caller) 174 mov r0, #-1 175 RET 176END(dtrace_caller) 177 178/* 179uint32_t 180dtrace_cas32(uint32_t *target, uint32_t cmp, uint32_t new) 181 182void * 183dtrace_casptr(volatile void *target, volatile void *cmp, volatile void *new) 184*/ 185ENTRY(dtrace_cas32) 186EENTRY(dtrace_casptr) 1871: ldrex r3, [r0] /* Load target */ 188 cmp r3, r1 /* Check if *target == cmp */ 189 bne 2f /* No, return */ 190 strex ip, r2, [r0] /* Store new to target */ 191 cmp ip, #0 /* Did the store succeed? */ 192 bne 1b /* No, try again */ 1932: mov r0, r3 /* Return the value loaded from target */ 194 RET 195EEND(dtrace_casptr) 196END(dtrace_cas32) 197