1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 * 21 * Portions Copyright 2010 The FreeBSD Foundation 22 * 23 * $FreeBSD$ 24 */ 25 26 /* 27 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 28 * Use is subject to license terms. 29 */ 30 31 #if defined(sun) 32 #pragma ident "%Z%%M% %I% %E% SMI" 33 #endif 34 35 #include <sys/fasttrap_isa.h> 36 #include <sys/fasttrap_impl.h> 37 #include <sys/dtrace.h> 38 #include <sys/dtrace_impl.h> 39 #include <sys/cmn_err.h> 40 #if defined(sun) 41 #include <sys/regset.h> 42 #include <sys/privregs.h> 43 #include <sys/segments.h> 44 #include <sys/x86_archext.h> 45 #else 46 #include <cddl/dev/dtrace/dtrace_cddl.h> 47 #include <sys/types.h> 48 #include <sys/proc.h> 49 #include <sys/dtrace_bsd.h> 50 #include <cddl/dev/dtrace/i386/regset.h> 51 #include <machine/segments.h> 52 #include <machine/reg.h> 53 #include <machine/pcb.h> 54 #endif 55 #include <sys/sysmacros.h> 56 #if defined(sun) 57 #include <sys/trap.h> 58 #include <sys/archsystm.h> 59 #else 60 #include <sys/ptrace.h> 61 62 static int 63 proc_ops(int op, proc_t *p, void *kaddr, off_t uaddr, size_t len) 64 { 65 struct iovec iov; 66 struct uio uio; 67 68 iov.iov_base = kaddr; 69 iov.iov_len = len; 70 uio.uio_offset = uaddr; 71 uio.uio_iov = &iov; 72 uio.uio_resid = len; 73 uio.uio_iovcnt = 1; 74 uio.uio_segflg = UIO_SYSSPACE; 75 uio.uio_td = curthread; 76 uio.uio_rw = op; 77 PHOLD(p); 78 if (proc_rwmem(p, &uio) < 0) { 79 PRELE(p); 80 return (-1); 81 } 82 PRELE(p); 83 84 return (0); 85 } 86 87 static int 88 uread(proc_t *p, void *kaddr, size_t len, uintptr_t uaddr) 89 { 90 91 return (proc_ops(UIO_READ, p, kaddr, uaddr, len)); 92 } 93 94 static int 95 uwrite(proc_t *p, void *kaddr, size_t len, uintptr_t uaddr) 96 { 97 98 return (proc_ops(UIO_WRITE, p, kaddr, uaddr, len)); 99 } 100 #endif 101 #ifdef __i386__ 102 #define r_rax r_eax 103 #define r_rbx r_ebx 104 #define r_rip r_eip 105 #define r_rflags r_eflags 106 #define r_rsp r_esp 107 #endif 108 109 /* 110 * Lossless User-Land Tracing on x86 111 * --------------------------------- 112 * 113 * The execution of most instructions is not dependent on the address; for 114 * these instructions it is sufficient to copy them into the user process's 115 * address space and execute them. To effectively single-step an instruction 116 * in user-land, we copy out the following sequence of instructions to scratch 117 * space in the user thread's ulwp_t structure. 118 * 119 * We then set the program counter (%eip or %rip) to point to this scratch 120 * space. Once execution resumes, the original instruction is executed and 121 * then control flow is redirected to what was originally the subsequent 122 * instruction. If the kernel attemps to deliver a signal while single- 123 * stepping, the signal is deferred and the program counter is moved into the 124 * second sequence of instructions. The second sequence ends in a trap into 125 * the kernel where the deferred signal is then properly handled and delivered. 126 * 127 * For instructions whose execute is position dependent, we perform simple 128 * emulation. These instructions are limited to control transfer 129 * instructions in 32-bit mode, but in 64-bit mode there's the added wrinkle 130 * of %rip-relative addressing that means that almost any instruction can be 131 * position dependent. For all the details on how we emulate generic 132 * instructions included %rip-relative instructions, see the code in 133 * fasttrap_pid_probe() below where we handle instructions of type 134 * FASTTRAP_T_COMMON (under the header: Generic Instruction Tracing). 135 */ 136 137 #define FASTTRAP_MODRM_MOD(modrm) (((modrm) >> 6) & 0x3) 138 #define FASTTRAP_MODRM_REG(modrm) (((modrm) >> 3) & 0x7) 139 #define FASTTRAP_MODRM_RM(modrm) ((modrm) & 0x7) 140 #define FASTTRAP_MODRM(mod, reg, rm) (((mod) << 6) | ((reg) << 3) | (rm)) 141 142 #define FASTTRAP_SIB_SCALE(sib) (((sib) >> 6) & 0x3) 143 #define FASTTRAP_SIB_INDEX(sib) (((sib) >> 3) & 0x7) 144 #define FASTTRAP_SIB_BASE(sib) ((sib) & 0x7) 145 146 #define FASTTRAP_REX_W(rex) (((rex) >> 3) & 1) 147 #define FASTTRAP_REX_R(rex) (((rex) >> 2) & 1) 148 #define FASTTRAP_REX_X(rex) (((rex) >> 1) & 1) 149 #define FASTTRAP_REX_B(rex) ((rex) & 1) 150 #define FASTTRAP_REX(w, r, x, b) \ 151 (0x40 | ((w) << 3) | ((r) << 2) | ((x) << 1) | (b)) 152 153 /* 154 * Single-byte op-codes. 155 */ 156 #define FASTTRAP_PUSHL_EBP 0x55 157 158 #define FASTTRAP_JO 0x70 159 #define FASTTRAP_JNO 0x71 160 #define FASTTRAP_JB 0x72 161 #define FASTTRAP_JAE 0x73 162 #define FASTTRAP_JE 0x74 163 #define FASTTRAP_JNE 0x75 164 #define FASTTRAP_JBE 0x76 165 #define FASTTRAP_JA 0x77 166 #define FASTTRAP_JS 0x78 167 #define FASTTRAP_JNS 0x79 168 #define FASTTRAP_JP 0x7a 169 #define FASTTRAP_JNP 0x7b 170 #define FASTTRAP_JL 0x7c 171 #define FASTTRAP_JGE 0x7d 172 #define FASTTRAP_JLE 0x7e 173 #define FASTTRAP_JG 0x7f 174 175 #define FASTTRAP_NOP 0x90 176 177 #define FASTTRAP_MOV_EAX 0xb8 178 #define FASTTRAP_MOV_ECX 0xb9 179 180 #define FASTTRAP_RET16 0xc2 181 #define FASTTRAP_RET 0xc3 182 183 #define FASTTRAP_LOOPNZ 0xe0 184 #define FASTTRAP_LOOPZ 0xe1 185 #define FASTTRAP_LOOP 0xe2 186 #define FASTTRAP_JCXZ 0xe3 187 188 #define FASTTRAP_CALL 0xe8 189 #define FASTTRAP_JMP32 0xe9 190 #define FASTTRAP_JMP8 0xeb 191 192 #define FASTTRAP_INT3 0xcc 193 #define FASTTRAP_INT 0xcd 194 195 #define FASTTRAP_2_BYTE_OP 0x0f 196 #define FASTTRAP_GROUP5_OP 0xff 197 198 /* 199 * Two-byte op-codes (second byte only). 200 */ 201 #define FASTTRAP_0F_JO 0x80 202 #define FASTTRAP_0F_JNO 0x81 203 #define FASTTRAP_0F_JB 0x82 204 #define FASTTRAP_0F_JAE 0x83 205 #define FASTTRAP_0F_JE 0x84 206 #define FASTTRAP_0F_JNE 0x85 207 #define FASTTRAP_0F_JBE 0x86 208 #define FASTTRAP_0F_JA 0x87 209 #define FASTTRAP_0F_JS 0x88 210 #define FASTTRAP_0F_JNS 0x89 211 #define FASTTRAP_0F_JP 0x8a 212 #define FASTTRAP_0F_JNP 0x8b 213 #define FASTTRAP_0F_JL 0x8c 214 #define FASTTRAP_0F_JGE 0x8d 215 #define FASTTRAP_0F_JLE 0x8e 216 #define FASTTRAP_0F_JG 0x8f 217 218 #define FASTTRAP_EFLAGS_OF 0x800 219 #define FASTTRAP_EFLAGS_DF 0x400 220 #define FASTTRAP_EFLAGS_SF 0x080 221 #define FASTTRAP_EFLAGS_ZF 0x040 222 #define FASTTRAP_EFLAGS_AF 0x010 223 #define FASTTRAP_EFLAGS_PF 0x004 224 #define FASTTRAP_EFLAGS_CF 0x001 225 226 /* 227 * Instruction prefixes. 228 */ 229 #define FASTTRAP_PREFIX_OPERAND 0x66 230 #define FASTTRAP_PREFIX_ADDRESS 0x67 231 #define FASTTRAP_PREFIX_CS 0x2E 232 #define FASTTRAP_PREFIX_DS 0x3E 233 #define FASTTRAP_PREFIX_ES 0x26 234 #define FASTTRAP_PREFIX_FS 0x64 235 #define FASTTRAP_PREFIX_GS 0x65 236 #define FASTTRAP_PREFIX_SS 0x36 237 #define FASTTRAP_PREFIX_LOCK 0xF0 238 #define FASTTRAP_PREFIX_REP 0xF3 239 #define FASTTRAP_PREFIX_REPNE 0xF2 240 241 #define FASTTRAP_NOREG 0xff 242 243 /* 244 * Map between instruction register encodings and the kernel constants which 245 * correspond to indicies into struct regs. 246 */ 247 #ifdef __amd64 248 static const uint8_t regmap[16] = { 249 REG_RAX, REG_RCX, REG_RDX, REG_RBX, REG_RSP, REG_RBP, REG_RSI, REG_RDI, 250 REG_R8, REG_R9, REG_R10, REG_R11, REG_R12, REG_R13, REG_R14, REG_R15, 251 }; 252 #else 253 static const uint8_t regmap[8] = { 254 EAX, ECX, EDX, EBX, UESP, EBP, ESI, EDI 255 }; 256 #endif 257 258 static ulong_t fasttrap_getreg(struct reg *, uint_t); 259 260 static uint64_t 261 fasttrap_anarg(struct reg *rp, int function_entry, int argno) 262 { 263 uint64_t value = 0; 264 int shift = function_entry ? 1 : 0; 265 266 #ifdef __amd64 267 if (curproc->p_model == DATAMODEL_LP64) { 268 uintptr_t *stack; 269 270 /* 271 * In 64-bit mode, the first six arguments are stored in 272 * registers. 273 */ 274 if (argno < 6) 275 return ((&rp->r_rdi)[argno]); 276 277 stack = (uintptr_t *)rp->r_rsp; 278 DTRACE_CPUFLAG_SET(CPU_DTRACE_NOFAULT); 279 value = dtrace_fulword(&stack[argno - 6 + shift]); 280 DTRACE_CPUFLAG_CLEAR(CPU_DTRACE_NOFAULT | CPU_DTRACE_BADADDR); 281 } else { 282 #endif 283 #ifdef __i386 284 uint32_t *stack = (uint32_t *)rp->r_esp; 285 DTRACE_CPUFLAG_SET(CPU_DTRACE_NOFAULT); 286 value = dtrace_fuword32(&stack[argno + shift]); 287 DTRACE_CPUFLAG_CLEAR(CPU_DTRACE_NOFAULT | CPU_DTRACE_BADADDR); 288 #endif 289 #ifdef __amd64 290 } 291 #endif 292 293 return (value); 294 } 295 296 /*ARGSUSED*/ 297 int 298 fasttrap_tracepoint_init(proc_t *p, fasttrap_tracepoint_t *tp, uintptr_t pc, 299 fasttrap_probe_type_t type) 300 { 301 uint8_t instr[FASTTRAP_MAX_INSTR_SIZE + 10]; 302 size_t len = FASTTRAP_MAX_INSTR_SIZE; 303 size_t first = MIN(len, PAGESIZE - (pc & PAGEOFFSET)); 304 uint_t start = 0; 305 int rmindex, size; 306 uint8_t seg, rex = 0; 307 308 /* 309 * Read the instruction at the given address out of the process's 310 * address space. We don't have to worry about a debugger 311 * changing this instruction before we overwrite it with our trap 312 * instruction since P_PR_LOCK is set. Since instructions can span 313 * pages, we potentially read the instruction in two parts. If the 314 * second part fails, we just zero out that part of the instruction. 315 */ 316 if (uread(p, &instr[0], first, pc) != 0) 317 return (-1); 318 if (len > first && 319 uread(p, &instr[first], len - first, pc + first) != 0) { 320 bzero(&instr[first], len - first); 321 len = first; 322 } 323 324 /* 325 * If the disassembly fails, then we have a malformed instruction. 326 */ 327 if ((size = dtrace_instr_size_isa(instr, p->p_model, &rmindex)) <= 0) 328 return (-1); 329 330 /* 331 * Make sure the disassembler isn't completely broken. 332 */ 333 ASSERT(-1 <= rmindex && rmindex < size); 334 335 /* 336 * If the computed size is greater than the number of bytes read, 337 * then it was a malformed instruction possibly because it fell on a 338 * page boundary and the subsequent page was missing or because of 339 * some malicious user. 340 */ 341 if (size > len) 342 return (-1); 343 344 tp->ftt_size = (uint8_t)size; 345 tp->ftt_segment = FASTTRAP_SEG_NONE; 346 347 /* 348 * Find the start of the instruction's opcode by processing any 349 * legacy prefixes. 350 */ 351 for (;;) { 352 seg = 0; 353 switch (instr[start]) { 354 case FASTTRAP_PREFIX_SS: 355 seg++; 356 /*FALLTHRU*/ 357 case FASTTRAP_PREFIX_GS: 358 seg++; 359 /*FALLTHRU*/ 360 case FASTTRAP_PREFIX_FS: 361 seg++; 362 /*FALLTHRU*/ 363 case FASTTRAP_PREFIX_ES: 364 seg++; 365 /*FALLTHRU*/ 366 case FASTTRAP_PREFIX_DS: 367 seg++; 368 /*FALLTHRU*/ 369 case FASTTRAP_PREFIX_CS: 370 seg++; 371 /*FALLTHRU*/ 372 case FASTTRAP_PREFIX_OPERAND: 373 case FASTTRAP_PREFIX_ADDRESS: 374 case FASTTRAP_PREFIX_LOCK: 375 case FASTTRAP_PREFIX_REP: 376 case FASTTRAP_PREFIX_REPNE: 377 if (seg != 0) { 378 /* 379 * It's illegal for an instruction to specify 380 * two segment prefixes -- give up on this 381 * illegal instruction. 382 */ 383 if (tp->ftt_segment != FASTTRAP_SEG_NONE) 384 return (-1); 385 386 tp->ftt_segment = seg; 387 } 388 start++; 389 continue; 390 } 391 break; 392 } 393 394 #ifdef __amd64 395 /* 396 * Identify the REX prefix on 64-bit processes. 397 */ 398 if (p->p_model == DATAMODEL_LP64 && (instr[start] & 0xf0) == 0x40) 399 rex = instr[start++]; 400 #endif 401 402 /* 403 * Now that we're pretty sure that the instruction is okay, copy the 404 * valid part to the tracepoint. 405 */ 406 bcopy(instr, tp->ftt_instr, FASTTRAP_MAX_INSTR_SIZE); 407 408 tp->ftt_type = FASTTRAP_T_COMMON; 409 if (instr[start] == FASTTRAP_2_BYTE_OP) { 410 switch (instr[start + 1]) { 411 case FASTTRAP_0F_JO: 412 case FASTTRAP_0F_JNO: 413 case FASTTRAP_0F_JB: 414 case FASTTRAP_0F_JAE: 415 case FASTTRAP_0F_JE: 416 case FASTTRAP_0F_JNE: 417 case FASTTRAP_0F_JBE: 418 case FASTTRAP_0F_JA: 419 case FASTTRAP_0F_JS: 420 case FASTTRAP_0F_JNS: 421 case FASTTRAP_0F_JP: 422 case FASTTRAP_0F_JNP: 423 case FASTTRAP_0F_JL: 424 case FASTTRAP_0F_JGE: 425 case FASTTRAP_0F_JLE: 426 case FASTTRAP_0F_JG: 427 tp->ftt_type = FASTTRAP_T_JCC; 428 tp->ftt_code = (instr[start + 1] & 0x0f) | FASTTRAP_JO; 429 tp->ftt_dest = pc + tp->ftt_size + 430 /* LINTED - alignment */ 431 *(int32_t *)&instr[start + 2]; 432 break; 433 } 434 } else if (instr[start] == FASTTRAP_GROUP5_OP) { 435 uint_t mod = FASTTRAP_MODRM_MOD(instr[start + 1]); 436 uint_t reg = FASTTRAP_MODRM_REG(instr[start + 1]); 437 uint_t rm = FASTTRAP_MODRM_RM(instr[start + 1]); 438 439 if (reg == 2 || reg == 4) { 440 uint_t i, sz; 441 442 if (reg == 2) 443 tp->ftt_type = FASTTRAP_T_CALL; 444 else 445 tp->ftt_type = FASTTRAP_T_JMP; 446 447 if (mod == 3) 448 tp->ftt_code = 2; 449 else 450 tp->ftt_code = 1; 451 452 ASSERT(p->p_model == DATAMODEL_LP64 || rex == 0); 453 454 /* 455 * See AMD x86-64 Architecture Programmer's Manual 456 * Volume 3, Section 1.2.7, Table 1-12, and 457 * Appendix A.3.1, Table A-15. 458 */ 459 if (mod != 3 && rm == 4) { 460 uint8_t sib = instr[start + 2]; 461 uint_t index = FASTTRAP_SIB_INDEX(sib); 462 uint_t base = FASTTRAP_SIB_BASE(sib); 463 464 tp->ftt_scale = FASTTRAP_SIB_SCALE(sib); 465 466 tp->ftt_index = (index == 4) ? 467 FASTTRAP_NOREG : 468 regmap[index | (FASTTRAP_REX_X(rex) << 3)]; 469 tp->ftt_base = (mod == 0 && base == 5) ? 470 FASTTRAP_NOREG : 471 regmap[base | (FASTTRAP_REX_B(rex) << 3)]; 472 473 i = 3; 474 sz = mod == 1 ? 1 : 4; 475 } else { 476 /* 477 * In 64-bit mode, mod == 0 and r/m == 5 478 * denotes %rip-relative addressing; in 32-bit 479 * mode, the base register isn't used. In both 480 * modes, there is a 32-bit operand. 481 */ 482 if (mod == 0 && rm == 5) { 483 #ifdef __amd64 484 if (p->p_model == DATAMODEL_LP64) 485 tp->ftt_base = REG_RIP; 486 else 487 #endif 488 tp->ftt_base = FASTTRAP_NOREG; 489 sz = 4; 490 } else { 491 uint8_t base = rm | 492 (FASTTRAP_REX_B(rex) << 3); 493 494 tp->ftt_base = regmap[base]; 495 sz = mod == 1 ? 1 : mod == 2 ? 4 : 0; 496 } 497 tp->ftt_index = FASTTRAP_NOREG; 498 i = 2; 499 } 500 501 if (sz == 1) { 502 tp->ftt_dest = *(int8_t *)&instr[start + i]; 503 } else if (sz == 4) { 504 /* LINTED - alignment */ 505 tp->ftt_dest = *(int32_t *)&instr[start + i]; 506 } else { 507 tp->ftt_dest = 0; 508 } 509 } 510 } else { 511 switch (instr[start]) { 512 case FASTTRAP_RET: 513 tp->ftt_type = FASTTRAP_T_RET; 514 break; 515 516 case FASTTRAP_RET16: 517 tp->ftt_type = FASTTRAP_T_RET16; 518 /* LINTED - alignment */ 519 tp->ftt_dest = *(uint16_t *)&instr[start + 1]; 520 break; 521 522 case FASTTRAP_JO: 523 case FASTTRAP_JNO: 524 case FASTTRAP_JB: 525 case FASTTRAP_JAE: 526 case FASTTRAP_JE: 527 case FASTTRAP_JNE: 528 case FASTTRAP_JBE: 529 case FASTTRAP_JA: 530 case FASTTRAP_JS: 531 case FASTTRAP_JNS: 532 case FASTTRAP_JP: 533 case FASTTRAP_JNP: 534 case FASTTRAP_JL: 535 case FASTTRAP_JGE: 536 case FASTTRAP_JLE: 537 case FASTTRAP_JG: 538 tp->ftt_type = FASTTRAP_T_JCC; 539 tp->ftt_code = instr[start]; 540 tp->ftt_dest = pc + tp->ftt_size + 541 (int8_t)instr[start + 1]; 542 break; 543 544 case FASTTRAP_LOOPNZ: 545 case FASTTRAP_LOOPZ: 546 case FASTTRAP_LOOP: 547 tp->ftt_type = FASTTRAP_T_LOOP; 548 tp->ftt_code = instr[start]; 549 tp->ftt_dest = pc + tp->ftt_size + 550 (int8_t)instr[start + 1]; 551 break; 552 553 case FASTTRAP_JCXZ: 554 tp->ftt_type = FASTTRAP_T_JCXZ; 555 tp->ftt_dest = pc + tp->ftt_size + 556 (int8_t)instr[start + 1]; 557 break; 558 559 case FASTTRAP_CALL: 560 tp->ftt_type = FASTTRAP_T_CALL; 561 tp->ftt_dest = pc + tp->ftt_size + 562 /* LINTED - alignment */ 563 *(int32_t *)&instr[start + 1]; 564 tp->ftt_code = 0; 565 break; 566 567 case FASTTRAP_JMP32: 568 tp->ftt_type = FASTTRAP_T_JMP; 569 tp->ftt_dest = pc + tp->ftt_size + 570 /* LINTED - alignment */ 571 *(int32_t *)&instr[start + 1]; 572 break; 573 case FASTTRAP_JMP8: 574 tp->ftt_type = FASTTRAP_T_JMP; 575 tp->ftt_dest = pc + tp->ftt_size + 576 (int8_t)instr[start + 1]; 577 break; 578 579 case FASTTRAP_PUSHL_EBP: 580 if (start == 0) 581 tp->ftt_type = FASTTRAP_T_PUSHL_EBP; 582 break; 583 584 case FASTTRAP_NOP: 585 #ifdef __amd64 586 ASSERT(p->p_model == DATAMODEL_LP64 || rex == 0); 587 588 /* 589 * On amd64 we have to be careful not to confuse a nop 590 * (actually xchgl %eax, %eax) with an instruction using 591 * the same opcode, but that does something different 592 * (e.g. xchgl %r8d, %eax or xcghq %r8, %rax). 593 */ 594 if (FASTTRAP_REX_B(rex) == 0) 595 #endif 596 tp->ftt_type = FASTTRAP_T_NOP; 597 break; 598 599 case FASTTRAP_INT3: 600 /* 601 * The pid provider shares the int3 trap with debugger 602 * breakpoints so we can't instrument them. 603 */ 604 ASSERT(instr[start] == FASTTRAP_INSTR); 605 return (-1); 606 607 case FASTTRAP_INT: 608 /* 609 * Interrupts seem like they could be traced with 610 * no negative implications, but it's possible that 611 * a thread could be redirected by the trap handling 612 * code which would eventually return to the 613 * instruction after the interrupt. If the interrupt 614 * were in our scratch space, the subsequent 615 * instruction might be overwritten before we return. 616 * Accordingly we refuse to instrument any interrupt. 617 */ 618 return (-1); 619 } 620 } 621 622 #ifdef __amd64 623 if (p->p_model == DATAMODEL_LP64 && tp->ftt_type == FASTTRAP_T_COMMON) { 624 /* 625 * If the process is 64-bit and the instruction type is still 626 * FASTTRAP_T_COMMON -- meaning we're going to copy it out an 627 * execute it -- we need to watch for %rip-relative 628 * addressing mode. See the portion of fasttrap_pid_probe() 629 * below where we handle tracepoints with type 630 * FASTTRAP_T_COMMON for how we emulate instructions that 631 * employ %rip-relative addressing. 632 */ 633 if (rmindex != -1) { 634 uint_t mod = FASTTRAP_MODRM_MOD(instr[rmindex]); 635 uint_t reg = FASTTRAP_MODRM_REG(instr[rmindex]); 636 uint_t rm = FASTTRAP_MODRM_RM(instr[rmindex]); 637 638 ASSERT(rmindex > start); 639 640 if (mod == 0 && rm == 5) { 641 /* 642 * We need to be sure to avoid other 643 * registers used by this instruction. While 644 * the reg field may determine the op code 645 * rather than denoting a register, assuming 646 * that it denotes a register is always safe. 647 * We leave the REX field intact and use 648 * whatever value's there for simplicity. 649 */ 650 if (reg != 0) { 651 tp->ftt_ripmode = FASTTRAP_RIP_1 | 652 (FASTTRAP_RIP_X * 653 FASTTRAP_REX_B(rex)); 654 rm = 0; 655 } else { 656 tp->ftt_ripmode = FASTTRAP_RIP_2 | 657 (FASTTRAP_RIP_X * 658 FASTTRAP_REX_B(rex)); 659 rm = 1; 660 } 661 662 tp->ftt_modrm = tp->ftt_instr[rmindex]; 663 tp->ftt_instr[rmindex] = 664 FASTTRAP_MODRM(2, reg, rm); 665 } 666 } 667 } 668 #endif 669 670 return (0); 671 } 672 673 int 674 fasttrap_tracepoint_install(proc_t *p, fasttrap_tracepoint_t *tp) 675 { 676 fasttrap_instr_t instr = FASTTRAP_INSTR; 677 678 if (uwrite(p, &instr, 1, tp->ftt_pc) != 0) 679 return (-1); 680 681 return (0); 682 } 683 684 int 685 fasttrap_tracepoint_remove(proc_t *p, fasttrap_tracepoint_t *tp) 686 { 687 uint8_t instr; 688 689 /* 690 * Distinguish between read or write failures and a changed 691 * instruction. 692 */ 693 if (uread(p, &instr, 1, tp->ftt_pc) != 0) 694 return (0); 695 if (instr != FASTTRAP_INSTR) 696 return (0); 697 if (uwrite(p, &tp->ftt_instr[0], 1, tp->ftt_pc) != 0) 698 return (-1); 699 700 return (0); 701 } 702 703 #ifdef __amd64 704 static uintptr_t 705 fasttrap_fulword_noerr(const void *uaddr) 706 { 707 uintptr_t ret; 708 709 if ((ret = fasttrap_fulword(uaddr)) != -1) 710 return (ret); 711 712 return (0); 713 } 714 #endif 715 716 #ifdef __i386__ 717 static uint32_t 718 fasttrap_fuword32_noerr(const void *uaddr) 719 { 720 uint32_t ret; 721 722 if ((ret = fasttrap_fuword32(uaddr)) != -1) 723 return (ret); 724 725 return (0); 726 } 727 #endif 728 729 static void 730 fasttrap_return_common(struct reg *rp, uintptr_t pc, pid_t pid, 731 uintptr_t new_pc) 732 { 733 fasttrap_tracepoint_t *tp; 734 fasttrap_bucket_t *bucket; 735 fasttrap_id_t *id; 736 #if defined(sun) 737 kmutex_t *pid_mtx; 738 #endif 739 740 #if defined(sun) 741 pid_mtx = &cpu_core[CPU->cpu_id].cpuc_pid_lock; 742 mutex_enter(pid_mtx); 743 #endif 744 bucket = &fasttrap_tpoints.fth_table[FASTTRAP_TPOINTS_INDEX(pid, pc)]; 745 746 for (tp = bucket->ftb_data; tp != NULL; tp = tp->ftt_next) { 747 if (pid == tp->ftt_pid && pc == tp->ftt_pc && 748 tp->ftt_proc->ftpc_acount != 0) 749 break; 750 } 751 752 /* 753 * Don't sweat it if we can't find the tracepoint again; unlike 754 * when we're in fasttrap_pid_probe(), finding the tracepoint here 755 * is not essential to the correct execution of the process. 756 */ 757 if (tp == NULL) { 758 #if defined(sun) 759 mutex_exit(pid_mtx); 760 #endif 761 return; 762 } 763 764 for (id = tp->ftt_retids; id != NULL; id = id->fti_next) { 765 /* 766 * If there's a branch that could act as a return site, we 767 * need to trace it, and check here if the program counter is 768 * external to the function. 769 */ 770 if (tp->ftt_type != FASTTRAP_T_RET && 771 tp->ftt_type != FASTTRAP_T_RET16 && 772 new_pc - id->fti_probe->ftp_faddr < 773 id->fti_probe->ftp_fsize) 774 continue; 775 776 dtrace_probe(id->fti_probe->ftp_id, 777 pc - id->fti_probe->ftp_faddr, 778 rp->r_rax, rp->r_rbx, 0, 0); 779 } 780 781 #if defined(sun) 782 mutex_exit(pid_mtx); 783 #endif 784 } 785 786 static void 787 fasttrap_sigsegv(proc_t *p, kthread_t *t, uintptr_t addr) 788 { 789 #if defined(sun) 790 sigqueue_t *sqp = kmem_zalloc(sizeof (sigqueue_t), KM_SLEEP); 791 792 sqp->sq_info.si_signo = SIGSEGV; 793 sqp->sq_info.si_code = SEGV_MAPERR; 794 sqp->sq_info.si_addr = (caddr_t)addr; 795 796 mutex_enter(&p->p_lock); 797 sigaddqa(p, t, sqp); 798 mutex_exit(&p->p_lock); 799 800 if (t != NULL) 801 aston(t); 802 #else 803 ksiginfo_t *ksi = kmem_zalloc(sizeof (ksiginfo_t), KM_SLEEP); 804 805 ksiginfo_init(ksi); 806 ksi->ksi_signo = SIGSEGV; 807 ksi->ksi_code = SEGV_MAPERR; 808 ksi->ksi_addr = (caddr_t)addr; 809 (void) tdksignal(t, SIGSEGV, ksi); 810 #endif 811 } 812 813 #ifdef __amd64 814 static void 815 fasttrap_usdt_args64(fasttrap_probe_t *probe, struct reg *rp, int argc, 816 uintptr_t *argv) 817 { 818 int i, x, cap = MIN(argc, probe->ftp_nargs); 819 uintptr_t *stack = (uintptr_t *)rp->r_rsp; 820 821 for (i = 0; i < cap; i++) { 822 x = probe->ftp_argmap[i]; 823 824 if (x < 6) 825 argv[i] = (&rp->r_rdi)[x]; 826 else 827 argv[i] = fasttrap_fulword_noerr(&stack[x]); 828 } 829 830 for (; i < argc; i++) { 831 argv[i] = 0; 832 } 833 } 834 #endif 835 836 #ifdef __i386__ 837 static void 838 fasttrap_usdt_args32(fasttrap_probe_t *probe, struct reg *rp, int argc, 839 uint32_t *argv) 840 { 841 int i, x, cap = MIN(argc, probe->ftp_nargs); 842 uint32_t *stack = (uint32_t *)rp->r_rsp; 843 844 for (i = 0; i < cap; i++) { 845 x = probe->ftp_argmap[i]; 846 847 argv[i] = fasttrap_fuword32_noerr(&stack[x]); 848 } 849 850 for (; i < argc; i++) { 851 argv[i] = 0; 852 } 853 } 854 #endif 855 856 static int 857 fasttrap_do_seg(fasttrap_tracepoint_t *tp, struct reg *rp, uintptr_t *addr) 858 { 859 proc_t *p = curproc; 860 #ifdef __i386__ 861 struct segment_descriptor *desc; 862 #else 863 struct user_segment_descriptor *desc; 864 #endif 865 uint16_t sel = 0, ndx, type; 866 uintptr_t limit; 867 868 switch (tp->ftt_segment) { 869 case FASTTRAP_SEG_CS: 870 sel = rp->r_cs; 871 break; 872 case FASTTRAP_SEG_DS: 873 sel = rp->r_ds; 874 break; 875 case FASTTRAP_SEG_ES: 876 sel = rp->r_es; 877 break; 878 case FASTTRAP_SEG_FS: 879 sel = rp->r_fs; 880 break; 881 case FASTTRAP_SEG_GS: 882 sel = rp->r_gs; 883 break; 884 case FASTTRAP_SEG_SS: 885 sel = rp->r_ss; 886 break; 887 } 888 889 /* 890 * Make sure the given segment register specifies a user priority 891 * selector rather than a kernel selector. 892 */ 893 if (ISPL(sel) != SEL_UPL) 894 return (-1); 895 896 ndx = IDXSEL(sel); 897 898 /* 899 * Check the bounds and grab the descriptor out of the specified 900 * descriptor table. 901 */ 902 if (ISLDT(sel)) { 903 #ifdef __i386__ 904 if (ndx > p->p_md.md_ldt->ldt_len) 905 return (-1); 906 907 desc = (struct segment_descriptor *) 908 p->p_md.md_ldt[ndx].ldt_base; 909 #else 910 if (ndx > max_ldt_segment) 911 return (-1); 912 913 desc = (struct user_segment_descriptor *) 914 p->p_md.md_ldt[ndx].ldt_base; 915 #endif 916 917 } else { 918 if (ndx >= NGDT) 919 return (-1); 920 921 #ifdef __i386__ 922 desc = &gdt[ndx].sd; 923 #else 924 desc = &gdt[ndx]; 925 #endif 926 } 927 928 /* 929 * The descriptor must have user privilege level and it must be 930 * present in memory. 931 */ 932 if (desc->sd_dpl != SEL_UPL || desc->sd_p != 1) 933 return (-1); 934 935 type = desc->sd_type; 936 937 /* 938 * If the S bit in the type field is not set, this descriptor can 939 * only be used in system context. 940 */ 941 if ((type & 0x10) != 0x10) 942 return (-1); 943 944 limit = USD_GETLIMIT(desc) * (desc->sd_gran ? PAGESIZE : 1); 945 946 if (tp->ftt_segment == FASTTRAP_SEG_CS) { 947 /* 948 * The code/data bit and readable bit must both be set. 949 */ 950 if ((type & 0xa) != 0xa) 951 return (-1); 952 953 if (*addr > limit) 954 return (-1); 955 } else { 956 /* 957 * The code/data bit must be clear. 958 */ 959 if ((type & 0x8) != 0) 960 return (-1); 961 962 /* 963 * If the expand-down bit is clear, we just check the limit as 964 * it would naturally be applied. Otherwise, we need to check 965 * that the address is the range [limit + 1 .. 0xffff] or 966 * [limit + 1 ... 0xffffffff] depending on if the default 967 * operand size bit is set. 968 */ 969 if ((type & 0x4) == 0) { 970 if (*addr > limit) 971 return (-1); 972 } else if (desc->sd_def32) { 973 if (*addr < limit + 1 || 0xffff < *addr) 974 return (-1); 975 } else { 976 if (*addr < limit + 1 || 0xffffffff < *addr) 977 return (-1); 978 } 979 } 980 981 *addr += USD_GETBASE(desc); 982 983 return (0); 984 } 985 986 int 987 fasttrap_pid_probe(struct reg *rp) 988 { 989 proc_t *p = curproc; 990 uintptr_t pc = rp->r_rip - 1; 991 uintptr_t new_pc = 0; 992 fasttrap_bucket_t *bucket; 993 #if defined(sun) 994 kmutex_t *pid_mtx; 995 #endif 996 fasttrap_tracepoint_t *tp, tp_local; 997 pid_t pid; 998 dtrace_icookie_t cookie; 999 uint_t is_enabled = 0; 1000 1001 /* 1002 * It's possible that a user (in a veritable orgy of bad planning) 1003 * could redirect this thread's flow of control before it reached the 1004 * return probe fasttrap. In this case we need to kill the process 1005 * since it's in a unrecoverable state. 1006 */ 1007 if (curthread->t_dtrace_step) { 1008 ASSERT(curthread->t_dtrace_on); 1009 fasttrap_sigtrap(p, curthread, pc); 1010 return (0); 1011 } 1012 1013 /* 1014 * Clear all user tracing flags. 1015 */ 1016 curthread->t_dtrace_ft = 0; 1017 curthread->t_dtrace_pc = 0; 1018 curthread->t_dtrace_npc = 0; 1019 curthread->t_dtrace_scrpc = 0; 1020 curthread->t_dtrace_astpc = 0; 1021 #ifdef __amd64 1022 curthread->t_dtrace_regv = 0; 1023 #endif 1024 1025 #if defined(sun) 1026 /* 1027 * Treat a child created by a call to vfork(2) as if it were its 1028 * parent. We know that there's only one thread of control in such a 1029 * process: this one. 1030 */ 1031 while (p->p_flag & SVFORK) { 1032 p = p->p_parent; 1033 } 1034 #endif 1035 1036 PROC_LOCK(p); 1037 pid = p->p_pid; 1038 #if defined(sun) 1039 pid_mtx = &cpu_core[CPU->cpu_id].cpuc_pid_lock; 1040 mutex_enter(pid_mtx); 1041 #endif 1042 bucket = &fasttrap_tpoints.fth_table[FASTTRAP_TPOINTS_INDEX(pid, pc)]; 1043 1044 /* 1045 * Lookup the tracepoint that the process just hit. 1046 */ 1047 for (tp = bucket->ftb_data; tp != NULL; tp = tp->ftt_next) { 1048 if (pid == tp->ftt_pid && pc == tp->ftt_pc && 1049 tp->ftt_proc->ftpc_acount != 0) 1050 break; 1051 } 1052 1053 /* 1054 * If we couldn't find a matching tracepoint, either a tracepoint has 1055 * been inserted without using the pid<pid> ioctl interface (see 1056 * fasttrap_ioctl), or somehow we have mislaid this tracepoint. 1057 */ 1058 if (tp == NULL) { 1059 #if defined(sun) 1060 mutex_exit(pid_mtx); 1061 #endif 1062 PROC_UNLOCK(p); 1063 return (-1); 1064 } 1065 1066 /* 1067 * Set the program counter to the address of the traced instruction 1068 * so that it looks right in ustack() output. 1069 */ 1070 rp->r_rip = pc; 1071 1072 if (tp->ftt_ids != NULL) { 1073 fasttrap_id_t *id; 1074 1075 #ifdef __amd64 1076 if (p->p_model == DATAMODEL_LP64) { 1077 for (id = tp->ftt_ids; id != NULL; id = id->fti_next) { 1078 fasttrap_probe_t *probe = id->fti_probe; 1079 1080 if (id->fti_ptype == DTFTP_ENTRY) { 1081 /* 1082 * We note that this was an entry 1083 * probe to help ustack() find the 1084 * first caller. 1085 */ 1086 cookie = dtrace_interrupt_disable(); 1087 DTRACE_CPUFLAG_SET(CPU_DTRACE_ENTRY); 1088 dtrace_probe(probe->ftp_id, rp->r_rdi, 1089 rp->r_rsi, rp->r_rdx, rp->r_rcx, 1090 rp->r_r8); 1091 DTRACE_CPUFLAG_CLEAR(CPU_DTRACE_ENTRY); 1092 dtrace_interrupt_enable(cookie); 1093 } else if (id->fti_ptype == DTFTP_IS_ENABLED) { 1094 /* 1095 * Note that in this case, we don't 1096 * call dtrace_probe() since it's only 1097 * an artificial probe meant to change 1098 * the flow of control so that it 1099 * encounters the true probe. 1100 */ 1101 is_enabled = 1; 1102 } else if (probe->ftp_argmap == NULL) { 1103 dtrace_probe(probe->ftp_id, rp->r_rdi, 1104 rp->r_rsi, rp->r_rdx, rp->r_rcx, 1105 rp->r_r8); 1106 } else { 1107 uintptr_t t[5]; 1108 1109 fasttrap_usdt_args64(probe, rp, 1110 sizeof (t) / sizeof (t[0]), t); 1111 1112 dtrace_probe(probe->ftp_id, t[0], t[1], 1113 t[2], t[3], t[4]); 1114 } 1115 } 1116 } else { 1117 #else /* __amd64 */ 1118 uintptr_t s0, s1, s2, s3, s4, s5; 1119 uint32_t *stack = (uint32_t *)rp->r_esp; 1120 1121 /* 1122 * In 32-bit mode, all arguments are passed on the 1123 * stack. If this is a function entry probe, we need 1124 * to skip the first entry on the stack as it 1125 * represents the return address rather than a 1126 * parameter to the function. 1127 */ 1128 s0 = fasttrap_fuword32_noerr(&stack[0]); 1129 s1 = fasttrap_fuword32_noerr(&stack[1]); 1130 s2 = fasttrap_fuword32_noerr(&stack[2]); 1131 s3 = fasttrap_fuword32_noerr(&stack[3]); 1132 s4 = fasttrap_fuword32_noerr(&stack[4]); 1133 s5 = fasttrap_fuword32_noerr(&stack[5]); 1134 1135 for (id = tp->ftt_ids; id != NULL; id = id->fti_next) { 1136 fasttrap_probe_t *probe = id->fti_probe; 1137 1138 if (id->fti_ptype == DTFTP_ENTRY) { 1139 /* 1140 * We note that this was an entry 1141 * probe to help ustack() find the 1142 * first caller. 1143 */ 1144 cookie = dtrace_interrupt_disable(); 1145 DTRACE_CPUFLAG_SET(CPU_DTRACE_ENTRY); 1146 dtrace_probe(probe->ftp_id, s1, s2, 1147 s3, s4, s5); 1148 DTRACE_CPUFLAG_CLEAR(CPU_DTRACE_ENTRY); 1149 dtrace_interrupt_enable(cookie); 1150 } else if (id->fti_ptype == DTFTP_IS_ENABLED) { 1151 /* 1152 * Note that in this case, we don't 1153 * call dtrace_probe() since it's only 1154 * an artificial probe meant to change 1155 * the flow of control so that it 1156 * encounters the true probe. 1157 */ 1158 is_enabled = 1; 1159 } else if (probe->ftp_argmap == NULL) { 1160 dtrace_probe(probe->ftp_id, s0, s1, 1161 s2, s3, s4); 1162 } else { 1163 uint32_t t[5]; 1164 1165 fasttrap_usdt_args32(probe, rp, 1166 sizeof (t) / sizeof (t[0]), t); 1167 1168 dtrace_probe(probe->ftp_id, t[0], t[1], 1169 t[2], t[3], t[4]); 1170 } 1171 } 1172 #endif /* __amd64 */ 1173 #ifdef __amd64 1174 } 1175 #endif 1176 } 1177 1178 /* 1179 * We're about to do a bunch of work so we cache a local copy of 1180 * the tracepoint to emulate the instruction, and then find the 1181 * tracepoint again later if we need to light up any return probes. 1182 */ 1183 tp_local = *tp; 1184 PROC_UNLOCK(p); 1185 #if defined(sun) 1186 mutex_exit(pid_mtx); 1187 #endif 1188 tp = &tp_local; 1189 1190 /* 1191 * Set the program counter to appear as though the traced instruction 1192 * had completely executed. This ensures that fasttrap_getreg() will 1193 * report the expected value for REG_RIP. 1194 */ 1195 rp->r_rip = pc + tp->ftt_size; 1196 1197 /* 1198 * If there's an is-enabled probe connected to this tracepoint it 1199 * means that there was a 'xorl %eax, %eax' or 'xorq %rax, %rax' 1200 * instruction that was placed there by DTrace when the binary was 1201 * linked. As this probe is, in fact, enabled, we need to stuff 1 1202 * into %eax or %rax. Accordingly, we can bypass all the instruction 1203 * emulation logic since we know the inevitable result. It's possible 1204 * that a user could construct a scenario where the 'is-enabled' 1205 * probe was on some other instruction, but that would be a rather 1206 * exotic way to shoot oneself in the foot. 1207 */ 1208 if (is_enabled) { 1209 rp->r_rax = 1; 1210 new_pc = rp->r_rip; 1211 goto done; 1212 } 1213 1214 /* 1215 * We emulate certain types of instructions to ensure correctness 1216 * (in the case of position dependent instructions) or optimize 1217 * common cases. The rest we have the thread execute back in user- 1218 * land. 1219 */ 1220 switch (tp->ftt_type) { 1221 case FASTTRAP_T_RET: 1222 case FASTTRAP_T_RET16: 1223 { 1224 uintptr_t dst = 0; 1225 uintptr_t addr = 0; 1226 int ret = 0; 1227 1228 /* 1229 * We have to emulate _every_ facet of the behavior of a ret 1230 * instruction including what happens if the load from %esp 1231 * fails; in that case, we send a SIGSEGV. 1232 */ 1233 #ifdef __amd64 1234 if (p->p_model == DATAMODEL_NATIVE) { 1235 ret = dst = fasttrap_fulword((void *)rp->r_rsp); 1236 addr = rp->r_rsp + sizeof (uintptr_t); 1237 } else { 1238 #endif 1239 #ifdef __i386__ 1240 uint32_t dst32; 1241 ret = dst32 = fasttrap_fuword32((void *)rp->r_esp); 1242 dst = dst32; 1243 addr = rp->r_esp + sizeof (uint32_t); 1244 #endif 1245 #ifdef __amd64 1246 } 1247 #endif 1248 1249 if (ret == -1) { 1250 fasttrap_sigsegv(p, curthread, rp->r_rsp); 1251 new_pc = pc; 1252 break; 1253 } 1254 1255 if (tp->ftt_type == FASTTRAP_T_RET16) 1256 addr += tp->ftt_dest; 1257 1258 rp->r_rsp = addr; 1259 new_pc = dst; 1260 break; 1261 } 1262 1263 case FASTTRAP_T_JCC: 1264 { 1265 uint_t taken = 0; 1266 1267 switch (tp->ftt_code) { 1268 case FASTTRAP_JO: 1269 taken = (rp->r_rflags & FASTTRAP_EFLAGS_OF) != 0; 1270 break; 1271 case FASTTRAP_JNO: 1272 taken = (rp->r_rflags & FASTTRAP_EFLAGS_OF) == 0; 1273 break; 1274 case FASTTRAP_JB: 1275 taken = (rp->r_rflags & FASTTRAP_EFLAGS_CF) != 0; 1276 break; 1277 case FASTTRAP_JAE: 1278 taken = (rp->r_rflags & FASTTRAP_EFLAGS_CF) == 0; 1279 break; 1280 case FASTTRAP_JE: 1281 taken = (rp->r_rflags & FASTTRAP_EFLAGS_ZF) != 0; 1282 break; 1283 case FASTTRAP_JNE: 1284 taken = (rp->r_rflags & FASTTRAP_EFLAGS_ZF) == 0; 1285 break; 1286 case FASTTRAP_JBE: 1287 taken = (rp->r_rflags & FASTTRAP_EFLAGS_CF) != 0 || 1288 (rp->r_rflags & FASTTRAP_EFLAGS_ZF) != 0; 1289 break; 1290 case FASTTRAP_JA: 1291 taken = (rp->r_rflags & FASTTRAP_EFLAGS_CF) == 0 && 1292 (rp->r_rflags & FASTTRAP_EFLAGS_ZF) == 0; 1293 break; 1294 case FASTTRAP_JS: 1295 taken = (rp->r_rflags & FASTTRAP_EFLAGS_SF) != 0; 1296 break; 1297 case FASTTRAP_JNS: 1298 taken = (rp->r_rflags & FASTTRAP_EFLAGS_SF) == 0; 1299 break; 1300 case FASTTRAP_JP: 1301 taken = (rp->r_rflags & FASTTRAP_EFLAGS_PF) != 0; 1302 break; 1303 case FASTTRAP_JNP: 1304 taken = (rp->r_rflags & FASTTRAP_EFLAGS_PF) == 0; 1305 break; 1306 case FASTTRAP_JL: 1307 taken = ((rp->r_rflags & FASTTRAP_EFLAGS_SF) == 0) != 1308 ((rp->r_rflags & FASTTRAP_EFLAGS_OF) == 0); 1309 break; 1310 case FASTTRAP_JGE: 1311 taken = ((rp->r_rflags & FASTTRAP_EFLAGS_SF) == 0) == 1312 ((rp->r_rflags & FASTTRAP_EFLAGS_OF) == 0); 1313 break; 1314 case FASTTRAP_JLE: 1315 taken = (rp->r_rflags & FASTTRAP_EFLAGS_ZF) != 0 || 1316 ((rp->r_rflags & FASTTRAP_EFLAGS_SF) == 0) != 1317 ((rp->r_rflags & FASTTRAP_EFLAGS_OF) == 0); 1318 break; 1319 case FASTTRAP_JG: 1320 taken = (rp->r_rflags & FASTTRAP_EFLAGS_ZF) == 0 && 1321 ((rp->r_rflags & FASTTRAP_EFLAGS_SF) == 0) == 1322 ((rp->r_rflags & FASTTRAP_EFLAGS_OF) == 0); 1323 break; 1324 1325 } 1326 1327 if (taken) 1328 new_pc = tp->ftt_dest; 1329 else 1330 new_pc = pc + tp->ftt_size; 1331 break; 1332 } 1333 1334 case FASTTRAP_T_LOOP: 1335 { 1336 uint_t taken = 0; 1337 #ifdef __amd64 1338 greg_t cx = rp->r_rcx--; 1339 #else 1340 greg_t cx = rp->r_ecx--; 1341 #endif 1342 1343 switch (tp->ftt_code) { 1344 case FASTTRAP_LOOPNZ: 1345 taken = (rp->r_rflags & FASTTRAP_EFLAGS_ZF) == 0 && 1346 cx != 0; 1347 break; 1348 case FASTTRAP_LOOPZ: 1349 taken = (rp->r_rflags & FASTTRAP_EFLAGS_ZF) != 0 && 1350 cx != 0; 1351 break; 1352 case FASTTRAP_LOOP: 1353 taken = (cx != 0); 1354 break; 1355 } 1356 1357 if (taken) 1358 new_pc = tp->ftt_dest; 1359 else 1360 new_pc = pc + tp->ftt_size; 1361 break; 1362 } 1363 1364 case FASTTRAP_T_JCXZ: 1365 { 1366 #ifdef __amd64 1367 greg_t cx = rp->r_rcx; 1368 #else 1369 greg_t cx = rp->r_ecx; 1370 #endif 1371 1372 if (cx == 0) 1373 new_pc = tp->ftt_dest; 1374 else 1375 new_pc = pc + tp->ftt_size; 1376 break; 1377 } 1378 1379 case FASTTRAP_T_PUSHL_EBP: 1380 { 1381 int ret = 0; 1382 uintptr_t addr = 0; 1383 #ifdef __amd64 1384 if (p->p_model == DATAMODEL_NATIVE) { 1385 addr = rp->r_rsp - sizeof (uintptr_t); 1386 ret = fasttrap_sulword((void *)addr, &rp->r_rsp); 1387 } else { 1388 #endif 1389 #ifdef __i386__ 1390 addr = rp->r_rsp - sizeof (uint32_t); 1391 ret = fasttrap_suword32((void *)addr, &rp->r_rsp); 1392 #endif 1393 #ifdef __amd64 1394 } 1395 #endif 1396 1397 if (ret == -1) { 1398 fasttrap_sigsegv(p, curthread, addr); 1399 new_pc = pc; 1400 break; 1401 } 1402 1403 rp->r_rsp = addr; 1404 new_pc = pc + tp->ftt_size; 1405 break; 1406 } 1407 1408 case FASTTRAP_T_NOP: 1409 new_pc = pc + tp->ftt_size; 1410 break; 1411 1412 case FASTTRAP_T_JMP: 1413 case FASTTRAP_T_CALL: 1414 if (tp->ftt_code == 0) { 1415 new_pc = tp->ftt_dest; 1416 } else { 1417 #ifdef __amd64 1418 uintptr_t value; 1419 #endif 1420 uintptr_t addr = tp->ftt_dest; 1421 1422 if (tp->ftt_base != FASTTRAP_NOREG) 1423 addr += fasttrap_getreg(rp, tp->ftt_base); 1424 if (tp->ftt_index != FASTTRAP_NOREG) 1425 addr += fasttrap_getreg(rp, tp->ftt_index) << 1426 tp->ftt_scale; 1427 1428 if (tp->ftt_code == 1) { 1429 /* 1430 * If there's a segment prefix for this 1431 * instruction, we'll need to check permissions 1432 * and bounds on the given selector, and adjust 1433 * the address accordingly. 1434 */ 1435 if (tp->ftt_segment != FASTTRAP_SEG_NONE && 1436 fasttrap_do_seg(tp, rp, &addr) != 0) { 1437 fasttrap_sigsegv(p, curthread, addr); 1438 new_pc = pc; 1439 break; 1440 } 1441 1442 #ifdef __amd64 1443 if (p->p_model == DATAMODEL_NATIVE) { 1444 if ((value = fasttrap_fulword((void *)addr)) 1445 == -1) { 1446 fasttrap_sigsegv(p, curthread, 1447 addr); 1448 new_pc = pc; 1449 break; 1450 } 1451 new_pc = value; 1452 } else { 1453 #endif 1454 #ifdef __i386__ 1455 uint32_t value32; 1456 addr = (uintptr_t)(uint32_t)addr; 1457 if ((value32 = fasttrap_fuword32((void *)addr)) 1458 == -1) { 1459 fasttrap_sigsegv(p, curthread, 1460 addr); 1461 new_pc = pc; 1462 break; 1463 } 1464 new_pc = value32; 1465 #endif 1466 } 1467 #ifdef __amd64 1468 } else { 1469 new_pc = addr; 1470 } 1471 #endif 1472 } 1473 1474 /* 1475 * If this is a call instruction, we need to push the return 1476 * address onto the stack. If this fails, we send the process 1477 * a SIGSEGV and reset the pc to emulate what would happen if 1478 * this instruction weren't traced. 1479 */ 1480 if (tp->ftt_type == FASTTRAP_T_CALL) { 1481 int ret = 0; 1482 uintptr_t addr = 0, pcps; 1483 #ifdef __amd64 1484 if (p->p_model == DATAMODEL_NATIVE) { 1485 addr = rp->r_rsp - sizeof (uintptr_t); 1486 pcps = pc + tp->ftt_size; 1487 ret = fasttrap_sulword((void *)addr, &pcps); 1488 } else { 1489 #endif 1490 #ifdef __i386__ 1491 addr = rp->r_rsp - sizeof (uint32_t); 1492 pcps = (uint32_t)(pc + tp->ftt_size); 1493 ret = fasttrap_suword32((void *)addr, &pcps); 1494 #endif 1495 #ifdef __amd64 1496 } 1497 #endif 1498 1499 if (ret == -1) { 1500 fasttrap_sigsegv(p, curthread, addr); 1501 new_pc = pc; 1502 break; 1503 } 1504 1505 rp->r_rsp = addr; 1506 } 1507 1508 break; 1509 1510 case FASTTRAP_T_COMMON: 1511 { 1512 uintptr_t addr; 1513 #if defined(__amd64) 1514 uint8_t scratch[2 * FASTTRAP_MAX_INSTR_SIZE + 22]; 1515 #else 1516 uint8_t scratch[2 * FASTTRAP_MAX_INSTR_SIZE + 7]; 1517 #endif 1518 uint_t i = 0; 1519 #if defined(sun) 1520 klwp_t *lwp = ttolwp(curthread); 1521 #endif 1522 1523 /* 1524 * Compute the address of the ulwp_t and step over the 1525 * ul_self pointer. The method used to store the user-land 1526 * thread pointer is very different on 32- and 64-bit 1527 * kernels. 1528 */ 1529 #if defined(sun) 1530 #if defined(__amd64) 1531 if (p->p_model == DATAMODEL_LP64) { 1532 addr = lwp->lwp_pcb.pcb_fsbase; 1533 addr += sizeof (void *); 1534 } else { 1535 addr = lwp->lwp_pcb.pcb_gsbase; 1536 addr += sizeof (caddr32_t); 1537 } 1538 #else 1539 addr = USD_GETBASE(&lwp->lwp_pcb.pcb_gsdesc); 1540 addr += sizeof (void *); 1541 #endif 1542 #endif /* sun */ 1543 #ifdef __i386__ 1544 addr = USD_GETBASE(&curthread->td_pcb->pcb_gsd); 1545 #else 1546 addr = curthread->td_pcb->pcb_gsbase; 1547 #endif 1548 addr += sizeof (void *); 1549 1550 /* 1551 * Generic Instruction Tracing 1552 * --------------------------- 1553 * 1554 * This is the layout of the scratch space in the user-land 1555 * thread structure for our generated instructions. 1556 * 1557 * 32-bit mode bytes 1558 * ------------------------ ----- 1559 * a: <original instruction> <= 15 1560 * jmp <pc + tp->ftt_size> 5 1561 * b: <original instrction> <= 15 1562 * int T_DTRACE_RET 2 1563 * ----- 1564 * <= 37 1565 * 1566 * 64-bit mode bytes 1567 * ------------------------ ----- 1568 * a: <original instruction> <= 15 1569 * jmp 0(%rip) 6 1570 * <pc + tp->ftt_size> 8 1571 * b: <original instruction> <= 15 1572 * int T_DTRACE_RET 2 1573 * ----- 1574 * <= 46 1575 * 1576 * The %pc is set to a, and curthread->t_dtrace_astpc is set 1577 * to b. If we encounter a signal on the way out of the 1578 * kernel, trap() will set %pc to curthread->t_dtrace_astpc 1579 * so that we execute the original instruction and re-enter 1580 * the kernel rather than redirecting to the next instruction. 1581 * 1582 * If there are return probes (so we know that we're going to 1583 * need to reenter the kernel after executing the original 1584 * instruction), the scratch space will just contain the 1585 * original instruction followed by an interrupt -- the same 1586 * data as at b. 1587 * 1588 * %rip-relative Addressing 1589 * ------------------------ 1590 * 1591 * There's a further complication in 64-bit mode due to %rip- 1592 * relative addressing. While this is clearly a beneficial 1593 * architectural decision for position independent code, it's 1594 * hard not to see it as a personal attack against the pid 1595 * provider since before there was a relatively small set of 1596 * instructions to emulate; with %rip-relative addressing, 1597 * almost every instruction can potentially depend on the 1598 * address at which it's executed. Rather than emulating 1599 * the broad spectrum of instructions that can now be 1600 * position dependent, we emulate jumps and others as in 1601 * 32-bit mode, and take a different tack for instructions 1602 * using %rip-relative addressing. 1603 * 1604 * For every instruction that uses the ModRM byte, the 1605 * in-kernel disassembler reports its location. We use the 1606 * ModRM byte to identify that an instruction uses 1607 * %rip-relative addressing and to see what other registers 1608 * the instruction uses. To emulate those instructions, 1609 * we modify the instruction to be %rax-relative rather than 1610 * %rip-relative (or %rcx-relative if the instruction uses 1611 * %rax; or %r8- or %r9-relative if the REX.B is present so 1612 * we don't have to rewrite the REX prefix). We then load 1613 * the value that %rip would have been into the scratch 1614 * register and generate an instruction to reset the scratch 1615 * register back to its original value. The instruction 1616 * sequence looks like this: 1617 * 1618 * 64-mode %rip-relative bytes 1619 * ------------------------ ----- 1620 * a: <modified instruction> <= 15 1621 * movq $<value>, %<scratch> 6 1622 * jmp 0(%rip) 6 1623 * <pc + tp->ftt_size> 8 1624 * b: <modified instruction> <= 15 1625 * int T_DTRACE_RET 2 1626 * ----- 1627 * 52 1628 * 1629 * We set curthread->t_dtrace_regv so that upon receiving 1630 * a signal we can reset the value of the scratch register. 1631 */ 1632 1633 ASSERT(tp->ftt_size < FASTTRAP_MAX_INSTR_SIZE); 1634 1635 curthread->t_dtrace_scrpc = addr; 1636 bcopy(tp->ftt_instr, &scratch[i], tp->ftt_size); 1637 i += tp->ftt_size; 1638 1639 #ifdef __amd64 1640 if (tp->ftt_ripmode != 0) { 1641 greg_t *reg = NULL; 1642 1643 ASSERT(p->p_model == DATAMODEL_LP64); 1644 ASSERT(tp->ftt_ripmode & 1645 (FASTTRAP_RIP_1 | FASTTRAP_RIP_2)); 1646 1647 /* 1648 * If this was a %rip-relative instruction, we change 1649 * it to be either a %rax- or %rcx-relative 1650 * instruction (depending on whether those registers 1651 * are used as another operand; or %r8- or %r9- 1652 * relative depending on the value of REX.B). We then 1653 * set that register and generate a movq instruction 1654 * to reset the value. 1655 */ 1656 if (tp->ftt_ripmode & FASTTRAP_RIP_X) 1657 scratch[i++] = FASTTRAP_REX(1, 0, 0, 1); 1658 else 1659 scratch[i++] = FASTTRAP_REX(1, 0, 0, 0); 1660 1661 if (tp->ftt_ripmode & FASTTRAP_RIP_1) 1662 scratch[i++] = FASTTRAP_MOV_EAX; 1663 else 1664 scratch[i++] = FASTTRAP_MOV_ECX; 1665 1666 switch (tp->ftt_ripmode) { 1667 case FASTTRAP_RIP_1: 1668 reg = &rp->r_rax; 1669 curthread->t_dtrace_reg = REG_RAX; 1670 break; 1671 case FASTTRAP_RIP_2: 1672 reg = &rp->r_rcx; 1673 curthread->t_dtrace_reg = REG_RCX; 1674 break; 1675 case FASTTRAP_RIP_1 | FASTTRAP_RIP_X: 1676 reg = &rp->r_r8; 1677 curthread->t_dtrace_reg = REG_R8; 1678 break; 1679 case FASTTRAP_RIP_2 | FASTTRAP_RIP_X: 1680 reg = &rp->r_r9; 1681 curthread->t_dtrace_reg = REG_R9; 1682 break; 1683 } 1684 1685 /* LINTED - alignment */ 1686 *(uint64_t *)&scratch[i] = *reg; 1687 curthread->t_dtrace_regv = *reg; 1688 *reg = pc + tp->ftt_size; 1689 i += sizeof (uint64_t); 1690 } 1691 #endif 1692 1693 /* 1694 * Generate the branch instruction to what would have 1695 * normally been the subsequent instruction. In 32-bit mode, 1696 * this is just a relative branch; in 64-bit mode this is a 1697 * %rip-relative branch that loads the 64-bit pc value 1698 * immediately after the jmp instruction. 1699 */ 1700 #ifdef __amd64 1701 if (p->p_model == DATAMODEL_LP64) { 1702 scratch[i++] = FASTTRAP_GROUP5_OP; 1703 scratch[i++] = FASTTRAP_MODRM(0, 4, 5); 1704 /* LINTED - alignment */ 1705 *(uint32_t *)&scratch[i] = 0; 1706 i += sizeof (uint32_t); 1707 /* LINTED - alignment */ 1708 *(uint64_t *)&scratch[i] = pc + tp->ftt_size; 1709 i += sizeof (uint64_t); 1710 } else { 1711 #endif 1712 #ifdef __i386__ 1713 /* 1714 * Set up the jmp to the next instruction; note that 1715 * the size of the traced instruction cancels out. 1716 */ 1717 scratch[i++] = FASTTRAP_JMP32; 1718 /* LINTED - alignment */ 1719 *(uint32_t *)&scratch[i] = pc - addr - 5; 1720 i += sizeof (uint32_t); 1721 #endif 1722 #ifdef __amd64 1723 } 1724 #endif 1725 1726 curthread->t_dtrace_astpc = addr + i; 1727 bcopy(tp->ftt_instr, &scratch[i], tp->ftt_size); 1728 i += tp->ftt_size; 1729 scratch[i++] = FASTTRAP_INT; 1730 scratch[i++] = T_DTRACE_RET; 1731 1732 ASSERT(i <= sizeof (scratch)); 1733 1734 if (fasttrap_copyout(scratch, (char *)addr, i)) { 1735 fasttrap_sigtrap(p, curthread, pc); 1736 new_pc = pc; 1737 break; 1738 } 1739 1740 if (tp->ftt_retids != NULL) { 1741 curthread->t_dtrace_step = 1; 1742 curthread->t_dtrace_ret = 1; 1743 new_pc = curthread->t_dtrace_astpc; 1744 } else { 1745 new_pc = curthread->t_dtrace_scrpc; 1746 } 1747 1748 curthread->t_dtrace_pc = pc; 1749 curthread->t_dtrace_npc = pc + tp->ftt_size; 1750 curthread->t_dtrace_on = 1; 1751 break; 1752 } 1753 1754 default: 1755 panic("fasttrap: mishandled an instruction"); 1756 } 1757 1758 done: 1759 /* 1760 * If there were no return probes when we first found the tracepoint, 1761 * we should feel no obligation to honor any return probes that were 1762 * subsequently enabled -- they'll just have to wait until the next 1763 * time around. 1764 */ 1765 if (tp->ftt_retids != NULL) { 1766 /* 1767 * We need to wait until the results of the instruction are 1768 * apparent before invoking any return probes. If this 1769 * instruction was emulated we can just call 1770 * fasttrap_return_common(); if it needs to be executed, we 1771 * need to wait until the user thread returns to the kernel. 1772 */ 1773 if (tp->ftt_type != FASTTRAP_T_COMMON) { 1774 /* 1775 * Set the program counter to the address of the traced 1776 * instruction so that it looks right in ustack() 1777 * output. We had previously set it to the end of the 1778 * instruction to simplify %rip-relative addressing. 1779 */ 1780 rp->r_rip = pc; 1781 1782 fasttrap_return_common(rp, pc, pid, new_pc); 1783 } else { 1784 ASSERT(curthread->t_dtrace_ret != 0); 1785 ASSERT(curthread->t_dtrace_pc == pc); 1786 ASSERT(curthread->t_dtrace_scrpc != 0); 1787 ASSERT(new_pc == curthread->t_dtrace_astpc); 1788 } 1789 } 1790 1791 rp->r_rip = new_pc; 1792 set_regs(curthread, rp); 1793 1794 return (0); 1795 } 1796 1797 int 1798 fasttrap_return_probe(struct reg *rp) 1799 { 1800 proc_t *p = curproc; 1801 uintptr_t pc = curthread->t_dtrace_pc; 1802 uintptr_t npc = curthread->t_dtrace_npc; 1803 1804 curthread->t_dtrace_pc = 0; 1805 curthread->t_dtrace_npc = 0; 1806 curthread->t_dtrace_scrpc = 0; 1807 curthread->t_dtrace_astpc = 0; 1808 1809 #if defined(sun) 1810 /* 1811 * Treat a child created by a call to vfork(2) as if it were its 1812 * parent. We know that there's only one thread of control in such a 1813 * process: this one. 1814 */ 1815 while (p->p_flag & SVFORK) { 1816 p = p->p_parent; 1817 } 1818 #endif 1819 1820 /* 1821 * We set rp->r_rip to the address of the traced instruction so 1822 * that it appears to dtrace_probe() that we're on the original 1823 * instruction, and so that the user can't easily detect our 1824 * complex web of lies. dtrace_return_probe() (our caller) 1825 * will correctly set %pc after we return. 1826 */ 1827 rp->r_rip = pc; 1828 1829 fasttrap_return_common(rp, pc, p->p_pid, npc); 1830 1831 return (0); 1832 } 1833 1834 /*ARGSUSED*/ 1835 uint64_t 1836 fasttrap_pid_getarg(void *arg, dtrace_id_t id, void *parg, int argno, 1837 int aframes) 1838 { 1839 struct reg r; 1840 1841 fill_regs(curthread, &r); 1842 1843 return (fasttrap_anarg(&r, 1, argno)); 1844 } 1845 1846 /*ARGSUSED*/ 1847 uint64_t 1848 fasttrap_usdt_getarg(void *arg, dtrace_id_t id, void *parg, int argno, 1849 int aframes) 1850 { 1851 struct reg r; 1852 1853 fill_regs(curthread, &r); 1854 1855 return (fasttrap_anarg(&r, 0, argno)); 1856 } 1857 1858 static ulong_t 1859 fasttrap_getreg(struct reg *rp, uint_t reg) 1860 { 1861 #ifdef __amd64 1862 switch (reg) { 1863 case REG_R15: return (rp->r_r15); 1864 case REG_R14: return (rp->r_r14); 1865 case REG_R13: return (rp->r_r13); 1866 case REG_R12: return (rp->r_r12); 1867 case REG_R11: return (rp->r_r11); 1868 case REG_R10: return (rp->r_r10); 1869 case REG_R9: return (rp->r_r9); 1870 case REG_R8: return (rp->r_r8); 1871 case REG_RDI: return (rp->r_rdi); 1872 case REG_RSI: return (rp->r_rsi); 1873 case REG_RBP: return (rp->r_rbp); 1874 case REG_RBX: return (rp->r_rbx); 1875 case REG_RDX: return (rp->r_rdx); 1876 case REG_RCX: return (rp->r_rcx); 1877 case REG_RAX: return (rp->r_rax); 1878 case REG_TRAPNO: return (rp->r_trapno); 1879 case REG_ERR: return (rp->r_err); 1880 case REG_RIP: return (rp->r_rip); 1881 case REG_CS: return (rp->r_cs); 1882 #if defined(sun) 1883 case REG_RFL: return (rp->r_rfl); 1884 #endif 1885 case REG_RSP: return (rp->r_rsp); 1886 case REG_SS: return (rp->r_ss); 1887 case REG_FS: return (rp->r_fs); 1888 case REG_GS: return (rp->r_gs); 1889 case REG_DS: return (rp->r_ds); 1890 case REG_ES: return (rp->r_es); 1891 case REG_FSBASE: return (rdmsr(MSR_FSBASE)); 1892 case REG_GSBASE: return (rdmsr(MSR_GSBASE)); 1893 } 1894 1895 panic("dtrace: illegal register constant"); 1896 /*NOTREACHED*/ 1897 #else 1898 #define _NGREG 19 1899 if (reg >= _NGREG) 1900 panic("dtrace: illegal register constant"); 1901 1902 return (((greg_t *)&rp->r_gs)[reg]); 1903 #endif 1904 } 1905