1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 * 21 * Portions Copyright 2010 The FreeBSD Foundation 22 * 23 * $FreeBSD$ 24 */ 25 26 /* 27 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 28 * Use is subject to license terms. 29 */ 30 31 #if defined(sun) 32 #pragma ident "%Z%%M% %I% %E% SMI" 33 #endif 34 35 #include <sys/fasttrap_isa.h> 36 #include <sys/fasttrap_impl.h> 37 #include <sys/dtrace.h> 38 #include <sys/dtrace_impl.h> 39 #include <sys/cmn_err.h> 40 #if defined(sun) 41 #include <sys/regset.h> 42 #include <sys/privregs.h> 43 #include <sys/segments.h> 44 #include <sys/x86_archext.h> 45 #else 46 #include <cddl/dev/dtrace/dtrace_cddl.h> 47 #include <sys/types.h> 48 #include <sys/proc.h> 49 #include <sys/dtrace_bsd.h> 50 #include <cddl/dev/dtrace/i386/regset.h> 51 #include <machine/segments.h> 52 #include <machine/reg.h> 53 #include <machine/pcb.h> 54 #endif 55 #include <sys/sysmacros.h> 56 #if defined(sun) 57 #include <sys/trap.h> 58 #include <sys/archsystm.h> 59 #else 60 #include <sys/ptrace.h> 61 62 static int 63 proc_ops(int op, proc_t *p, void *kaddr, off_t uaddr, size_t len) 64 { 65 struct iovec iov; 66 struct uio uio; 67 68 iov.iov_base = kaddr; 69 iov.iov_len = len; 70 uio.uio_offset = uaddr; 71 uio.uio_iov = &iov; 72 uio.uio_resid = len; 73 uio.uio_iovcnt = 1; 74 uio.uio_segflg = UIO_SYSSPACE; 75 uio.uio_td = curthread; 76 uio.uio_rw = op; 77 _PHOLD(p); 78 PROC_UNLOCK(p); 79 if (proc_rwmem(p, &uio) < 0) { 80 PROC_LOCK(p); 81 _PRELE(p); 82 return (-1); 83 } 84 PROC_LOCK(p); 85 _PRELE(p); 86 87 return (0); 88 } 89 90 static int 91 uread(proc_t *p, void *kaddr, size_t len, uintptr_t uaddr) 92 { 93 94 return (proc_ops(UIO_READ, p, kaddr, uaddr, len)); 95 } 96 97 static int 98 uwrite(proc_t *p, void *kaddr, size_t len, uintptr_t uaddr) 99 { 100 101 return (proc_ops(UIO_WRITE, p, kaddr, uaddr, len)); 102 } 103 #endif 104 #ifdef __i386__ 105 #define r_rax r_eax 106 #define r_rbx r_ebx 107 #define r_rip r_eip 108 #define r_rflags r_eflags 109 #define r_rsp r_esp 110 #endif 111 112 /* 113 * Lossless User-Land Tracing on x86 114 * --------------------------------- 115 * 116 * The execution of most instructions is not dependent on the address; for 117 * these instructions it is sufficient to copy them into the user process's 118 * address space and execute them. To effectively single-step an instruction 119 * in user-land, we copy out the following sequence of instructions to scratch 120 * space in the user thread's ulwp_t structure. 121 * 122 * We then set the program counter (%eip or %rip) to point to this scratch 123 * space. Once execution resumes, the original instruction is executed and 124 * then control flow is redirected to what was originally the subsequent 125 * instruction. If the kernel attemps to deliver a signal while single- 126 * stepping, the signal is deferred and the program counter is moved into the 127 * second sequence of instructions. The second sequence ends in a trap into 128 * the kernel where the deferred signal is then properly handled and delivered. 129 * 130 * For instructions whose execute is position dependent, we perform simple 131 * emulation. These instructions are limited to control transfer 132 * instructions in 32-bit mode, but in 64-bit mode there's the added wrinkle 133 * of %rip-relative addressing that means that almost any instruction can be 134 * position dependent. For all the details on how we emulate generic 135 * instructions included %rip-relative instructions, see the code in 136 * fasttrap_pid_probe() below where we handle instructions of type 137 * FASTTRAP_T_COMMON (under the header: Generic Instruction Tracing). 138 */ 139 140 #define FASTTRAP_MODRM_MOD(modrm) (((modrm) >> 6) & 0x3) 141 #define FASTTRAP_MODRM_REG(modrm) (((modrm) >> 3) & 0x7) 142 #define FASTTRAP_MODRM_RM(modrm) ((modrm) & 0x7) 143 #define FASTTRAP_MODRM(mod, reg, rm) (((mod) << 6) | ((reg) << 3) | (rm)) 144 145 #define FASTTRAP_SIB_SCALE(sib) (((sib) >> 6) & 0x3) 146 #define FASTTRAP_SIB_INDEX(sib) (((sib) >> 3) & 0x7) 147 #define FASTTRAP_SIB_BASE(sib) ((sib) & 0x7) 148 149 #define FASTTRAP_REX_W(rex) (((rex) >> 3) & 1) 150 #define FASTTRAP_REX_R(rex) (((rex) >> 2) & 1) 151 #define FASTTRAP_REX_X(rex) (((rex) >> 1) & 1) 152 #define FASTTRAP_REX_B(rex) ((rex) & 1) 153 #define FASTTRAP_REX(w, r, x, b) \ 154 (0x40 | ((w) << 3) | ((r) << 2) | ((x) << 1) | (b)) 155 156 /* 157 * Single-byte op-codes. 158 */ 159 #define FASTTRAP_PUSHL_EBP 0x55 160 161 #define FASTTRAP_JO 0x70 162 #define FASTTRAP_JNO 0x71 163 #define FASTTRAP_JB 0x72 164 #define FASTTRAP_JAE 0x73 165 #define FASTTRAP_JE 0x74 166 #define FASTTRAP_JNE 0x75 167 #define FASTTRAP_JBE 0x76 168 #define FASTTRAP_JA 0x77 169 #define FASTTRAP_JS 0x78 170 #define FASTTRAP_JNS 0x79 171 #define FASTTRAP_JP 0x7a 172 #define FASTTRAP_JNP 0x7b 173 #define FASTTRAP_JL 0x7c 174 #define FASTTRAP_JGE 0x7d 175 #define FASTTRAP_JLE 0x7e 176 #define FASTTRAP_JG 0x7f 177 178 #define FASTTRAP_NOP 0x90 179 180 #define FASTTRAP_MOV_EAX 0xb8 181 #define FASTTRAP_MOV_ECX 0xb9 182 183 #define FASTTRAP_RET16 0xc2 184 #define FASTTRAP_RET 0xc3 185 186 #define FASTTRAP_LOOPNZ 0xe0 187 #define FASTTRAP_LOOPZ 0xe1 188 #define FASTTRAP_LOOP 0xe2 189 #define FASTTRAP_JCXZ 0xe3 190 191 #define FASTTRAP_CALL 0xe8 192 #define FASTTRAP_JMP32 0xe9 193 #define FASTTRAP_JMP8 0xeb 194 195 #define FASTTRAP_INT3 0xcc 196 #define FASTTRAP_INT 0xcd 197 198 #define FASTTRAP_2_BYTE_OP 0x0f 199 #define FASTTRAP_GROUP5_OP 0xff 200 201 /* 202 * Two-byte op-codes (second byte only). 203 */ 204 #define FASTTRAP_0F_JO 0x80 205 #define FASTTRAP_0F_JNO 0x81 206 #define FASTTRAP_0F_JB 0x82 207 #define FASTTRAP_0F_JAE 0x83 208 #define FASTTRAP_0F_JE 0x84 209 #define FASTTRAP_0F_JNE 0x85 210 #define FASTTRAP_0F_JBE 0x86 211 #define FASTTRAP_0F_JA 0x87 212 #define FASTTRAP_0F_JS 0x88 213 #define FASTTRAP_0F_JNS 0x89 214 #define FASTTRAP_0F_JP 0x8a 215 #define FASTTRAP_0F_JNP 0x8b 216 #define FASTTRAP_0F_JL 0x8c 217 #define FASTTRAP_0F_JGE 0x8d 218 #define FASTTRAP_0F_JLE 0x8e 219 #define FASTTRAP_0F_JG 0x8f 220 221 #define FASTTRAP_EFLAGS_OF 0x800 222 #define FASTTRAP_EFLAGS_DF 0x400 223 #define FASTTRAP_EFLAGS_SF 0x080 224 #define FASTTRAP_EFLAGS_ZF 0x040 225 #define FASTTRAP_EFLAGS_AF 0x010 226 #define FASTTRAP_EFLAGS_PF 0x004 227 #define FASTTRAP_EFLAGS_CF 0x001 228 229 /* 230 * Instruction prefixes. 231 */ 232 #define FASTTRAP_PREFIX_OPERAND 0x66 233 #define FASTTRAP_PREFIX_ADDRESS 0x67 234 #define FASTTRAP_PREFIX_CS 0x2E 235 #define FASTTRAP_PREFIX_DS 0x3E 236 #define FASTTRAP_PREFIX_ES 0x26 237 #define FASTTRAP_PREFIX_FS 0x64 238 #define FASTTRAP_PREFIX_GS 0x65 239 #define FASTTRAP_PREFIX_SS 0x36 240 #define FASTTRAP_PREFIX_LOCK 0xF0 241 #define FASTTRAP_PREFIX_REP 0xF3 242 #define FASTTRAP_PREFIX_REPNE 0xF2 243 244 #define FASTTRAP_NOREG 0xff 245 246 /* 247 * Map between instruction register encodings and the kernel constants which 248 * correspond to indicies into struct regs. 249 */ 250 #ifdef __amd64 251 static const uint8_t regmap[16] = { 252 REG_RAX, REG_RCX, REG_RDX, REG_RBX, REG_RSP, REG_RBP, REG_RSI, REG_RDI, 253 REG_R8, REG_R9, REG_R10, REG_R11, REG_R12, REG_R13, REG_R14, REG_R15, 254 }; 255 #else 256 static const uint8_t regmap[8] = { 257 EAX, ECX, EDX, EBX, UESP, EBP, ESI, EDI 258 }; 259 #endif 260 261 static ulong_t fasttrap_getreg(struct reg *, uint_t); 262 263 static uint64_t 264 fasttrap_anarg(struct reg *rp, int function_entry, int argno) 265 { 266 uint64_t value = 0; 267 int shift = function_entry ? 1 : 0; 268 269 #ifdef __amd64 270 if (curproc->p_model == DATAMODEL_LP64) { 271 uintptr_t *stack; 272 273 /* 274 * In 64-bit mode, the first six arguments are stored in 275 * registers. 276 */ 277 if (argno < 6) 278 return ((&rp->r_rdi)[argno]); 279 280 stack = (uintptr_t *)rp->r_rsp; 281 DTRACE_CPUFLAG_SET(CPU_DTRACE_NOFAULT); 282 value = dtrace_fulword(&stack[argno - 6 + shift]); 283 DTRACE_CPUFLAG_CLEAR(CPU_DTRACE_NOFAULT | CPU_DTRACE_BADADDR); 284 } else { 285 #endif 286 #ifdef __i386 287 uint32_t *stack = (uint32_t *)rp->r_esp; 288 DTRACE_CPUFLAG_SET(CPU_DTRACE_NOFAULT); 289 value = dtrace_fuword32(&stack[argno + shift]); 290 DTRACE_CPUFLAG_CLEAR(CPU_DTRACE_NOFAULT | CPU_DTRACE_BADADDR); 291 #endif 292 #ifdef __amd64 293 } 294 #endif 295 296 return (value); 297 } 298 299 /*ARGSUSED*/ 300 int 301 fasttrap_tracepoint_init(proc_t *p, fasttrap_tracepoint_t *tp, uintptr_t pc, 302 fasttrap_probe_type_t type) 303 { 304 uint8_t instr[FASTTRAP_MAX_INSTR_SIZE + 10]; 305 size_t len = FASTTRAP_MAX_INSTR_SIZE; 306 size_t first = MIN(len, PAGESIZE - (pc & PAGEOFFSET)); 307 uint_t start = 0; 308 int rmindex, size; 309 uint8_t seg, rex = 0; 310 311 /* 312 * Read the instruction at the given address out of the process's 313 * address space. We don't have to worry about a debugger 314 * changing this instruction before we overwrite it with our trap 315 * instruction since P_PR_LOCK is set. Since instructions can span 316 * pages, we potentially read the instruction in two parts. If the 317 * second part fails, we just zero out that part of the instruction. 318 */ 319 if (uread(p, &instr[0], first, pc) != 0) 320 return (-1); 321 if (len > first && 322 uread(p, &instr[first], len - first, pc + first) != 0) { 323 bzero(&instr[first], len - first); 324 len = first; 325 } 326 327 /* 328 * If the disassembly fails, then we have a malformed instruction. 329 */ 330 if ((size = dtrace_instr_size_isa(instr, p->p_model, &rmindex)) <= 0) 331 return (-1); 332 333 /* 334 * Make sure the disassembler isn't completely broken. 335 */ 336 ASSERT(-1 <= rmindex && rmindex < size); 337 338 /* 339 * If the computed size is greater than the number of bytes read, 340 * then it was a malformed instruction possibly because it fell on a 341 * page boundary and the subsequent page was missing or because of 342 * some malicious user. 343 */ 344 if (size > len) 345 return (-1); 346 347 tp->ftt_size = (uint8_t)size; 348 tp->ftt_segment = FASTTRAP_SEG_NONE; 349 350 /* 351 * Find the start of the instruction's opcode by processing any 352 * legacy prefixes. 353 */ 354 for (;;) { 355 seg = 0; 356 switch (instr[start]) { 357 case FASTTRAP_PREFIX_SS: 358 seg++; 359 /*FALLTHRU*/ 360 case FASTTRAP_PREFIX_GS: 361 seg++; 362 /*FALLTHRU*/ 363 case FASTTRAP_PREFIX_FS: 364 seg++; 365 /*FALLTHRU*/ 366 case FASTTRAP_PREFIX_ES: 367 seg++; 368 /*FALLTHRU*/ 369 case FASTTRAP_PREFIX_DS: 370 seg++; 371 /*FALLTHRU*/ 372 case FASTTRAP_PREFIX_CS: 373 seg++; 374 /*FALLTHRU*/ 375 case FASTTRAP_PREFIX_OPERAND: 376 case FASTTRAP_PREFIX_ADDRESS: 377 case FASTTRAP_PREFIX_LOCK: 378 case FASTTRAP_PREFIX_REP: 379 case FASTTRAP_PREFIX_REPNE: 380 if (seg != 0) { 381 /* 382 * It's illegal for an instruction to specify 383 * two segment prefixes -- give up on this 384 * illegal instruction. 385 */ 386 if (tp->ftt_segment != FASTTRAP_SEG_NONE) 387 return (-1); 388 389 tp->ftt_segment = seg; 390 } 391 start++; 392 continue; 393 } 394 break; 395 } 396 397 #ifdef __amd64 398 /* 399 * Identify the REX prefix on 64-bit processes. 400 */ 401 if (p->p_model == DATAMODEL_LP64 && (instr[start] & 0xf0) == 0x40) 402 rex = instr[start++]; 403 #endif 404 405 /* 406 * Now that we're pretty sure that the instruction is okay, copy the 407 * valid part to the tracepoint. 408 */ 409 bcopy(instr, tp->ftt_instr, FASTTRAP_MAX_INSTR_SIZE); 410 411 tp->ftt_type = FASTTRAP_T_COMMON; 412 if (instr[start] == FASTTRAP_2_BYTE_OP) { 413 switch (instr[start + 1]) { 414 case FASTTRAP_0F_JO: 415 case FASTTRAP_0F_JNO: 416 case FASTTRAP_0F_JB: 417 case FASTTRAP_0F_JAE: 418 case FASTTRAP_0F_JE: 419 case FASTTRAP_0F_JNE: 420 case FASTTRAP_0F_JBE: 421 case FASTTRAP_0F_JA: 422 case FASTTRAP_0F_JS: 423 case FASTTRAP_0F_JNS: 424 case FASTTRAP_0F_JP: 425 case FASTTRAP_0F_JNP: 426 case FASTTRAP_0F_JL: 427 case FASTTRAP_0F_JGE: 428 case FASTTRAP_0F_JLE: 429 case FASTTRAP_0F_JG: 430 tp->ftt_type = FASTTRAP_T_JCC; 431 tp->ftt_code = (instr[start + 1] & 0x0f) | FASTTRAP_JO; 432 tp->ftt_dest = pc + tp->ftt_size + 433 /* LINTED - alignment */ 434 *(int32_t *)&instr[start + 2]; 435 break; 436 } 437 } else if (instr[start] == FASTTRAP_GROUP5_OP) { 438 uint_t mod = FASTTRAP_MODRM_MOD(instr[start + 1]); 439 uint_t reg = FASTTRAP_MODRM_REG(instr[start + 1]); 440 uint_t rm = FASTTRAP_MODRM_RM(instr[start + 1]); 441 442 if (reg == 2 || reg == 4) { 443 uint_t i, sz; 444 445 if (reg == 2) 446 tp->ftt_type = FASTTRAP_T_CALL; 447 else 448 tp->ftt_type = FASTTRAP_T_JMP; 449 450 if (mod == 3) 451 tp->ftt_code = 2; 452 else 453 tp->ftt_code = 1; 454 455 ASSERT(p->p_model == DATAMODEL_LP64 || rex == 0); 456 457 /* 458 * See AMD x86-64 Architecture Programmer's Manual 459 * Volume 3, Section 1.2.7, Table 1-12, and 460 * Appendix A.3.1, Table A-15. 461 */ 462 if (mod != 3 && rm == 4) { 463 uint8_t sib = instr[start + 2]; 464 uint_t index = FASTTRAP_SIB_INDEX(sib); 465 uint_t base = FASTTRAP_SIB_BASE(sib); 466 467 tp->ftt_scale = FASTTRAP_SIB_SCALE(sib); 468 469 tp->ftt_index = (index == 4) ? 470 FASTTRAP_NOREG : 471 regmap[index | (FASTTRAP_REX_X(rex) << 3)]; 472 tp->ftt_base = (mod == 0 && base == 5) ? 473 FASTTRAP_NOREG : 474 regmap[base | (FASTTRAP_REX_B(rex) << 3)]; 475 476 i = 3; 477 sz = mod == 1 ? 1 : 4; 478 } else { 479 /* 480 * In 64-bit mode, mod == 0 and r/m == 5 481 * denotes %rip-relative addressing; in 32-bit 482 * mode, the base register isn't used. In both 483 * modes, there is a 32-bit operand. 484 */ 485 if (mod == 0 && rm == 5) { 486 #ifdef __amd64 487 if (p->p_model == DATAMODEL_LP64) 488 tp->ftt_base = REG_RIP; 489 else 490 #endif 491 tp->ftt_base = FASTTRAP_NOREG; 492 sz = 4; 493 } else { 494 uint8_t base = rm | 495 (FASTTRAP_REX_B(rex) << 3); 496 497 tp->ftt_base = regmap[base]; 498 sz = mod == 1 ? 1 : mod == 2 ? 4 : 0; 499 } 500 tp->ftt_index = FASTTRAP_NOREG; 501 i = 2; 502 } 503 504 if (sz == 1) { 505 tp->ftt_dest = *(int8_t *)&instr[start + i]; 506 } else if (sz == 4) { 507 /* LINTED - alignment */ 508 tp->ftt_dest = *(int32_t *)&instr[start + i]; 509 } else { 510 tp->ftt_dest = 0; 511 } 512 } 513 } else { 514 switch (instr[start]) { 515 case FASTTRAP_RET: 516 tp->ftt_type = FASTTRAP_T_RET; 517 break; 518 519 case FASTTRAP_RET16: 520 tp->ftt_type = FASTTRAP_T_RET16; 521 /* LINTED - alignment */ 522 tp->ftt_dest = *(uint16_t *)&instr[start + 1]; 523 break; 524 525 case FASTTRAP_JO: 526 case FASTTRAP_JNO: 527 case FASTTRAP_JB: 528 case FASTTRAP_JAE: 529 case FASTTRAP_JE: 530 case FASTTRAP_JNE: 531 case FASTTRAP_JBE: 532 case FASTTRAP_JA: 533 case FASTTRAP_JS: 534 case FASTTRAP_JNS: 535 case FASTTRAP_JP: 536 case FASTTRAP_JNP: 537 case FASTTRAP_JL: 538 case FASTTRAP_JGE: 539 case FASTTRAP_JLE: 540 case FASTTRAP_JG: 541 tp->ftt_type = FASTTRAP_T_JCC; 542 tp->ftt_code = instr[start]; 543 tp->ftt_dest = pc + tp->ftt_size + 544 (int8_t)instr[start + 1]; 545 break; 546 547 case FASTTRAP_LOOPNZ: 548 case FASTTRAP_LOOPZ: 549 case FASTTRAP_LOOP: 550 tp->ftt_type = FASTTRAP_T_LOOP; 551 tp->ftt_code = instr[start]; 552 tp->ftt_dest = pc + tp->ftt_size + 553 (int8_t)instr[start + 1]; 554 break; 555 556 case FASTTRAP_JCXZ: 557 tp->ftt_type = FASTTRAP_T_JCXZ; 558 tp->ftt_dest = pc + tp->ftt_size + 559 (int8_t)instr[start + 1]; 560 break; 561 562 case FASTTRAP_CALL: 563 tp->ftt_type = FASTTRAP_T_CALL; 564 tp->ftt_dest = pc + tp->ftt_size + 565 /* LINTED - alignment */ 566 *(int32_t *)&instr[start + 1]; 567 tp->ftt_code = 0; 568 break; 569 570 case FASTTRAP_JMP32: 571 tp->ftt_type = FASTTRAP_T_JMP; 572 tp->ftt_dest = pc + tp->ftt_size + 573 /* LINTED - alignment */ 574 *(int32_t *)&instr[start + 1]; 575 break; 576 case FASTTRAP_JMP8: 577 tp->ftt_type = FASTTRAP_T_JMP; 578 tp->ftt_dest = pc + tp->ftt_size + 579 (int8_t)instr[start + 1]; 580 break; 581 582 case FASTTRAP_PUSHL_EBP: 583 if (start == 0) 584 tp->ftt_type = FASTTRAP_T_PUSHL_EBP; 585 break; 586 587 case FASTTRAP_NOP: 588 #ifdef __amd64 589 ASSERT(p->p_model == DATAMODEL_LP64 || rex == 0); 590 591 /* 592 * On amd64 we have to be careful not to confuse a nop 593 * (actually xchgl %eax, %eax) with an instruction using 594 * the same opcode, but that does something different 595 * (e.g. xchgl %r8d, %eax or xcghq %r8, %rax). 596 */ 597 if (FASTTRAP_REX_B(rex) == 0) 598 #endif 599 tp->ftt_type = FASTTRAP_T_NOP; 600 break; 601 602 case FASTTRAP_INT3: 603 /* 604 * The pid provider shares the int3 trap with debugger 605 * breakpoints so we can't instrument them. 606 */ 607 ASSERT(instr[start] == FASTTRAP_INSTR); 608 return (-1); 609 610 case FASTTRAP_INT: 611 /* 612 * Interrupts seem like they could be traced with 613 * no negative implications, but it's possible that 614 * a thread could be redirected by the trap handling 615 * code which would eventually return to the 616 * instruction after the interrupt. If the interrupt 617 * were in our scratch space, the subsequent 618 * instruction might be overwritten before we return. 619 * Accordingly we refuse to instrument any interrupt. 620 */ 621 return (-1); 622 } 623 } 624 625 #ifdef __amd64 626 if (p->p_model == DATAMODEL_LP64 && tp->ftt_type == FASTTRAP_T_COMMON) { 627 /* 628 * If the process is 64-bit and the instruction type is still 629 * FASTTRAP_T_COMMON -- meaning we're going to copy it out an 630 * execute it -- we need to watch for %rip-relative 631 * addressing mode. See the portion of fasttrap_pid_probe() 632 * below where we handle tracepoints with type 633 * FASTTRAP_T_COMMON for how we emulate instructions that 634 * employ %rip-relative addressing. 635 */ 636 if (rmindex != -1) { 637 uint_t mod = FASTTRAP_MODRM_MOD(instr[rmindex]); 638 uint_t reg = FASTTRAP_MODRM_REG(instr[rmindex]); 639 uint_t rm = FASTTRAP_MODRM_RM(instr[rmindex]); 640 641 ASSERT(rmindex > start); 642 643 if (mod == 0 && rm == 5) { 644 /* 645 * We need to be sure to avoid other 646 * registers used by this instruction. While 647 * the reg field may determine the op code 648 * rather than denoting a register, assuming 649 * that it denotes a register is always safe. 650 * We leave the REX field intact and use 651 * whatever value's there for simplicity. 652 */ 653 if (reg != 0) { 654 tp->ftt_ripmode = FASTTRAP_RIP_1 | 655 (FASTTRAP_RIP_X * 656 FASTTRAP_REX_B(rex)); 657 rm = 0; 658 } else { 659 tp->ftt_ripmode = FASTTRAP_RIP_2 | 660 (FASTTRAP_RIP_X * 661 FASTTRAP_REX_B(rex)); 662 rm = 1; 663 } 664 665 tp->ftt_modrm = tp->ftt_instr[rmindex]; 666 tp->ftt_instr[rmindex] = 667 FASTTRAP_MODRM(2, reg, rm); 668 } 669 } 670 } 671 #endif 672 673 return (0); 674 } 675 676 int 677 fasttrap_tracepoint_install(proc_t *p, fasttrap_tracepoint_t *tp) 678 { 679 fasttrap_instr_t instr = FASTTRAP_INSTR; 680 681 if (uwrite(p, &instr, 1, tp->ftt_pc) != 0) 682 return (-1); 683 684 return (0); 685 } 686 687 int 688 fasttrap_tracepoint_remove(proc_t *p, fasttrap_tracepoint_t *tp) 689 { 690 uint8_t instr; 691 692 /* 693 * Distinguish between read or write failures and a changed 694 * instruction. 695 */ 696 if (uread(p, &instr, 1, tp->ftt_pc) != 0) 697 return (0); 698 if (instr != FASTTRAP_INSTR) 699 return (0); 700 if (uwrite(p, &tp->ftt_instr[0], 1, tp->ftt_pc) != 0) 701 return (-1); 702 703 return (0); 704 } 705 706 #ifdef __amd64 707 static uintptr_t 708 fasttrap_fulword_noerr(const void *uaddr) 709 { 710 uintptr_t ret; 711 712 if ((ret = fasttrap_fulword(uaddr)) != -1) 713 return (ret); 714 715 return (0); 716 } 717 #endif 718 719 #ifdef __i386__ 720 static uint32_t 721 fasttrap_fuword32_noerr(const void *uaddr) 722 { 723 uint32_t ret; 724 725 if ((ret = fasttrap_fuword32(uaddr)) != -1) 726 return (ret); 727 728 return (0); 729 } 730 #endif 731 732 static void 733 fasttrap_return_common(struct reg *rp, uintptr_t pc, pid_t pid, 734 uintptr_t new_pc) 735 { 736 fasttrap_tracepoint_t *tp; 737 fasttrap_bucket_t *bucket; 738 fasttrap_id_t *id; 739 #if defined(sun) 740 kmutex_t *pid_mtx; 741 #endif 742 743 #if defined(sun) 744 pid_mtx = &cpu_core[CPU->cpu_id].cpuc_pid_lock; 745 mutex_enter(pid_mtx); 746 #endif 747 bucket = &fasttrap_tpoints.fth_table[FASTTRAP_TPOINTS_INDEX(pid, pc)]; 748 749 for (tp = bucket->ftb_data; tp != NULL; tp = tp->ftt_next) { 750 if (pid == tp->ftt_pid && pc == tp->ftt_pc && 751 tp->ftt_proc->ftpc_acount != 0) 752 break; 753 } 754 755 /* 756 * Don't sweat it if we can't find the tracepoint again; unlike 757 * when we're in fasttrap_pid_probe(), finding the tracepoint here 758 * is not essential to the correct execution of the process. 759 */ 760 if (tp == NULL) { 761 #if defined(sun) 762 mutex_exit(pid_mtx); 763 #endif 764 return; 765 } 766 767 for (id = tp->ftt_retids; id != NULL; id = id->fti_next) { 768 /* 769 * If there's a branch that could act as a return site, we 770 * need to trace it, and check here if the program counter is 771 * external to the function. 772 */ 773 if (tp->ftt_type != FASTTRAP_T_RET && 774 tp->ftt_type != FASTTRAP_T_RET16 && 775 new_pc - id->fti_probe->ftp_faddr < 776 id->fti_probe->ftp_fsize) 777 continue; 778 779 dtrace_probe(id->fti_probe->ftp_id, 780 pc - id->fti_probe->ftp_faddr, 781 rp->r_rax, rp->r_rbx, 0, 0); 782 } 783 784 #if defined(sun) 785 mutex_exit(pid_mtx); 786 #endif 787 } 788 789 static void 790 fasttrap_sigsegv(proc_t *p, kthread_t *t, uintptr_t addr) 791 { 792 #if defined(sun) 793 sigqueue_t *sqp = kmem_zalloc(sizeof (sigqueue_t), KM_SLEEP); 794 795 sqp->sq_info.si_signo = SIGSEGV; 796 sqp->sq_info.si_code = SEGV_MAPERR; 797 sqp->sq_info.si_addr = (caddr_t)addr; 798 799 mutex_enter(&p->p_lock); 800 sigaddqa(p, t, sqp); 801 mutex_exit(&p->p_lock); 802 803 if (t != NULL) 804 aston(t); 805 #else 806 ksiginfo_t *ksi = kmem_zalloc(sizeof (ksiginfo_t), KM_SLEEP); 807 808 ksiginfo_init(ksi); 809 ksi->ksi_signo = SIGSEGV; 810 ksi->ksi_code = SEGV_MAPERR; 811 ksi->ksi_addr = (caddr_t)addr; 812 (void) tdksignal(t, SIGSEGV, ksi); 813 #endif 814 } 815 816 #ifdef __amd64 817 static void 818 fasttrap_usdt_args64(fasttrap_probe_t *probe, struct reg *rp, int argc, 819 uintptr_t *argv) 820 { 821 int i, x, cap = MIN(argc, probe->ftp_nargs); 822 uintptr_t *stack = (uintptr_t *)rp->r_rsp; 823 824 for (i = 0; i < cap; i++) { 825 x = probe->ftp_argmap[i]; 826 827 if (x < 6) 828 argv[i] = (&rp->r_rdi)[x]; 829 else 830 argv[i] = fasttrap_fulword_noerr(&stack[x]); 831 } 832 833 for (; i < argc; i++) { 834 argv[i] = 0; 835 } 836 } 837 #endif 838 839 #ifdef __i386__ 840 static void 841 fasttrap_usdt_args32(fasttrap_probe_t *probe, struct reg *rp, int argc, 842 uint32_t *argv) 843 { 844 int i, x, cap = MIN(argc, probe->ftp_nargs); 845 uint32_t *stack = (uint32_t *)rp->r_rsp; 846 847 for (i = 0; i < cap; i++) { 848 x = probe->ftp_argmap[i]; 849 850 argv[i] = fasttrap_fuword32_noerr(&stack[x]); 851 } 852 853 for (; i < argc; i++) { 854 argv[i] = 0; 855 } 856 } 857 #endif 858 859 static int 860 fasttrap_do_seg(fasttrap_tracepoint_t *tp, struct reg *rp, uintptr_t *addr) 861 { 862 proc_t *p = curproc; 863 #ifdef __i386__ 864 struct segment_descriptor *desc; 865 #else 866 struct user_segment_descriptor *desc; 867 #endif 868 uint16_t sel = 0, ndx, type; 869 uintptr_t limit; 870 871 switch (tp->ftt_segment) { 872 case FASTTRAP_SEG_CS: 873 sel = rp->r_cs; 874 break; 875 case FASTTRAP_SEG_DS: 876 sel = rp->r_ds; 877 break; 878 case FASTTRAP_SEG_ES: 879 sel = rp->r_es; 880 break; 881 case FASTTRAP_SEG_FS: 882 sel = rp->r_fs; 883 break; 884 case FASTTRAP_SEG_GS: 885 sel = rp->r_gs; 886 break; 887 case FASTTRAP_SEG_SS: 888 sel = rp->r_ss; 889 break; 890 } 891 892 /* 893 * Make sure the given segment register specifies a user priority 894 * selector rather than a kernel selector. 895 */ 896 if (ISPL(sel) != SEL_UPL) 897 return (-1); 898 899 ndx = IDXSEL(sel); 900 901 /* 902 * Check the bounds and grab the descriptor out of the specified 903 * descriptor table. 904 */ 905 if (ISLDT(sel)) { 906 #ifdef __i386__ 907 if (ndx > p->p_md.md_ldt->ldt_len) 908 return (-1); 909 910 desc = (struct segment_descriptor *) 911 p->p_md.md_ldt[ndx].ldt_base; 912 #else 913 if (ndx > max_ldt_segment) 914 return (-1); 915 916 desc = (struct user_segment_descriptor *) 917 p->p_md.md_ldt[ndx].ldt_base; 918 #endif 919 920 } else { 921 if (ndx >= NGDT) 922 return (-1); 923 924 #ifdef __i386__ 925 desc = &gdt[ndx].sd; 926 #else 927 desc = &gdt[ndx]; 928 #endif 929 } 930 931 /* 932 * The descriptor must have user privilege level and it must be 933 * present in memory. 934 */ 935 if (desc->sd_dpl != SEL_UPL || desc->sd_p != 1) 936 return (-1); 937 938 type = desc->sd_type; 939 940 /* 941 * If the S bit in the type field is not set, this descriptor can 942 * only be used in system context. 943 */ 944 if ((type & 0x10) != 0x10) 945 return (-1); 946 947 limit = USD_GETLIMIT(desc) * (desc->sd_gran ? PAGESIZE : 1); 948 949 if (tp->ftt_segment == FASTTRAP_SEG_CS) { 950 /* 951 * The code/data bit and readable bit must both be set. 952 */ 953 if ((type & 0xa) != 0xa) 954 return (-1); 955 956 if (*addr > limit) 957 return (-1); 958 } else { 959 /* 960 * The code/data bit must be clear. 961 */ 962 if ((type & 0x8) != 0) 963 return (-1); 964 965 /* 966 * If the expand-down bit is clear, we just check the limit as 967 * it would naturally be applied. Otherwise, we need to check 968 * that the address is the range [limit + 1 .. 0xffff] or 969 * [limit + 1 ... 0xffffffff] depending on if the default 970 * operand size bit is set. 971 */ 972 if ((type & 0x4) == 0) { 973 if (*addr > limit) 974 return (-1); 975 } else if (desc->sd_def32) { 976 if (*addr < limit + 1 || 0xffff < *addr) 977 return (-1); 978 } else { 979 if (*addr < limit + 1 || 0xffffffff < *addr) 980 return (-1); 981 } 982 } 983 984 *addr += USD_GETBASE(desc); 985 986 return (0); 987 } 988 989 int 990 fasttrap_pid_probe(struct reg *rp) 991 { 992 proc_t *p = curproc; 993 uintptr_t pc = rp->r_rip - 1; 994 uintptr_t new_pc = 0; 995 fasttrap_bucket_t *bucket; 996 #if defined(sun) 997 kmutex_t *pid_mtx; 998 #endif 999 fasttrap_tracepoint_t *tp, tp_local; 1000 pid_t pid; 1001 dtrace_icookie_t cookie; 1002 uint_t is_enabled = 0; 1003 1004 /* 1005 * It's possible that a user (in a veritable orgy of bad planning) 1006 * could redirect this thread's flow of control before it reached the 1007 * return probe fasttrap. In this case we need to kill the process 1008 * since it's in a unrecoverable state. 1009 */ 1010 if (curthread->t_dtrace_step) { 1011 ASSERT(curthread->t_dtrace_on); 1012 fasttrap_sigtrap(p, curthread, pc); 1013 return (0); 1014 } 1015 1016 /* 1017 * Clear all user tracing flags. 1018 */ 1019 curthread->t_dtrace_ft = 0; 1020 curthread->t_dtrace_pc = 0; 1021 curthread->t_dtrace_npc = 0; 1022 curthread->t_dtrace_scrpc = 0; 1023 curthread->t_dtrace_astpc = 0; 1024 #ifdef __amd64 1025 curthread->t_dtrace_regv = 0; 1026 #endif 1027 1028 #if defined(sun) 1029 /* 1030 * Treat a child created by a call to vfork(2) as if it were its 1031 * parent. We know that there's only one thread of control in such a 1032 * process: this one. 1033 */ 1034 while (p->p_flag & SVFORK) { 1035 p = p->p_parent; 1036 } 1037 #endif 1038 1039 PROC_LOCK(p); 1040 pid = p->p_pid; 1041 #if defined(sun) 1042 pid_mtx = &cpu_core[CPU->cpu_id].cpuc_pid_lock; 1043 mutex_enter(pid_mtx); 1044 #endif 1045 bucket = &fasttrap_tpoints.fth_table[FASTTRAP_TPOINTS_INDEX(pid, pc)]; 1046 1047 /* 1048 * Lookup the tracepoint that the process just hit. 1049 */ 1050 for (tp = bucket->ftb_data; tp != NULL; tp = tp->ftt_next) { 1051 if (pid == tp->ftt_pid && pc == tp->ftt_pc && 1052 tp->ftt_proc->ftpc_acount != 0) 1053 break; 1054 } 1055 1056 /* 1057 * If we couldn't find a matching tracepoint, either a tracepoint has 1058 * been inserted without using the pid<pid> ioctl interface (see 1059 * fasttrap_ioctl), or somehow we have mislaid this tracepoint. 1060 */ 1061 if (tp == NULL) { 1062 #if defined(sun) 1063 mutex_exit(pid_mtx); 1064 #endif 1065 PROC_UNLOCK(p); 1066 return (-1); 1067 } 1068 1069 /* 1070 * Set the program counter to the address of the traced instruction 1071 * so that it looks right in ustack() output. 1072 */ 1073 rp->r_rip = pc; 1074 1075 if (tp->ftt_ids != NULL) { 1076 fasttrap_id_t *id; 1077 1078 #ifdef __amd64 1079 if (p->p_model == DATAMODEL_LP64) { 1080 for (id = tp->ftt_ids; id != NULL; id = id->fti_next) { 1081 fasttrap_probe_t *probe = id->fti_probe; 1082 1083 if (id->fti_ptype == DTFTP_ENTRY) { 1084 /* 1085 * We note that this was an entry 1086 * probe to help ustack() find the 1087 * first caller. 1088 */ 1089 cookie = dtrace_interrupt_disable(); 1090 DTRACE_CPUFLAG_SET(CPU_DTRACE_ENTRY); 1091 dtrace_probe(probe->ftp_id, rp->r_rdi, 1092 rp->r_rsi, rp->r_rdx, rp->r_rcx, 1093 rp->r_r8); 1094 DTRACE_CPUFLAG_CLEAR(CPU_DTRACE_ENTRY); 1095 dtrace_interrupt_enable(cookie); 1096 } else if (id->fti_ptype == DTFTP_IS_ENABLED) { 1097 /* 1098 * Note that in this case, we don't 1099 * call dtrace_probe() since it's only 1100 * an artificial probe meant to change 1101 * the flow of control so that it 1102 * encounters the true probe. 1103 */ 1104 is_enabled = 1; 1105 } else if (probe->ftp_argmap == NULL) { 1106 dtrace_probe(probe->ftp_id, rp->r_rdi, 1107 rp->r_rsi, rp->r_rdx, rp->r_rcx, 1108 rp->r_r8); 1109 } else { 1110 uintptr_t t[5]; 1111 1112 fasttrap_usdt_args64(probe, rp, 1113 sizeof (t) / sizeof (t[0]), t); 1114 1115 dtrace_probe(probe->ftp_id, t[0], t[1], 1116 t[2], t[3], t[4]); 1117 } 1118 } 1119 } else { 1120 #else /* __amd64 */ 1121 uintptr_t s0, s1, s2, s3, s4, s5; 1122 uint32_t *stack = (uint32_t *)rp->r_esp; 1123 1124 /* 1125 * In 32-bit mode, all arguments are passed on the 1126 * stack. If this is a function entry probe, we need 1127 * to skip the first entry on the stack as it 1128 * represents the return address rather than a 1129 * parameter to the function. 1130 */ 1131 s0 = fasttrap_fuword32_noerr(&stack[0]); 1132 s1 = fasttrap_fuword32_noerr(&stack[1]); 1133 s2 = fasttrap_fuword32_noerr(&stack[2]); 1134 s3 = fasttrap_fuword32_noerr(&stack[3]); 1135 s4 = fasttrap_fuword32_noerr(&stack[4]); 1136 s5 = fasttrap_fuword32_noerr(&stack[5]); 1137 1138 for (id = tp->ftt_ids; id != NULL; id = id->fti_next) { 1139 fasttrap_probe_t *probe = id->fti_probe; 1140 1141 if (id->fti_ptype == DTFTP_ENTRY) { 1142 /* 1143 * We note that this was an entry 1144 * probe to help ustack() find the 1145 * first caller. 1146 */ 1147 cookie = dtrace_interrupt_disable(); 1148 DTRACE_CPUFLAG_SET(CPU_DTRACE_ENTRY); 1149 dtrace_probe(probe->ftp_id, s1, s2, 1150 s3, s4, s5); 1151 DTRACE_CPUFLAG_CLEAR(CPU_DTRACE_ENTRY); 1152 dtrace_interrupt_enable(cookie); 1153 } else if (id->fti_ptype == DTFTP_IS_ENABLED) { 1154 /* 1155 * Note that in this case, we don't 1156 * call dtrace_probe() since it's only 1157 * an artificial probe meant to change 1158 * the flow of control so that it 1159 * encounters the true probe. 1160 */ 1161 is_enabled = 1; 1162 } else if (probe->ftp_argmap == NULL) { 1163 dtrace_probe(probe->ftp_id, s0, s1, 1164 s2, s3, s4); 1165 } else { 1166 uint32_t t[5]; 1167 1168 fasttrap_usdt_args32(probe, rp, 1169 sizeof (t) / sizeof (t[0]), t); 1170 1171 dtrace_probe(probe->ftp_id, t[0], t[1], 1172 t[2], t[3], t[4]); 1173 } 1174 } 1175 #endif /* __amd64 */ 1176 #ifdef __amd64 1177 } 1178 #endif 1179 } 1180 1181 /* 1182 * We're about to do a bunch of work so we cache a local copy of 1183 * the tracepoint to emulate the instruction, and then find the 1184 * tracepoint again later if we need to light up any return probes. 1185 */ 1186 tp_local = *tp; 1187 PROC_UNLOCK(p); 1188 #if defined(sun) 1189 mutex_exit(pid_mtx); 1190 #endif 1191 tp = &tp_local; 1192 1193 /* 1194 * Set the program counter to appear as though the traced instruction 1195 * had completely executed. This ensures that fasttrap_getreg() will 1196 * report the expected value for REG_RIP. 1197 */ 1198 rp->r_rip = pc + tp->ftt_size; 1199 1200 /* 1201 * If there's an is-enabled probe connected to this tracepoint it 1202 * means that there was a 'xorl %eax, %eax' or 'xorq %rax, %rax' 1203 * instruction that was placed there by DTrace when the binary was 1204 * linked. As this probe is, in fact, enabled, we need to stuff 1 1205 * into %eax or %rax. Accordingly, we can bypass all the instruction 1206 * emulation logic since we know the inevitable result. It's possible 1207 * that a user could construct a scenario where the 'is-enabled' 1208 * probe was on some other instruction, but that would be a rather 1209 * exotic way to shoot oneself in the foot. 1210 */ 1211 if (is_enabled) { 1212 rp->r_rax = 1; 1213 new_pc = rp->r_rip; 1214 goto done; 1215 } 1216 1217 /* 1218 * We emulate certain types of instructions to ensure correctness 1219 * (in the case of position dependent instructions) or optimize 1220 * common cases. The rest we have the thread execute back in user- 1221 * land. 1222 */ 1223 switch (tp->ftt_type) { 1224 case FASTTRAP_T_RET: 1225 case FASTTRAP_T_RET16: 1226 { 1227 uintptr_t dst = 0; 1228 uintptr_t addr = 0; 1229 int ret = 0; 1230 1231 /* 1232 * We have to emulate _every_ facet of the behavior of a ret 1233 * instruction including what happens if the load from %esp 1234 * fails; in that case, we send a SIGSEGV. 1235 */ 1236 #ifdef __amd64 1237 if (p->p_model == DATAMODEL_NATIVE) { 1238 ret = dst = fasttrap_fulword((void *)rp->r_rsp); 1239 addr = rp->r_rsp + sizeof (uintptr_t); 1240 } else { 1241 #endif 1242 #ifdef __i386__ 1243 uint32_t dst32; 1244 ret = dst32 = fasttrap_fuword32((void *)rp->r_esp); 1245 dst = dst32; 1246 addr = rp->r_esp + sizeof (uint32_t); 1247 #endif 1248 #ifdef __amd64 1249 } 1250 #endif 1251 1252 if (ret == -1) { 1253 fasttrap_sigsegv(p, curthread, rp->r_rsp); 1254 new_pc = pc; 1255 break; 1256 } 1257 1258 if (tp->ftt_type == FASTTRAP_T_RET16) 1259 addr += tp->ftt_dest; 1260 1261 rp->r_rsp = addr; 1262 new_pc = dst; 1263 break; 1264 } 1265 1266 case FASTTRAP_T_JCC: 1267 { 1268 uint_t taken = 0; 1269 1270 switch (tp->ftt_code) { 1271 case FASTTRAP_JO: 1272 taken = (rp->r_rflags & FASTTRAP_EFLAGS_OF) != 0; 1273 break; 1274 case FASTTRAP_JNO: 1275 taken = (rp->r_rflags & FASTTRAP_EFLAGS_OF) == 0; 1276 break; 1277 case FASTTRAP_JB: 1278 taken = (rp->r_rflags & FASTTRAP_EFLAGS_CF) != 0; 1279 break; 1280 case FASTTRAP_JAE: 1281 taken = (rp->r_rflags & FASTTRAP_EFLAGS_CF) == 0; 1282 break; 1283 case FASTTRAP_JE: 1284 taken = (rp->r_rflags & FASTTRAP_EFLAGS_ZF) != 0; 1285 break; 1286 case FASTTRAP_JNE: 1287 taken = (rp->r_rflags & FASTTRAP_EFLAGS_ZF) == 0; 1288 break; 1289 case FASTTRAP_JBE: 1290 taken = (rp->r_rflags & FASTTRAP_EFLAGS_CF) != 0 || 1291 (rp->r_rflags & FASTTRAP_EFLAGS_ZF) != 0; 1292 break; 1293 case FASTTRAP_JA: 1294 taken = (rp->r_rflags & FASTTRAP_EFLAGS_CF) == 0 && 1295 (rp->r_rflags & FASTTRAP_EFLAGS_ZF) == 0; 1296 break; 1297 case FASTTRAP_JS: 1298 taken = (rp->r_rflags & FASTTRAP_EFLAGS_SF) != 0; 1299 break; 1300 case FASTTRAP_JNS: 1301 taken = (rp->r_rflags & FASTTRAP_EFLAGS_SF) == 0; 1302 break; 1303 case FASTTRAP_JP: 1304 taken = (rp->r_rflags & FASTTRAP_EFLAGS_PF) != 0; 1305 break; 1306 case FASTTRAP_JNP: 1307 taken = (rp->r_rflags & FASTTRAP_EFLAGS_PF) == 0; 1308 break; 1309 case FASTTRAP_JL: 1310 taken = ((rp->r_rflags & FASTTRAP_EFLAGS_SF) == 0) != 1311 ((rp->r_rflags & FASTTRAP_EFLAGS_OF) == 0); 1312 break; 1313 case FASTTRAP_JGE: 1314 taken = ((rp->r_rflags & FASTTRAP_EFLAGS_SF) == 0) == 1315 ((rp->r_rflags & FASTTRAP_EFLAGS_OF) == 0); 1316 break; 1317 case FASTTRAP_JLE: 1318 taken = (rp->r_rflags & FASTTRAP_EFLAGS_ZF) != 0 || 1319 ((rp->r_rflags & FASTTRAP_EFLAGS_SF) == 0) != 1320 ((rp->r_rflags & FASTTRAP_EFLAGS_OF) == 0); 1321 break; 1322 case FASTTRAP_JG: 1323 taken = (rp->r_rflags & FASTTRAP_EFLAGS_ZF) == 0 && 1324 ((rp->r_rflags & FASTTRAP_EFLAGS_SF) == 0) == 1325 ((rp->r_rflags & FASTTRAP_EFLAGS_OF) == 0); 1326 break; 1327 1328 } 1329 1330 if (taken) 1331 new_pc = tp->ftt_dest; 1332 else 1333 new_pc = pc + tp->ftt_size; 1334 break; 1335 } 1336 1337 case FASTTRAP_T_LOOP: 1338 { 1339 uint_t taken = 0; 1340 #ifdef __amd64 1341 greg_t cx = rp->r_rcx--; 1342 #else 1343 greg_t cx = rp->r_ecx--; 1344 #endif 1345 1346 switch (tp->ftt_code) { 1347 case FASTTRAP_LOOPNZ: 1348 taken = (rp->r_rflags & FASTTRAP_EFLAGS_ZF) == 0 && 1349 cx != 0; 1350 break; 1351 case FASTTRAP_LOOPZ: 1352 taken = (rp->r_rflags & FASTTRAP_EFLAGS_ZF) != 0 && 1353 cx != 0; 1354 break; 1355 case FASTTRAP_LOOP: 1356 taken = (cx != 0); 1357 break; 1358 } 1359 1360 if (taken) 1361 new_pc = tp->ftt_dest; 1362 else 1363 new_pc = pc + tp->ftt_size; 1364 break; 1365 } 1366 1367 case FASTTRAP_T_JCXZ: 1368 { 1369 #ifdef __amd64 1370 greg_t cx = rp->r_rcx; 1371 #else 1372 greg_t cx = rp->r_ecx; 1373 #endif 1374 1375 if (cx == 0) 1376 new_pc = tp->ftt_dest; 1377 else 1378 new_pc = pc + tp->ftt_size; 1379 break; 1380 } 1381 1382 case FASTTRAP_T_PUSHL_EBP: 1383 { 1384 int ret = 0; 1385 uintptr_t addr = 0; 1386 #ifdef __amd64 1387 if (p->p_model == DATAMODEL_NATIVE) { 1388 addr = rp->r_rsp - sizeof (uintptr_t); 1389 ret = fasttrap_sulword((void *)addr, &rp->r_rsp); 1390 } else { 1391 #endif 1392 #ifdef __i386__ 1393 addr = rp->r_rsp - sizeof (uint32_t); 1394 ret = fasttrap_suword32((void *)addr, &rp->r_rsp); 1395 #endif 1396 #ifdef __amd64 1397 } 1398 #endif 1399 1400 if (ret == -1) { 1401 fasttrap_sigsegv(p, curthread, addr); 1402 new_pc = pc; 1403 break; 1404 } 1405 1406 rp->r_rsp = addr; 1407 new_pc = pc + tp->ftt_size; 1408 break; 1409 } 1410 1411 case FASTTRAP_T_NOP: 1412 new_pc = pc + tp->ftt_size; 1413 break; 1414 1415 case FASTTRAP_T_JMP: 1416 case FASTTRAP_T_CALL: 1417 if (tp->ftt_code == 0) { 1418 new_pc = tp->ftt_dest; 1419 } else { 1420 #ifdef __amd64 1421 uintptr_t value; 1422 #endif 1423 uintptr_t addr = tp->ftt_dest; 1424 1425 if (tp->ftt_base != FASTTRAP_NOREG) 1426 addr += fasttrap_getreg(rp, tp->ftt_base); 1427 if (tp->ftt_index != FASTTRAP_NOREG) 1428 addr += fasttrap_getreg(rp, tp->ftt_index) << 1429 tp->ftt_scale; 1430 1431 if (tp->ftt_code == 1) { 1432 /* 1433 * If there's a segment prefix for this 1434 * instruction, we'll need to check permissions 1435 * and bounds on the given selector, and adjust 1436 * the address accordingly. 1437 */ 1438 if (tp->ftt_segment != FASTTRAP_SEG_NONE && 1439 fasttrap_do_seg(tp, rp, &addr) != 0) { 1440 fasttrap_sigsegv(p, curthread, addr); 1441 new_pc = pc; 1442 break; 1443 } 1444 1445 #ifdef __amd64 1446 if (p->p_model == DATAMODEL_NATIVE) { 1447 if ((value = fasttrap_fulword((void *)addr)) 1448 == -1) { 1449 fasttrap_sigsegv(p, curthread, 1450 addr); 1451 new_pc = pc; 1452 break; 1453 } 1454 new_pc = value; 1455 } else { 1456 #endif 1457 #ifdef __i386__ 1458 uint32_t value32; 1459 addr = (uintptr_t)(uint32_t)addr; 1460 if ((value32 = fasttrap_fuword32((void *)addr)) 1461 == -1) { 1462 fasttrap_sigsegv(p, curthread, 1463 addr); 1464 new_pc = pc; 1465 break; 1466 } 1467 new_pc = value32; 1468 #endif 1469 } 1470 #ifdef __amd64 1471 } else { 1472 new_pc = addr; 1473 } 1474 #endif 1475 } 1476 1477 /* 1478 * If this is a call instruction, we need to push the return 1479 * address onto the stack. If this fails, we send the process 1480 * a SIGSEGV and reset the pc to emulate what would happen if 1481 * this instruction weren't traced. 1482 */ 1483 if (tp->ftt_type == FASTTRAP_T_CALL) { 1484 int ret = 0; 1485 uintptr_t addr = 0, pcps; 1486 #ifdef __amd64 1487 if (p->p_model == DATAMODEL_NATIVE) { 1488 addr = rp->r_rsp - sizeof (uintptr_t); 1489 pcps = pc + tp->ftt_size; 1490 ret = fasttrap_sulword((void *)addr, &pcps); 1491 } else { 1492 #endif 1493 #ifdef __i386__ 1494 addr = rp->r_rsp - sizeof (uint32_t); 1495 pcps = (uint32_t)(pc + tp->ftt_size); 1496 ret = fasttrap_suword32((void *)addr, &pcps); 1497 #endif 1498 #ifdef __amd64 1499 } 1500 #endif 1501 1502 if (ret == -1) { 1503 fasttrap_sigsegv(p, curthread, addr); 1504 new_pc = pc; 1505 break; 1506 } 1507 1508 rp->r_rsp = addr; 1509 } 1510 1511 break; 1512 1513 case FASTTRAP_T_COMMON: 1514 { 1515 uintptr_t addr; 1516 #if defined(__amd64) 1517 uint8_t scratch[2 * FASTTRAP_MAX_INSTR_SIZE + 22]; 1518 #else 1519 uint8_t scratch[2 * FASTTRAP_MAX_INSTR_SIZE + 7]; 1520 #endif 1521 uint_t i = 0; 1522 #if defined(sun) 1523 klwp_t *lwp = ttolwp(curthread); 1524 #endif 1525 1526 /* 1527 * Compute the address of the ulwp_t and step over the 1528 * ul_self pointer. The method used to store the user-land 1529 * thread pointer is very different on 32- and 64-bit 1530 * kernels. 1531 */ 1532 #if defined(sun) 1533 #if defined(__amd64) 1534 if (p->p_model == DATAMODEL_LP64) { 1535 addr = lwp->lwp_pcb.pcb_fsbase; 1536 addr += sizeof (void *); 1537 } else { 1538 addr = lwp->lwp_pcb.pcb_gsbase; 1539 addr += sizeof (caddr32_t); 1540 } 1541 #else 1542 addr = USD_GETBASE(&lwp->lwp_pcb.pcb_gsdesc); 1543 addr += sizeof (void *); 1544 #endif 1545 #endif /* sun */ 1546 #ifdef __i386__ 1547 addr = USD_GETBASE(&curthread->td_pcb->pcb_gsd); 1548 #else 1549 addr = curthread->td_pcb->pcb_gsbase; 1550 #endif 1551 addr += sizeof (void *); 1552 1553 /* 1554 * Generic Instruction Tracing 1555 * --------------------------- 1556 * 1557 * This is the layout of the scratch space in the user-land 1558 * thread structure for our generated instructions. 1559 * 1560 * 32-bit mode bytes 1561 * ------------------------ ----- 1562 * a: <original instruction> <= 15 1563 * jmp <pc + tp->ftt_size> 5 1564 * b: <original instrction> <= 15 1565 * int T_DTRACE_RET 2 1566 * ----- 1567 * <= 37 1568 * 1569 * 64-bit mode bytes 1570 * ------------------------ ----- 1571 * a: <original instruction> <= 15 1572 * jmp 0(%rip) 6 1573 * <pc + tp->ftt_size> 8 1574 * b: <original instruction> <= 15 1575 * int T_DTRACE_RET 2 1576 * ----- 1577 * <= 46 1578 * 1579 * The %pc is set to a, and curthread->t_dtrace_astpc is set 1580 * to b. If we encounter a signal on the way out of the 1581 * kernel, trap() will set %pc to curthread->t_dtrace_astpc 1582 * so that we execute the original instruction and re-enter 1583 * the kernel rather than redirecting to the next instruction. 1584 * 1585 * If there are return probes (so we know that we're going to 1586 * need to reenter the kernel after executing the original 1587 * instruction), the scratch space will just contain the 1588 * original instruction followed by an interrupt -- the same 1589 * data as at b. 1590 * 1591 * %rip-relative Addressing 1592 * ------------------------ 1593 * 1594 * There's a further complication in 64-bit mode due to %rip- 1595 * relative addressing. While this is clearly a beneficial 1596 * architectural decision for position independent code, it's 1597 * hard not to see it as a personal attack against the pid 1598 * provider since before there was a relatively small set of 1599 * instructions to emulate; with %rip-relative addressing, 1600 * almost every instruction can potentially depend on the 1601 * address at which it's executed. Rather than emulating 1602 * the broad spectrum of instructions that can now be 1603 * position dependent, we emulate jumps and others as in 1604 * 32-bit mode, and take a different tack for instructions 1605 * using %rip-relative addressing. 1606 * 1607 * For every instruction that uses the ModRM byte, the 1608 * in-kernel disassembler reports its location. We use the 1609 * ModRM byte to identify that an instruction uses 1610 * %rip-relative addressing and to see what other registers 1611 * the instruction uses. To emulate those instructions, 1612 * we modify the instruction to be %rax-relative rather than 1613 * %rip-relative (or %rcx-relative if the instruction uses 1614 * %rax; or %r8- or %r9-relative if the REX.B is present so 1615 * we don't have to rewrite the REX prefix). We then load 1616 * the value that %rip would have been into the scratch 1617 * register and generate an instruction to reset the scratch 1618 * register back to its original value. The instruction 1619 * sequence looks like this: 1620 * 1621 * 64-mode %rip-relative bytes 1622 * ------------------------ ----- 1623 * a: <modified instruction> <= 15 1624 * movq $<value>, %<scratch> 6 1625 * jmp 0(%rip) 6 1626 * <pc + tp->ftt_size> 8 1627 * b: <modified instruction> <= 15 1628 * int T_DTRACE_RET 2 1629 * ----- 1630 * 52 1631 * 1632 * We set curthread->t_dtrace_regv so that upon receiving 1633 * a signal we can reset the value of the scratch register. 1634 */ 1635 1636 ASSERT(tp->ftt_size < FASTTRAP_MAX_INSTR_SIZE); 1637 1638 curthread->t_dtrace_scrpc = addr; 1639 bcopy(tp->ftt_instr, &scratch[i], tp->ftt_size); 1640 i += tp->ftt_size; 1641 1642 #ifdef __amd64 1643 if (tp->ftt_ripmode != 0) { 1644 greg_t *reg = NULL; 1645 1646 ASSERT(p->p_model == DATAMODEL_LP64); 1647 ASSERT(tp->ftt_ripmode & 1648 (FASTTRAP_RIP_1 | FASTTRAP_RIP_2)); 1649 1650 /* 1651 * If this was a %rip-relative instruction, we change 1652 * it to be either a %rax- or %rcx-relative 1653 * instruction (depending on whether those registers 1654 * are used as another operand; or %r8- or %r9- 1655 * relative depending on the value of REX.B). We then 1656 * set that register and generate a movq instruction 1657 * to reset the value. 1658 */ 1659 if (tp->ftt_ripmode & FASTTRAP_RIP_X) 1660 scratch[i++] = FASTTRAP_REX(1, 0, 0, 1); 1661 else 1662 scratch[i++] = FASTTRAP_REX(1, 0, 0, 0); 1663 1664 if (tp->ftt_ripmode & FASTTRAP_RIP_1) 1665 scratch[i++] = FASTTRAP_MOV_EAX; 1666 else 1667 scratch[i++] = FASTTRAP_MOV_ECX; 1668 1669 switch (tp->ftt_ripmode) { 1670 case FASTTRAP_RIP_1: 1671 reg = &rp->r_rax; 1672 curthread->t_dtrace_reg = REG_RAX; 1673 break; 1674 case FASTTRAP_RIP_2: 1675 reg = &rp->r_rcx; 1676 curthread->t_dtrace_reg = REG_RCX; 1677 break; 1678 case FASTTRAP_RIP_1 | FASTTRAP_RIP_X: 1679 reg = &rp->r_r8; 1680 curthread->t_dtrace_reg = REG_R8; 1681 break; 1682 case FASTTRAP_RIP_2 | FASTTRAP_RIP_X: 1683 reg = &rp->r_r9; 1684 curthread->t_dtrace_reg = REG_R9; 1685 break; 1686 } 1687 1688 /* LINTED - alignment */ 1689 *(uint64_t *)&scratch[i] = *reg; 1690 curthread->t_dtrace_regv = *reg; 1691 *reg = pc + tp->ftt_size; 1692 i += sizeof (uint64_t); 1693 } 1694 #endif 1695 1696 /* 1697 * Generate the branch instruction to what would have 1698 * normally been the subsequent instruction. In 32-bit mode, 1699 * this is just a relative branch; in 64-bit mode this is a 1700 * %rip-relative branch that loads the 64-bit pc value 1701 * immediately after the jmp instruction. 1702 */ 1703 #ifdef __amd64 1704 if (p->p_model == DATAMODEL_LP64) { 1705 scratch[i++] = FASTTRAP_GROUP5_OP; 1706 scratch[i++] = FASTTRAP_MODRM(0, 4, 5); 1707 /* LINTED - alignment */ 1708 *(uint32_t *)&scratch[i] = 0; 1709 i += sizeof (uint32_t); 1710 /* LINTED - alignment */ 1711 *(uint64_t *)&scratch[i] = pc + tp->ftt_size; 1712 i += sizeof (uint64_t); 1713 } else { 1714 #endif 1715 #ifdef __i386__ 1716 /* 1717 * Set up the jmp to the next instruction; note that 1718 * the size of the traced instruction cancels out. 1719 */ 1720 scratch[i++] = FASTTRAP_JMP32; 1721 /* LINTED - alignment */ 1722 *(uint32_t *)&scratch[i] = pc - addr - 5; 1723 i += sizeof (uint32_t); 1724 #endif 1725 #ifdef __amd64 1726 } 1727 #endif 1728 1729 curthread->t_dtrace_astpc = addr + i; 1730 bcopy(tp->ftt_instr, &scratch[i], tp->ftt_size); 1731 i += tp->ftt_size; 1732 scratch[i++] = FASTTRAP_INT; 1733 scratch[i++] = T_DTRACE_RET; 1734 1735 ASSERT(i <= sizeof (scratch)); 1736 1737 if (fasttrap_copyout(scratch, (char *)addr, i)) { 1738 fasttrap_sigtrap(p, curthread, pc); 1739 new_pc = pc; 1740 break; 1741 } 1742 1743 if (tp->ftt_retids != NULL) { 1744 curthread->t_dtrace_step = 1; 1745 curthread->t_dtrace_ret = 1; 1746 new_pc = curthread->t_dtrace_astpc; 1747 } else { 1748 new_pc = curthread->t_dtrace_scrpc; 1749 } 1750 1751 curthread->t_dtrace_pc = pc; 1752 curthread->t_dtrace_npc = pc + tp->ftt_size; 1753 curthread->t_dtrace_on = 1; 1754 break; 1755 } 1756 1757 default: 1758 panic("fasttrap: mishandled an instruction"); 1759 } 1760 1761 done: 1762 /* 1763 * If there were no return probes when we first found the tracepoint, 1764 * we should feel no obligation to honor any return probes that were 1765 * subsequently enabled -- they'll just have to wait until the next 1766 * time around. 1767 */ 1768 if (tp->ftt_retids != NULL) { 1769 /* 1770 * We need to wait until the results of the instruction are 1771 * apparent before invoking any return probes. If this 1772 * instruction was emulated we can just call 1773 * fasttrap_return_common(); if it needs to be executed, we 1774 * need to wait until the user thread returns to the kernel. 1775 */ 1776 if (tp->ftt_type != FASTTRAP_T_COMMON) { 1777 /* 1778 * Set the program counter to the address of the traced 1779 * instruction so that it looks right in ustack() 1780 * output. We had previously set it to the end of the 1781 * instruction to simplify %rip-relative addressing. 1782 */ 1783 rp->r_rip = pc; 1784 1785 fasttrap_return_common(rp, pc, pid, new_pc); 1786 } else { 1787 ASSERT(curthread->t_dtrace_ret != 0); 1788 ASSERT(curthread->t_dtrace_pc == pc); 1789 ASSERT(curthread->t_dtrace_scrpc != 0); 1790 ASSERT(new_pc == curthread->t_dtrace_astpc); 1791 } 1792 } 1793 1794 rp->r_rip = new_pc; 1795 set_regs(curthread, rp); 1796 1797 return (0); 1798 } 1799 1800 int 1801 fasttrap_return_probe(struct reg *rp) 1802 { 1803 proc_t *p = curproc; 1804 uintptr_t pc = curthread->t_dtrace_pc; 1805 uintptr_t npc = curthread->t_dtrace_npc; 1806 1807 curthread->t_dtrace_pc = 0; 1808 curthread->t_dtrace_npc = 0; 1809 curthread->t_dtrace_scrpc = 0; 1810 curthread->t_dtrace_astpc = 0; 1811 1812 #if defined(sun) 1813 /* 1814 * Treat a child created by a call to vfork(2) as if it were its 1815 * parent. We know that there's only one thread of control in such a 1816 * process: this one. 1817 */ 1818 while (p->p_flag & SVFORK) { 1819 p = p->p_parent; 1820 } 1821 #endif 1822 1823 /* 1824 * We set rp->r_rip to the address of the traced instruction so 1825 * that it appears to dtrace_probe() that we're on the original 1826 * instruction, and so that the user can't easily detect our 1827 * complex web of lies. dtrace_return_probe() (our caller) 1828 * will correctly set %pc after we return. 1829 */ 1830 rp->r_rip = pc; 1831 1832 fasttrap_return_common(rp, pc, p->p_pid, npc); 1833 1834 return (0); 1835 } 1836 1837 /*ARGSUSED*/ 1838 uint64_t 1839 fasttrap_pid_getarg(void *arg, dtrace_id_t id, void *parg, int argno, 1840 int aframes) 1841 { 1842 struct reg r; 1843 1844 fill_regs(curthread, &r); 1845 1846 return (fasttrap_anarg(&r, 1, argno)); 1847 } 1848 1849 /*ARGSUSED*/ 1850 uint64_t 1851 fasttrap_usdt_getarg(void *arg, dtrace_id_t id, void *parg, int argno, 1852 int aframes) 1853 { 1854 struct reg r; 1855 1856 fill_regs(curthread, &r); 1857 1858 return (fasttrap_anarg(&r, 0, argno)); 1859 } 1860 1861 static ulong_t 1862 fasttrap_getreg(struct reg *rp, uint_t reg) 1863 { 1864 #ifdef __amd64 1865 switch (reg) { 1866 case REG_R15: return (rp->r_r15); 1867 case REG_R14: return (rp->r_r14); 1868 case REG_R13: return (rp->r_r13); 1869 case REG_R12: return (rp->r_r12); 1870 case REG_R11: return (rp->r_r11); 1871 case REG_R10: return (rp->r_r10); 1872 case REG_R9: return (rp->r_r9); 1873 case REG_R8: return (rp->r_r8); 1874 case REG_RDI: return (rp->r_rdi); 1875 case REG_RSI: return (rp->r_rsi); 1876 case REG_RBP: return (rp->r_rbp); 1877 case REG_RBX: return (rp->r_rbx); 1878 case REG_RDX: return (rp->r_rdx); 1879 case REG_RCX: return (rp->r_rcx); 1880 case REG_RAX: return (rp->r_rax); 1881 case REG_TRAPNO: return (rp->r_trapno); 1882 case REG_ERR: return (rp->r_err); 1883 case REG_RIP: return (rp->r_rip); 1884 case REG_CS: return (rp->r_cs); 1885 #if defined(sun) 1886 case REG_RFL: return (rp->r_rfl); 1887 #endif 1888 case REG_RSP: return (rp->r_rsp); 1889 case REG_SS: return (rp->r_ss); 1890 case REG_FS: return (rp->r_fs); 1891 case REG_GS: return (rp->r_gs); 1892 case REG_DS: return (rp->r_ds); 1893 case REG_ES: return (rp->r_es); 1894 case REG_FSBASE: return (rdmsr(MSR_FSBASE)); 1895 case REG_GSBASE: return (rdmsr(MSR_GSBASE)); 1896 } 1897 1898 panic("dtrace: illegal register constant"); 1899 /*NOTREACHED*/ 1900 #else 1901 #define _NGREG 19 1902 if (reg >= _NGREG) 1903 panic("dtrace: illegal register constant"); 1904 1905 return (((greg_t *)&rp->r_gs)[reg]); 1906 #endif 1907 } 1908