xref: /freebsd/sys/cam/scsi/scsi_da.h (revision a8445737e740901f5f2c8d24c12ef7fc8b00134e)
1 /*
2  * Structures and definitions for SCSI commands to Direct Access Devices
3  */
4 
5 /*
6  * Some lines of this file come from a file of the name "scsi.h"
7  * distributed by OSF as part of mach2.5,
8  *  so the following disclaimer has been kept.
9  *
10  * Copyright 1990 by Open Software Foundation,
11  * Grenoble, FRANCE
12  *
13  * 		All Rights Reserved
14  *
15  *   Permission to use, copy, modify, and distribute this software and
16  * its documentation for any purpose and without fee is hereby granted,
17  * provided that the above copyright notice appears in all copies and
18  * that both the copyright notice and this permission notice appear in
19  * supporting documentation, and that the name of OSF or Open Software
20  * Foundation not be used in advertising or publicity pertaining to
21  * distribution of the software without specific, written prior
22  * permission.
23  *
24  *   OSF DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE
25  * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS,
26  * IN NO EVENT SHALL OSF BE LIABLE FOR ANY SPECIAL, INDIRECT, OR
27  * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
28  * LOSS OF USE, DATA OR PROFITS, WHETHER IN ACTION OF CONTRACT,
29  * NEGLIGENCE, OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION
30  * WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
31  */
32 
33 /*
34  * Largely written by Julian Elischer (julian@tfs.com)
35  * for TRW Financial Systems.
36  *
37  * TRW Financial Systems, in accordance with their agreement with Carnegie
38  * Mellon University, makes this software available to CMU to distribute
39  * or use in any manner that they see fit as long as this message is kept with
40  * the software. For this reason TFS also grants any other persons or
41  * organisations permission to use or modify this software.
42  *
43  * TFS supplies this software to be publicly redistributed
44  * on the understanding that TFS is not responsible for the correct
45  * functioning of this software in any circumstances.
46  *
47  * Ported to run under 386BSD by Julian Elischer (julian@tfs.com) Sept 1992
48  *
49  *	$Id$
50  */
51 
52 #ifndef	_SCSI_SCSI_DA_H
53 #define _SCSI_SCSI_DA_H 1
54 
55 #include <sys/cdefs.h>
56 
57 struct scsi_rezero_unit
58 {
59 	u_int8_t opcode;
60 #define SRZU_LUN_MASK 0xE0
61 	u_int8_t byte2;
62 	u_int8_t reserved[3];
63 	u_int8_t control;
64 };
65 
66 struct scsi_reassign_blocks
67 {
68 	u_int8_t opcode;
69 	u_int8_t byte2;
70 	u_int8_t unused[3];
71 	u_int8_t control;
72 };
73 
74 struct scsi_rw_6
75 {
76 	u_int8_t opcode;
77 	u_int8_t addr[3];
78 /* only 5 bits are valid in the MSB address byte */
79 #define	SRW_TOPADDR	0x1F
80 	u_int8_t length;
81 	u_int8_t control;
82 };
83 
84 struct scsi_rw_10
85 {
86 	u_int8_t opcode;
87 #define	SRW10_RELADDR	0x01
88 #define SRW10_FUA	0x08
89 #define	SRW10_DPO	0x10
90 	u_int8_t byte2;
91 	u_int8_t addr[4];
92 	u_int8_t reserved;
93 	u_int8_t length[2];
94 	u_int8_t control;
95 };
96 
97 struct scsi_rw_12
98 {
99 	u_int8_t opcode;
100 #define	SRW12_RELADDR	0x01
101 #define SRW12_FUA	0x08
102 #define	SRW12_DPO	0x10
103 	u_int8_t byte2;
104 	u_int8_t addr[4];
105 	u_int8_t reserved;
106 	u_int8_t length[4];
107 	u_int8_t control;
108 };
109 
110 struct scsi_start_stop_unit
111 {
112 	u_int8_t opcode;
113 	u_int8_t byte2;
114 #define	SSS_IMMED		0x01
115 	u_int8_t reserved[2];
116 	u_int8_t how;
117 #define	SSS_START		0x01
118 #define	SSS_LOEJ		0x02
119 	u_int8_t control;
120 };
121 
122 struct scsi_read_defect_data_10
123 {
124 	u_int8_t opcode;
125 
126 	/*
127 	 * The most significant 3 bits are the LUN, the other 5 are
128 	 * reserved.
129 	 */
130 #define SRDD10_LUN_MASK 0xE0
131 	u_int8_t byte2;
132 #define SRDD10_GLIST 0x08
133 #define SRDD10_PLIST 0x10
134 #define SRDD10_DLIST_FORMAT_MASK 0x07
135 #define SRDD10_BLOCK_FORMAT            0x00
136 #define SRDD10_BYTES_FROM_INDEX_FORMAT 0x04
137 #define SRDD10_PHYSICAL_SECTOR_FORMAT  0x05
138 	u_int8_t format;
139 
140 	u_int8_t reserved[4];
141 
142 	u_int8_t alloc_length[2];
143 
144 	u_int8_t control;
145 };
146 
147 struct scsi_read_defect_data_12
148 {
149 	u_int8_t opcode;
150 
151 	/*
152 	 * The most significant 3 bits are the LUN, the other 5 are
153 	 * reserved.
154 	 */
155 #define SRDD12_LUN_MASK 0xE0
156 	u_int8_t byte2;
157 
158 #define SRDD12_GLIST 0x08
159 #define SRDD12_PLIST 0x10
160 #define SRDD12_DLIST_FORMAT_MASK 0x07
161 #define SRDD12_BLOCK_FORMAT            0x00
162 #define SRDD12_BYTES_FROM_INDEX_FORMAT 0x04
163 #define SRDD12_PHYSICAL_SECTOR_FORMAT  0x05
164 	u_int8_t format;
165 
166 	u_int8_t reserved[4];
167 
168 	u_int8_t alloc_length[4];
169 
170 	u_int8_t control;
171 
172 };
173 
174 
175 /*
176  * Opcodes
177  */
178 #define REZERO_UNIT		0x01
179 #define	REASSIGN_BLOCKS		0x07
180 #define	READ_6			0x08
181 #define WRITE_6			0x0a
182 #define MODE_SELECT		0x15
183 #define MODE_SENSE		0x1a
184 #define START_STOP_UNIT		0x1b
185 #define	READ_10			0x28
186 #define WRITE_10		0x2a
187 #define READ_DEFECT_DATA_10	0x37
188 #define READ_12			0xa8
189 #define WRITE_12		0xaa
190 #define READ_DEFECT_DATA_12	0xb7
191 
192 
193 struct scsi_reassign_blocks_data
194 {
195 	u_int8_t reserved[2];
196 	u_int8_t length[2];
197 	struct {
198 		u_int8_t dlbaddr[4];	/* defect logical block address */
199 	} defect_descriptor[1];
200 };
201 
202 
203 /*
204  * This is the list header for the READ DEFECT DATA(10) command above.
205  * It may be a bit wrong to append the 10 at the end of the data structure,
206  * since it's only 4 bytes but it does tie it to the 10 byte command.
207  */
208 struct scsi_read_defect_data_hdr_10
209 {
210 	u_int8_t reserved;
211 #define SRDDH10_GLIST 0x08
212 #define SRDDH10_PLIST 0x10
213 #define SRDDH10_DLIST_FORMAT_MASK 0x07
214 #define SRDDH10_BLOCK_FORMAT            0x00
215 #define SRDDH10_BYTES_FROM_INDEX_FORMAT 0x04
216 #define SRDDH10_PHYSICAL_SECTOR_FORMAT  0x05
217 	u_int8_t format;
218 	u_int8_t length[2];
219 };
220 
221 struct scsi_defect_desc_block
222 {
223 	u_int8_t address[4];
224 };
225 
226 struct scsi_defect_desc_bytes_from_index
227 {
228 	u_int8_t cylinder[3];
229 	u_int8_t head;
230 	u_int8_t bytes_from_index[4];
231 };
232 
233 struct scsi_defect_desc_phys_sector
234 {
235 	u_int8_t cylinder[3];
236 	u_int8_t head;
237 	u_int8_t sector[4];
238 };
239 
240 struct scsi_read_defect_data_hdr_12
241 {
242 	u_int8_t reserved;
243 #define SRDDH12_GLIST 0x08
244 #define SRDDH12_PLIST 0x10
245 #define SRDDH12_DLIST_FORMAT_MASK 0x07
246 #define SRDDH12_BLOCK_FORMAT            0x00
247 #define SRDDH12_BYTES_FROM_INDEX_FORMAT 0x04
248 #define SRDDH12_PHYSICAL_SECTOR_FORMAT  0x05
249 	u_int8_t format;
250 	u_int8_t length[4];
251 };
252 
253 union	disk_pages /* this is the structure copied from osf */
254 {
255 	struct format_device_page {
256 		u_int8_t pg_code;	/* page code (should be 3)	      */
257 #define	SMS_FORMAT_DEVICE_PAGE	0x03	/* only 6 bits valid */
258 		u_int8_t pg_length;	/* page length (should be 0x16)	      */
259 #define	SMS_FORMAT_DEVICE_PLEN	0x16
260 		u_int8_t trk_z_1;	/* tracks per zone (MSB)	      */
261 		u_int8_t trk_z_0;	/* tracks per zone (LSB)	      */
262 		u_int8_t alt_sec_1;	/* alternate sectors per zone (MSB)   */
263 		u_int8_t alt_sec_0;	/* alternate sectors per zone (LSB)   */
264 		u_int8_t alt_trk_z_1;	/* alternate tracks per zone (MSB)    */
265 		u_int8_t alt_trk_z_0;	/* alternate tracks per zone (LSB)    */
266 		u_int8_t alt_trk_v_1;	/* alternate tracks per volume (MSB)  */
267 		u_int8_t alt_trk_v_0;	/* alternate tracks per volume (LSB)  */
268 		u_int8_t ph_sec_t_1;	/* physical sectors per track (MSB)   */
269 		u_int8_t ph_sec_t_0;	/* physical sectors per track (LSB)   */
270 		u_int8_t bytes_s_1;	/* bytes per sector (MSB)	      */
271 		u_int8_t bytes_s_0;	/* bytes per sector (LSB)	      */
272 		u_int8_t interleave_1;	/* interleave (MSB)		      */
273 		u_int8_t interleave_0;	/* interleave (LSB)		      */
274 		u_int8_t trk_skew_1;	/* track skew factor (MSB)	      */
275 		u_int8_t trk_skew_0;	/* track skew factor (LSB)	      */
276 		u_int8_t cyl_skew_1;	/* cylinder skew (MSB)		      */
277 		u_int8_t cyl_skew_0;	/* cylinder skew (LSB)		      */
278 		u_int8_t flags;		/* various */
279 #define			DISK_FMT_SURF	0x10
280 #define	       		DISK_FMT_RMB	0x20
281 #define			DISK_FMT_HSEC	0x40
282 #define			DISK_FMT_SSEC	0x80
283 		u_int8_t reserved21;
284 		u_int8_t reserved22;
285 		u_int8_t reserved23;
286 	} format_device;
287 	struct rigid_geometry_page {
288 		u_int8_t pg_code;	/* page code (should be 4)	      */
289 #define SMS_RIGID_GEOMETRY_PAGE 0x04
290 		u_int8_t pg_length;	/* page length (should be 0x16)	      */
291 #define SMS_RIGID_GEOMETRY_PLEN 0x16
292 		u_int8_t ncyl_2;	/* number of cylinders (MSB)	      */
293 		u_int8_t ncyl_1;	/* number of cylinders 		      */
294 		u_int8_t ncyl_0;	/* number of cylinders (LSB)	      */
295 		u_int8_t nheads;	/* number of heads 		      */
296 		u_int8_t st_cyl_wp_2;	/* starting cyl., write precomp (MSB) */
297 		u_int8_t st_cyl_wp_1;	/* starting cyl., write precomp	      */
298 		u_int8_t st_cyl_wp_0;	/* starting cyl., write precomp (LSB) */
299 		u_int8_t st_cyl_rwc_2;	/* starting cyl., red. write cur (MSB)*/
300 		u_int8_t st_cyl_rwc_1;	/* starting cyl., red. write cur      */
301 		u_int8_t st_cyl_rwc_0;	/* starting cyl., red. write cur (LSB)*/
302 		u_int8_t driv_step_1;	/* drive step rate (MSB)	      */
303 		u_int8_t driv_step_0;	/* drive step rate (LSB)	      */
304 		u_int8_t land_zone_2;	/* landing zone cylinder (MSB)	      */
305 		u_int8_t land_zone_1;	/* landing zone cylinder 	      */
306 		u_int8_t land_zone_0;	/* landing zone cylinder (LSB)	      */
307 		u_int8_t rpl;		/* rotational position locking (2 bits) */
308 		u_int8_t rot_offset;	/* rotational offset */
309 		u_int8_t reserved19;
310 		u_int8_t medium_rot_rate_1; /* medium rotation rate (RPM) (MSB) */
311 		u_int8_t medium_rot_rate_0; /* medium rotation rate (RPM) (LSB) */
312 		u_int8_t reserved22;
313 		u_int8_t reserved23;
314     	} rigid_geometry;
315 	struct flexible_disk_page {
316 		u_int8_t pg_code;	/* page code (should be 5)	      */
317 #define SMS_FLEXIBLE_GEOMETRY_PAGE 0x05
318 		u_int8_t pg_length;	/* page length (should be 0x1E)	      */
319 #define SMS_FLEXIBLE_GEOMETRY_PLEN 0x0x1E
320 		u_int8_t xfr_rate_1;	/* transfer rate (MSB)		      */
321 		u_int8_t xfr_rate_0;	/* transfer rate (LSB)		      */
322 		u_int8_t nheads;	/* number of heads 		      */
323 		u_int8_t sec_per_track;	/* Sectors per track		      */
324 		u_int8_t bytes_s_1;	/* bytes per sector (MSB)	      */
325 		u_int8_t bytes_s_0;	/* bytes per sector (LSB)	      */
326 		u_int8_t ncyl_1;	/* number of cylinders (MSB)	      */
327 		u_int8_t ncyl_0;	/* number of cylinders (LSB)	      */
328 		u_int8_t st_cyl_wp_1;	/* starting cyl., write precomp (MSB) */
329 		u_int8_t st_cyl_wp_0;	/* starting cyl., write precomp (LSB) */
330 		u_int8_t st_cyl_rwc_1;	/* starting cyl., red. write cur (MSB)*/
331 		u_int8_t st_cyl_rwc_0;	/* starting cyl., red. write cur (LSB)*/
332 		u_int8_t driv_step_1;	/* drive step rate (MSB)	      */
333 		u_int8_t driv_step_0;	/* drive step rate (LSB)	      */
334 		u_int8_t driv_step_pw;	/* drive step pulse width	      */
335 		u_int8_t head_stl_del_1;/* Head settle delay (MSB)	      */
336 		u_int8_t head_stl_del_0;/* Head settle delay (LSB)	      */
337 		u_int8_t motor_on_del;	/* Motor on delay		      */
338 		u_int8_t motor_off_del;	/* Motor off delay		      */
339 		u_int8_t trdy_ssn_mo;	/* XXX ??? */
340 		u_int8_t spc;		/* XXX ??? */
341 		u_int8_t write_comp;	/* Write compensation */
342 		u_int8_t head_load_del; /* Head load delay */
343 		u_int8_t head_uload_del;/* Head un-load delay */
344 		u_int8_t pin32_pin2;
345 		u_int8_t pin4_pint1;
346 		u_int8_t medium_rot_rate_1; /* medium rotation rate (RPM) (MSB) */
347 		u_int8_t medium_rot_rate_0; /* medium rotation rate (RPM) (LSB) */
348 		u_int8_t reserved30;
349 		u_int8_t reserved31;
350     	} flexible_disk;
351 };
352 
353 struct scsi_da_rw_recovery_page {
354 	u_int8_t page_code;
355 #define SMS_RW_ERROR_RECOVERY_PAGE	0x01
356 	u_int8_t page_length;
357 	u_int8_t byte3;
358 #define SMS_RWER_AWRE			0x80
359 #define SMS_RWER_ARRE			0x40
360 #define SMS_RWER_TB			0x20
361 #define SMS_RWER_RC			0x10
362 #define SMS_RWER_EER			0x08
363 #define SMS_RWER_PER			0x04
364 #define SMS_RWER_DTE			0x02
365 #define SMS_RWER_DCR			0x01
366 	u_int8_t read_retry_count;
367 	u_int8_t correction_span;
368 	u_int8_t head_offset_count;
369 	u_int8_t data_strobe_offset_cnt;
370 	u_int8_t reserved;
371 	u_int8_t write_retry_count;
372 	u_int8_t reserved2;
373 	u_int8_t recovery_time_limit[2];
374 };
375 
376 __BEGIN_DECLS
377 void scsi_read_write(struct ccb_scsiio *csio, u_int32_t retries,
378 		     void (*cbfcnp)(struct cam_periph *, union ccb *),
379 		     u_int8_t tag_action, int readop, u_int8_t byte2,
380 		     int minimum_cmd_size, u_int32_t lba,
381 		     u_int32_t block_count, u_int8_t *data_ptr,
382 		     u_int32_t dxfer_len, u_int8_t sense_len,
383 		     u_int32_t timeout);
384 
385 void scsi_start_stop(struct ccb_scsiio *csio, u_int32_t retries,
386 		     void (*cbfcnp)(struct cam_periph *, union ccb *),
387 		     u_int8_t tag_action, int start, int load_eject,
388 		     int immediate, u_int8_t sense_len, u_int32_t timeout);
389 __END_DECLS
390 
391 #endif /* _SCSI_SCSI_DA_H */
392