1 /*- 2 * Data structures and definitions for CAM Control Blocks (CCBs). 3 * 4 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 5 * 6 * Copyright (c) 1997, 1998 Justin T. Gibbs. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions, and the following disclaimer, 14 * without modification, immediately at the beginning of the file. 15 * 2. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 22 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * $FreeBSD$ 31 */ 32 33 #ifndef _CAM_CAM_CCB_H 34 #define _CAM_CAM_CCB_H 1 35 36 #include <sys/queue.h> 37 #include <sys/cdefs.h> 38 #include <sys/time.h> 39 #include <sys/limits.h> 40 #ifndef _KERNEL 41 #include <sys/callout.h> 42 #endif 43 #include <cam/cam_debug.h> 44 #include <cam/scsi/scsi_all.h> 45 #include <cam/ata/ata_all.h> 46 #include <cam/nvme/nvme_all.h> 47 #include <cam/mmc/mmc_all.h> 48 49 /* General allocation length definitions for CCB structures */ 50 #define IOCDBLEN CAM_MAX_CDBLEN /* Space for CDB bytes/pointer */ 51 #define VUHBALEN 14 /* Vendor Unique HBA length */ 52 #define SIM_IDLEN 16 /* ASCII string len for SIM ID */ 53 #define HBA_IDLEN 16 /* ASCII string len for HBA ID */ 54 #define DEV_IDLEN 16 /* ASCII string len for device names */ 55 #define CCB_PERIPH_PRIV_SIZE 2 /* size of peripheral private area */ 56 #define CCB_SIM_PRIV_SIZE 2 /* size of sim private area */ 57 58 /* Struct definitions for CAM control blocks */ 59 60 /* Common CCB header */ 61 62 /* CCB memory allocation flags */ 63 typedef enum { 64 CAM_CCB_FROM_UMA = 0x00000001,/* CCB from a periph UMA zone */ 65 } ccb_alloc_flags; 66 67 /* CAM CCB flags */ 68 typedef enum { 69 CAM_CDB_POINTER = 0x00000001,/* The CDB field is a pointer */ 70 CAM_unused1 = 0x00000002, 71 CAM_unused2 = 0x00000004, 72 CAM_NEGOTIATE = 0x00000008,/* 73 * Perform transport negotiation 74 * with this command. 75 */ 76 CAM_DATA_ISPHYS = 0x00000010,/* Data type with physical addrs */ 77 CAM_DIS_AUTOSENSE = 0x00000020,/* Disable autosense feature */ 78 CAM_DIR_BOTH = 0x00000000,/* Data direction (00:IN/OUT) */ 79 CAM_DIR_IN = 0x00000040,/* Data direction (01:DATA IN) */ 80 CAM_DIR_OUT = 0x00000080,/* Data direction (10:DATA OUT) */ 81 CAM_DIR_NONE = 0x000000C0,/* Data direction (11:no data) */ 82 CAM_DIR_MASK = 0x000000C0,/* Data direction Mask */ 83 CAM_DATA_VADDR = 0x00000000,/* Data type (000:Virtual) */ 84 CAM_DATA_PADDR = 0x00000010,/* Data type (001:Physical) */ 85 CAM_DATA_SG = 0x00040000,/* Data type (010:sglist) */ 86 CAM_DATA_SG_PADDR = 0x00040010,/* Data type (011:sglist phys) */ 87 CAM_DATA_BIO = 0x00200000,/* Data type (100:bio) */ 88 CAM_DATA_MASK = 0x00240010,/* Data type mask */ 89 CAM_unused3 = 0x00000100, 90 CAM_unused4 = 0x00000200, 91 CAM_DEV_QFRZDIS = 0x00000400,/* Disable DEV Q freezing */ 92 CAM_DEV_QFREEZE = 0x00000800,/* Freeze DEV Q on execution */ 93 CAM_HIGH_POWER = 0x00001000,/* Command takes a lot of power */ 94 CAM_SENSE_PTR = 0x00002000,/* Sense data is a pointer */ 95 CAM_SENSE_PHYS = 0x00004000,/* Sense pointer is physical addr*/ 96 CAM_TAG_ACTION_VALID = 0x00008000,/* Use the tag action in this ccb*/ 97 CAM_PASS_ERR_RECOVER = 0x00010000,/* Pass driver does err. recovery*/ 98 CAM_DIS_DISCONNECT = 0x00020000,/* Disable disconnect */ 99 CAM_unused5 = 0x00080000, 100 CAM_unused6 = 0x00100000, 101 CAM_CDB_PHYS = 0x00400000,/* CDB poiner is physical */ 102 CAM_unused7 = 0x00800000, 103 104 /* Phase cognizant mode flags */ 105 CAM_unused8 = 0x01000000, 106 CAM_unused9 = 0x02000000, 107 CAM_unused10 = 0x04000000, 108 CAM_unused11 = 0x08000000, 109 CAM_unused12 = 0x10000000, 110 CAM_unused13 = 0x20000000, 111 CAM_unused14 = 0x40000000, 112 113 /* Host target Mode flags */ 114 CAM_SEND_SENSE = 0x08000000,/* Send sense data with status */ 115 CAM_unused15 = 0x10000000, 116 CAM_unused16 = 0x20000000, 117 CAM_SEND_STATUS = 0x40000000,/* Send status after data phase */ 118 119 CAM_UNLOCKED = 0x80000000 /* Call callback without lock. */ 120 } ccb_flags; 121 122 typedef enum { 123 CAM_USER_DATA_ADDR = 0x00000002,/* Userspace data pointers */ 124 CAM_SG_FORMAT_IOVEC = 0x00000004,/* iovec instead of busdma S/G*/ 125 CAM_UNMAPPED_BUF = 0x00000008 /* use unmapped I/O */ 126 } ccb_xflags; 127 128 /* XPT Opcodes for xpt_action */ 129 typedef enum { 130 /* Function code flags are bits greater than 0xff */ 131 XPT_FC_QUEUED = 0x100, 132 /* Non-immediate function code */ 133 XPT_FC_USER_CCB = 0x200, 134 XPT_FC_XPT_ONLY = 0x400, 135 /* Only for the transport layer device */ 136 XPT_FC_DEV_QUEUED = 0x800 | XPT_FC_QUEUED, 137 /* Passes through the device queues */ 138 /* Common function commands: 0x00->0x0F */ 139 XPT_NOOP = 0x00, 140 /* Execute Nothing */ 141 XPT_SCSI_IO = 0x01 | XPT_FC_DEV_QUEUED, 142 /* Execute the requested I/O operation */ 143 XPT_GDEV_TYPE = 0x02, 144 /* Get type information for specified device */ 145 XPT_GDEVLIST = 0x03, 146 /* Get a list of peripheral devices */ 147 XPT_PATH_INQ = 0x04, 148 /* Path routing inquiry */ 149 XPT_REL_SIMQ = 0x05, 150 /* Release a frozen device queue */ 151 XPT_SASYNC_CB = 0x06, 152 /* Set Asynchronous Callback Parameters */ 153 XPT_SDEV_TYPE = 0x07, 154 /* Set device type information */ 155 XPT_SCAN_BUS = 0x08 | XPT_FC_QUEUED | XPT_FC_USER_CCB 156 | XPT_FC_XPT_ONLY, 157 /* (Re)Scan the SCSI Bus */ 158 XPT_DEV_MATCH = 0x09 | XPT_FC_XPT_ONLY, 159 /* Get EDT entries matching the given pattern */ 160 XPT_DEBUG = 0x0a, 161 /* Turn on debugging for a bus, target or lun */ 162 XPT_PATH_STATS = 0x0b, 163 /* Path statistics (error counts, etc.) */ 164 XPT_GDEV_STATS = 0x0c, 165 /* Device statistics (error counts, etc.) */ 166 XPT_DEV_ADVINFO = 0x0e, 167 /* Get/Set Device advanced information */ 168 XPT_ASYNC = 0x0f | XPT_FC_QUEUED | XPT_FC_USER_CCB 169 | XPT_FC_XPT_ONLY, 170 /* Asynchronous event */ 171 /* SCSI Control Functions: 0x10->0x1F */ 172 XPT_ABORT = 0x10, 173 /* Abort the specified CCB */ 174 XPT_RESET_BUS = 0x11 | XPT_FC_XPT_ONLY, 175 /* Reset the specified SCSI bus */ 176 XPT_RESET_DEV = 0x12 | XPT_FC_DEV_QUEUED, 177 /* Bus Device Reset the specified SCSI device */ 178 XPT_TERM_IO = 0x13, 179 /* Terminate the I/O process */ 180 XPT_SCAN_LUN = 0x14 | XPT_FC_QUEUED | XPT_FC_USER_CCB 181 | XPT_FC_XPT_ONLY, 182 /* Scan Logical Unit */ 183 XPT_GET_TRAN_SETTINGS = 0x15, 184 /* 185 * Get default/user transfer settings 186 * for the target 187 */ 188 XPT_SET_TRAN_SETTINGS = 0x16, 189 /* 190 * Set transfer rate/width 191 * negotiation settings 192 */ 193 XPT_CALC_GEOMETRY = 0x17, 194 /* 195 * Calculate the geometry parameters for 196 * a device give the sector size and 197 * volume size. 198 */ 199 XPT_ATA_IO = 0x18 | XPT_FC_DEV_QUEUED, 200 /* Execute the requested ATA I/O operation */ 201 202 XPT_GET_SIM_KNOB_OLD = 0x18, /* Compat only */ 203 204 XPT_SET_SIM_KNOB = 0x19, 205 /* 206 * Set SIM specific knob values. 207 */ 208 209 XPT_GET_SIM_KNOB = 0x1a, 210 /* 211 * Get SIM specific knob values. 212 */ 213 214 XPT_SMP_IO = 0x1b | XPT_FC_DEV_QUEUED, 215 /* Serial Management Protocol */ 216 217 XPT_NVME_IO = 0x1c | XPT_FC_DEV_QUEUED, 218 /* Execute the requested NVMe I/O operation */ 219 220 XPT_MMC_IO = 0x1d | XPT_FC_DEV_QUEUED, 221 /* Placeholder for MMC / SD / SDIO I/O stuff */ 222 223 XPT_SCAN_TGT = 0x1e | XPT_FC_QUEUED | XPT_FC_USER_CCB 224 | XPT_FC_XPT_ONLY, 225 /* Scan Target */ 226 227 XPT_NVME_ADMIN = 0x1f | XPT_FC_DEV_QUEUED, 228 /* Execute the requested NVMe Admin operation */ 229 230 /* HBA engine commands 0x20->0x2F */ 231 XPT_ENG_INQ = 0x20 | XPT_FC_XPT_ONLY, 232 /* HBA engine feature inquiry */ 233 XPT_ENG_EXEC = 0x21 | XPT_FC_DEV_QUEUED, 234 /* HBA execute engine request */ 235 236 /* Target mode commands: 0x30->0x3F */ 237 XPT_EN_LUN = 0x30, 238 /* Enable LUN as a target */ 239 XPT_TARGET_IO = 0x31 | XPT_FC_DEV_QUEUED, 240 /* Execute target I/O request */ 241 XPT_ACCEPT_TARGET_IO = 0x32 | XPT_FC_QUEUED | XPT_FC_USER_CCB, 242 /* Accept Host Target Mode CDB */ 243 XPT_CONT_TARGET_IO = 0x33 | XPT_FC_DEV_QUEUED, 244 /* Continue Host Target I/O Connection */ 245 XPT_IMMED_NOTIFY = 0x34 | XPT_FC_QUEUED | XPT_FC_USER_CCB, 246 /* Notify Host Target driver of event (obsolete) */ 247 XPT_NOTIFY_ACK = 0x35, 248 /* Acknowledgement of event (obsolete) */ 249 XPT_IMMEDIATE_NOTIFY = 0x36 | XPT_FC_QUEUED | XPT_FC_USER_CCB, 250 /* Notify Host Target driver of event */ 251 XPT_NOTIFY_ACKNOWLEDGE = 0x37 | XPT_FC_QUEUED | XPT_FC_USER_CCB, 252 /* Acknowledgement of event */ 253 XPT_REPROBE_LUN = 0x38 | XPT_FC_QUEUED | XPT_FC_USER_CCB, 254 /* Query device capacity and notify GEOM */ 255 256 XPT_MMC_SET_TRAN_SETTINGS = 0x40 | XPT_FC_DEV_QUEUED, 257 XPT_MMC_GET_TRAN_SETTINGS = 0x41 | XPT_FC_DEV_QUEUED, 258 259 /* Vendor Unique codes: 0x80->0x8F */ 260 XPT_VUNIQUE = 0x80 261 } xpt_opcode; 262 263 #define XPT_FC_GROUP_MASK 0xF0 264 #define XPT_FC_GROUP(op) ((op) & XPT_FC_GROUP_MASK) 265 #define XPT_FC_GROUP_COMMON 0x00 266 #define XPT_FC_GROUP_SCSI_CONTROL 0x10 267 #define XPT_FC_GROUP_HBA_ENGINE 0x20 268 #define XPT_FC_GROUP_TMODE 0x30 269 #define XPT_FC_GROUP_VENDOR_UNIQUE 0x80 270 271 #define XPT_FC_IS_DEV_QUEUED(ccb) \ 272 (((ccb)->ccb_h.func_code & XPT_FC_DEV_QUEUED) == XPT_FC_DEV_QUEUED) 273 #define XPT_FC_IS_QUEUED(ccb) \ 274 (((ccb)->ccb_h.func_code & XPT_FC_QUEUED) != 0) 275 276 typedef enum { 277 PROTO_UNKNOWN, 278 PROTO_UNSPECIFIED, 279 PROTO_SCSI, /* Small Computer System Interface */ 280 PROTO_ATA, /* AT Attachment */ 281 PROTO_ATAPI, /* AT Attachment Packetized Interface */ 282 PROTO_SATAPM, /* SATA Port Multiplier */ 283 PROTO_SEMB, /* SATA Enclosure Management Bridge */ 284 PROTO_NVME, /* NVME */ 285 PROTO_MMCSD, /* MMC, SD, SDIO */ 286 } cam_proto; 287 288 typedef enum { 289 XPORT_UNKNOWN, 290 XPORT_UNSPECIFIED, 291 XPORT_SPI, /* SCSI Parallel Interface */ 292 XPORT_FC, /* Fiber Channel */ 293 XPORT_SSA, /* Serial Storage Architecture */ 294 XPORT_USB, /* Universal Serial Bus */ 295 XPORT_PPB, /* Parallel Port Bus */ 296 XPORT_ATA, /* AT Attachment */ 297 XPORT_SAS, /* Serial Attached SCSI */ 298 XPORT_SATA, /* Serial AT Attachment */ 299 XPORT_ISCSI, /* iSCSI */ 300 XPORT_SRP, /* SCSI RDMA Protocol */ 301 XPORT_NVME, /* NVMe over PCIe */ 302 XPORT_MMCSD, /* MMC, SD, SDIO card */ 303 } cam_xport; 304 305 #define XPORT_IS_NVME(t) ((t) == XPORT_NVME) 306 #define XPORT_IS_ATA(t) ((t) == XPORT_ATA || (t) == XPORT_SATA) 307 #define XPORT_IS_SCSI(t) ((t) != XPORT_UNKNOWN && \ 308 (t) != XPORT_UNSPECIFIED && \ 309 !XPORT_IS_ATA(t) && !XPORT_IS_NVME(t)) 310 #define XPORT_DEVSTAT_TYPE(t) (XPORT_IS_ATA(t) ? DEVSTAT_TYPE_IF_IDE : \ 311 XPORT_IS_SCSI(t) ? DEVSTAT_TYPE_IF_SCSI : \ 312 DEVSTAT_TYPE_IF_OTHER) 313 314 #define PROTO_VERSION_UNKNOWN (UINT_MAX - 1) 315 #define PROTO_VERSION_UNSPECIFIED UINT_MAX 316 #define XPORT_VERSION_UNKNOWN (UINT_MAX - 1) 317 #define XPORT_VERSION_UNSPECIFIED UINT_MAX 318 319 typedef union { 320 LIST_ENTRY(ccb_hdr) le; 321 SLIST_ENTRY(ccb_hdr) sle; 322 TAILQ_ENTRY(ccb_hdr) tqe; 323 STAILQ_ENTRY(ccb_hdr) stqe; 324 } camq_entry; 325 326 typedef union { 327 void *ptr; 328 u_long field; 329 u_int8_t bytes[sizeof(uintptr_t)]; 330 } ccb_priv_entry; 331 332 typedef union { 333 ccb_priv_entry entries[CCB_PERIPH_PRIV_SIZE]; 334 u_int8_t bytes[CCB_PERIPH_PRIV_SIZE * sizeof(ccb_priv_entry)]; 335 } ccb_ppriv_area; 336 337 typedef union { 338 ccb_priv_entry entries[CCB_SIM_PRIV_SIZE]; 339 u_int8_t bytes[CCB_SIM_PRIV_SIZE * sizeof(ccb_priv_entry)]; 340 } ccb_spriv_area; 341 342 typedef struct { 343 struct timeval *etime; 344 uintptr_t sim_data; 345 uintptr_t periph_data; 346 } ccb_qos_area; 347 348 struct ccb_hdr { 349 cam_pinfo pinfo; /* Info for priority scheduling */ 350 camq_entry xpt_links; /* For chaining in the XPT layer */ 351 camq_entry sim_links; /* For chaining in the SIM layer */ 352 camq_entry periph_links; /* For chaining in the type driver */ 353 #if BYTE_ORDER == LITTLE_ENDIAN 354 u_int16_t retry_count; 355 u_int16_t alloc_flags; /* ccb_alloc_flags */ 356 #else 357 u_int16_t alloc_flags; /* ccb_alloc_flags */ 358 u_int16_t retry_count; 359 #endif 360 void (*cbfcnp)(struct cam_periph *, union ccb *); 361 /* Callback on completion function */ 362 xpt_opcode func_code; /* XPT function code */ 363 u_int32_t status; /* Status returned by CAM subsystem */ 364 struct cam_path *path; /* Compiled path for this ccb */ 365 path_id_t path_id; /* Path ID for the request */ 366 target_id_t target_id; /* Target device ID */ 367 lun_id_t target_lun; /* Target LUN number */ 368 u_int32_t flags; /* ccb_flags */ 369 u_int32_t xflags; /* Extended flags */ 370 ccb_ppriv_area periph_priv; 371 ccb_spriv_area sim_priv; 372 ccb_qos_area qos; 373 u_int32_t timeout; /* Hard timeout value in mseconds */ 374 struct timeval softtimeout; /* Soft timeout value in sec + usec */ 375 }; 376 377 /* Get Device Information CCB */ 378 struct ccb_getdev { 379 struct ccb_hdr ccb_h; 380 cam_proto protocol; 381 struct scsi_inquiry_data inq_data; 382 struct ata_params ident_data; 383 u_int8_t serial_num[252]; 384 u_int8_t inq_flags; 385 u_int8_t serial_num_len; 386 void *padding[2]; 387 }; 388 389 /* Device Statistics CCB */ 390 struct ccb_getdevstats { 391 struct ccb_hdr ccb_h; 392 int dev_openings; /* Space left for more work on device*/ 393 int dev_active; /* Transactions running on the device */ 394 int allocated; /* CCBs allocated for the device */ 395 int queued; /* CCBs queued to be sent to the device */ 396 int held; /* 397 * CCBs held by peripheral drivers 398 * for this device 399 */ 400 int maxtags; /* 401 * Boundary conditions for number of 402 * tagged operations 403 */ 404 int mintags; 405 struct timeval last_reset; /* Time of last bus reset/loop init */ 406 }; 407 408 typedef enum { 409 CAM_GDEVLIST_LAST_DEVICE, 410 CAM_GDEVLIST_LIST_CHANGED, 411 CAM_GDEVLIST_MORE_DEVS, 412 CAM_GDEVLIST_ERROR 413 } ccb_getdevlist_status_e; 414 415 struct ccb_getdevlist { 416 struct ccb_hdr ccb_h; 417 char periph_name[DEV_IDLEN]; 418 u_int32_t unit_number; 419 unsigned int generation; 420 u_int32_t index; 421 ccb_getdevlist_status_e status; 422 }; 423 424 typedef enum { 425 PERIPH_MATCH_NONE = 0x000, 426 PERIPH_MATCH_PATH = 0x001, 427 PERIPH_MATCH_TARGET = 0x002, 428 PERIPH_MATCH_LUN = 0x004, 429 PERIPH_MATCH_NAME = 0x008, 430 PERIPH_MATCH_UNIT = 0x010, 431 PERIPH_MATCH_ANY = 0x01f 432 } periph_pattern_flags; 433 434 struct periph_match_pattern { 435 char periph_name[DEV_IDLEN]; 436 u_int32_t unit_number; 437 path_id_t path_id; 438 target_id_t target_id; 439 lun_id_t target_lun; 440 periph_pattern_flags flags; 441 }; 442 443 typedef enum { 444 DEV_MATCH_NONE = 0x000, 445 DEV_MATCH_PATH = 0x001, 446 DEV_MATCH_TARGET = 0x002, 447 DEV_MATCH_LUN = 0x004, 448 DEV_MATCH_INQUIRY = 0x008, 449 DEV_MATCH_DEVID = 0x010, 450 DEV_MATCH_ANY = 0x00f 451 } dev_pattern_flags; 452 453 struct device_id_match_pattern { 454 uint8_t id_len; 455 uint8_t id[256]; 456 }; 457 458 struct device_match_pattern { 459 path_id_t path_id; 460 target_id_t target_id; 461 lun_id_t target_lun; 462 dev_pattern_flags flags; 463 union { 464 struct scsi_static_inquiry_pattern inq_pat; 465 struct device_id_match_pattern devid_pat; 466 } data; 467 }; 468 469 typedef enum { 470 BUS_MATCH_NONE = 0x000, 471 BUS_MATCH_PATH = 0x001, 472 BUS_MATCH_NAME = 0x002, 473 BUS_MATCH_UNIT = 0x004, 474 BUS_MATCH_BUS_ID = 0x008, 475 BUS_MATCH_ANY = 0x00f 476 } bus_pattern_flags; 477 478 struct bus_match_pattern { 479 path_id_t path_id; 480 char dev_name[DEV_IDLEN]; 481 u_int32_t unit_number; 482 u_int32_t bus_id; 483 bus_pattern_flags flags; 484 }; 485 486 union match_pattern { 487 struct periph_match_pattern periph_pattern; 488 struct device_match_pattern device_pattern; 489 struct bus_match_pattern bus_pattern; 490 }; 491 492 typedef enum { 493 DEV_MATCH_PERIPH, 494 DEV_MATCH_DEVICE, 495 DEV_MATCH_BUS 496 } dev_match_type; 497 498 struct dev_match_pattern { 499 dev_match_type type; 500 union match_pattern pattern; 501 }; 502 503 struct periph_match_result { 504 char periph_name[DEV_IDLEN]; 505 u_int32_t unit_number; 506 path_id_t path_id; 507 target_id_t target_id; 508 lun_id_t target_lun; 509 }; 510 511 typedef enum { 512 DEV_RESULT_NOFLAG = 0x00, 513 DEV_RESULT_UNCONFIGURED = 0x01 514 } dev_result_flags; 515 516 struct device_match_result { 517 path_id_t path_id; 518 target_id_t target_id; 519 lun_id_t target_lun; 520 cam_proto protocol; 521 struct scsi_inquiry_data inq_data; 522 struct ata_params ident_data; 523 dev_result_flags flags; 524 }; 525 526 struct bus_match_result { 527 path_id_t path_id; 528 char dev_name[DEV_IDLEN]; 529 u_int32_t unit_number; 530 u_int32_t bus_id; 531 }; 532 533 union match_result { 534 struct periph_match_result periph_result; 535 struct device_match_result device_result; 536 struct bus_match_result bus_result; 537 }; 538 539 struct dev_match_result { 540 dev_match_type type; 541 union match_result result; 542 }; 543 544 typedef enum { 545 CAM_DEV_MATCH_LAST, 546 CAM_DEV_MATCH_MORE, 547 CAM_DEV_MATCH_LIST_CHANGED, 548 CAM_DEV_MATCH_SIZE_ERROR, 549 CAM_DEV_MATCH_ERROR 550 } ccb_dev_match_status; 551 552 typedef enum { 553 CAM_DEV_POS_NONE = 0x000, 554 CAM_DEV_POS_BUS = 0x001, 555 CAM_DEV_POS_TARGET = 0x002, 556 CAM_DEV_POS_DEVICE = 0x004, 557 CAM_DEV_POS_PERIPH = 0x008, 558 CAM_DEV_POS_PDPTR = 0x010, 559 CAM_DEV_POS_TYPEMASK = 0xf00, 560 CAM_DEV_POS_EDT = 0x100, 561 CAM_DEV_POS_PDRV = 0x200 562 } dev_pos_type; 563 564 struct ccb_dm_cookie { 565 void *bus; 566 void *target; 567 void *device; 568 void *periph; 569 void *pdrv; 570 }; 571 572 struct ccb_dev_position { 573 u_int generations[4]; 574 #define CAM_BUS_GENERATION 0x00 575 #define CAM_TARGET_GENERATION 0x01 576 #define CAM_DEV_GENERATION 0x02 577 #define CAM_PERIPH_GENERATION 0x03 578 dev_pos_type position_type; 579 struct ccb_dm_cookie cookie; 580 }; 581 582 struct ccb_dev_match { 583 struct ccb_hdr ccb_h; 584 ccb_dev_match_status status; 585 u_int32_t num_patterns; 586 u_int32_t pattern_buf_len; 587 struct dev_match_pattern *patterns; 588 u_int32_t num_matches; 589 u_int32_t match_buf_len; 590 struct dev_match_result *matches; 591 struct ccb_dev_position pos; 592 }; 593 594 /* 595 * Definitions for the path inquiry CCB fields. 596 */ 597 #define CAM_VERSION 0x19 /* Hex value for current version */ 598 599 typedef enum { 600 PI_MDP_ABLE = 0x80, /* Supports MDP message */ 601 PI_WIDE_32 = 0x40, /* Supports 32 bit wide SCSI */ 602 PI_WIDE_16 = 0x20, /* Supports 16 bit wide SCSI */ 603 PI_SDTR_ABLE = 0x10, /* Supports SDTR message */ 604 PI_LINKED_CDB = 0x08, /* Supports linked CDBs */ 605 PI_SATAPM = 0x04, /* Supports SATA PM */ 606 PI_TAG_ABLE = 0x02, /* Supports tag queue messages */ 607 PI_SOFT_RST = 0x01 /* Supports soft reset alternative */ 608 } pi_inqflag; 609 610 typedef enum { 611 PIT_PROCESSOR = 0x80, /* Target mode processor mode */ 612 PIT_PHASE = 0x40, /* Target mode phase cog. mode */ 613 PIT_DISCONNECT = 0x20, /* Disconnects supported in target mode */ 614 PIT_TERM_IO = 0x10, /* Terminate I/O message supported in TM */ 615 PIT_GRP_6 = 0x08, /* Group 6 commands supported */ 616 PIT_GRP_7 = 0x04 /* Group 7 commands supported */ 617 } pi_tmflag; 618 619 typedef enum { 620 PIM_ATA_EXT = 0x200,/* ATA requests can understand ata_ext requests */ 621 PIM_EXTLUNS = 0x100,/* 64bit extended LUNs supported */ 622 PIM_SCANHILO = 0x80, /* Bus scans from high ID to low ID */ 623 PIM_NOREMOVE = 0x40, /* Removeable devices not included in scan */ 624 PIM_NOINITIATOR = 0x20, /* Initiator role not supported. */ 625 PIM_NOBUSRESET = 0x10, /* User has disabled initial BUS RESET */ 626 PIM_NO_6_BYTE = 0x08, /* Do not send 6-byte commands */ 627 PIM_SEQSCAN = 0x04, /* Do bus scans sequentially, not in parallel */ 628 PIM_UNMAPPED = 0x02, 629 PIM_NOSCAN = 0x01 /* SIM does its own scanning */ 630 } pi_miscflag; 631 632 /* Path Inquiry CCB */ 633 struct ccb_pathinq_settings_spi { 634 u_int8_t ppr_options; 635 }; 636 637 struct ccb_pathinq_settings_fc { 638 u_int64_t wwnn; /* world wide node name */ 639 u_int64_t wwpn; /* world wide port name */ 640 u_int32_t port; /* 24 bit port id, if known */ 641 u_int32_t bitrate; /* Mbps */ 642 }; 643 644 struct ccb_pathinq_settings_sas { 645 u_int32_t bitrate; /* Mbps */ 646 }; 647 648 #define NVME_DEV_NAME_LEN 52 649 struct ccb_pathinq_settings_nvme { 650 uint32_t nsid; /* Namespace ID for this path */ 651 uint32_t domain; 652 uint8_t bus; 653 uint8_t slot; 654 uint8_t function; 655 uint8_t extra; 656 char dev_name[NVME_DEV_NAME_LEN]; /* nvme controller dev name for this device */ 657 }; 658 _Static_assert(sizeof(struct ccb_pathinq_settings_nvme) == 64, 659 "ccb_pathinq_settings_nvme too big"); 660 661 #define PATHINQ_SETTINGS_SIZE 128 662 663 struct ccb_pathinq { 664 struct ccb_hdr ccb_h; 665 u_int8_t version_num; /* Version number for the SIM/HBA */ 666 u_int8_t hba_inquiry; /* Mimic of INQ byte 7 for the HBA */ 667 u_int16_t target_sprt; /* Flags for target mode support */ 668 u_int32_t hba_misc; /* Misc HBA features */ 669 u_int16_t hba_eng_cnt; /* HBA engine count */ 670 /* Vendor Unique capabilities */ 671 u_int8_t vuhba_flags[VUHBALEN]; 672 u_int32_t max_target; /* Maximum supported Target */ 673 u_int32_t max_lun; /* Maximum supported Lun */ 674 u_int32_t async_flags; /* Installed Async handlers */ 675 path_id_t hpath_id; /* Highest Path ID in the subsystem */ 676 target_id_t initiator_id; /* ID of the HBA on the SCSI bus */ 677 char sim_vid[SIM_IDLEN]; /* Vendor ID of the SIM */ 678 char hba_vid[HBA_IDLEN]; /* Vendor ID of the HBA */ 679 char dev_name[DEV_IDLEN];/* Device name for SIM */ 680 u_int32_t unit_number; /* Unit number for SIM */ 681 u_int32_t bus_id; /* Bus ID for SIM */ 682 u_int32_t base_transfer_speed;/* Base bus speed in KB/sec */ 683 cam_proto protocol; 684 u_int protocol_version; 685 cam_xport transport; 686 u_int transport_version; 687 union { 688 struct ccb_pathinq_settings_spi spi; 689 struct ccb_pathinq_settings_fc fc; 690 struct ccb_pathinq_settings_sas sas; 691 struct ccb_pathinq_settings_nvme nvme; 692 char ccb_pathinq_settings_opaque[PATHINQ_SETTINGS_SIZE]; 693 } xport_specific; 694 u_int maxio; /* Max supported I/O size, in bytes. */ 695 u_int16_t hba_vendor; /* HBA vendor ID */ 696 u_int16_t hba_device; /* HBA device ID */ 697 u_int16_t hba_subvendor; /* HBA subvendor ID */ 698 u_int16_t hba_subdevice; /* HBA subdevice ID */ 699 }; 700 701 /* Path Statistics CCB */ 702 struct ccb_pathstats { 703 struct ccb_hdr ccb_h; 704 struct timeval last_reset; /* Time of last bus reset/loop init */ 705 }; 706 707 typedef enum { 708 SMP_FLAG_NONE = 0x00, 709 SMP_FLAG_REQ_SG = 0x01, 710 SMP_FLAG_RSP_SG = 0x02 711 } ccb_smp_pass_flags; 712 713 /* 714 * Serial Management Protocol CCB 715 * XXX Currently the semantics for this CCB are that it is executed either 716 * by the addressed device, or that device's parent (i.e. an expander for 717 * any device on an expander) if the addressed device doesn't support SMP. 718 * Later, once we have the ability to probe SMP-only devices and put them 719 * in CAM's topology, the CCB will only be executed by the addressed device 720 * if possible. 721 */ 722 struct ccb_smpio { 723 struct ccb_hdr ccb_h; 724 uint8_t *smp_request; 725 int smp_request_len; 726 uint16_t smp_request_sglist_cnt; 727 uint8_t *smp_response; 728 int smp_response_len; 729 uint16_t smp_response_sglist_cnt; 730 ccb_smp_pass_flags flags; 731 }; 732 733 typedef union { 734 u_int8_t *sense_ptr; /* 735 * Pointer to storage 736 * for sense information 737 */ 738 /* Storage Area for sense information */ 739 struct scsi_sense_data sense_buf; 740 } sense_t; 741 742 typedef union { 743 u_int8_t *cdb_ptr; /* Pointer to the CDB bytes to send */ 744 /* Area for the CDB send */ 745 u_int8_t cdb_bytes[IOCDBLEN]; 746 } cdb_t; 747 748 /* 749 * SCSI I/O Request CCB used for the XPT_SCSI_IO and XPT_CONT_TARGET_IO 750 * function codes. 751 */ 752 struct ccb_scsiio { 753 struct ccb_hdr ccb_h; 754 union ccb *next_ccb; /* Ptr for next CCB for action */ 755 u_int8_t *req_map; /* Ptr to mapping info */ 756 u_int8_t *data_ptr; /* Ptr to the data buf/SG list */ 757 u_int32_t dxfer_len; /* Data transfer length */ 758 /* Autosense storage */ 759 struct scsi_sense_data sense_data; 760 u_int8_t sense_len; /* Number of bytes to autosense */ 761 u_int8_t cdb_len; /* Number of bytes for the CDB */ 762 u_int16_t sglist_cnt; /* Number of SG list entries */ 763 u_int8_t scsi_status; /* Returned SCSI status */ 764 u_int8_t sense_resid; /* Autosense resid length: 2's comp */ 765 u_int32_t resid; /* Transfer residual length: 2's comp */ 766 cdb_t cdb_io; /* Union for CDB bytes/pointer */ 767 u_int8_t *msg_ptr; /* Pointer to the message buffer */ 768 u_int16_t msg_len; /* Number of bytes for the Message */ 769 u_int8_t tag_action; /* What to do for tag queueing */ 770 /* 771 * The tag action should be either the define below (to send a 772 * non-tagged transaction) or one of the defined scsi tag messages 773 * from scsi_message.h. 774 */ 775 #define CAM_TAG_ACTION_NONE 0x00 776 uint8_t priority; /* Command priority for SIMPLE tag */ 777 u_int tag_id; /* tag id from initator (target mode) */ 778 u_int init_id; /* initiator id of who selected */ 779 #if defined(BUF_TRACKING) || defined(FULL_BUF_TRACKING) 780 struct bio *bio; /* Associated bio */ 781 #endif 782 }; 783 784 static __inline uint8_t * 785 scsiio_cdb_ptr(struct ccb_scsiio *ccb) 786 { 787 return ((ccb->ccb_h.flags & CAM_CDB_POINTER) ? 788 ccb->cdb_io.cdb_ptr : ccb->cdb_io.cdb_bytes); 789 } 790 791 /* 792 * ATA I/O Request CCB used for the XPT_ATA_IO function code. 793 */ 794 struct ccb_ataio { 795 struct ccb_hdr ccb_h; 796 union ccb *next_ccb; /* Ptr for next CCB for action */ 797 struct ata_cmd cmd; /* ATA command register set */ 798 struct ata_res res; /* ATA result register set */ 799 u_int8_t *data_ptr; /* Ptr to the data buf/SG list */ 800 u_int32_t dxfer_len; /* Data transfer length */ 801 u_int32_t resid; /* Transfer residual length: 2's comp */ 802 u_int8_t ata_flags; /* Flags for the rest of the buffer */ 803 #define ATA_FLAG_AUX 0x1 804 #define ATA_FLAG_ICC 0x2 805 uint8_t icc; /* Isochronous Command Completion */ 806 uint32_t aux; 807 uint32_t unused; 808 }; 809 810 /* 811 * MMC I/O Request CCB used for the XPT_MMC_IO function code. 812 */ 813 struct ccb_mmcio { 814 struct ccb_hdr ccb_h; 815 union ccb *next_ccb; /* Ptr for next CCB for action */ 816 struct mmc_command cmd; 817 struct mmc_command stop; 818 }; 819 820 struct ccb_accept_tio { 821 struct ccb_hdr ccb_h; 822 cdb_t cdb_io; /* Union for CDB bytes/pointer */ 823 u_int8_t cdb_len; /* Number of bytes for the CDB */ 824 u_int8_t tag_action; /* What to do for tag queueing */ 825 u_int8_t sense_len; /* Number of bytes of Sense Data */ 826 uint8_t priority; /* Command priority for SIMPLE tag */ 827 u_int tag_id; /* tag id from initator (target mode) */ 828 u_int init_id; /* initiator id of who selected */ 829 struct scsi_sense_data sense_data; 830 }; 831 832 static __inline uint8_t * 833 atio_cdb_ptr(struct ccb_accept_tio *ccb) 834 { 835 return ((ccb->ccb_h.flags & CAM_CDB_POINTER) ? 836 ccb->cdb_io.cdb_ptr : ccb->cdb_io.cdb_bytes); 837 } 838 839 /* Release SIM Queue */ 840 struct ccb_relsim { 841 struct ccb_hdr ccb_h; 842 u_int32_t release_flags; 843 #define RELSIM_ADJUST_OPENINGS 0x01 844 #define RELSIM_RELEASE_AFTER_TIMEOUT 0x02 845 #define RELSIM_RELEASE_AFTER_CMDCMPLT 0x04 846 #define RELSIM_RELEASE_AFTER_QEMPTY 0x08 847 u_int32_t openings; 848 u_int32_t release_timeout; /* Abstract argument. */ 849 u_int32_t qfrozen_cnt; 850 }; 851 852 /* 853 * NVMe I/O Request CCB used for the XPT_NVME_IO and XPT_NVME_ADMIN function codes. 854 */ 855 struct ccb_nvmeio { 856 struct ccb_hdr ccb_h; 857 union ccb *next_ccb; /* Ptr for next CCB for action */ 858 struct nvme_command cmd; /* NVME command, per NVME standard */ 859 struct nvme_completion cpl; /* NVME completion, per NVME standard */ 860 uint8_t *data_ptr; /* Ptr to the data buf/SG list */ 861 uint32_t dxfer_len; /* Data transfer length */ 862 uint16_t sglist_cnt; /* Number of SG list entries */ 863 uint16_t unused; /* padding for removed uint32_t */ 864 }; 865 866 /* 867 * Definitions for the asynchronous callback CCB fields. 868 */ 869 typedef enum { 870 AC_UNIT_ATTENTION = 0x4000,/* Device reported UNIT ATTENTION */ 871 AC_ADVINFO_CHANGED = 0x2000,/* Advance info might have changes */ 872 AC_CONTRACT = 0x1000,/* A contractual callback */ 873 AC_GETDEV_CHANGED = 0x800,/* Getdev info might have changed */ 874 AC_INQ_CHANGED = 0x400,/* Inquiry info might have changed */ 875 AC_TRANSFER_NEG = 0x200,/* New transfer settings in effect */ 876 AC_LOST_DEVICE = 0x100,/* A device went away */ 877 AC_FOUND_DEVICE = 0x080,/* A new device was found */ 878 AC_PATH_DEREGISTERED = 0x040,/* A path has de-registered */ 879 AC_PATH_REGISTERED = 0x020,/* A new path has been registered */ 880 AC_SENT_BDR = 0x010,/* A BDR message was sent to target */ 881 AC_SCSI_AEN = 0x008,/* A SCSI AEN has been received */ 882 AC_UNSOL_RESEL = 0x002,/* Unsolicited reselection occurred */ 883 AC_BUS_RESET = 0x001 /* A SCSI bus reset occurred */ 884 } ac_code; 885 886 typedef void ac_callback_t (void *softc, u_int32_t code, 887 struct cam_path *path, void *args); 888 889 /* 890 * Generic Asynchronous callbacks. 891 * 892 * Generic arguments passed bac which are then interpreted between a per-system 893 * contract number. 894 */ 895 #define AC_CONTRACT_DATA_MAX (128 - sizeof (u_int64_t)) 896 struct ac_contract { 897 u_int64_t contract_number; 898 u_int8_t contract_data[AC_CONTRACT_DATA_MAX]; 899 }; 900 901 #define AC_CONTRACT_DEV_CHG 1 902 struct ac_device_changed { 903 u_int64_t wwpn; 904 u_int32_t port; 905 target_id_t target; 906 u_int8_t arrived; 907 }; 908 909 /* Set Asynchronous Callback CCB */ 910 struct ccb_setasync { 911 struct ccb_hdr ccb_h; 912 u_int32_t event_enable; /* Async Event enables */ 913 ac_callback_t *callback; 914 void *callback_arg; 915 }; 916 917 /* Set Device Type CCB */ 918 struct ccb_setdev { 919 struct ccb_hdr ccb_h; 920 u_int8_t dev_type; /* Value for dev type field in EDT */ 921 }; 922 923 /* SCSI Control Functions */ 924 925 /* Abort XPT request CCB */ 926 struct ccb_abort { 927 struct ccb_hdr ccb_h; 928 union ccb *abort_ccb; /* Pointer to CCB to abort */ 929 }; 930 931 /* Reset SCSI Bus CCB */ 932 struct ccb_resetbus { 933 struct ccb_hdr ccb_h; 934 }; 935 936 /* Reset SCSI Device CCB */ 937 struct ccb_resetdev { 938 struct ccb_hdr ccb_h; 939 }; 940 941 /* Terminate I/O Process Request CCB */ 942 struct ccb_termio { 943 struct ccb_hdr ccb_h; 944 union ccb *termio_ccb; /* Pointer to CCB to terminate */ 945 }; 946 947 typedef enum { 948 CTS_TYPE_CURRENT_SETTINGS, 949 CTS_TYPE_USER_SETTINGS 950 } cts_type; 951 952 struct ccb_trans_settings_scsi 953 { 954 u_int valid; /* Which fields to honor */ 955 #define CTS_SCSI_VALID_TQ 0x01 956 u_int flags; 957 #define CTS_SCSI_FLAGS_TAG_ENB 0x01 958 }; 959 960 struct ccb_trans_settings_ata 961 { 962 u_int valid; /* Which fields to honor */ 963 #define CTS_ATA_VALID_TQ 0x01 964 u_int flags; 965 #define CTS_ATA_FLAGS_TAG_ENB 0x01 966 }; 967 968 struct ccb_trans_settings_spi 969 { 970 u_int valid; /* Which fields to honor */ 971 #define CTS_SPI_VALID_SYNC_RATE 0x01 972 #define CTS_SPI_VALID_SYNC_OFFSET 0x02 973 #define CTS_SPI_VALID_BUS_WIDTH 0x04 974 #define CTS_SPI_VALID_DISC 0x08 975 #define CTS_SPI_VALID_PPR_OPTIONS 0x10 976 u_int flags; 977 #define CTS_SPI_FLAGS_DISC_ENB 0x01 978 u_int sync_period; 979 u_int sync_offset; 980 u_int bus_width; 981 u_int ppr_options; 982 }; 983 984 struct ccb_trans_settings_fc { 985 u_int valid; /* Which fields to honor */ 986 #define CTS_FC_VALID_WWNN 0x8000 987 #define CTS_FC_VALID_WWPN 0x4000 988 #define CTS_FC_VALID_PORT 0x2000 989 #define CTS_FC_VALID_SPEED 0x1000 990 u_int64_t wwnn; /* world wide node name */ 991 u_int64_t wwpn; /* world wide port name */ 992 u_int32_t port; /* 24 bit port id, if known */ 993 u_int32_t bitrate; /* Mbps */ 994 }; 995 996 struct ccb_trans_settings_sas { 997 u_int valid; /* Which fields to honor */ 998 #define CTS_SAS_VALID_SPEED 0x1000 999 u_int32_t bitrate; /* Mbps */ 1000 }; 1001 1002 struct ccb_trans_settings_pata { 1003 u_int valid; /* Which fields to honor */ 1004 #define CTS_ATA_VALID_MODE 0x01 1005 #define CTS_ATA_VALID_BYTECOUNT 0x02 1006 #define CTS_ATA_VALID_ATAPI 0x20 1007 #define CTS_ATA_VALID_CAPS 0x40 1008 int mode; /* Mode */ 1009 u_int bytecount; /* Length of PIO transaction */ 1010 u_int atapi; /* Length of ATAPI CDB */ 1011 u_int caps; /* Device and host SATA caps. */ 1012 #define CTS_ATA_CAPS_H 0x0000ffff 1013 #define CTS_ATA_CAPS_H_DMA48 0x00000001 /* 48-bit DMA */ 1014 #define CTS_ATA_CAPS_D 0xffff0000 1015 }; 1016 1017 struct ccb_trans_settings_sata { 1018 u_int valid; /* Which fields to honor */ 1019 #define CTS_SATA_VALID_MODE 0x01 1020 #define CTS_SATA_VALID_BYTECOUNT 0x02 1021 #define CTS_SATA_VALID_REVISION 0x04 1022 #define CTS_SATA_VALID_PM 0x08 1023 #define CTS_SATA_VALID_TAGS 0x10 1024 #define CTS_SATA_VALID_ATAPI 0x20 1025 #define CTS_SATA_VALID_CAPS 0x40 1026 int mode; /* Legacy PATA mode */ 1027 u_int bytecount; /* Length of PIO transaction */ 1028 int revision; /* SATA revision */ 1029 u_int pm_present; /* PM is present (XPT->SIM) */ 1030 u_int tags; /* Number of allowed tags */ 1031 u_int atapi; /* Length of ATAPI CDB */ 1032 u_int caps; /* Device and host SATA caps. */ 1033 #define CTS_SATA_CAPS_H 0x0000ffff 1034 #define CTS_SATA_CAPS_H_PMREQ 0x00000001 1035 #define CTS_SATA_CAPS_H_APST 0x00000002 1036 #define CTS_SATA_CAPS_H_DMAAA 0x00000010 /* Auto-activation */ 1037 #define CTS_SATA_CAPS_H_AN 0x00000020 /* Async. notification */ 1038 #define CTS_SATA_CAPS_D 0xffff0000 1039 #define CTS_SATA_CAPS_D_PMREQ 0x00010000 1040 #define CTS_SATA_CAPS_D_APST 0x00020000 1041 }; 1042 1043 struct ccb_trans_settings_nvme 1044 { 1045 u_int valid; /* Which fields to honor */ 1046 #define CTS_NVME_VALID_SPEC 0x01 1047 #define CTS_NVME_VALID_CAPS 0x02 1048 #define CTS_NVME_VALID_LINK 0x04 1049 uint32_t spec; /* NVMe spec implemented -- same as vs register */ 1050 uint32_t max_xfer; /* Max transfer size (0 -> unlimited */ 1051 uint32_t caps; 1052 uint8_t lanes; /* Number of PCIe lanes */ 1053 uint8_t speed; /* PCIe generation for each lane */ 1054 uint8_t max_lanes; /* Number of PCIe lanes */ 1055 uint8_t max_speed; /* PCIe generation for each lane */ 1056 }; 1057 1058 #include <cam/mmc/mmc_bus.h> 1059 struct ccb_trans_settings_mmc { 1060 struct mmc_ios ios; 1061 #define MMC_CLK (1 << 1) 1062 #define MMC_VDD (1 << 2) 1063 #define MMC_CS (1 << 3) 1064 #define MMC_BW (1 << 4) 1065 #define MMC_PM (1 << 5) 1066 #define MMC_BT (1 << 6) 1067 #define MMC_BM (1 << 7) 1068 #define MMC_VCCQ (1 << 8) 1069 uint32_t ios_valid; 1070 /* The folowing is used only for GET_TRAN_SETTINGS */ 1071 uint32_t host_ocr; 1072 int host_f_min; 1073 int host_f_max; 1074 /* Copied from sys/dev/mmc/bridge.h */ 1075 #define MMC_CAP_4_BIT_DATA (1 << 0) /* Can do 4-bit data transfers */ 1076 #define MMC_CAP_8_BIT_DATA (1 << 1) /* Can do 8-bit data transfers */ 1077 #define MMC_CAP_HSPEED (1 << 2) /* Can do High Speed transfers */ 1078 #define MMC_CAP_BOOT_NOACC (1 << 4) /* Cannot access boot partitions */ 1079 #define MMC_CAP_WAIT_WHILE_BUSY (1 << 5) /* Host waits for busy responses */ 1080 #define MMC_CAP_UHS_SDR12 (1 << 6) /* Can do UHS SDR12 */ 1081 #define MMC_CAP_UHS_SDR25 (1 << 7) /* Can do UHS SDR25 */ 1082 #define MMC_CAP_UHS_SDR50 (1 << 8) /* Can do UHS SDR50 */ 1083 #define MMC_CAP_UHS_SDR104 (1 << 9) /* Can do UHS SDR104 */ 1084 #define MMC_CAP_UHS_DDR50 (1 << 10) /* Can do UHS DDR50 */ 1085 #define MMC_CAP_MMC_DDR52_120 (1 << 11) /* Can do eMMC DDR52 at 1.2 V */ 1086 #define MMC_CAP_MMC_DDR52_180 (1 << 12) /* Can do eMMC DDR52 at 1.8 V */ 1087 #define MMC_CAP_MMC_DDR52 (MMC_CAP_MMC_DDR52_120 | MMC_CAP_MMC_DDR52_180) 1088 #define MMC_CAP_MMC_HS200_120 (1 << 13) /* Can do eMMC HS200 at 1.2 V */ 1089 #define MMC_CAP_MMC_HS200_180 (1 << 14) /* Can do eMMC HS200 at 1.8 V */ 1090 #define MMC_CAP_MMC_HS200 (MMC_CAP_MMC_HS200_120| MMC_CAP_MMC_HS200_180) 1091 #define MMC_CAP_MMC_HS400_120 (1 << 15) /* Can do eMMC HS400 at 1.2 V */ 1092 #define MMC_CAP_MMC_HS400_180 (1 << 16) /* Can do eMMC HS400 at 1.8 V */ 1093 #define MMC_CAP_MMC_HS400 (MMC_CAP_MMC_HS400_120 | MMC_CAP_MMC_HS400_180) 1094 #define MMC_CAP_MMC_HSX00_120 (MMC_CAP_MMC_HS200_120 | MMC_CAP_MMC_HS400_120) 1095 #define MMC_CAP_MMC_ENH_STROBE (1 << 17) /* Can do eMMC Enhanced Strobe */ 1096 #define MMC_CAP_SIGNALING_120 (1 << 18) /* Can do signaling at 1.2 V */ 1097 #define MMC_CAP_SIGNALING_180 (1 << 19) /* Can do signaling at 1.8 V */ 1098 #define MMC_CAP_SIGNALING_330 (1 << 20) /* Can do signaling at 3.3 V */ 1099 #define MMC_CAP_DRIVER_TYPE_A (1 << 21) /* Can do Driver Type A */ 1100 #define MMC_CAP_DRIVER_TYPE_C (1 << 22) /* Can do Driver Type C */ 1101 #define MMC_CAP_DRIVER_TYPE_D (1 << 23) /* Can do Driver Type D */ 1102 1103 uint32_t host_caps; 1104 uint32_t host_max_data; 1105 }; 1106 1107 /* Get/Set transfer rate/width/disconnection/tag queueing settings */ 1108 struct ccb_trans_settings { 1109 struct ccb_hdr ccb_h; 1110 cts_type type; /* Current or User settings */ 1111 cam_proto protocol; 1112 u_int protocol_version; 1113 cam_xport transport; 1114 u_int transport_version; 1115 union { 1116 u_int valid; /* Which fields to honor */ 1117 struct ccb_trans_settings_ata ata; 1118 struct ccb_trans_settings_scsi scsi; 1119 struct ccb_trans_settings_nvme nvme; 1120 struct ccb_trans_settings_mmc mmc; 1121 } proto_specific; 1122 union { 1123 u_int valid; /* Which fields to honor */ 1124 struct ccb_trans_settings_spi spi; 1125 struct ccb_trans_settings_fc fc; 1126 struct ccb_trans_settings_sas sas; 1127 struct ccb_trans_settings_pata ata; 1128 struct ccb_trans_settings_sata sata; 1129 struct ccb_trans_settings_nvme nvme; 1130 } xport_specific; 1131 }; 1132 1133 /* 1134 * Calculate the geometry parameters for a device 1135 * give the block size and volume size in blocks. 1136 */ 1137 struct ccb_calc_geometry { 1138 struct ccb_hdr ccb_h; 1139 u_int32_t block_size; 1140 u_int64_t volume_size; 1141 u_int32_t cylinders; 1142 u_int8_t heads; 1143 u_int8_t secs_per_track; 1144 }; 1145 1146 /* 1147 * Set or get SIM (and transport) specific knobs 1148 */ 1149 1150 #define KNOB_VALID_ADDRESS 0x1 1151 #define KNOB_VALID_ROLE 0x2 1152 1153 #define KNOB_ROLE_NONE 0x0 1154 #define KNOB_ROLE_INITIATOR 0x1 1155 #define KNOB_ROLE_TARGET 0x2 1156 #define KNOB_ROLE_BOTH 0x3 1157 1158 struct ccb_sim_knob_settings_spi { 1159 u_int valid; 1160 u_int initiator_id; 1161 u_int role; 1162 }; 1163 1164 struct ccb_sim_knob_settings_fc { 1165 u_int valid; 1166 u_int64_t wwnn; /* world wide node name */ 1167 u_int64_t wwpn; /* world wide port name */ 1168 u_int role; 1169 }; 1170 1171 struct ccb_sim_knob_settings_sas { 1172 u_int valid; 1173 u_int64_t wwnn; /* world wide node name */ 1174 u_int role; 1175 }; 1176 #define KNOB_SETTINGS_SIZE 128 1177 1178 struct ccb_sim_knob { 1179 struct ccb_hdr ccb_h; 1180 union { 1181 u_int valid; /* Which fields to honor */ 1182 struct ccb_sim_knob_settings_spi spi; 1183 struct ccb_sim_knob_settings_fc fc; 1184 struct ccb_sim_knob_settings_sas sas; 1185 char pad[KNOB_SETTINGS_SIZE]; 1186 } xport_specific; 1187 }; 1188 1189 /* 1190 * Rescan the given bus, or bus/target/lun 1191 */ 1192 struct ccb_rescan { 1193 struct ccb_hdr ccb_h; 1194 cam_flags flags; 1195 }; 1196 1197 /* 1198 * Turn on debugging for the given bus, bus/target, or bus/target/lun. 1199 */ 1200 struct ccb_debug { 1201 struct ccb_hdr ccb_h; 1202 cam_debug_flags flags; 1203 }; 1204 1205 /* Target mode structures. */ 1206 1207 struct ccb_en_lun { 1208 struct ccb_hdr ccb_h; 1209 u_int16_t grp6_len; /* Group 6 VU CDB length */ 1210 u_int16_t grp7_len; /* Group 7 VU CDB length */ 1211 u_int8_t enable; 1212 }; 1213 1214 /* old, barely used immediate notify, binary compatibility */ 1215 struct ccb_immed_notify { 1216 struct ccb_hdr ccb_h; 1217 struct scsi_sense_data sense_data; 1218 u_int8_t sense_len; /* Number of bytes in sense buffer */ 1219 u_int8_t initiator_id; /* Id of initiator that selected */ 1220 u_int8_t message_args[7]; /* Message Arguments */ 1221 }; 1222 1223 struct ccb_notify_ack { 1224 struct ccb_hdr ccb_h; 1225 u_int16_t seq_id; /* Sequence identifier */ 1226 u_int8_t event; /* Event flags */ 1227 }; 1228 1229 struct ccb_immediate_notify { 1230 struct ccb_hdr ccb_h; 1231 u_int tag_id; /* Tag for immediate notify */ 1232 u_int seq_id; /* Tag for target of notify */ 1233 u_int initiator_id; /* Initiator Identifier */ 1234 u_int arg; /* Function specific */ 1235 }; 1236 1237 struct ccb_notify_acknowledge { 1238 struct ccb_hdr ccb_h; 1239 u_int tag_id; /* Tag for immediate notify */ 1240 u_int seq_id; /* Tar for target of notify */ 1241 u_int initiator_id; /* Initiator Identifier */ 1242 u_int arg; /* Response information */ 1243 /* 1244 * Lower byte of arg is one of RESPONSE CODE values defined below 1245 * (subset of response codes from SPL-4 and FCP-4 specifications), 1246 * upper 3 bytes is code-specific ADDITIONAL RESPONSE INFORMATION. 1247 */ 1248 #define CAM_RSP_TMF_COMPLETE 0x00 1249 #define CAM_RSP_TMF_REJECTED 0x04 1250 #define CAM_RSP_TMF_FAILED 0x05 1251 #define CAM_RSP_TMF_SUCCEEDED 0x08 1252 #define CAM_RSP_TMF_INCORRECT_LUN 0x09 1253 }; 1254 1255 /* HBA engine structures. */ 1256 1257 typedef enum { 1258 EIT_BUFFER, /* Engine type: buffer memory */ 1259 EIT_LOSSLESS, /* Engine type: lossless compression */ 1260 EIT_LOSSY, /* Engine type: lossy compression */ 1261 EIT_ENCRYPT /* Engine type: encryption */ 1262 } ei_type; 1263 1264 typedef enum { 1265 EAD_VUNIQUE, /* Engine algorithm ID: vendor unique */ 1266 EAD_LZ1V1, /* Engine algorithm ID: LZ1 var.1 */ 1267 EAD_LZ2V1, /* Engine algorithm ID: LZ2 var.1 */ 1268 EAD_LZ2V2 /* Engine algorithm ID: LZ2 var.2 */ 1269 } ei_algo; 1270 1271 struct ccb_eng_inq { 1272 struct ccb_hdr ccb_h; 1273 u_int16_t eng_num; /* The engine number for this inquiry */ 1274 ei_type eng_type; /* Returned engine type */ 1275 ei_algo eng_algo; /* Returned engine algorithm type */ 1276 u_int32_t eng_memeory; /* Returned engine memory size */ 1277 }; 1278 1279 struct ccb_eng_exec { /* This structure must match SCSIIO size */ 1280 struct ccb_hdr ccb_h; 1281 u_int8_t *pdrv_ptr; /* Ptr used by the peripheral driver */ 1282 u_int8_t *req_map; /* Ptr for mapping info on the req. */ 1283 u_int8_t *data_ptr; /* Pointer to the data buf/SG list */ 1284 u_int32_t dxfer_len; /* Data transfer length */ 1285 u_int8_t *engdata_ptr; /* Pointer to the engine buffer data */ 1286 u_int16_t sglist_cnt; /* Num of scatter gather list entries */ 1287 u_int32_t dmax_len; /* Destination data maximum length */ 1288 u_int32_t dest_len; /* Destination data length */ 1289 int32_t src_resid; /* Source residual length: 2's comp */ 1290 u_int32_t timeout; /* Timeout value */ 1291 u_int16_t eng_num; /* Engine number for this request */ 1292 u_int16_t vu_flags; /* Vendor Unique flags */ 1293 }; 1294 1295 /* 1296 * Definitions for the timeout field in the SCSI I/O CCB. 1297 */ 1298 #define CAM_TIME_DEFAULT 0x00000000 /* Use SIM default value */ 1299 #define CAM_TIME_INFINITY 0xFFFFFFFF /* Infinite timeout */ 1300 1301 #define CAM_SUCCESS 0 /* For signaling general success */ 1302 1303 #define XPT_CCB_INVALID -1 /* for signaling a bad CCB to free */ 1304 1305 /* 1306 * CCB for working with advanced device information. This operates in a fashion 1307 * similar to XPT_GDEV_TYPE. Specify the target in ccb_h, the buffer 1308 * type requested, and provide a buffer size/buffer to write to. If the 1309 * buffer is too small, provsiz will be larger than bufsiz. 1310 */ 1311 struct ccb_dev_advinfo { 1312 struct ccb_hdr ccb_h; 1313 uint32_t flags; 1314 #define CDAI_FLAG_NONE 0x0 /* No flags set */ 1315 #define CDAI_FLAG_STORE 0x1 /* If set, action becomes store */ 1316 uint32_t buftype; /* IN: Type of data being requested */ 1317 /* NB: buftype is interpreted on a per-transport basis */ 1318 #define CDAI_TYPE_SCSI_DEVID 1 1319 #define CDAI_TYPE_SERIAL_NUM 2 1320 #define CDAI_TYPE_PHYS_PATH 3 1321 #define CDAI_TYPE_RCAPLONG 4 1322 #define CDAI_TYPE_EXT_INQ 5 1323 #define CDAI_TYPE_NVME_CNTRL 6 /* NVMe Identify Controller data */ 1324 #define CDAI_TYPE_NVME_NS 7 /* NVMe Identify Namespace data */ 1325 #define CDAI_TYPE_MMC_PARAMS 8 /* MMC/SD ident */ 1326 off_t bufsiz; /* IN: Size of external buffer */ 1327 #define CAM_SCSI_DEVID_MAXLEN 65536 /* length in buffer is an uint16_t */ 1328 off_t provsiz; /* OUT: Size required/used */ 1329 uint8_t *buf; /* IN/OUT: Buffer for requested data */ 1330 }; 1331 1332 /* 1333 * CCB for sending async events 1334 */ 1335 struct ccb_async { 1336 struct ccb_hdr ccb_h; 1337 uint32_t async_code; 1338 off_t async_arg_size; 1339 void *async_arg_ptr; 1340 }; 1341 1342 /* 1343 * Union of all CCB types for kernel space allocation. This union should 1344 * never be used for manipulating CCBs - its only use is for the allocation 1345 * and deallocation of raw CCB space and is the return type of xpt_ccb_alloc 1346 * and the argument to xpt_ccb_free. 1347 */ 1348 union ccb { 1349 struct ccb_hdr ccb_h; /* For convenience */ 1350 struct ccb_scsiio csio; 1351 struct ccb_getdev cgd; 1352 struct ccb_getdevlist cgdl; 1353 struct ccb_pathinq cpi; 1354 struct ccb_relsim crs; 1355 struct ccb_setasync csa; 1356 struct ccb_setdev csd; 1357 struct ccb_pathstats cpis; 1358 struct ccb_getdevstats cgds; 1359 struct ccb_dev_match cdm; 1360 struct ccb_trans_settings cts; 1361 struct ccb_calc_geometry ccg; 1362 struct ccb_sim_knob knob; 1363 struct ccb_abort cab; 1364 struct ccb_resetbus crb; 1365 struct ccb_resetdev crd; 1366 struct ccb_termio tio; 1367 struct ccb_accept_tio atio; 1368 struct ccb_scsiio ctio; 1369 struct ccb_en_lun cel; 1370 struct ccb_immed_notify cin; 1371 struct ccb_notify_ack cna; 1372 struct ccb_immediate_notify cin1; 1373 struct ccb_notify_acknowledge cna2; 1374 struct ccb_eng_inq cei; 1375 struct ccb_eng_exec cee; 1376 struct ccb_smpio smpio; 1377 struct ccb_rescan crcn; 1378 struct ccb_debug cdbg; 1379 struct ccb_ataio ataio; 1380 struct ccb_dev_advinfo cdai; 1381 struct ccb_async casync; 1382 struct ccb_nvmeio nvmeio; 1383 struct ccb_mmcio mmcio; 1384 }; 1385 1386 #define CCB_CLEAR_ALL_EXCEPT_HDR(ccbp) \ 1387 bzero((char *)(ccbp) + sizeof((ccbp)->ccb_h), \ 1388 sizeof(*(ccbp)) - sizeof((ccbp)->ccb_h)) 1389 1390 __BEGIN_DECLS 1391 static __inline void 1392 cam_fill_csio(struct ccb_scsiio *csio, u_int32_t retries, 1393 void (*cbfcnp)(struct cam_periph *, union ccb *), 1394 u_int32_t flags, u_int8_t tag_action, 1395 u_int8_t *data_ptr, u_int32_t dxfer_len, 1396 u_int8_t sense_len, u_int8_t cdb_len, 1397 u_int32_t timeout) 1398 { 1399 csio->ccb_h.func_code = XPT_SCSI_IO; 1400 csio->ccb_h.flags = flags; 1401 csio->ccb_h.xflags = 0; 1402 csio->ccb_h.retry_count = retries; 1403 csio->ccb_h.cbfcnp = cbfcnp; 1404 csio->ccb_h.timeout = timeout; 1405 csio->data_ptr = data_ptr; 1406 csio->dxfer_len = dxfer_len; 1407 csio->sense_len = sense_len; 1408 csio->cdb_len = cdb_len; 1409 csio->tag_action = tag_action; 1410 csio->priority = 0; 1411 #if defined(BUF_TRACKING) || defined(FULL_BUF_TRACKING) 1412 csio->bio = NULL; 1413 #endif 1414 } 1415 1416 static __inline void 1417 cam_fill_ctio(struct ccb_scsiio *csio, u_int32_t retries, 1418 void (*cbfcnp)(struct cam_periph *, union ccb *), 1419 u_int32_t flags, u_int tag_action, u_int tag_id, 1420 u_int init_id, u_int scsi_status, u_int8_t *data_ptr, 1421 u_int32_t dxfer_len, u_int32_t timeout) 1422 { 1423 csio->ccb_h.func_code = XPT_CONT_TARGET_IO; 1424 csio->ccb_h.flags = flags; 1425 csio->ccb_h.xflags = 0; 1426 csio->ccb_h.retry_count = retries; 1427 csio->ccb_h.cbfcnp = cbfcnp; 1428 csio->ccb_h.timeout = timeout; 1429 csio->data_ptr = data_ptr; 1430 csio->dxfer_len = dxfer_len; 1431 csio->scsi_status = scsi_status; 1432 csio->tag_action = tag_action; 1433 csio->priority = 0; 1434 csio->tag_id = tag_id; 1435 csio->init_id = init_id; 1436 } 1437 1438 static __inline void 1439 cam_fill_ataio(struct ccb_ataio *ataio, u_int32_t retries, 1440 void (*cbfcnp)(struct cam_periph *, union ccb *), 1441 u_int32_t flags, u_int tag_action __unused, 1442 u_int8_t *data_ptr, u_int32_t dxfer_len, 1443 u_int32_t timeout) 1444 { 1445 ataio->ccb_h.func_code = XPT_ATA_IO; 1446 ataio->ccb_h.flags = flags; 1447 ataio->ccb_h.retry_count = retries; 1448 ataio->ccb_h.cbfcnp = cbfcnp; 1449 ataio->ccb_h.timeout = timeout; 1450 ataio->data_ptr = data_ptr; 1451 ataio->dxfer_len = dxfer_len; 1452 ataio->ata_flags = 0; 1453 } 1454 1455 static __inline void 1456 cam_fill_smpio(struct ccb_smpio *smpio, uint32_t retries, 1457 void (*cbfcnp)(struct cam_periph *, union ccb *), uint32_t flags, 1458 uint8_t *smp_request, int smp_request_len, 1459 uint8_t *smp_response, int smp_response_len, 1460 uint32_t timeout) 1461 { 1462 #ifdef _KERNEL 1463 KASSERT((flags & CAM_DIR_MASK) == CAM_DIR_BOTH, 1464 ("direction != CAM_DIR_BOTH")); 1465 KASSERT((smp_request != NULL) && (smp_response != NULL), 1466 ("need valid request and response buffers")); 1467 KASSERT((smp_request_len != 0) && (smp_response_len != 0), 1468 ("need non-zero request and response lengths")); 1469 #endif /*_KERNEL*/ 1470 smpio->ccb_h.func_code = XPT_SMP_IO; 1471 smpio->ccb_h.flags = flags; 1472 smpio->ccb_h.retry_count = retries; 1473 smpio->ccb_h.cbfcnp = cbfcnp; 1474 smpio->ccb_h.timeout = timeout; 1475 smpio->smp_request = smp_request; 1476 smpio->smp_request_len = smp_request_len; 1477 smpio->smp_response = smp_response; 1478 smpio->smp_response_len = smp_response_len; 1479 } 1480 1481 static __inline void 1482 cam_fill_mmcio(struct ccb_mmcio *mmcio, uint32_t retries, 1483 void (*cbfcnp)(struct cam_periph *, union ccb *), uint32_t flags, 1484 uint32_t mmc_opcode, uint32_t mmc_arg, uint32_t mmc_flags, 1485 struct mmc_data *mmc_d, 1486 uint32_t timeout) 1487 { 1488 mmcio->ccb_h.func_code = XPT_MMC_IO; 1489 mmcio->ccb_h.flags = flags; 1490 mmcio->ccb_h.retry_count = retries; 1491 mmcio->ccb_h.cbfcnp = cbfcnp; 1492 mmcio->ccb_h.timeout = timeout; 1493 mmcio->cmd.opcode = mmc_opcode; 1494 mmcio->cmd.arg = mmc_arg; 1495 mmcio->cmd.flags = mmc_flags; 1496 mmcio->stop.opcode = 0; 1497 mmcio->stop.arg = 0; 1498 mmcio->stop.flags = 0; 1499 if (mmc_d != NULL) { 1500 mmcio->cmd.data = mmc_d; 1501 } else 1502 mmcio->cmd.data = NULL; 1503 mmcio->cmd.resp[0] = 0; 1504 mmcio->cmd.resp[1] = 0; 1505 mmcio->cmd.resp[2] = 0; 1506 mmcio->cmd.resp[3] = 0; 1507 } 1508 1509 static __inline void 1510 cam_set_ccbstatus(union ccb *ccb, cam_status status) 1511 { 1512 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 1513 ccb->ccb_h.status |= status; 1514 } 1515 1516 static __inline cam_status 1517 cam_ccb_status(union ccb *ccb) 1518 { 1519 return ((cam_status)(ccb->ccb_h.status & CAM_STATUS_MASK)); 1520 } 1521 1522 void cam_calc_geometry(struct ccb_calc_geometry *ccg, int extended); 1523 1524 static __inline void 1525 cam_fill_nvmeio(struct ccb_nvmeio *nvmeio, u_int32_t retries, 1526 void (*cbfcnp)(struct cam_periph *, union ccb *), 1527 u_int32_t flags, u_int8_t *data_ptr, u_int32_t dxfer_len, 1528 u_int32_t timeout) 1529 { 1530 nvmeio->ccb_h.func_code = XPT_NVME_IO; 1531 nvmeio->ccb_h.flags = flags; 1532 nvmeio->ccb_h.retry_count = retries; 1533 nvmeio->ccb_h.cbfcnp = cbfcnp; 1534 nvmeio->ccb_h.timeout = timeout; 1535 nvmeio->data_ptr = data_ptr; 1536 nvmeio->dxfer_len = dxfer_len; 1537 } 1538 1539 static __inline void 1540 cam_fill_nvmeadmin(struct ccb_nvmeio *nvmeio, u_int32_t retries, 1541 void (*cbfcnp)(struct cam_periph *, union ccb *), 1542 u_int32_t flags, u_int8_t *data_ptr, u_int32_t dxfer_len, 1543 u_int32_t timeout) 1544 { 1545 nvmeio->ccb_h.func_code = XPT_NVME_ADMIN; 1546 nvmeio->ccb_h.flags = flags; 1547 nvmeio->ccb_h.retry_count = retries; 1548 nvmeio->ccb_h.cbfcnp = cbfcnp; 1549 nvmeio->ccb_h.timeout = timeout; 1550 nvmeio->data_ptr = data_ptr; 1551 nvmeio->dxfer_len = dxfer_len; 1552 } 1553 __END_DECLS 1554 1555 #endif /* _CAM_CAM_CCB_H */ 1556