1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (C) 2018 The FreeBSD Foundation 5 * 6 * This software was developed by Alexandru Elisei under sponsorship 7 * from the FreeBSD Foundation. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #ifndef _VGIC_V3_REG_H_ 32 #define _VGIC_V3_REG_H_ 33 34 /* Interrupt Controller End of Interrupt Status Register */ 35 #define ICH_EISR_EL2_STATUS_MASK 0xffff 36 #define ICH_EISR_EL2_EOI_NOT_HANDLED(lr) ((1 << lr) & ICH_EISR_EL2_STATUS_MASK) 37 38 /* Interrupt Controller Empty List Register Status Register */ 39 #define ICH_ELSR_EL2_STATUS_MASK 0xffff 40 #define ICH_ELSR_EL2_LR_EMPTY(x) ((1 << x) & ICH_ELSR_EL2_STATUS_MASK) 41 42 /* Interrupt Controller Hyp Control Register */ 43 #define ICH_HCR_EL2_EOICOUNT_SHIFT 27 44 #define ICH_HCR_EL2_EOICOUNT_MASK (0x1f << ICH_HCR_EL2_EOICOUNT_SHIFT) 45 #define ICH_HCR_EL2_TDIR (1 << 14) /* Trap non-secure EL1 writes to IC{C, V}_DIR_EL1 */ 46 #define ICH_HCR_EL2_TSEI (1 << 14) /* Trap System Error Interupts (SEI) to EL2 */ 47 #define ICH_HCR_EL2_TALL1 (1 << 12) /* Trap non-secure EL1 accesses to IC{C, V}_* for Group 1 interrupts */ 48 #define ICH_HCR_EL2_TALL0 (1 << 11) /* Trap non-secure EL1 accesses to IC{C, V}_* for Group 0 interrupts */ 49 #define ICH_HCR_EL2_TC (1 << 10) /* Trap non-secure EL1 accesses to common IC{C, V}_* registers */ 50 #define ICH_HCR_EL2_VGRP1DIE (1 << 7) /* VM Group 1 Disabled Interrupt Enable */ 51 #define ICH_HCR_EL2_VGRP1EIE (1 << 6) /* VM Group 1 Enabled Interrupt Enable */ 52 #define ICH_HCR_EL2_VGRP0DIE (1 << 5) /* VM Group 0 Disabled Interrupt Enable */ 53 #define ICH_HCR_EL2_VGRP0EIE (1 << 4) /* VM Group 0 Enabled Interrupt Enable */ 54 #define ICH_HCR_EL2_NPIE (1 << 3) /* No Pending Interrupt Enable */ 55 #define ICH_HCR_EL2_LRENPIE (1 << 2) /* List Register Entry Not Present Interrupt Enable */ 56 #define ICH_HCR_EL2_UIE (1 << 1) /* Underflow Interrupt Enable */ 57 #define ICH_HCR_EL2_En (1 << 0) /* Global enable for the virtual CPU interface */ 58 59 /* Interrupt Controller List Registers */ 60 #define ICH_LR_EL2_VINTID_MASK 0xffffffff 61 #define ICH_LR_EL2_VINTID(x) ((x) & ICH_LR_EL2_VINTID_MASK) 62 #define ICH_LR_EL2_PINTID_SHIFT 32 63 #define ICH_LR_EL2_PINTID_MASK (0x3fUL << ICH_LR_EL2_PINTID_SHIFT) 64 /* Raise a maintanance IRQ when deactivated (only non-HW virqs) */ 65 #define ICH_LR_EL2_EOI (1UL << 41) 66 #define ICH_LR_EL2_PRIO_SHIFT 48 67 #define ICH_LR_EL2_PRIO_MASK (0xffUL << ICH_LR_EL2_PRIO_SHIFT) 68 #define ICH_LR_EL2_GROUP_SHIFT 60 69 #define ICH_LR_EL2_GROUP1 (1UL << ICH_LR_EL2_GROUP_SHIFT) 70 #define ICH_LR_EL2_HW (1UL << 61) 71 #define ICH_LR_EL2_STATE_SHIFT 62 72 #define ICH_LR_EL2_STATE_MASK (0x3UL << ICH_LR_EL2_STATE_SHIFT) 73 #define ICH_LR_EL2_STATE(x) ((x) & ICH_LR_EL2_STATE_MASK) 74 #define ICH_LR_EL2_STATE_INACTIVE (0x0UL << ICH_LR_EL2_STATE_SHIFT) 75 #define ICH_LR_EL2_STATE_PENDING (0x1UL << ICH_LR_EL2_STATE_SHIFT) 76 #define ICH_LR_EL2_STATE_ACTIVE (0x2UL << ICH_LR_EL2_STATE_SHIFT) 77 #define ICH_LR_EL2_STATE_PENDING_ACTIVE (0x3UL << ICH_LR_EL2_STATE_SHIFT) 78 79 /* Interrupt Controller Maintenance Interrupt State Register */ 80 #define ICH_MISR_EL2_VGRP1D (1 << 7) /* vPE Group 1 Disabled */ 81 #define ICH_MISR_EL2_VGRP1E (1 << 6) /* vPE Group 1 Enabled */ 82 #define ICH_MISR_EL2_VGRP0D (1 << 5) /* vPE Group 0 Disabled */ 83 #define ICH_MISR_EL2_VGRP0E (1 << 4) /* vPE Group 0 Enabled */ 84 #define ICH_MISR_EL2_NP (1 << 3) /* No Pending */ 85 #define ICH_MISR_EL2_LRENP (1 << 2) /* List Register Entry Not Present */ 86 #define ICH_MISR_EL2_U (1 << 1) /* Underflow */ 87 #define ICH_MISR_EL2_EOI (1 << 0) /* End Of Interrupt */ 88 89 /* Interrupt Controller Virtual Machine Control Register */ 90 #define ICH_VMCR_EL2_VPMR_SHIFT 24 91 #define ICH_VMCR_EL2_VPMR_MASK (0xff << ICH_VMCR_EL2_VPMR_SHIFT) 92 #define ICH_VMCR_EL2_VPMR_PRIO_LOWEST (0xff << ICH_VMCR_EL2_VPMR_SHIFT) 93 #define ICH_VMCR_EL2_VPMR_PRIO_HIGHEST (0x00 << ICH_VMCR_EL2_VPMR_SHIFT) 94 #define ICH_VMCR_EL2_VBPR0_SHIFT 21 95 #define ICH_VMCR_EL2_VBPR0_MASK (0x7 << ICH_VMCR_EL2_VBPR0_SHIFT) 96 #define ICH_VMCR_EL2_VBPR0_NO_PREEMPTION \ 97 (0x7 << ICH_VMCR_EL2_VBPR0_SHIFT) 98 #define ICH_VMCR_EL2_VBPR1_SHIFT 18 99 #define ICH_VMCR_EL2_VBPR1_MASK (0x7 << ICH_VMCR_EL2_VBPR1_SHIFT) 100 #define ICH_VMCR_EL2_VBPR1_NO_PREEMPTION \ 101 (0x7 << ICH_VMCR_EL2_VBPR1_SHIFT) 102 #define ICH_VMCR_EL2_VEOIM (1 << 9) /* Virtual EOI mode */ 103 #define ICH_VMCR_EL2_VCBPR (1 << 4) /* Virtual Common binary Point Register */ 104 #define ICH_VMCR_EL2_VFIQEN (1 << 3) /* Virtual FIQ enable */ 105 #define ICH_VMCR_EL2_VACKCTL (1 << 2) /* Virtual AckCtl */ 106 #define ICH_VMCR_EL2_VENG1 (1 << 1) /* Virtual Group 1 Interrupt Enable */ 107 #define ICH_VMCR_EL2_VENG0 (1 << 0) /* Virtual Group 0 Interrupt Enable */ 108 109 /* Interrupt Controller VGIC Type Register */ 110 #define ICH_VTR_EL2_PRIBITS_SHIFT 29 111 #define ICH_VTR_EL2_PRIBITS_MASK (0x7 << ICH_VTR_EL2_PRIBITS_SHIFT) 112 #define ICH_VTR_EL2_PRIBITS(x) \ 113 ((((x) & ICH_VTR_EL2_PRIBITS_MASK) >> ICH_VTR_EL2_PRIBITS_SHIFT) + 1) 114 #define ICH_VTR_EL2_PREBITS_SHIFT 26 115 #define ICH_VTR_EL2_PREBITS_MASK (0x7 << ICH_VTR_EL2_PREBITS_SHIFT) 116 #define ICH_VTR_EL2_PREBITS(x) \ 117 (((x) & ICH_VTR_EL2_PREBITS_MASK) >> ICH_VTR_EL2_PREBITS_SHIFT) 118 #define ICH_VTR_EL2_SEIS (1 << 22) /* System Error Interrupt (SEI) Support */ 119 #define ICH_VTR_EL2_A3V (1 << 21) /* Affinity 3 Valid */ 120 #define ICH_VTR_EL2_NV4 (1 << 20) /* Direct injection of virtual interrupts. RES1 for GICv3 */ 121 #define ICH_VTR_EL2_TDS (1 << 19) /* Implementation supports ICH_HCR_EL2.TDIR */ 122 #define ICH_VTR_EL2_LISTREGS_MASK 0x1f 123 /* 124 * ICH_VTR_EL2.ListRegs holds the number of list registers, minus one. Add one 125 * to get the actual number of list registers. 126 */ 127 #define ICH_VTR_EL2_LISTREGS(x) (((x) & ICH_VTR_EL2_LISTREGS_MASK) + 1) 128 129 #endif /* !_VGIC_V3_REG_H_ */ 130