xref: /freebsd/sys/arm64/rockchip/rk_pinctrl.c (revision ddc0daea20280c3a06a910b72b14ffe3f624df71)
1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3  *
4  * Copyright (c) 2018 Emmanuel Vadot <manu@FreeBSD.org>
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26  * SUCH DAMAGE.
27  *
28  */
29 
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
32 
33 #include <sys/param.h>
34 #include <sys/systm.h>
35 #include <sys/bus.h>
36 
37 #include <sys/gpio.h>
38 #include <sys/kernel.h>
39 #include <sys/lock.h>
40 #include <sys/module.h>
41 #include <sys/mutex.h>
42 #include <sys/rman.h>
43 
44 #include <machine/bus.h>
45 #include <machine/resource.h>
46 #include <machine/intr.h>
47 
48 #include <dev/fdt/simplebus.h>
49 
50 #include <dev/ofw/ofw_bus.h>
51 #include <dev/ofw/ofw_bus_subr.h>
52 
53 #include <dev/fdt/fdt_pinctrl.h>
54 
55 #include <dev/extres/syscon/syscon.h>
56 
57 #include "gpio_if.h"
58 #include "syscon_if.h"
59 
60 struct rk_pinctrl_pin_drive {
61 	uint32_t	bank;
62 	uint32_t	subbank;
63 	uint32_t	offset;
64 	uint32_t	value;
65 	uint32_t	ma;
66 };
67 
68 struct rk_pinctrl_bank {
69 	uint32_t	bank;
70 	uint32_t	subbank;
71 	uint32_t	offset;
72 	uint32_t	nbits;
73 };
74 
75 struct rk_pinctrl_pin_fixup {
76 	uint32_t	bank;
77 	uint32_t	subbank;
78 	uint32_t	pin;
79 	uint32_t	reg;
80 	uint32_t	bit;
81 	uint32_t	mask;
82 };
83 
84 struct rk_pinctrl_gpio {
85 	uint32_t	bank;
86 	char		*gpio_name;
87 	device_t	gpio_dev;
88 };
89 
90 
91 struct rk_pinctrl_softc;
92 
93 struct rk_pinctrl_conf {
94 	struct rk_pinctrl_bank		*iomux_conf;
95 	uint32_t			iomux_nbanks;
96 	struct rk_pinctrl_pin_fixup	*pin_fixup;
97 	uint32_t			npin_fixup;
98 	struct rk_pinctrl_pin_drive	*pin_drive;
99 	uint32_t			npin_drive;
100 	struct rk_pinctrl_gpio		*gpio_bank;
101 	uint32_t			ngpio_bank;
102 	uint32_t	(*get_pd_offset)(struct rk_pinctrl_softc *, uint32_t);
103 	struct syscon	*(*get_syscon)(struct rk_pinctrl_softc *, uint32_t);
104 };
105 
106 struct rk_pinctrl_softc {
107 	struct simplebus_softc	simplebus_sc;
108 	device_t		dev;
109 	struct syscon		*grf;
110 	struct syscon		*pmu;
111 	struct rk_pinctrl_conf	*conf;
112 };
113 
114 #define	RK_IOMUX(_bank, _subbank, _offset, _nbits)			\
115 {									\
116 	.bank = _bank,							\
117 	.subbank = _subbank,						\
118 	.offset = _offset,						\
119 	.nbits = _nbits,						\
120 }
121 
122 #define	RK_PINFIX(_bank, _pin, _reg, _bit, _mask)			\
123 {									\
124 	.bank = _bank,							\
125 	.pin = _pin,							\
126 	.reg = _reg,							\
127 	.bit = _bit,							\
128 	.mask = _mask,							\
129 }
130 
131 #define	RK_PINDRIVE(_bank, _subbank, _offset, _value, _ma)		\
132 {									\
133 	.bank = _bank,							\
134 	.subbank = _subbank,						\
135 	.offset = _offset,						\
136 	.value = _value,						\
137 	.ma = _ma,							\
138 }
139 #define	RK_GPIO(_bank, _name)						\
140 {									\
141 	.bank = _bank,							\
142 	.gpio_name = _name,						\
143 }
144 
145 static struct rk_pinctrl_gpio rk3288_gpio_bank[] = {
146 	RK_GPIO(0, "gpio0"),
147 	RK_GPIO(1, "gpio1"),
148 	RK_GPIO(2, "gpio2"),
149 	RK_GPIO(3, "gpio3"),
150 	RK_GPIO(4, "gpio4"),
151 	RK_GPIO(5, "gpio5"),
152 	RK_GPIO(6, "gpio6"),
153 	RK_GPIO(7, "gpio7"),
154 	RK_GPIO(8, "gpio8"),
155 };
156 
157 static struct rk_pinctrl_bank rk3288_iomux_bank[] = {
158 	/*    bank sub  offs   nbits */
159 	/* PMU */
160 	RK_IOMUX(0, 0, 0x0084, 2),
161 	RK_IOMUX(0, 1, 0x0088, 2),
162 	RK_IOMUX(0, 2, 0x008C, 2),
163 	/* GFR */
164 	RK_IOMUX(1, 3, 0x000C, 2),
165 	RK_IOMUX(2, 0, 0x0010, 2),
166 	RK_IOMUX(2, 1, 0x0014, 2),
167 	RK_IOMUX(2, 2, 0x0018, 2),
168 	RK_IOMUX(2, 3, 0x001C, 2),
169 	RK_IOMUX(3, 0, 0x0020, 2),
170 	RK_IOMUX(3, 1, 0x0024, 2),
171 	RK_IOMUX(3, 2, 0x0028, 2),
172 	RK_IOMUX(3, 3, 0x002C, 4),
173 	RK_IOMUX(4, 0, 0x0034, 4),
174 	RK_IOMUX(4, 1, 0x003C, 4),
175 	RK_IOMUX(4, 2, 0x0044, 2),
176 	RK_IOMUX(4, 3, 0x0048, 2),
177 	/* 5,0 - Empty */
178 	RK_IOMUX(5, 1, 0x0050, 2),
179 	RK_IOMUX(5, 2, 0x0054, 2),
180 	/* 5,3 - Empty */
181 	RK_IOMUX(6, 0, 0x005C, 2),
182 	RK_IOMUX(6, 1, 0x0060, 2),
183 	RK_IOMUX(6, 2, 0x0064, 2),
184 	/* 6,3 - Empty */
185 	RK_IOMUX(7, 0, 0x006C, 2),
186 	RK_IOMUX(7, 1, 0x0070, 2),
187 	RK_IOMUX(7, 2, 0x0074, 4),
188 	/* 7,3 - Empty */
189 	RK_IOMUX(8, 0, 0x0080, 2),
190 	RK_IOMUX(8, 1, 0x0084, 2),
191 	/* 8,2 - Empty */
192 	/* 8,3 - Empty */
193 
194 };
195 
196 static struct rk_pinctrl_pin_fixup rk3288_pin_fixup[] = {
197 };
198 
199 static struct rk_pinctrl_pin_drive rk3288_pin_drive[] = {
200 	/*       bank sub offs val ma */
201 	/* GPIO0A (PMU)*/
202 	RK_PINDRIVE(0, 0, 0x070, 0, 2),
203 	RK_PINDRIVE(0, 0, 0x070, 1, 4),
204 	RK_PINDRIVE(0, 0, 0x070, 2, 8),
205 	RK_PINDRIVE(0, 0, 0x070, 3, 12),
206 
207 	/* GPIO0B (PMU)*/
208 	RK_PINDRIVE(0, 1, 0x074, 0, 2),
209 	RK_PINDRIVE(0, 1, 0x074, 1, 4),
210 	RK_PINDRIVE(0, 1, 0x074, 2, 8),
211 	RK_PINDRIVE(0, 1, 0x074, 3, 12),
212 
213 	/* GPIO0C (PMU)*/
214 	RK_PINDRIVE(0, 2, 0x078, 0, 2),
215 	RK_PINDRIVE(0, 2, 0x078, 1, 4),
216 	RK_PINDRIVE(0, 2, 0x078, 2, 8),
217 	RK_PINDRIVE(0, 2, 0x078, 3, 12),
218 
219 	/* GPIO1D */
220 	RK_PINDRIVE(1, 3, 0x1CC, 0, 2),
221 	RK_PINDRIVE(1, 3, 0x1CC, 1, 4),
222 	RK_PINDRIVE(1, 3, 0x1CC, 2, 8),
223 	RK_PINDRIVE(1, 3, 0x1CC, 3, 12),
224 
225 	/* GPIO2A */
226 	RK_PINDRIVE(2, 0, 0x1D0, 0, 2),
227 	RK_PINDRIVE(2, 0, 0x1D0, 1, 4),
228 	RK_PINDRIVE(2, 0, 0x1D0, 2, 8),
229 	RK_PINDRIVE(2, 0, 0x1D0, 3, 12),
230 
231 	/* GPIO2B */
232 	RK_PINDRIVE(2, 1, 0x1D4, 0, 2),
233 	RK_PINDRIVE(2, 1, 0x1D4, 1, 4),
234 	RK_PINDRIVE(2, 1, 0x1D4, 2, 8),
235 	RK_PINDRIVE(2, 1, 0x1D4, 3, 12),
236 
237 	/* GPIO2C */
238 	RK_PINDRIVE(2, 2, 0x1D8, 0, 2),
239 	RK_PINDRIVE(2, 2, 0x1D8, 1, 4),
240 	RK_PINDRIVE(2, 2, 0x1D8, 2, 8),
241 	RK_PINDRIVE(2, 2, 0x1D8, 3, 12),
242 
243 	/* GPIO2D */
244 	RK_PINDRIVE(2, 3, 0x1DC, 0, 2),
245 	RK_PINDRIVE(2, 3, 0x1DC, 1, 4),
246 	RK_PINDRIVE(2, 3, 0x1DC, 2, 8),
247 	RK_PINDRIVE(2, 3, 0x1DC, 3, 12),
248 
249 	/* GPIO3A */
250 	RK_PINDRIVE(3, 0, 0x1E0, 0, 2),
251 	RK_PINDRIVE(3, 0, 0x1E0, 1, 4),
252 	RK_PINDRIVE(3, 0, 0x1E0, 2, 8),
253 	RK_PINDRIVE(3, 0, 0x1E0, 3, 12),
254 
255 	/* GPIO3B */
256 	RK_PINDRIVE(3, 1, 0x1E4, 0, 2),
257 	RK_PINDRIVE(3, 1, 0x1E4, 1, 4),
258 	RK_PINDRIVE(3, 1, 0x1E4, 2, 8),
259 	RK_PINDRIVE(3, 1, 0x1E4, 3, 12),
260 
261 	/* GPIO3C */
262 	RK_PINDRIVE(3, 2, 0x1E8, 0, 2),
263 	RK_PINDRIVE(3, 2, 0x1E8, 1, 4),
264 	RK_PINDRIVE(3, 2, 0x1E8, 2, 8),
265 	RK_PINDRIVE(3, 2, 0x1E8, 3, 12),
266 
267 	/* GPIO3D */
268 	RK_PINDRIVE(3, 3, 0x1EC, 0, 2),
269 	RK_PINDRIVE(3, 3, 0x1EC, 1, 4),
270 	RK_PINDRIVE(3, 3, 0x1EC, 2, 8),
271 	RK_PINDRIVE(3, 3, 0x1EC, 3, 12),
272 
273 	/* GPIO4A */
274 	RK_PINDRIVE(4, 0, 0x1F0, 0, 2),
275 	RK_PINDRIVE(4, 0, 0x1F0, 1, 4),
276 	RK_PINDRIVE(4, 0, 0x1F0, 2, 8),
277 	RK_PINDRIVE(4, 0, 0x1F0, 3, 12),
278 
279 	/* GPIO4B */
280 	RK_PINDRIVE(4, 1, 0x1F4, 0, 2),
281 	RK_PINDRIVE(4, 1, 0x1F4, 1, 4),
282 	RK_PINDRIVE(4, 1, 0x1F4, 2, 8),
283 	RK_PINDRIVE(4, 1, 0x1F4, 3, 12),
284 
285 	/* GPIO4C */
286 	RK_PINDRIVE(4, 2, 0x1F8, 0, 2),
287 	RK_PINDRIVE(4, 2, 0x1F8, 1, 4),
288 	RK_PINDRIVE(4, 2, 0x1F8, 2, 8),
289 	RK_PINDRIVE(4, 2, 0x1F8, 3, 12),
290 
291 	/* GPIO4D */
292 	RK_PINDRIVE(4, 3, 0x1FC, 0, 2),
293 	RK_PINDRIVE(4, 3, 0x1FC, 1, 4),
294 	RK_PINDRIVE(4, 3, 0x1FC, 2, 8),
295 	RK_PINDRIVE(4, 3, 0x1FC, 3, 12),
296 
297 	/* GPIO5B */
298 	RK_PINDRIVE(5, 1, 0x204, 0, 2),
299 	RK_PINDRIVE(5, 1, 0x204, 1, 4),
300 	RK_PINDRIVE(5, 1, 0x204, 2, 8),
301 	RK_PINDRIVE(5, 1, 0x204, 3, 12),
302 
303 	/* GPIO5C */
304 	RK_PINDRIVE(5, 2, 0x208, 0, 2),
305 	RK_PINDRIVE(5, 2, 0x208, 1, 4),
306 	RK_PINDRIVE(5, 2, 0x208, 2, 8),
307 	RK_PINDRIVE(5, 2, 0x208, 3, 12),
308 
309 	/* GPIO6A */
310 	RK_PINDRIVE(6, 0, 0x210, 0, 2),
311 	RK_PINDRIVE(6, 0, 0x210, 1, 4),
312 	RK_PINDRIVE(6, 0, 0x210, 2, 8),
313 	RK_PINDRIVE(6, 0, 0x210, 3, 12),
314 
315 	/* GPIO6B */
316 	RK_PINDRIVE(6, 1, 0x214, 0, 2),
317 	RK_PINDRIVE(6, 1, 0x214, 1, 4),
318 	RK_PINDRIVE(6, 1, 0x214, 2, 8),
319 	RK_PINDRIVE(6, 1, 0x214, 3, 12),
320 
321 	/* GPIO6C */
322 	RK_PINDRIVE(6, 2, 0x218, 0, 2),
323 	RK_PINDRIVE(6, 2, 0x218, 1, 4),
324 	RK_PINDRIVE(6, 2, 0x218, 2, 8),
325 	RK_PINDRIVE(6, 2, 0x218, 3, 12),
326 
327 	/* GPIO7A */
328 	RK_PINDRIVE(7, 0, 0x220, 0, 2),
329 	RK_PINDRIVE(7, 0, 0x220, 1, 4),
330 	RK_PINDRIVE(7, 0, 0x220, 2, 8),
331 	RK_PINDRIVE(7, 0, 0x220, 3, 12),
332 
333 	/* GPIO7B */
334 	RK_PINDRIVE(7, 1, 0x224, 0, 2),
335 	RK_PINDRIVE(7, 1, 0x224, 1, 4),
336 	RK_PINDRIVE(7, 1, 0x224, 2, 8),
337 	RK_PINDRIVE(7, 1, 0x224, 3, 12),
338 
339 	/* GPIO7C */
340 	RK_PINDRIVE(7, 2, 0x228, 0, 2),
341 	RK_PINDRIVE(7, 2, 0x228, 1, 4),
342 	RK_PINDRIVE(7, 2, 0x228, 2, 8),
343 	RK_PINDRIVE(7, 2, 0x228, 3, 12),
344 
345 	/* GPIO8A */
346 	RK_PINDRIVE(8, 0, 0x230, 0, 2),
347 	RK_PINDRIVE(8, 0, 0x230, 1, 4),
348 	RK_PINDRIVE(8, 0, 0x230, 2, 8),
349 	RK_PINDRIVE(8, 0, 0x230, 3, 12),
350 
351 	/* GPIO8B */
352 	RK_PINDRIVE(8, 1, 0x234, 0, 2),
353 	RK_PINDRIVE(8, 1, 0x234, 1, 4),
354 	RK_PINDRIVE(8, 1, 0x234, 2, 8),
355 	RK_PINDRIVE(8, 1, 0x234, 3, 12),
356 };
357 
358 static uint32_t
359 rk3288_get_pd_offset(struct rk_pinctrl_softc *sc, uint32_t bank)
360 {
361 	if (bank == 0)
362 		return (0x064);		/* PMU */
363 	return (0x130);
364 }
365 
366 static struct syscon *
367 rk3288_get_syscon(struct rk_pinctrl_softc *sc, uint32_t bank)
368 {
369 	if (bank == 0)
370 		return (sc->pmu);
371 	return (sc->grf);
372 }
373 
374 struct rk_pinctrl_conf rk3288_conf = {
375 	.iomux_conf = rk3288_iomux_bank,
376 	.iomux_nbanks = nitems(rk3288_iomux_bank),
377 	.pin_fixup = rk3288_pin_fixup,
378 	.npin_fixup = nitems(rk3288_pin_fixup),
379 	.pin_drive = rk3288_pin_drive,
380 	.npin_drive = nitems(rk3288_pin_drive),
381 	.gpio_bank = rk3288_gpio_bank,
382 	.ngpio_bank = nitems(rk3288_gpio_bank),
383 	.get_pd_offset = rk3288_get_pd_offset,
384 	.get_syscon = rk3288_get_syscon,
385 };
386 
387 static struct rk_pinctrl_gpio rk3328_gpio_bank[] = {
388 	RK_GPIO(0, "gpio0"),
389 	RK_GPIO(1, "gpio1"),
390 	RK_GPIO(2, "gpio2"),
391 	RK_GPIO(3, "gpio3"),
392 };
393 
394 static struct rk_pinctrl_bank rk3328_iomux_bank[] = {
395 	/*    bank sub offs nbits */
396 	RK_IOMUX(0, 0, 0x0000, 2),
397 	RK_IOMUX(0, 1, 0x0004, 2),
398 	RK_IOMUX(0, 2, 0x0008, 2),
399 	RK_IOMUX(0, 3, 0x000C, 2),
400 	RK_IOMUX(1, 0, 0x0010, 2),
401 	RK_IOMUX(1, 1, 0x0014, 2),
402 	RK_IOMUX(1, 2, 0x0018, 2),
403 	RK_IOMUX(1, 3, 0x001C, 2),
404 	RK_IOMUX(2, 0, 0x0020, 2),
405 	RK_IOMUX(2, 1, 0x0024, 3),
406 	RK_IOMUX(2, 2, 0x002c, 3),
407 	RK_IOMUX(2, 3, 0x0034, 2),
408 	RK_IOMUX(3, 0, 0x0038, 3),
409 	RK_IOMUX(3, 1, 0x0040, 3),
410 	RK_IOMUX(3, 2, 0x0048, 2),
411 	RK_IOMUX(3, 3, 0x004c, 2),
412 };
413 
414 static struct rk_pinctrl_pin_fixup rk3328_pin_fixup[] = {
415 	/*      bank  pin reg  bit  mask */
416 	RK_PINFIX(2, 12, 0x24,  8, 0x300),
417 	RK_PINFIX(2, 15, 0x28,  0, 0x7),
418 	RK_PINFIX(2, 23, 0x30, 14, 0x6000),
419 };
420 
421 
422 static struct rk_pinctrl_pin_drive rk3328_pin_drive[] = {
423 	/*       bank sub  offs val ma */
424 	RK_PINDRIVE(0, 0, 0x200, 0, 2),
425 	RK_PINDRIVE(0, 0, 0x200, 1, 4),
426 	RK_PINDRIVE(0, 0, 0x200, 2, 8),
427 	RK_PINDRIVE(0, 0, 0x200, 3, 12),
428 
429 	RK_PINDRIVE(0, 1, 0x204, 0, 2),
430 	RK_PINDRIVE(0, 1, 0x204, 1, 4),
431 	RK_PINDRIVE(0, 1, 0x204, 2, 8),
432 	RK_PINDRIVE(0, 1, 0x204, 3, 12),
433 
434 	RK_PINDRIVE(0, 2, 0x208, 0, 2),
435 	RK_PINDRIVE(0, 2, 0x208, 1, 4),
436 	RK_PINDRIVE(0, 2, 0x208, 2, 8),
437 	RK_PINDRIVE(0, 2, 0x208, 3, 12),
438 
439 	RK_PINDRIVE(0, 3, 0x20C, 0, 2),
440 	RK_PINDRIVE(0, 3, 0x20C, 1, 4),
441 	RK_PINDRIVE(0, 3, 0x20C, 2, 8),
442 	RK_PINDRIVE(0, 3, 0x20C, 3, 12),
443 
444 	RK_PINDRIVE(1, 0, 0x210, 0, 2),
445 	RK_PINDRIVE(1, 0, 0x210, 1, 4),
446 	RK_PINDRIVE(1, 0, 0x210, 2, 8),
447 	RK_PINDRIVE(1, 0, 0x210, 3, 12),
448 
449 	RK_PINDRIVE(1, 1, 0x214, 0, 2),
450 	RK_PINDRIVE(1, 1, 0x214, 1, 4),
451 	RK_PINDRIVE(1, 1, 0x214, 2, 8),
452 	RK_PINDRIVE(1, 1, 0x214, 3, 12),
453 
454 	RK_PINDRIVE(1, 2, 0x218, 0, 2),
455 	RK_PINDRIVE(1, 2, 0x218, 1, 4),
456 	RK_PINDRIVE(1, 2, 0x218, 2, 8),
457 	RK_PINDRIVE(1, 2, 0x218, 3, 12),
458 
459 	RK_PINDRIVE(1, 3, 0x21C, 0, 2),
460 	RK_PINDRIVE(1, 3, 0x21C, 1, 4),
461 	RK_PINDRIVE(1, 3, 0x21C, 2, 8),
462 	RK_PINDRIVE(1, 3, 0x21C, 3, 12),
463 
464 	RK_PINDRIVE(2, 0, 0x220, 0, 2),
465 	RK_PINDRIVE(2, 0, 0x220, 1, 4),
466 	RK_PINDRIVE(2, 0, 0x220, 2, 8),
467 	RK_PINDRIVE(2, 0, 0x220, 3, 12),
468 
469 	RK_PINDRIVE(2, 1, 0x224, 0, 2),
470 	RK_PINDRIVE(2, 1, 0x224, 1, 4),
471 	RK_PINDRIVE(2, 1, 0x224, 2, 8),
472 	RK_PINDRIVE(2, 1, 0x224, 3, 12),
473 
474 	RK_PINDRIVE(2, 2, 0x228, 0, 2),
475 	RK_PINDRIVE(2, 2, 0x228, 1, 4),
476 	RK_PINDRIVE(2, 2, 0x228, 2, 8),
477 	RK_PINDRIVE(2, 2, 0x228, 3, 12),
478 
479 	RK_PINDRIVE(2, 3, 0x22C, 0, 2),
480 	RK_PINDRIVE(2, 3, 0x22C, 1, 4),
481 	RK_PINDRIVE(2, 3, 0x22C, 2, 8),
482 	RK_PINDRIVE(2, 3, 0x22C, 3, 12),
483 
484 	RK_PINDRIVE(3, 0, 0x230, 0, 2),
485 	RK_PINDRIVE(3, 0, 0x230, 1, 4),
486 	RK_PINDRIVE(3, 0, 0x230, 2, 8),
487 	RK_PINDRIVE(3, 0, 0x230, 3, 12),
488 
489 	RK_PINDRIVE(3, 1, 0x234, 0, 2),
490 	RK_PINDRIVE(3, 1, 0x234, 1, 4),
491 	RK_PINDRIVE(3, 1, 0x234, 2, 8),
492 	RK_PINDRIVE(3, 1, 0x234, 3, 12),
493 
494 	RK_PINDRIVE(3, 2, 0x238, 0, 2),
495 	RK_PINDRIVE(3, 2, 0x238, 1, 4),
496 	RK_PINDRIVE(3, 2, 0x238, 2, 8),
497 	RK_PINDRIVE(3, 2, 0x238, 3, 12),
498 
499 	RK_PINDRIVE(3, 3, 0x23C, 0, 2),
500 	RK_PINDRIVE(3, 3, 0x23C, 1, 4),
501 	RK_PINDRIVE(3, 3, 0x23C, 2, 8),
502 	RK_PINDRIVE(3, 3, 0x23C, 3, 12),
503 };
504 
505 static uint32_t
506 rk3328_get_pd_offset(struct rk_pinctrl_softc *sc, uint32_t bank)
507 {
508 	return (0x100);
509 }
510 
511 static struct syscon *
512 rk3328_get_syscon(struct rk_pinctrl_softc *sc, uint32_t bank)
513 {
514 	return (sc->grf);
515 }
516 
517 struct rk_pinctrl_conf rk3328_conf = {
518 	.iomux_conf = rk3328_iomux_bank,
519 	.iomux_nbanks = nitems(rk3328_iomux_bank),
520 	.pin_fixup = rk3328_pin_fixup,
521 	.npin_fixup = nitems(rk3328_pin_fixup),
522 	.pin_drive = rk3328_pin_drive,
523 	.npin_drive = nitems(rk3328_pin_drive),
524 	.gpio_bank = rk3328_gpio_bank,
525 	.ngpio_bank = nitems(rk3328_gpio_bank),
526 	.get_pd_offset = rk3328_get_pd_offset,
527 	.get_syscon = rk3328_get_syscon,
528 };
529 
530 static struct rk_pinctrl_gpio rk3399_gpio_bank[] = {
531 	RK_GPIO(0, "gpio0"),
532 	RK_GPIO(1, "gpio1"),
533 	RK_GPIO(2, "gpio2"),
534 	RK_GPIO(3, "gpio3"),
535 	RK_GPIO(4, "gpio4"),
536 };
537 
538 static struct rk_pinctrl_bank rk3399_iomux_bank[] = {
539 	/*    bank sub  offs   nbits */
540 	RK_IOMUX(0, 0, 0x0000, 2),
541 	RK_IOMUX(0, 1, 0x0004, 2),
542 	RK_IOMUX(0, 2, 0x0008, 2),
543 	RK_IOMUX(0, 3, 0x000C, 2),
544 	RK_IOMUX(1, 0, 0x0010, 2),
545 	RK_IOMUX(1, 1, 0x0014, 2),
546 	RK_IOMUX(1, 2, 0x0018, 2),
547 	RK_IOMUX(1, 3, 0x001C, 2),
548 	RK_IOMUX(2, 0, 0xE000, 2),
549 	RK_IOMUX(2, 1, 0xE004, 2),
550 	RK_IOMUX(2, 2, 0xE008, 2),
551 	RK_IOMUX(2, 3, 0xE00C, 2),
552 	RK_IOMUX(3, 0, 0xE010, 2),
553 	RK_IOMUX(3, 1, 0xE014, 2),
554 	RK_IOMUX(3, 2, 0xE018, 2),
555 	RK_IOMUX(3, 3, 0xE01C, 2),
556 	RK_IOMUX(4, 0, 0xE020, 2),
557 	RK_IOMUX(4, 1, 0xE024, 2),
558 	RK_IOMUX(4, 2, 0xE028, 2),
559 	RK_IOMUX(4, 3, 0xE02C, 2),
560 };
561 
562 static struct rk_pinctrl_pin_fixup rk3399_pin_fixup[] = {};
563 
564 static struct rk_pinctrl_pin_drive rk3399_pin_drive[] = {
565 	/*       bank sub offs val ma */
566 	/* GPIO0A */
567 	RK_PINDRIVE(0, 0, 0x80, 0, 5),
568 	RK_PINDRIVE(0, 0, 0x80, 1, 10),
569 	RK_PINDRIVE(0, 0, 0x80, 2, 15),
570 	RK_PINDRIVE(0, 0, 0x80, 3, 20),
571 
572 	/* GPIOB */
573 	RK_PINDRIVE(0, 1, 0x88, 0, 5),
574 	RK_PINDRIVE(0, 1, 0x88, 1, 10),
575 	RK_PINDRIVE(0, 1, 0x88, 2, 15),
576 	RK_PINDRIVE(0, 1, 0x88, 3, 20),
577 
578 	/* GPIO1A */
579 	RK_PINDRIVE(1, 0, 0xA0, 0, 3),
580 	RK_PINDRIVE(1, 0, 0xA0, 1, 6),
581 	RK_PINDRIVE(1, 0, 0xA0, 2, 9),
582 	RK_PINDRIVE(1, 0, 0xA0, 3, 12),
583 
584 	/* GPIO1B */
585 	RK_PINDRIVE(1, 1, 0xA8, 0, 3),
586 	RK_PINDRIVE(1, 1, 0xA8, 1, 6),
587 	RK_PINDRIVE(1, 1, 0xA8, 2, 9),
588 	RK_PINDRIVE(1, 1, 0xA8, 3, 12),
589 
590 	/* GPIO1C */
591 	RK_PINDRIVE(1, 2, 0xB0, 0, 3),
592 	RK_PINDRIVE(1, 2, 0xB0, 1, 6),
593 	RK_PINDRIVE(1, 2, 0xB0, 2, 9),
594 	RK_PINDRIVE(1, 2, 0xB0, 3, 12),
595 
596 	/* GPIO1D */
597 	RK_PINDRIVE(1, 3, 0xB8, 0, 3),
598 	RK_PINDRIVE(1, 3, 0xB8, 1, 6),
599 	RK_PINDRIVE(1, 3, 0xB8, 2, 9),
600 	RK_PINDRIVE(1, 3, 0xB8, 3, 12),
601 };
602 
603 static uint32_t
604 rk3399_get_pd_offset(struct rk_pinctrl_softc *sc, uint32_t bank)
605 {
606 	if (bank < 2)
607 		return (0x40);
608 
609 	return (0xE040);
610 }
611 
612 static struct syscon *
613 rk3399_get_syscon(struct rk_pinctrl_softc *sc, uint32_t bank)
614 {
615 	if (bank < 2)
616 		return (sc->pmu);
617 
618 	return (sc->grf);
619 }
620 
621 struct rk_pinctrl_conf rk3399_conf = {
622 	.iomux_conf = rk3399_iomux_bank,
623 	.iomux_nbanks = nitems(rk3399_iomux_bank),
624 	.pin_fixup = rk3399_pin_fixup,
625 	.npin_fixup = nitems(rk3399_pin_fixup),
626 	.pin_drive = rk3399_pin_drive,
627 	.npin_drive = nitems(rk3399_pin_drive),
628 	.gpio_bank = rk3399_gpio_bank,
629 	.ngpio_bank = nitems(rk3399_gpio_bank),
630 	.get_pd_offset = rk3399_get_pd_offset,
631 	.get_syscon = rk3399_get_syscon,
632 };
633 
634 static struct ofw_compat_data compat_data[] = {
635 	{"rockchip,rk3288-pinctrl", (uintptr_t)&rk3288_conf},
636 	{"rockchip,rk3328-pinctrl", (uintptr_t)&rk3328_conf},
637 	{"rockchip,rk3399-pinctrl", (uintptr_t)&rk3399_conf},
638 	{NULL,             0}
639 };
640 
641 static int
642 rk_pinctrl_parse_bias(phandle_t node)
643 {
644 	if (OF_hasprop(node, "bias-disable"))
645 		return (0);
646 	if (OF_hasprop(node, "bias-pull-up"))
647 		return (1);
648 	if (OF_hasprop(node, "bias-pull-down"))
649 		return (2);
650 
651 	return (-1);
652 }
653 
654 static int
655 rk_pinctrl_parse_drive(struct rk_pinctrl_softc *sc, phandle_t node,
656   uint32_t bank, uint32_t subbank, uint32_t *drive, uint32_t *offset)
657 {
658 	uint32_t value;
659 	int i;
660 
661 	if (OF_getencprop(node, "drive-strength", &value,
662 	    sizeof(value)) != 0)
663 		return (-1);
664 
665 	/* Map to the correct drive value */
666 	for (i = 0; i < sc->conf->npin_drive; i++) {
667 		if (sc->conf->pin_drive[i].bank != bank &&
668 		    sc->conf->pin_drive[i].subbank != subbank)
669 			continue;
670 		if (sc->conf->pin_drive[i].ma == value) {
671 			*drive = sc->conf->pin_drive[i].value;
672 			return (0);
673 		}
674 	}
675 
676 	return (-1);
677 }
678 
679 static void
680 rk_pinctrl_get_fixup(struct rk_pinctrl_softc *sc, uint32_t bank, uint32_t pin,
681     uint32_t *reg, uint32_t *mask, uint32_t *bit)
682 {
683 	int i;
684 
685 	for (i = 0; i < sc->conf->npin_fixup; i++)
686 		if (sc->conf->pin_fixup[i].bank == bank &&
687 		    sc->conf->pin_fixup[i].pin == pin) {
688 			*reg = sc->conf->pin_fixup[i].reg;
689 			*mask = sc->conf->pin_fixup[i].mask;
690 			*bit = sc->conf->pin_fixup[i].bit;
691 
692 			return;
693 		}
694 }
695 
696 static int
697 rk_pinctrl_handle_io(struct rk_pinctrl_softc *sc, phandle_t node, uint32_t bank,
698 uint32_t pin)
699 {
700 	bool have_cfg, have_direction, have_value;
701 	uint32_t  direction_value, pin_value;
702 	struct rk_pinctrl_gpio *gpio;
703 	int i, rv;
704 
705 	have_cfg = false;
706 	have_direction = false;
707 	have_value = false;
708 
709 	/* Get (subset of) GPIO pin properties. */
710 	if (OF_hasprop(node, "output-disable")) {
711 		have_cfg = true;
712 		have_direction = true;
713 		direction_value = GPIO_PIN_INPUT;
714 	}
715 
716 	if (OF_hasprop(node, "output-enable")) {
717 		have_cfg = true;
718 		have_direction = true;
719 		direction_value = GPIO_PIN_OUTPUT;
720 	}
721 
722 	if (OF_hasprop(node, "output-low")) {
723 		have_cfg = true;
724 		have_direction = true;
725 		direction_value = GPIO_PIN_OUTPUT;
726 		have_value = true;
727 		pin_value = 0;
728 	}
729 
730 	if (OF_hasprop(node, "output-high")) {
731 		have_cfg = true;
732 		have_direction = true;
733 		direction_value = GPIO_PIN_OUTPUT;
734 		have_value = true;
735 		pin_value = 1;
736 	}
737 
738 	if (!have_cfg)
739 		return (0);
740 
741 	/* Find gpio */
742 	gpio = NULL;
743 	for(i = 0; i < sc->conf->ngpio_bank; i++) {
744 		if (bank ==  sc->conf->gpio_bank[i].bank) {
745 			gpio = sc->conf->gpio_bank + i;
746 			break;
747 		}
748 	}
749 	if (gpio == NULL) {
750 		device_printf(sc->dev, "Cannot find GPIO bank %d\n", bank);
751 		return (ENXIO);
752 	}
753 	if (gpio->gpio_dev == NULL) {
754 		device_printf(sc->dev,
755 		    "No GPIO subdevice found for bank %d\n", bank);
756 		return (ENXIO);
757 	}
758 
759 	rv = 0;
760 	if (have_value) {
761 		rv = GPIO_PIN_SET(gpio->gpio_dev, pin, pin_value);
762 		if (rv != 0) {
763 			device_printf(sc->dev, "Cannot set GPIO value: %d\n",
764 			    rv);
765 			return (rv);
766 		}
767 	}
768 
769 	if (have_direction) {
770 		rv = GPIO_PIN_SETFLAGS(gpio->gpio_dev, pin, direction_value);
771 		if (rv != 0) {
772 			device_printf(sc->dev,
773 			    "Cannot set GPIO direction: %d\n", rv);
774 			return (rv);
775 		}
776 	}
777 
778 	return (0);
779 }
780 
781 static void
782 rk_pinctrl_configure_pin(struct rk_pinctrl_softc *sc, uint32_t *pindata)
783 {
784 	phandle_t pin_conf;
785 	struct syscon *syscon;
786 	uint32_t bank, subbank, pin, function, bias;
787 	uint32_t bit, mask, reg, drive;
788 	int i, rv;
789 
790 	bank = pindata[0];
791 	pin = pindata[1];
792 	function = pindata[2];
793 	pin_conf = OF_node_from_xref(pindata[3]);
794 	subbank = pin / 8;
795 
796 	for (i = 0; i < sc->conf->iomux_nbanks; i++)
797 		if (sc->conf->iomux_conf[i].bank == bank &&
798 		    sc->conf->iomux_conf[i].subbank == subbank)
799 			break;
800 
801 	if (i == sc->conf->iomux_nbanks) {
802 		device_printf(sc->dev, "Unknown pin %d in bank %d\n", pin,
803 		    bank);
804 		return;
805 	}
806 
807 	/* Find syscon */
808 	syscon = sc->conf->get_syscon(sc, bank);
809 
810 	/* Parse pin function */
811 	reg = sc->conf->iomux_conf[i].offset;
812 	switch (sc->conf->iomux_conf[i].nbits) {
813 	case 4:
814 		if ((pin % 8) >= 4)
815 			reg += 0x4;
816 		bit = (pin % 4) * 4;
817 		mask = (0xF << bit);
818 		break;
819 	case 3:
820 		if ((pin % 8) >= 5)
821 			reg += 4;
822 		bit = (pin % 8 % 5) * 3;
823 		mask = (0x7 << bit);
824 		break;
825 	case 2:
826 		bit = (pin % 8) * 2;
827 		mask = (0x3 << bit);
828 		break;
829 	default:
830 		device_printf(sc->dev,
831 		    "Unknown pin stride width %d in bank %d\n",
832 		    sc->conf->iomux_conf[i].nbits, bank);
833 		return;
834 	}
835 	rk_pinctrl_get_fixup(sc, bank, pin, &reg, &mask, &bit);
836 
837 	/*
838 	 * NOTE: not all syscon registers uses hi-word write mask, thus
839 	 * register modify method should be used.
840 	 * XXXX We should not pass write mask to syscon register
841 	 * without hi-word write mask.
842 	 */
843 	SYSCON_MODIFY_4(syscon, reg, mask, function << bit | (mask << 16));
844 
845 	/* Pull-Up/Down */
846 	bias = rk_pinctrl_parse_bias(pin_conf);
847 	if (bias >= 0) {
848 		reg = sc->conf->get_pd_offset(sc, bank);
849 
850 		reg += bank * 0x10 + ((pin / 8) * 0x4);
851 		bit = (pin % 8) * 2;
852 		mask = (0x3 << bit) << 16;
853 		SYSCON_MODIFY_4(syscon, reg, mask, bias << bit | (mask << 16));
854 	}
855 
856 	/* Drive Strength */
857 	rv = rk_pinctrl_parse_drive(sc, pin_conf, bank, subbank, &drive, &reg);
858 	if (rv == 0) {
859 		bit = (pin % 8) * 2;
860 		mask = (0x3 << bit) << 16;
861 		SYSCON_MODIFY_4(syscon, reg, mask, drive << bit | (mask << 16));
862 	}
863 
864 	/* Input/Outpot + default level */
865 	rv = rk_pinctrl_handle_io(sc, pin_conf, bank, pin);
866 }
867 
868 static int
869 rk_pinctrl_configure_pins(device_t dev, phandle_t cfgxref)
870 {
871 	struct rk_pinctrl_softc *sc;
872 	phandle_t node;
873 	uint32_t *pins;
874 	int i, npins;
875 
876 	sc = device_get_softc(dev);
877 	node = OF_node_from_xref(cfgxref);
878 
879 	npins = OF_getencprop_alloc_multi(node, "rockchip,pins",  sizeof(*pins),
880 	    (void **)&pins);
881 	if (npins <= 0)
882 		return (ENOENT);
883 
884 	for (i = 0; i != npins; i += 4)
885 		rk_pinctrl_configure_pin(sc, pins + i);
886 
887 	return (0);
888 }
889 
890 
891 static int
892 rk_pinctrl_register_gpio(struct rk_pinctrl_softc *sc, char *gpio_name,
893     device_t gpio_dev)
894 {
895 	int i;
896 
897 	for(i = 0; i < sc->conf->ngpio_bank; i++) {
898 		if (strcmp(gpio_name, sc->conf->gpio_bank[i].gpio_name) != 0)
899 			continue;
900 		sc->conf->gpio_bank[i].gpio_dev = gpio_dev;
901 		return(0);
902 	}
903 	return (ENXIO);
904 }
905 
906 static int
907 rk_pinctrl_probe(device_t dev)
908 {
909 
910 	if (!ofw_bus_status_okay(dev))
911 		return (ENXIO);
912 
913 	if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
914 		return (ENXIO);
915 
916 	device_set_desc(dev, "RockChip Pinctrl controller");
917 	return (BUS_PROBE_DEFAULT);
918 }
919 
920 static int
921 rk_pinctrl_attach(device_t dev)
922 {
923 	struct rk_pinctrl_softc *sc;
924 	phandle_t node;
925 	device_t cdev;
926 	char *gpio_name, *eptr;
927 	int rv;
928 
929 	sc = device_get_softc(dev);
930 	sc->dev = dev;
931 
932 	node = ofw_bus_get_node(dev);
933 
934 	if (OF_hasprop(node, "rockchip,grf") &&
935 	    syscon_get_by_ofw_property(dev, node,
936 	    "rockchip,grf", &sc->grf) != 0) {
937 		device_printf(dev, "cannot get grf driver handle\n");
938 		return (ENXIO);
939 	}
940 
941 	/* RK3399,RK3288 has banks in PMU. RK3328 does not have a PMU. */
942 	if (ofw_bus_node_is_compatible(node, "rockchip,rk3399-pinctrl") ||
943 	    ofw_bus_node_is_compatible(node, "rockchip,rk3288-pinctrl")) {
944 		if (OF_hasprop(node, "rockchip,pmu") &&
945 		    syscon_get_by_ofw_property(dev, node,
946 		    "rockchip,pmu", &sc->pmu) != 0) {
947 			device_printf(dev, "cannot get pmu driver handle\n");
948 			return (ENXIO);
949 		}
950 	}
951 
952 	sc->conf = (struct rk_pinctrl_conf *)ofw_bus_search_compatible(dev,
953 	    compat_data)->ocd_data;
954 
955 	fdt_pinctrl_register(dev, "rockchip,pins");
956 
957 	simplebus_init(dev, node);
958 
959 	bus_generic_probe(dev);
960 
961 	/* Attach child devices */
962 	for (node = OF_child(node); node > 0; node = OF_peer(node)) {
963 		if (!ofw_bus_node_is_compatible(node, "rockchip,gpio-bank"))
964 			continue;
965 
966 		rv = OF_getprop_alloc(node, "name", (void **)&gpio_name);
967 		if (rv <= 0) {
968 			device_printf(sc->dev, "Cannot GPIO subdevice name.\n");
969 			continue;
970 		}
971 
972 		cdev = simplebus_add_device(dev, node, 0, NULL, -1, NULL);
973 		if (cdev == NULL) {
974 			device_printf(dev, " Cannot add GPIO subdevice: %s\n",
975 			    gpio_name);
976 			OF_prop_free(gpio_name);
977 			continue;
978 		}
979 
980 		rv = device_probe_and_attach(cdev);
981 		if (rv != 0) {
982 			device_printf(sc->dev,
983 			    "Cannot attach GPIO subdevice: %s\n", gpio_name);
984 			OF_prop_free(gpio_name);
985 			continue;
986 		}
987 
988 		/* Grep device name from name property */
989 		eptr = gpio_name;
990 		strsep(&eptr, "@");
991 		if (gpio_name == eptr) {
992 			device_printf(sc->dev,
993 			    "Unrecognized format of GPIO subdevice name: %s\n",
994 			    gpio_name);
995 			OF_prop_free(gpio_name);
996 			continue;
997 		}
998 		rv =  rk_pinctrl_register_gpio(sc, gpio_name, cdev);
999 		if (rv != 0) {
1000 			device_printf(sc->dev,
1001 			    "Cannot register GPIO subdevice %s: %d\n",
1002 			    gpio_name, rv);
1003 			OF_prop_free(gpio_name);
1004 			continue;
1005 		}
1006 		OF_prop_free(gpio_name);
1007 	}
1008 
1009 	fdt_pinctrl_configure_tree(dev);
1010 
1011 	return (bus_generic_attach(dev));
1012 }
1013 
1014 static int
1015 rk_pinctrl_detach(device_t dev)
1016 {
1017 
1018 	return (EBUSY);
1019 }
1020 
1021 static device_method_t rk_pinctrl_methods[] = {
1022 	/* Device interface */
1023 	DEVMETHOD(device_probe,			rk_pinctrl_probe),
1024 	DEVMETHOD(device_attach,		rk_pinctrl_attach),
1025 	DEVMETHOD(device_detach,		rk_pinctrl_detach),
1026 
1027         /* fdt_pinctrl interface */
1028 	DEVMETHOD(fdt_pinctrl_configure,	rk_pinctrl_configure_pins),
1029 
1030 	DEVMETHOD_END
1031 };
1032 
1033 static devclass_t rk_pinctrl_devclass;
1034 
1035 DEFINE_CLASS_1(rk_pinctrl, rk_pinctrl_driver, rk_pinctrl_methods,
1036     sizeof(struct rk_pinctrl_softc), simplebus_driver);
1037 
1038 EARLY_DRIVER_MODULE(rk_pinctrl, simplebus, rk_pinctrl_driver,
1039     rk_pinctrl_devclass, 0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE);
1040 MODULE_VERSION(rk_pinctrl, 1);
1041