1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2018 Emmanuel Vadot <manu@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 */ 28 29 #include <sys/cdefs.h> 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/bus.h> 33 34 #include <sys/gpio.h> 35 #include <sys/kernel.h> 36 #include <sys/lock.h> 37 #include <sys/module.h> 38 #include <sys/mutex.h> 39 #include <sys/rman.h> 40 41 #include <machine/bus.h> 42 #include <machine/resource.h> 43 #include <machine/intr.h> 44 45 #include <dev/fdt/simplebus.h> 46 47 #include <dev/ofw/ofw_bus.h> 48 #include <dev/ofw/ofw_bus_subr.h> 49 50 #include <dev/fdt/fdt_pinctrl.h> 51 52 #include <dev/extres/syscon/syscon.h> 53 54 #include "gpio_if.h" 55 #include "syscon_if.h" 56 #include "fdt_pinctrl_if.h" 57 58 struct rk_pinctrl_pin_drive { 59 uint32_t bank; 60 uint32_t subbank; 61 uint32_t offset; 62 uint32_t value; 63 uint32_t ma; 64 }; 65 66 struct rk_pinctrl_bank { 67 uint32_t bank; 68 uint32_t subbank; 69 uint32_t offset; 70 uint32_t nbits; 71 }; 72 73 struct rk_pinctrl_pin_fixup { 74 uint32_t bank; 75 uint32_t subbank; 76 uint32_t pin; 77 uint32_t reg; 78 uint32_t bit; 79 uint32_t mask; 80 }; 81 82 struct rk_pinctrl_gpio { 83 uint32_t bank; 84 char *gpio_name; 85 device_t gpio_dev; 86 }; 87 88 struct rk_pinctrl_softc; 89 90 struct rk_pinctrl_conf { 91 struct rk_pinctrl_bank *iomux_conf; 92 uint32_t iomux_nbanks; 93 struct rk_pinctrl_pin_fixup *pin_fixup; 94 uint32_t npin_fixup; 95 struct rk_pinctrl_pin_drive *pin_drive; 96 uint32_t npin_drive; 97 struct rk_pinctrl_gpio *gpio_bank; 98 uint32_t ngpio_bank; 99 uint32_t (*get_pd_offset)(struct rk_pinctrl_softc *, uint32_t); 100 struct syscon *(*get_syscon)(struct rk_pinctrl_softc *, uint32_t); 101 int (*parse_bias)(phandle_t, int); 102 int (*resolv_bias_value)(int, int); 103 int (*get_bias_value)(int, int); 104 }; 105 106 struct rk_pinctrl_softc { 107 struct simplebus_softc simplebus_sc; 108 device_t dev; 109 struct syscon *grf; 110 struct syscon *pmu; 111 struct rk_pinctrl_conf *conf; 112 struct mtx mtx; 113 }; 114 115 #define RK_PINCTRL_LOCK(_sc) mtx_lock_spin(&(_sc)->mtx) 116 #define RK_PINCTRL_UNLOCK(_sc) mtx_unlock_spin(&(_sc)->mtx) 117 #define RK_PINCTRL_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->mtx, MA_OWNED) 118 119 #define RK_IOMUX(_bank, _subbank, _offset, _nbits) \ 120 { \ 121 .bank = _bank, \ 122 .subbank = _subbank, \ 123 .offset = _offset, \ 124 .nbits = _nbits, \ 125 } 126 127 #define RK_PINFIX(_bank, _pin, _reg, _bit, _mask) \ 128 { \ 129 .bank = _bank, \ 130 .pin = _pin, \ 131 .reg = _reg, \ 132 .bit = _bit, \ 133 .mask = _mask, \ 134 } 135 136 #define RK_PINDRIVE(_bank, _subbank, _offset, _value, _ma) \ 137 { \ 138 .bank = _bank, \ 139 .subbank = _subbank, \ 140 .offset = _offset, \ 141 .value = _value, \ 142 .ma = _ma, \ 143 } 144 #define RK_GPIO(_bank, _name) \ 145 { \ 146 .bank = _bank, \ 147 .gpio_name = _name, \ 148 } 149 150 static struct rk_pinctrl_gpio rk3288_gpio_bank[] = { 151 RK_GPIO(0, "gpio0"), 152 RK_GPIO(1, "gpio1"), 153 RK_GPIO(2, "gpio2"), 154 RK_GPIO(3, "gpio3"), 155 RK_GPIO(4, "gpio4"), 156 RK_GPIO(5, "gpio5"), 157 RK_GPIO(6, "gpio6"), 158 RK_GPIO(7, "gpio7"), 159 RK_GPIO(8, "gpio8"), 160 }; 161 162 static struct rk_pinctrl_bank rk3288_iomux_bank[] = { 163 /* bank sub offs nbits */ 164 /* PMU */ 165 RK_IOMUX(0, 0, 0x0084, 2), 166 RK_IOMUX(0, 1, 0x0088, 2), 167 RK_IOMUX(0, 2, 0x008C, 2), 168 /* GFR */ 169 RK_IOMUX(1, 3, 0x000C, 2), 170 RK_IOMUX(2, 0, 0x0010, 2), 171 RK_IOMUX(2, 1, 0x0014, 2), 172 RK_IOMUX(2, 2, 0x0018, 2), 173 RK_IOMUX(2, 3, 0x001C, 2), 174 RK_IOMUX(3, 0, 0x0020, 2), 175 RK_IOMUX(3, 1, 0x0024, 2), 176 RK_IOMUX(3, 2, 0x0028, 2), 177 RK_IOMUX(3, 3, 0x002C, 4), 178 RK_IOMUX(4, 0, 0x0034, 4), 179 RK_IOMUX(4, 1, 0x003C, 4), 180 RK_IOMUX(4, 2, 0x0044, 2), 181 RK_IOMUX(4, 3, 0x0048, 2), 182 /* 5,0 - Empty */ 183 RK_IOMUX(5, 1, 0x0050, 2), 184 RK_IOMUX(5, 2, 0x0054, 2), 185 /* 5,3 - Empty */ 186 RK_IOMUX(6, 0, 0x005C, 2), 187 RK_IOMUX(6, 1, 0x0060, 2), 188 RK_IOMUX(6, 2, 0x0064, 2), 189 /* 6,3 - Empty */ 190 RK_IOMUX(7, 0, 0x006C, 2), 191 RK_IOMUX(7, 1, 0x0070, 2), 192 RK_IOMUX(7, 2, 0x0074, 4), 193 /* 7,3 - Empty */ 194 RK_IOMUX(8, 0, 0x0080, 2), 195 RK_IOMUX(8, 1, 0x0084, 2), 196 /* 8,2 - Empty */ 197 /* 8,3 - Empty */ 198 199 }; 200 201 static struct rk_pinctrl_pin_fixup rk3288_pin_fixup[] = { 202 }; 203 204 static struct rk_pinctrl_pin_drive rk3288_pin_drive[] = { 205 /* bank sub offs val ma */ 206 /* GPIO0A (PMU)*/ 207 RK_PINDRIVE(0, 0, 0x070, 0, 2), 208 RK_PINDRIVE(0, 0, 0x070, 1, 4), 209 RK_PINDRIVE(0, 0, 0x070, 2, 8), 210 RK_PINDRIVE(0, 0, 0x070, 3, 12), 211 212 /* GPIO0B (PMU)*/ 213 RK_PINDRIVE(0, 1, 0x074, 0, 2), 214 RK_PINDRIVE(0, 1, 0x074, 1, 4), 215 RK_PINDRIVE(0, 1, 0x074, 2, 8), 216 RK_PINDRIVE(0, 1, 0x074, 3, 12), 217 218 /* GPIO0C (PMU)*/ 219 RK_PINDRIVE(0, 2, 0x078, 0, 2), 220 RK_PINDRIVE(0, 2, 0x078, 1, 4), 221 RK_PINDRIVE(0, 2, 0x078, 2, 8), 222 RK_PINDRIVE(0, 2, 0x078, 3, 12), 223 224 /* GPIO1D */ 225 RK_PINDRIVE(1, 3, 0x1CC, 0, 2), 226 RK_PINDRIVE(1, 3, 0x1CC, 1, 4), 227 RK_PINDRIVE(1, 3, 0x1CC, 2, 8), 228 RK_PINDRIVE(1, 3, 0x1CC, 3, 12), 229 230 /* GPIO2A */ 231 RK_PINDRIVE(2, 0, 0x1D0, 0, 2), 232 RK_PINDRIVE(2, 0, 0x1D0, 1, 4), 233 RK_PINDRIVE(2, 0, 0x1D0, 2, 8), 234 RK_PINDRIVE(2, 0, 0x1D0, 3, 12), 235 236 /* GPIO2B */ 237 RK_PINDRIVE(2, 1, 0x1D4, 0, 2), 238 RK_PINDRIVE(2, 1, 0x1D4, 1, 4), 239 RK_PINDRIVE(2, 1, 0x1D4, 2, 8), 240 RK_PINDRIVE(2, 1, 0x1D4, 3, 12), 241 242 /* GPIO2C */ 243 RK_PINDRIVE(2, 2, 0x1D8, 0, 2), 244 RK_PINDRIVE(2, 2, 0x1D8, 1, 4), 245 RK_PINDRIVE(2, 2, 0x1D8, 2, 8), 246 RK_PINDRIVE(2, 2, 0x1D8, 3, 12), 247 248 /* GPIO2D */ 249 RK_PINDRIVE(2, 3, 0x1DC, 0, 2), 250 RK_PINDRIVE(2, 3, 0x1DC, 1, 4), 251 RK_PINDRIVE(2, 3, 0x1DC, 2, 8), 252 RK_PINDRIVE(2, 3, 0x1DC, 3, 12), 253 254 /* GPIO3A */ 255 RK_PINDRIVE(3, 0, 0x1E0, 0, 2), 256 RK_PINDRIVE(3, 0, 0x1E0, 1, 4), 257 RK_PINDRIVE(3, 0, 0x1E0, 2, 8), 258 RK_PINDRIVE(3, 0, 0x1E0, 3, 12), 259 260 /* GPIO3B */ 261 RK_PINDRIVE(3, 1, 0x1E4, 0, 2), 262 RK_PINDRIVE(3, 1, 0x1E4, 1, 4), 263 RK_PINDRIVE(3, 1, 0x1E4, 2, 8), 264 RK_PINDRIVE(3, 1, 0x1E4, 3, 12), 265 266 /* GPIO3C */ 267 RK_PINDRIVE(3, 2, 0x1E8, 0, 2), 268 RK_PINDRIVE(3, 2, 0x1E8, 1, 4), 269 RK_PINDRIVE(3, 2, 0x1E8, 2, 8), 270 RK_PINDRIVE(3, 2, 0x1E8, 3, 12), 271 272 /* GPIO3D */ 273 RK_PINDRIVE(3, 3, 0x1EC, 0, 2), 274 RK_PINDRIVE(3, 3, 0x1EC, 1, 4), 275 RK_PINDRIVE(3, 3, 0x1EC, 2, 8), 276 RK_PINDRIVE(3, 3, 0x1EC, 3, 12), 277 278 /* GPIO4A */ 279 RK_PINDRIVE(4, 0, 0x1F0, 0, 2), 280 RK_PINDRIVE(4, 0, 0x1F0, 1, 4), 281 RK_PINDRIVE(4, 0, 0x1F0, 2, 8), 282 RK_PINDRIVE(4, 0, 0x1F0, 3, 12), 283 284 /* GPIO4B */ 285 RK_PINDRIVE(4, 1, 0x1F4, 0, 2), 286 RK_PINDRIVE(4, 1, 0x1F4, 1, 4), 287 RK_PINDRIVE(4, 1, 0x1F4, 2, 8), 288 RK_PINDRIVE(4, 1, 0x1F4, 3, 12), 289 290 /* GPIO4C */ 291 RK_PINDRIVE(4, 2, 0x1F8, 0, 2), 292 RK_PINDRIVE(4, 2, 0x1F8, 1, 4), 293 RK_PINDRIVE(4, 2, 0x1F8, 2, 8), 294 RK_PINDRIVE(4, 2, 0x1F8, 3, 12), 295 296 /* GPIO4D */ 297 RK_PINDRIVE(4, 3, 0x1FC, 0, 2), 298 RK_PINDRIVE(4, 3, 0x1FC, 1, 4), 299 RK_PINDRIVE(4, 3, 0x1FC, 2, 8), 300 RK_PINDRIVE(4, 3, 0x1FC, 3, 12), 301 302 /* GPIO5B */ 303 RK_PINDRIVE(5, 1, 0x204, 0, 2), 304 RK_PINDRIVE(5, 1, 0x204, 1, 4), 305 RK_PINDRIVE(5, 1, 0x204, 2, 8), 306 RK_PINDRIVE(5, 1, 0x204, 3, 12), 307 308 /* GPIO5C */ 309 RK_PINDRIVE(5, 2, 0x208, 0, 2), 310 RK_PINDRIVE(5, 2, 0x208, 1, 4), 311 RK_PINDRIVE(5, 2, 0x208, 2, 8), 312 RK_PINDRIVE(5, 2, 0x208, 3, 12), 313 314 /* GPIO6A */ 315 RK_PINDRIVE(6, 0, 0x210, 0, 2), 316 RK_PINDRIVE(6, 0, 0x210, 1, 4), 317 RK_PINDRIVE(6, 0, 0x210, 2, 8), 318 RK_PINDRIVE(6, 0, 0x210, 3, 12), 319 320 /* GPIO6B */ 321 RK_PINDRIVE(6, 1, 0x214, 0, 2), 322 RK_PINDRIVE(6, 1, 0x214, 1, 4), 323 RK_PINDRIVE(6, 1, 0x214, 2, 8), 324 RK_PINDRIVE(6, 1, 0x214, 3, 12), 325 326 /* GPIO6C */ 327 RK_PINDRIVE(6, 2, 0x218, 0, 2), 328 RK_PINDRIVE(6, 2, 0x218, 1, 4), 329 RK_PINDRIVE(6, 2, 0x218, 2, 8), 330 RK_PINDRIVE(6, 2, 0x218, 3, 12), 331 332 /* GPIO7A */ 333 RK_PINDRIVE(7, 0, 0x220, 0, 2), 334 RK_PINDRIVE(7, 0, 0x220, 1, 4), 335 RK_PINDRIVE(7, 0, 0x220, 2, 8), 336 RK_PINDRIVE(7, 0, 0x220, 3, 12), 337 338 /* GPIO7B */ 339 RK_PINDRIVE(7, 1, 0x224, 0, 2), 340 RK_PINDRIVE(7, 1, 0x224, 1, 4), 341 RK_PINDRIVE(7, 1, 0x224, 2, 8), 342 RK_PINDRIVE(7, 1, 0x224, 3, 12), 343 344 /* GPIO7C */ 345 RK_PINDRIVE(7, 2, 0x228, 0, 2), 346 RK_PINDRIVE(7, 2, 0x228, 1, 4), 347 RK_PINDRIVE(7, 2, 0x228, 2, 8), 348 RK_PINDRIVE(7, 2, 0x228, 3, 12), 349 350 /* GPIO8A */ 351 RK_PINDRIVE(8, 0, 0x230, 0, 2), 352 RK_PINDRIVE(8, 0, 0x230, 1, 4), 353 RK_PINDRIVE(8, 0, 0x230, 2, 8), 354 RK_PINDRIVE(8, 0, 0x230, 3, 12), 355 356 /* GPIO8B */ 357 RK_PINDRIVE(8, 1, 0x234, 0, 2), 358 RK_PINDRIVE(8, 1, 0x234, 1, 4), 359 RK_PINDRIVE(8, 1, 0x234, 2, 8), 360 RK_PINDRIVE(8, 1, 0x234, 3, 12), 361 }; 362 363 static uint32_t 364 rk3288_get_pd_offset(struct rk_pinctrl_softc *sc, uint32_t bank) 365 { 366 if (bank == 0) 367 return (0x064); /* PMU */ 368 return (0x130); 369 } 370 371 static struct syscon * 372 rk3288_get_syscon(struct rk_pinctrl_softc *sc, uint32_t bank) 373 { 374 if (bank == 0) 375 return (sc->pmu); 376 return (sc->grf); 377 } 378 379 static int 380 rk3288_parse_bias(phandle_t node, int bank) 381 { 382 if (OF_hasprop(node, "bias-disable")) 383 return (0); 384 if (OF_hasprop(node, "bias-pull-up")) 385 return (1); 386 if (OF_hasprop(node, "bias-pull-down")) 387 return (2); 388 389 return (-1); 390 } 391 392 static int 393 rk3288_resolv_bias_value(int bank, int bias) 394 { 395 int rv = 0; 396 397 if (bias == 1) 398 rv = GPIO_PIN_PULLUP; 399 else if (bias == 2) 400 rv = GPIO_PIN_PULLDOWN; 401 402 return (rv); 403 } 404 405 static int 406 rk3288_get_bias_value(int bank, int bias) 407 { 408 int rv = 0; 409 410 if (bias & GPIO_PIN_PULLUP) 411 rv = 1; 412 else if (bias & GPIO_PIN_PULLDOWN) 413 rv = 2; 414 415 return (rv); 416 } 417 418 struct rk_pinctrl_conf rk3288_conf = { 419 .iomux_conf = rk3288_iomux_bank, 420 .iomux_nbanks = nitems(rk3288_iomux_bank), 421 .pin_fixup = rk3288_pin_fixup, 422 .npin_fixup = nitems(rk3288_pin_fixup), 423 .pin_drive = rk3288_pin_drive, 424 .npin_drive = nitems(rk3288_pin_drive), 425 .gpio_bank = rk3288_gpio_bank, 426 .ngpio_bank = nitems(rk3288_gpio_bank), 427 .get_pd_offset = rk3288_get_pd_offset, 428 .get_syscon = rk3288_get_syscon, 429 .parse_bias = rk3288_parse_bias, 430 .resolv_bias_value = rk3288_resolv_bias_value, 431 .get_bias_value = rk3288_get_bias_value, 432 }; 433 434 static struct rk_pinctrl_gpio rk3328_gpio_bank[] = { 435 RK_GPIO(0, "gpio0"), 436 RK_GPIO(1, "gpio1"), 437 RK_GPIO(2, "gpio2"), 438 RK_GPIO(3, "gpio3"), 439 }; 440 441 static struct rk_pinctrl_bank rk3328_iomux_bank[] = { 442 /* bank sub offs nbits */ 443 RK_IOMUX(0, 0, 0x0000, 2), 444 RK_IOMUX(0, 1, 0x0004, 2), 445 RK_IOMUX(0, 2, 0x0008, 2), 446 RK_IOMUX(0, 3, 0x000C, 2), 447 RK_IOMUX(1, 0, 0x0010, 2), 448 RK_IOMUX(1, 1, 0x0014, 2), 449 RK_IOMUX(1, 2, 0x0018, 2), 450 RK_IOMUX(1, 3, 0x001C, 2), 451 RK_IOMUX(2, 0, 0x0020, 2), 452 RK_IOMUX(2, 1, 0x0024, 3), 453 RK_IOMUX(2, 2, 0x002c, 3), 454 RK_IOMUX(2, 3, 0x0034, 2), 455 RK_IOMUX(3, 0, 0x0038, 3), 456 RK_IOMUX(3, 1, 0x0040, 3), 457 RK_IOMUX(3, 2, 0x0048, 2), 458 RK_IOMUX(3, 3, 0x004c, 2), 459 }; 460 461 static struct rk_pinctrl_pin_fixup rk3328_pin_fixup[] = { 462 /* bank pin reg bit mask */ 463 RK_PINFIX(2, 12, 0x24, 8, 0x300), 464 RK_PINFIX(2, 15, 0x28, 0, 0x7), 465 RK_PINFIX(2, 23, 0x30, 14, 0x6000), 466 }; 467 468 static struct rk_pinctrl_pin_drive rk3328_pin_drive[] = { 469 /* bank sub offs val ma */ 470 RK_PINDRIVE(0, 0, 0x200, 0, 2), 471 RK_PINDRIVE(0, 0, 0x200, 1, 4), 472 RK_PINDRIVE(0, 0, 0x200, 2, 8), 473 RK_PINDRIVE(0, 0, 0x200, 3, 12), 474 475 RK_PINDRIVE(0, 1, 0x204, 0, 2), 476 RK_PINDRIVE(0, 1, 0x204, 1, 4), 477 RK_PINDRIVE(0, 1, 0x204, 2, 8), 478 RK_PINDRIVE(0, 1, 0x204, 3, 12), 479 480 RK_PINDRIVE(0, 2, 0x208, 0, 2), 481 RK_PINDRIVE(0, 2, 0x208, 1, 4), 482 RK_PINDRIVE(0, 2, 0x208, 2, 8), 483 RK_PINDRIVE(0, 2, 0x208, 3, 12), 484 485 RK_PINDRIVE(0, 3, 0x20C, 0, 2), 486 RK_PINDRIVE(0, 3, 0x20C, 1, 4), 487 RK_PINDRIVE(0, 3, 0x20C, 2, 8), 488 RK_PINDRIVE(0, 3, 0x20C, 3, 12), 489 490 RK_PINDRIVE(1, 0, 0x210, 0, 2), 491 RK_PINDRIVE(1, 0, 0x210, 1, 4), 492 RK_PINDRIVE(1, 0, 0x210, 2, 8), 493 RK_PINDRIVE(1, 0, 0x210, 3, 12), 494 495 RK_PINDRIVE(1, 1, 0x214, 0, 2), 496 RK_PINDRIVE(1, 1, 0x214, 1, 4), 497 RK_PINDRIVE(1, 1, 0x214, 2, 8), 498 RK_PINDRIVE(1, 1, 0x214, 3, 12), 499 500 RK_PINDRIVE(1, 2, 0x218, 0, 2), 501 RK_PINDRIVE(1, 2, 0x218, 1, 4), 502 RK_PINDRIVE(1, 2, 0x218, 2, 8), 503 RK_PINDRIVE(1, 2, 0x218, 3, 12), 504 505 RK_PINDRIVE(1, 3, 0x21C, 0, 2), 506 RK_PINDRIVE(1, 3, 0x21C, 1, 4), 507 RK_PINDRIVE(1, 3, 0x21C, 2, 8), 508 RK_PINDRIVE(1, 3, 0x21C, 3, 12), 509 510 RK_PINDRIVE(2, 0, 0x220, 0, 2), 511 RK_PINDRIVE(2, 0, 0x220, 1, 4), 512 RK_PINDRIVE(2, 0, 0x220, 2, 8), 513 RK_PINDRIVE(2, 0, 0x220, 3, 12), 514 515 RK_PINDRIVE(2, 1, 0x224, 0, 2), 516 RK_PINDRIVE(2, 1, 0x224, 1, 4), 517 RK_PINDRIVE(2, 1, 0x224, 2, 8), 518 RK_PINDRIVE(2, 1, 0x224, 3, 12), 519 520 RK_PINDRIVE(2, 2, 0x228, 0, 2), 521 RK_PINDRIVE(2, 2, 0x228, 1, 4), 522 RK_PINDRIVE(2, 2, 0x228, 2, 8), 523 RK_PINDRIVE(2, 2, 0x228, 3, 12), 524 525 RK_PINDRIVE(2, 3, 0x22C, 0, 2), 526 RK_PINDRIVE(2, 3, 0x22C, 1, 4), 527 RK_PINDRIVE(2, 3, 0x22C, 2, 8), 528 RK_PINDRIVE(2, 3, 0x22C, 3, 12), 529 530 RK_PINDRIVE(3, 0, 0x230, 0, 2), 531 RK_PINDRIVE(3, 0, 0x230, 1, 4), 532 RK_PINDRIVE(3, 0, 0x230, 2, 8), 533 RK_PINDRIVE(3, 0, 0x230, 3, 12), 534 535 RK_PINDRIVE(3, 1, 0x234, 0, 2), 536 RK_PINDRIVE(3, 1, 0x234, 1, 4), 537 RK_PINDRIVE(3, 1, 0x234, 2, 8), 538 RK_PINDRIVE(3, 1, 0x234, 3, 12), 539 540 RK_PINDRIVE(3, 2, 0x238, 0, 2), 541 RK_PINDRIVE(3, 2, 0x238, 1, 4), 542 RK_PINDRIVE(3, 2, 0x238, 2, 8), 543 RK_PINDRIVE(3, 2, 0x238, 3, 12), 544 545 RK_PINDRIVE(3, 3, 0x23C, 0, 2), 546 RK_PINDRIVE(3, 3, 0x23C, 1, 4), 547 RK_PINDRIVE(3, 3, 0x23C, 2, 8), 548 RK_PINDRIVE(3, 3, 0x23C, 3, 12), 549 }; 550 551 static uint32_t 552 rk3328_get_pd_offset(struct rk_pinctrl_softc *sc, uint32_t bank) 553 { 554 return (0x100); 555 } 556 557 static struct syscon * 558 rk3328_get_syscon(struct rk_pinctrl_softc *sc, uint32_t bank) 559 { 560 return (sc->grf); 561 } 562 563 struct rk_pinctrl_conf rk3328_conf = { 564 .iomux_conf = rk3328_iomux_bank, 565 .iomux_nbanks = nitems(rk3328_iomux_bank), 566 .pin_fixup = rk3328_pin_fixup, 567 .npin_fixup = nitems(rk3328_pin_fixup), 568 .pin_drive = rk3328_pin_drive, 569 .npin_drive = nitems(rk3328_pin_drive), 570 .gpio_bank = rk3328_gpio_bank, 571 .ngpio_bank = nitems(rk3328_gpio_bank), 572 .get_pd_offset = rk3328_get_pd_offset, 573 .get_syscon = rk3328_get_syscon, 574 .parse_bias = rk3288_parse_bias, 575 .resolv_bias_value = rk3288_resolv_bias_value, 576 .get_bias_value = rk3288_get_bias_value, 577 }; 578 579 static struct rk_pinctrl_gpio rk3399_gpio_bank[] = { 580 RK_GPIO(0, "gpio0"), 581 RK_GPIO(1, "gpio1"), 582 RK_GPIO(2, "gpio2"), 583 RK_GPIO(3, "gpio3"), 584 RK_GPIO(4, "gpio4"), 585 }; 586 587 static struct rk_pinctrl_bank rk3399_iomux_bank[] = { 588 /* bank sub offs nbits */ 589 RK_IOMUX(0, 0, 0x0000, 2), 590 RK_IOMUX(0, 1, 0x0004, 2), 591 RK_IOMUX(0, 2, 0x0008, 2), 592 RK_IOMUX(0, 3, 0x000C, 2), 593 RK_IOMUX(1, 0, 0x0010, 2), 594 RK_IOMUX(1, 1, 0x0014, 2), 595 RK_IOMUX(1, 2, 0x0018, 2), 596 RK_IOMUX(1, 3, 0x001C, 2), 597 RK_IOMUX(2, 0, 0xE000, 2), 598 RK_IOMUX(2, 1, 0xE004, 2), 599 RK_IOMUX(2, 2, 0xE008, 2), 600 RK_IOMUX(2, 3, 0xE00C, 2), 601 RK_IOMUX(3, 0, 0xE010, 2), 602 RK_IOMUX(3, 1, 0xE014, 2), 603 RK_IOMUX(3, 2, 0xE018, 2), 604 RK_IOMUX(3, 3, 0xE01C, 2), 605 RK_IOMUX(4, 0, 0xE020, 2), 606 RK_IOMUX(4, 1, 0xE024, 2), 607 RK_IOMUX(4, 2, 0xE028, 2), 608 RK_IOMUX(4, 3, 0xE02C, 2), 609 }; 610 611 static struct rk_pinctrl_pin_fixup rk3399_pin_fixup[] = {}; 612 613 static struct rk_pinctrl_pin_drive rk3399_pin_drive[] = { 614 /* bank sub offs val ma */ 615 /* GPIO0A */ 616 RK_PINDRIVE(0, 0, 0x80, 0, 5), 617 RK_PINDRIVE(0, 0, 0x80, 1, 10), 618 RK_PINDRIVE(0, 0, 0x80, 2, 15), 619 RK_PINDRIVE(0, 0, 0x80, 3, 20), 620 621 /* GPIOB */ 622 RK_PINDRIVE(0, 1, 0x88, 0, 5), 623 RK_PINDRIVE(0, 1, 0x88, 1, 10), 624 RK_PINDRIVE(0, 1, 0x88, 2, 15), 625 RK_PINDRIVE(0, 1, 0x88, 3, 20), 626 627 /* GPIO1A */ 628 RK_PINDRIVE(1, 0, 0xA0, 0, 3), 629 RK_PINDRIVE(1, 0, 0xA0, 1, 6), 630 RK_PINDRIVE(1, 0, 0xA0, 2, 9), 631 RK_PINDRIVE(1, 0, 0xA0, 3, 12), 632 633 /* GPIO1B */ 634 RK_PINDRIVE(1, 1, 0xA8, 0, 3), 635 RK_PINDRIVE(1, 1, 0xA8, 1, 6), 636 RK_PINDRIVE(1, 1, 0xA8, 2, 9), 637 RK_PINDRIVE(1, 1, 0xA8, 3, 12), 638 639 /* GPIO1C */ 640 RK_PINDRIVE(1, 2, 0xB0, 0, 3), 641 RK_PINDRIVE(1, 2, 0xB0, 1, 6), 642 RK_PINDRIVE(1, 2, 0xB0, 2, 9), 643 RK_PINDRIVE(1, 2, 0xB0, 3, 12), 644 645 /* GPIO1D */ 646 RK_PINDRIVE(1, 3, 0xB8, 0, 3), 647 RK_PINDRIVE(1, 3, 0xB8, 1, 6), 648 RK_PINDRIVE(1, 3, 0xB8, 2, 9), 649 RK_PINDRIVE(1, 3, 0xB8, 3, 12), 650 }; 651 652 static uint32_t 653 rk3399_get_pd_offset(struct rk_pinctrl_softc *sc, uint32_t bank) 654 { 655 if (bank < 2) 656 return (0x40); 657 658 return (0xE040); 659 } 660 661 static struct syscon * 662 rk3399_get_syscon(struct rk_pinctrl_softc *sc, uint32_t bank) 663 { 664 if (bank < 2) 665 return (sc->pmu); 666 667 return (sc->grf); 668 } 669 670 static int 671 rk3399_parse_bias(phandle_t node, int bank) 672 { 673 int pullup, pulldown; 674 675 if (OF_hasprop(node, "bias-disable")) 676 return (0); 677 678 switch (bank) { 679 case 0: 680 case 2: 681 pullup = 3; 682 pulldown = 1; 683 break; 684 case 1: 685 case 3: 686 case 4: 687 pullup = 1; 688 pulldown = 2; 689 break; 690 } 691 692 if (OF_hasprop(node, "bias-pull-up")) 693 return (pullup); 694 if (OF_hasprop(node, "bias-pull-down")) 695 return (pulldown); 696 697 return (-1); 698 } 699 700 static int 701 rk3399_resolv_bias_value(int bank, int bias) 702 { 703 int rv = 0; 704 705 switch (bank) { 706 case 0: 707 case 2: 708 if (bias == 3) 709 rv = GPIO_PIN_PULLUP; 710 else if (bias == 1) 711 rv = GPIO_PIN_PULLDOWN; 712 break; 713 case 1: 714 case 3: 715 case 4: 716 if (bias == 1) 717 rv = GPIO_PIN_PULLUP; 718 else if (bias == 2) 719 rv = GPIO_PIN_PULLDOWN; 720 break; 721 } 722 723 return (rv); 724 } 725 726 static int 727 rk3399_get_bias_value(int bank, int bias) 728 { 729 int rv = 0; 730 731 switch (bank) { 732 case 0: 733 case 2: 734 if (bias & GPIO_PIN_PULLUP) 735 rv = 3; 736 else if (bias & GPIO_PIN_PULLDOWN) 737 rv = 1; 738 break; 739 case 1: 740 case 3: 741 case 4: 742 if (bias & GPIO_PIN_PULLUP) 743 rv = 1; 744 else if (bias & GPIO_PIN_PULLDOWN) 745 rv = 2; 746 break; 747 } 748 749 return (rv); 750 } 751 752 struct rk_pinctrl_conf rk3399_conf = { 753 .iomux_conf = rk3399_iomux_bank, 754 .iomux_nbanks = nitems(rk3399_iomux_bank), 755 .pin_fixup = rk3399_pin_fixup, 756 .npin_fixup = nitems(rk3399_pin_fixup), 757 .pin_drive = rk3399_pin_drive, 758 .npin_drive = nitems(rk3399_pin_drive), 759 .gpio_bank = rk3399_gpio_bank, 760 .ngpio_bank = nitems(rk3399_gpio_bank), 761 .get_pd_offset = rk3399_get_pd_offset, 762 .get_syscon = rk3399_get_syscon, 763 .parse_bias = rk3399_parse_bias, 764 .resolv_bias_value = rk3399_resolv_bias_value, 765 .get_bias_value = rk3399_get_bias_value, 766 }; 767 768 #define GRF_IOFUNC_SEL0 0x0300 769 #define GMAC1_IOMUX_SEL_M0 0x01000000 770 #define GMAC1_IOMUX_SEL_M1 0x01000100 771 772 static struct rk_pinctrl_gpio rk3568_gpio_bank[] = { 773 RK_GPIO(0, "gpio0"), 774 RK_GPIO(1, "gpio1"), 775 RK_GPIO(2, "gpio2"), 776 RK_GPIO(3, "gpio3"), 777 RK_GPIO(4, "gpio4"), 778 }; 779 780 static struct rk_pinctrl_bank rk3568_iomux_bank[] = { 781 /* bank sub offs nbits */ 782 RK_IOMUX(0, 0, 0x0000, 4), /* PMU_GRF */ 783 RK_IOMUX(0, 1, 0x0008, 4), 784 RK_IOMUX(0, 2, 0x0010, 4), 785 RK_IOMUX(0, 3, 0x0018, 4), 786 787 RK_IOMUX(1, 0, 0x0000, 4), /* SYS_GRF */ 788 RK_IOMUX(1, 1, 0x0008, 4), 789 RK_IOMUX(1, 2, 0x0010, 4), 790 RK_IOMUX(1, 3, 0x0018, 4), 791 RK_IOMUX(2, 0, 0x0020, 4), 792 RK_IOMUX(2, 1, 0x0028, 4), 793 RK_IOMUX(2, 2, 0x0030, 4), 794 RK_IOMUX(2, 3, 0x0038, 4), 795 RK_IOMUX(3, 0, 0x0040, 4), 796 RK_IOMUX(3, 1, 0x0048, 4), 797 RK_IOMUX(3, 2, 0x0050, 4), 798 RK_IOMUX(3, 3, 0x0058, 4), 799 RK_IOMUX(4, 0, 0x0060, 4), 800 RK_IOMUX(4, 1, 0x0068, 4), 801 RK_IOMUX(4, 2, 0x0070, 4), 802 RK_IOMUX(4, 3, 0x0078, 4), 803 }; 804 805 static struct rk_pinctrl_pin_fixup rk3568_pin_fixup[] = {}; 806 807 static struct rk_pinctrl_pin_drive rk3568_pin_drive[] = { 808 /* bank sub offs val ma */ 809 /* GPIO0A */ 810 RK_PINDRIVE(0, 0, 0x0020, 0, 2), 811 RK_PINDRIVE(0, 0, 0x0020, 1, 4), 812 RK_PINDRIVE(0, 0, 0x0020, 2, 8), 813 RK_PINDRIVE(0, 0, 0x0020, 3, 12), 814 815 /* GPIO0B */ 816 RK_PINDRIVE(0, 1, 0x0024, 0, 2), 817 RK_PINDRIVE(0, 1, 0x0024, 1, 4), 818 RK_PINDRIVE(0, 1, 0x0024, 2, 8), 819 RK_PINDRIVE(0, 1, 0x0024, 3, 12), 820 821 /* GPIO0C */ 822 RK_PINDRIVE(0, 1, 0x0028, 0, 2), 823 RK_PINDRIVE(0, 1, 0x0028, 1, 4), 824 RK_PINDRIVE(0, 1, 0x0028, 2, 8), 825 RK_PINDRIVE(0, 1, 0x0028, 3, 12), 826 827 /* GPIO0D */ 828 RK_PINDRIVE(0, 1, 0x002c, 0, 2), 829 RK_PINDRIVE(0, 1, 0x002c, 1, 4), 830 RK_PINDRIVE(0, 1, 0x002c, 2, 8), 831 RK_PINDRIVE(0, 1, 0x002c, 3, 12), 832 833 /* GPIO1A */ 834 RK_PINDRIVE(1, 0, 0x0080, 0, 2), 835 RK_PINDRIVE(1, 0, 0x0080, 1, 4), 836 RK_PINDRIVE(1, 0, 0x0080, 2, 8), 837 RK_PINDRIVE(1, 0, 0x0080, 3, 12), 838 839 /* GPIO1B */ 840 RK_PINDRIVE(1, 1, 0x0084, 0, 2), 841 RK_PINDRIVE(1, 1, 0x0084, 1, 4), 842 RK_PINDRIVE(1, 1, 0x0084, 2, 8), 843 RK_PINDRIVE(1, 1, 0x0084, 3, 12), 844 845 /* GPIO1C */ 846 RK_PINDRIVE(1, 2, 0x0088, 0, 2), 847 RK_PINDRIVE(1, 2, 0x0088, 1, 4), 848 RK_PINDRIVE(1, 2, 0x0088, 2, 8), 849 RK_PINDRIVE(1, 2, 0x0088, 3, 12), 850 851 /* GPIO1D */ 852 RK_PINDRIVE(1, 3, 0x008c, 0, 2), 853 RK_PINDRIVE(1, 3, 0x008c, 1, 4), 854 RK_PINDRIVE(1, 3, 0x008c, 2, 8), 855 RK_PINDRIVE(1, 3, 0x008c, 3, 12), 856 857 /* GPIO2A */ 858 RK_PINDRIVE(2, 0, 0x0090, 0, 2), 859 RK_PINDRIVE(2, 0, 0x0090, 1, 4), 860 RK_PINDRIVE(2, 0, 0x0090, 2, 8), 861 RK_PINDRIVE(2, 0, 0x0090, 3, 12), 862 863 /* GPIO2B */ 864 RK_PINDRIVE(2, 1, 0x0094, 0, 2), 865 RK_PINDRIVE(2, 1, 0x0094, 1, 4), 866 RK_PINDRIVE(2, 1, 0x0094, 2, 8), 867 RK_PINDRIVE(2, 1, 0x0094, 3, 12), 868 869 /* GPIO2C */ 870 RK_PINDRIVE(2, 2, 0x0098, 0, 2), 871 RK_PINDRIVE(2, 2, 0x0098, 1, 4), 872 RK_PINDRIVE(2, 2, 0x0098, 2, 8), 873 RK_PINDRIVE(2, 2, 0x0098, 3, 12), 874 875 /* GPIO2D */ 876 RK_PINDRIVE(2, 3, 0x009c, 0, 2), 877 RK_PINDRIVE(2, 3, 0x009c, 1, 4), 878 RK_PINDRIVE(2, 3, 0x009c, 2, 8), 879 RK_PINDRIVE(2, 3, 0x009c, 3, 12), 880 881 /* GPIO3A */ 882 RK_PINDRIVE(3, 0, 0x00a0, 0, 2), 883 RK_PINDRIVE(3, 0, 0x00a0, 1, 4), 884 RK_PINDRIVE(3, 0, 0x00a0, 2, 8), 885 RK_PINDRIVE(3, 0, 0x00a0, 3, 12), 886 887 /* GPIO3B */ 888 RK_PINDRIVE(3, 1, 0x00a4, 0, 2), 889 RK_PINDRIVE(3, 1, 0x00a4, 1, 4), 890 RK_PINDRIVE(3, 1, 0x00a4, 2, 8), 891 RK_PINDRIVE(3, 1, 0x00a4, 3, 12), 892 893 /* GPIO3C */ 894 RK_PINDRIVE(3, 2, 0x00a8, 0, 2), 895 RK_PINDRIVE(3, 2, 0x00a8, 1, 4), 896 RK_PINDRIVE(3, 2, 0x00a8, 2, 8), 897 RK_PINDRIVE(3, 2, 0x00a8, 3, 12), 898 899 /* GPIO3D */ 900 RK_PINDRIVE(3, 3, 0x00ac, 0, 2), 901 RK_PINDRIVE(3, 3, 0x00ac, 1, 4), 902 RK_PINDRIVE(3, 3, 0x00ac, 2, 8), 903 RK_PINDRIVE(3, 3, 0x00ac, 3, 12), 904 905 /* GPIO4A */ 906 RK_PINDRIVE(4, 0, 0x00b0, 0, 2), 907 RK_PINDRIVE(4, 0, 0x00b0, 1, 4), 908 RK_PINDRIVE(4, 0, 0x00b0, 2, 8), 909 RK_PINDRIVE(4, 0, 0x00b0, 3, 12), 910 911 /* GPIO4B */ 912 RK_PINDRIVE(4, 1, 0x00b4, 0, 2), 913 RK_PINDRIVE(4, 1, 0x00b4, 1, 4), 914 RK_PINDRIVE(4, 1, 0x00b4, 2, 8), 915 RK_PINDRIVE(4, 1, 0x00b4, 3, 12), 916 917 /* GPIO4C */ 918 RK_PINDRIVE(4, 2, 0x00b8, 0, 2), 919 RK_PINDRIVE(4, 2, 0x00b8, 1, 4), 920 RK_PINDRIVE(4, 2, 0x00b8, 2, 8), 921 RK_PINDRIVE(4, 2, 0x00b8, 3, 12), 922 923 /* GPIO4D */ 924 RK_PINDRIVE(4, 3, 0x00bc, 0, 2), 925 RK_PINDRIVE(4, 3, 0x00bc, 1, 4), 926 RK_PINDRIVE(4, 3, 0x00bc, 2, 8), 927 RK_PINDRIVE(4, 3, 0x00bc, 3, 12), 928 }; 929 930 static uint32_t 931 rk3568_get_pd_offset(struct rk_pinctrl_softc *sc, uint32_t bank) 932 { 933 934 if (bank == 0) 935 return (0x20); 936 937 /* 938 * Registers start at 0x80, but bank index starts at 1. Return 0x70 939 * so later calculations get the correct offset. 940 */ 941 return (0x70); 942 } 943 944 static struct syscon * 945 rk3568_get_syscon(struct rk_pinctrl_softc *sc, uint32_t bank) 946 { 947 948 if (bank) 949 return (sc->grf); 950 else 951 return (sc->pmu); 952 } 953 954 static int 955 rk3568_parse_bias(phandle_t node, int bank) 956 { 957 958 if (OF_hasprop(node, "bias-disable")) 959 return (0); 960 if (OF_hasprop(node, "bias-pull-up")) 961 return (1); 962 if (OF_hasprop(node, "bias-pull-down")) 963 return (2); 964 return (-1); 965 } 966 967 static int 968 rk3568_resolv_bias_value(int bank, int bias) 969 { 970 971 if (bias == 1) 972 return (GPIO_PIN_PULLUP); 973 if (bias == 2) 974 return (GPIO_PIN_PULLDOWN); 975 return (0); 976 } 977 978 static int 979 rk3568_get_bias_value(int bank, int bias) 980 { 981 982 if (bias & GPIO_PIN_PULLUP) 983 return (1); 984 if (bias & GPIO_PIN_PULLDOWN) 985 return (2); 986 return (0); 987 } 988 989 struct rk_pinctrl_conf rk3568_conf = { 990 .iomux_conf = rk3568_iomux_bank, 991 .iomux_nbanks = nitems(rk3568_iomux_bank), 992 .pin_fixup = rk3568_pin_fixup, 993 .npin_fixup = nitems(rk3568_pin_fixup), 994 .pin_drive = rk3568_pin_drive, 995 .npin_drive = nitems(rk3568_pin_drive), 996 .gpio_bank = rk3568_gpio_bank, 997 .ngpio_bank = nitems(rk3568_gpio_bank), 998 .get_pd_offset = rk3568_get_pd_offset, 999 .get_syscon = rk3568_get_syscon, 1000 .parse_bias = rk3568_parse_bias, 1001 .resolv_bias_value = rk3568_resolv_bias_value, 1002 .get_bias_value = rk3568_get_bias_value, 1003 }; 1004 1005 static struct ofw_compat_data compat_data[] = { 1006 {"rockchip,rk3288-pinctrl", (uintptr_t)&rk3288_conf}, 1007 {"rockchip,rk3328-pinctrl", (uintptr_t)&rk3328_conf}, 1008 {"rockchip,rk3399-pinctrl", (uintptr_t)&rk3399_conf}, 1009 {"rockchip,rk3568-pinctrl", (uintptr_t)&rk3568_conf}, 1010 {NULL, 0} 1011 }; 1012 1013 static int 1014 rk_pinctrl_parse_drive(struct rk_pinctrl_softc *sc, phandle_t node, 1015 uint32_t bank, uint32_t subbank, uint32_t *drive, uint32_t *offset) 1016 { 1017 uint32_t value; 1018 int i; 1019 1020 if (OF_getencprop(node, "drive-strength", &value, 1021 sizeof(value)) != 0) 1022 return (-1); 1023 1024 /* Map to the correct drive value */ 1025 for (i = 0; i < sc->conf->npin_drive; i++) { 1026 if (sc->conf->pin_drive[i].bank != bank && 1027 sc->conf->pin_drive[i].subbank != subbank) 1028 continue; 1029 if (sc->conf->pin_drive[i].ma == value) { 1030 *drive = sc->conf->pin_drive[i].value; 1031 return (0); 1032 } 1033 } 1034 1035 return (-1); 1036 } 1037 1038 static void 1039 rk_pinctrl_get_fixup(struct rk_pinctrl_softc *sc, uint32_t bank, uint32_t pin, 1040 uint32_t *reg, uint32_t *mask, uint32_t *bit) 1041 { 1042 int i; 1043 1044 for (i = 0; i < sc->conf->npin_fixup; i++) 1045 if (sc->conf->pin_fixup[i].bank == bank && 1046 sc->conf->pin_fixup[i].pin == pin) { 1047 *reg = sc->conf->pin_fixup[i].reg; 1048 *mask = sc->conf->pin_fixup[i].mask; 1049 *bit = sc->conf->pin_fixup[i].bit; 1050 1051 return; 1052 } 1053 } 1054 1055 static int 1056 rk_pinctrl_handle_io(struct rk_pinctrl_softc *sc, phandle_t node, uint32_t bank, 1057 uint32_t pin) 1058 { 1059 bool have_cfg, have_direction, have_value; 1060 uint32_t direction_value, pin_value; 1061 struct rk_pinctrl_gpio *gpio; 1062 int i, rv; 1063 1064 have_cfg = false; 1065 have_direction = false; 1066 have_value = false; 1067 1068 /* Get (subset of) GPIO pin properties. */ 1069 if (OF_hasprop(node, "output-disable")) { 1070 have_cfg = true; 1071 have_direction = true; 1072 direction_value = GPIO_PIN_INPUT; 1073 } 1074 1075 if (OF_hasprop(node, "output-enable")) { 1076 have_cfg = true; 1077 have_direction = true; 1078 direction_value = GPIO_PIN_OUTPUT; 1079 } 1080 1081 if (OF_hasprop(node, "output-low")) { 1082 have_cfg = true; 1083 have_direction = true; 1084 direction_value = GPIO_PIN_OUTPUT; 1085 have_value = true; 1086 pin_value = 0; 1087 } 1088 1089 if (OF_hasprop(node, "output-high")) { 1090 have_cfg = true; 1091 have_direction = true; 1092 direction_value = GPIO_PIN_OUTPUT; 1093 have_value = true; 1094 pin_value = 1; 1095 } 1096 1097 if (!have_cfg) 1098 return (0); 1099 1100 /* Find gpio */ 1101 gpio = NULL; 1102 for(i = 0; i < sc->conf->ngpio_bank; i++) { 1103 if (bank == sc->conf->gpio_bank[i].bank) { 1104 gpio = sc->conf->gpio_bank + i; 1105 break; 1106 } 1107 } 1108 if (gpio == NULL) { 1109 device_printf(sc->dev, "Cannot find GPIO bank %d\n", bank); 1110 return (ENXIO); 1111 } 1112 if (gpio->gpio_dev == NULL) { 1113 device_printf(sc->dev, 1114 "No GPIO subdevice found for bank %d\n", bank); 1115 return (ENXIO); 1116 } 1117 1118 rv = 0; 1119 if (have_value) { 1120 rv = GPIO_PIN_SET(gpio->gpio_dev, pin, pin_value); 1121 if (rv != 0) { 1122 device_printf(sc->dev, "Cannot set GPIO value: %d\n", 1123 rv); 1124 return (rv); 1125 } 1126 } 1127 1128 if (have_direction) { 1129 rv = GPIO_PIN_SETFLAGS(gpio->gpio_dev, pin, direction_value); 1130 if (rv != 0) { 1131 device_printf(sc->dev, 1132 "Cannot set GPIO direction: %d\n", rv); 1133 return (rv); 1134 } 1135 } 1136 1137 return (0); 1138 } 1139 1140 static void 1141 rk_pinctrl_configure_pin(struct rk_pinctrl_softc *sc, uint32_t *pindata) 1142 { 1143 phandle_t pin_conf; 1144 struct syscon *syscon; 1145 uint32_t bank, subbank, pin, function, bias; 1146 uint32_t bit, mask, reg, drive; 1147 int i, rv; 1148 1149 bank = pindata[0]; 1150 pin = pindata[1]; 1151 function = pindata[2]; 1152 pin_conf = OF_node_from_xref(pindata[3]); 1153 subbank = pin / 8; 1154 1155 for (i = 0; i < sc->conf->iomux_nbanks; i++) 1156 if (sc->conf->iomux_conf[i].bank == bank && 1157 sc->conf->iomux_conf[i].subbank == subbank) 1158 break; 1159 1160 if (i == sc->conf->iomux_nbanks) { 1161 device_printf(sc->dev, "Unknown pin %d in bank %d\n", pin, 1162 bank); 1163 return; 1164 } 1165 1166 /* Find syscon */ 1167 syscon = sc->conf->get_syscon(sc, bank); 1168 1169 /* Setup GPIO properties first */ 1170 rv = rk_pinctrl_handle_io(sc, pin_conf, bank, pin); 1171 1172 /* Then pin pull-up/down */ 1173 bias = sc->conf->parse_bias(pin_conf, bank); 1174 if (bias >= 0) { 1175 reg = sc->conf->get_pd_offset(sc, bank); 1176 reg += bank * 0x10 + ((pin / 8) * 0x4); 1177 bit = (pin % 8) * 2; 1178 mask = (0x3 << bit); 1179 SYSCON_MODIFY_4(syscon, reg, mask, bias << bit | (mask << 16)); 1180 } 1181 1182 /* Then drive strength */ 1183 if (ofw_bus_node_is_compatible(ofw_bus_get_node(sc->dev), 1184 "rockchip,rk3568-pinctrl")) { 1185 uint32_t value; 1186 if (OF_getencprop(pin_conf, "drive-strength", &value, 1187 sizeof(value)) == 0) { 1188 if (bank) 1189 reg = 0x01c0 + (bank * 0x40) + (pin / 2 * 4); 1190 else 1191 reg = 0x0070 + (pin / 2 * 4); 1192 1193 drive = ((1 << (value + 1)) - 1) << (pin % 2); 1194 1195 mask = 0x3f << (pin % 2);; 1196 1197 SYSCON_WRITE_4(syscon, reg, drive | (mask << 16)); 1198 } 1199 } else { 1200 rv = rk_pinctrl_parse_drive(sc, pin_conf, bank, subbank, &drive, 1201 ®); 1202 if (rv == 0) { 1203 bit = (pin % 8) * 2; 1204 mask = (0x3 << bit); 1205 SYSCON_MODIFY_4(syscon, reg, mask, 1206 drive << bit | (mask << 16)); 1207 } 1208 } 1209 1210 /* Finally set the pin function */ 1211 reg = sc->conf->iomux_conf[i].offset; 1212 switch (sc->conf->iomux_conf[i].nbits) { 1213 case 4: 1214 if ((pin % 8) >= 4) 1215 reg += 0x4; 1216 bit = (pin % 4) * 4; 1217 mask = (0xF << bit); 1218 break; 1219 case 3: 1220 if ((pin % 8) >= 5) 1221 reg += 4; 1222 bit = (pin % 8 % 5) * 3; 1223 mask = (0x7 << bit); 1224 break; 1225 case 2: 1226 bit = (pin % 8) * 2; 1227 mask = (0x3 << bit); 1228 break; 1229 default: 1230 device_printf(sc->dev, 1231 "Unknown pin stride width %d in bank %d\n", 1232 sc->conf->iomux_conf[i].nbits, bank); 1233 return; 1234 } 1235 rk_pinctrl_get_fixup(sc, bank, pin, ®, &mask, &bit); 1236 1237 /* 1238 * NOTE: not all syscon registers uses hi-word write mask, thus 1239 * register modify method should be used. 1240 * XXXX We should not pass write mask to syscon register 1241 * without hi-word write mask. 1242 */ 1243 SYSCON_MODIFY_4(syscon, reg, mask, function << bit | (mask << 16)); 1244 1245 /* RK3568 specific pin mux for various functionalities */ 1246 if (ofw_bus_node_is_compatible(ofw_bus_get_node(sc->dev), 1247 "rockchip,rk3568-pinctrl")) { 1248 if (bank == 3 && pin == 9 && function == 3) 1249 SYSCON_WRITE_4(sc->grf, 1250 GRF_IOFUNC_SEL0, GMAC1_IOMUX_SEL_M0); 1251 if (bank == 4 && pin == 7 && function == 3) 1252 SYSCON_WRITE_4(sc->grf, 1253 GRF_IOFUNC_SEL0, GMAC1_IOMUX_SEL_M1); 1254 } 1255 } 1256 1257 static int 1258 rk_pinctrl_configure_pins(device_t dev, phandle_t cfgxref) 1259 { 1260 struct rk_pinctrl_softc *sc; 1261 phandle_t node; 1262 uint32_t *pins; 1263 int i, npins; 1264 1265 sc = device_get_softc(dev); 1266 node = OF_node_from_xref(cfgxref); 1267 1268 npins = OF_getencprop_alloc_multi(node, "rockchip,pins", sizeof(*pins), 1269 (void **)&pins); 1270 if (npins <= 0) 1271 return (ENOENT); 1272 1273 for (i = 0; i != npins; i += 4) 1274 rk_pinctrl_configure_pin(sc, pins + i); 1275 1276 return (0); 1277 } 1278 1279 static int 1280 rk_pinctrl_is_gpio_locked(struct rk_pinctrl_softc *sc, struct syscon *syscon, 1281 int bank, uint32_t pin, bool *is_gpio) 1282 { 1283 uint32_t subbank, bit, mask, reg; 1284 uint32_t pinfunc; 1285 int i; 1286 1287 RK_PINCTRL_LOCK_ASSERT(sc); 1288 1289 subbank = pin / 8; 1290 *is_gpio = false; 1291 1292 for (i = 0; i < sc->conf->iomux_nbanks; i++) 1293 if (sc->conf->iomux_conf[i].bank == bank && 1294 sc->conf->iomux_conf[i].subbank == subbank) 1295 break; 1296 1297 if (i == sc->conf->iomux_nbanks) { 1298 device_printf(sc->dev, "Unknown pin %d in bank %d\n", pin, 1299 bank); 1300 return (EINVAL); 1301 } 1302 1303 syscon = sc->conf->get_syscon(sc, bank); 1304 1305 /* Parse pin function */ 1306 reg = sc->conf->iomux_conf[i].offset; 1307 switch (sc->conf->iomux_conf[i].nbits) { 1308 case 4: 1309 if ((pin % 8) >= 4) 1310 reg += 0x4; 1311 bit = (pin % 4) * 4; 1312 mask = (0xF << bit); 1313 break; 1314 case 3: 1315 if ((pin % 8) >= 5) 1316 reg += 4; 1317 bit = (pin % 8 % 5) * 3; 1318 mask = (0x7 << bit); 1319 break; 1320 case 2: 1321 bit = (pin % 8) * 2; 1322 mask = (0x3 << bit); 1323 break; 1324 default: 1325 device_printf(sc->dev, 1326 "Unknown pin stride width %d in bank %d\n", 1327 sc->conf->iomux_conf[i].nbits, bank); 1328 return (EINVAL); 1329 } 1330 rk_pinctrl_get_fixup(sc, bank, pin, ®, &mask, &bit); 1331 1332 reg = SYSCON_READ_4(syscon, reg); 1333 pinfunc = (reg & mask) >> bit; 1334 1335 /* Test if the pin is in gpio mode */ 1336 if (pinfunc == 0) 1337 *is_gpio = true; 1338 1339 return (0); 1340 } 1341 1342 static int 1343 rk_pinctrl_get_bank(struct rk_pinctrl_softc *sc, device_t gpio, int *bank) 1344 { 1345 int i; 1346 1347 for (i = 0; i < sc->conf->ngpio_bank; i++) { 1348 if (sc->conf->gpio_bank[i].gpio_dev == gpio) 1349 break; 1350 } 1351 if (i == sc->conf->ngpio_bank) 1352 return (EINVAL); 1353 1354 *bank = i; 1355 return (0); 1356 } 1357 1358 static int 1359 rk_pinctrl_is_gpio(device_t pinctrl, device_t gpio, uint32_t pin, bool *is_gpio) 1360 { 1361 struct rk_pinctrl_softc *sc; 1362 struct syscon *syscon; 1363 int bank; 1364 int rv; 1365 1366 sc = device_get_softc(pinctrl); 1367 RK_PINCTRL_LOCK(sc); 1368 1369 rv = rk_pinctrl_get_bank(sc, gpio, &bank); 1370 if (rv != 0) 1371 goto done; 1372 syscon = sc->conf->get_syscon(sc, bank); 1373 rv = rk_pinctrl_is_gpio_locked(sc, syscon, bank, pin, is_gpio); 1374 1375 done: 1376 RK_PINCTRL_UNLOCK(sc); 1377 1378 return (rv); 1379 } 1380 1381 static int 1382 rk_pinctrl_get_flags(device_t pinctrl, device_t gpio, uint32_t pin, 1383 uint32_t *flags) 1384 { 1385 struct rk_pinctrl_softc *sc; 1386 struct syscon *syscon; 1387 uint32_t reg, bit; 1388 uint32_t bias; 1389 int bank; 1390 int rv = 0; 1391 bool is_gpio; 1392 1393 sc = device_get_softc(pinctrl); 1394 RK_PINCTRL_LOCK(sc); 1395 1396 rv = rk_pinctrl_get_bank(sc, gpio, &bank); 1397 if (rv != 0) 1398 goto done; 1399 syscon = sc->conf->get_syscon(sc, bank); 1400 rv = rk_pinctrl_is_gpio_locked(sc, syscon, bank, pin, &is_gpio); 1401 if (rv != 0) 1402 goto done; 1403 if (!is_gpio) { 1404 rv = EINVAL; 1405 goto done; 1406 } 1407 /* Get the pullup/pulldown configuration */ 1408 reg = sc->conf->get_pd_offset(sc, bank); 1409 reg += bank * 0x10 + ((pin / 8) * 0x4); 1410 bit = (pin % 8) * 2; 1411 reg = SYSCON_READ_4(syscon, reg); 1412 reg = (reg >> bit) & 0x3; 1413 bias = sc->conf->resolv_bias_value(bank, reg); 1414 *flags = bias; 1415 1416 done: 1417 RK_PINCTRL_UNLOCK(sc); 1418 return (rv); 1419 } 1420 1421 static int 1422 rk_pinctrl_set_flags(device_t pinctrl, device_t gpio, uint32_t pin, 1423 uint32_t flags) 1424 { 1425 struct rk_pinctrl_softc *sc; 1426 struct syscon *syscon; 1427 uint32_t bit, mask, reg; 1428 uint32_t bias; 1429 int bank; 1430 int rv = 0; 1431 bool is_gpio; 1432 1433 sc = device_get_softc(pinctrl); 1434 RK_PINCTRL_LOCK(sc); 1435 1436 rv = rk_pinctrl_get_bank(sc, gpio, &bank); 1437 if (rv != 0) 1438 goto done; 1439 syscon = sc->conf->get_syscon(sc, bank); 1440 rv = rk_pinctrl_is_gpio_locked(sc, syscon, bank, pin, &is_gpio); 1441 if (rv != 0) 1442 goto done; 1443 if (!is_gpio) { 1444 rv = EINVAL; 1445 goto done; 1446 } 1447 /* Get the pullup/pulldown configuration */ 1448 reg = sc->conf->get_pd_offset(sc, bank); 1449 reg += bank * 0x10 + ((pin / 8) * 0x4); 1450 bit = (pin % 8) * 2; 1451 mask = (0x3 << bit); 1452 bias = sc->conf->get_bias_value(bank, flags); 1453 SYSCON_MODIFY_4(syscon, reg, mask, bias << bit | (mask << 16)); 1454 1455 done: 1456 RK_PINCTRL_UNLOCK(sc); 1457 return (rv); 1458 } 1459 1460 static int 1461 rk_pinctrl_probe(device_t dev) 1462 { 1463 1464 if (!ofw_bus_status_okay(dev)) 1465 return (ENXIO); 1466 1467 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 1468 return (ENXIO); 1469 1470 device_set_desc(dev, "RockChip Pinctrl controller"); 1471 return (BUS_PROBE_DEFAULT); 1472 } 1473 1474 static int 1475 rk_pinctrl_attach(device_t dev) 1476 { 1477 struct rk_pinctrl_softc *sc; 1478 phandle_t node; 1479 device_t cdev; 1480 int rv, gpio_unit; 1481 1482 sc = device_get_softc(dev); 1483 sc->dev = dev; 1484 1485 node = ofw_bus_get_node(dev); 1486 1487 if (OF_hasprop(node, "rockchip,grf") && 1488 syscon_get_by_ofw_property(dev, node, 1489 "rockchip,grf", &sc->grf) != 0) { 1490 device_printf(dev, "cannot get grf driver handle\n"); 1491 return (ENXIO); 1492 } 1493 1494 /* RK3568,RK3399,RK3288 have banks in PMU. RK3328 doesn't have a PMU. */ 1495 if (ofw_bus_node_is_compatible(node, "rockchip,rk3568-pinctrl") || 1496 ofw_bus_node_is_compatible(node, "rockchip,rk3399-pinctrl") || 1497 ofw_bus_node_is_compatible(node, "rockchip,rk3288-pinctrl")) { 1498 if (OF_hasprop(node, "rockchip,pmu") && 1499 syscon_get_by_ofw_property(dev, node, 1500 "rockchip,pmu", &sc->pmu) != 0) { 1501 device_printf(dev, "cannot get pmu driver handle\n"); 1502 return (ENXIO); 1503 } 1504 } 1505 1506 mtx_init(&sc->mtx, "rk pinctrl", "pinctrl", MTX_SPIN); 1507 1508 sc->conf = (struct rk_pinctrl_conf *)ofw_bus_search_compatible(dev, 1509 compat_data)->ocd_data; 1510 1511 fdt_pinctrl_register(dev, "rockchip,pins"); 1512 1513 simplebus_init(dev, node); 1514 1515 bus_generic_probe(dev); 1516 1517 /* Attach child devices */ 1518 for (node = OF_child(node), gpio_unit = 0; node > 0; 1519 node = OF_peer(node)) { 1520 if (!ofw_bus_node_is_compatible(node, "rockchip,gpio-bank")) 1521 continue; 1522 cdev = simplebus_add_device(dev, node, 0, NULL, -1, NULL); 1523 if (cdev == NULL) { 1524 device_printf(dev, " Cannot add GPIO subdevice\n"); 1525 gpio_unit += 1; 1526 continue; 1527 } 1528 rv = device_probe_and_attach(cdev); 1529 if (rv != 0) { 1530 device_printf(sc->dev, 1531 "Cannot attach GPIO subdevice\n"); 1532 gpio_unit += 1; 1533 continue; 1534 } 1535 sc->conf->gpio_bank[gpio_unit].gpio_dev = cdev; 1536 gpio_unit += 1; 1537 } 1538 1539 fdt_pinctrl_configure_tree(dev); 1540 1541 return (bus_generic_attach(dev)); 1542 } 1543 1544 static int 1545 rk_pinctrl_detach(device_t dev) 1546 { 1547 1548 return (EBUSY); 1549 } 1550 1551 static device_method_t rk_pinctrl_methods[] = { 1552 /* Device interface */ 1553 DEVMETHOD(device_probe, rk_pinctrl_probe), 1554 DEVMETHOD(device_attach, rk_pinctrl_attach), 1555 DEVMETHOD(device_detach, rk_pinctrl_detach), 1556 1557 /* fdt_pinctrl interface */ 1558 DEVMETHOD(fdt_pinctrl_configure, rk_pinctrl_configure_pins), 1559 DEVMETHOD(fdt_pinctrl_is_gpio, rk_pinctrl_is_gpio), 1560 DEVMETHOD(fdt_pinctrl_get_flags, rk_pinctrl_get_flags), 1561 DEVMETHOD(fdt_pinctrl_set_flags, rk_pinctrl_set_flags), 1562 1563 DEVMETHOD_END 1564 }; 1565 1566 DEFINE_CLASS_1(rk_pinctrl, rk_pinctrl_driver, rk_pinctrl_methods, 1567 sizeof(struct rk_pinctrl_softc), simplebus_driver); 1568 1569 EARLY_DRIVER_MODULE(rk_pinctrl, simplebus, rk_pinctrl_driver, 0, 0, 1570 BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE); 1571 MODULE_VERSION(rk_pinctrl, 1); 1572