1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2018 Emmanuel Vadot <manu@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/bus.h> 35 36 #include <sys/gpio.h> 37 #include <sys/kernel.h> 38 #include <sys/lock.h> 39 #include <sys/module.h> 40 #include <sys/mutex.h> 41 #include <sys/rman.h> 42 43 #include <machine/bus.h> 44 #include <machine/resource.h> 45 #include <machine/intr.h> 46 47 #include <dev/fdt/simplebus.h> 48 49 #include <dev/ofw/ofw_bus.h> 50 #include <dev/ofw/ofw_bus_subr.h> 51 52 #include <dev/fdt/fdt_pinctrl.h> 53 54 #include <dev/extres/syscon/syscon.h> 55 56 #include "gpio_if.h" 57 #include "syscon_if.h" 58 59 struct rk_pinctrl_pin_drive { 60 uint32_t bank; 61 uint32_t subbank; 62 uint32_t offset; 63 uint32_t value; 64 uint32_t ma; 65 }; 66 67 struct rk_pinctrl_bank { 68 uint32_t bank; 69 uint32_t subbank; 70 uint32_t offset; 71 uint32_t nbits; 72 }; 73 74 struct rk_pinctrl_pin_fixup { 75 uint32_t bank; 76 uint32_t subbank; 77 uint32_t pin; 78 uint32_t reg; 79 uint32_t bit; 80 uint32_t mask; 81 }; 82 83 struct rk_pinctrl_gpio { 84 uint32_t bank; 85 char *gpio_name; 86 device_t gpio_dev; 87 }; 88 89 90 struct rk_pinctrl_softc; 91 92 struct rk_pinctrl_conf { 93 struct rk_pinctrl_bank *iomux_conf; 94 uint32_t iomux_nbanks; 95 struct rk_pinctrl_pin_fixup *pin_fixup; 96 uint32_t npin_fixup; 97 struct rk_pinctrl_pin_drive *pin_drive; 98 uint32_t npin_drive; 99 struct rk_pinctrl_gpio *gpio_bank; 100 uint32_t ngpio_bank; 101 uint32_t (*get_pd_offset)(struct rk_pinctrl_softc *, uint32_t); 102 struct syscon *(*get_syscon)(struct rk_pinctrl_softc *, uint32_t); 103 int (*parse_bias)(phandle_t, int); 104 }; 105 106 struct rk_pinctrl_softc { 107 struct simplebus_softc simplebus_sc; 108 device_t dev; 109 struct syscon *grf; 110 struct syscon *pmu; 111 struct rk_pinctrl_conf *conf; 112 }; 113 114 #define RK_IOMUX(_bank, _subbank, _offset, _nbits) \ 115 { \ 116 .bank = _bank, \ 117 .subbank = _subbank, \ 118 .offset = _offset, \ 119 .nbits = _nbits, \ 120 } 121 122 #define RK_PINFIX(_bank, _pin, _reg, _bit, _mask) \ 123 { \ 124 .bank = _bank, \ 125 .pin = _pin, \ 126 .reg = _reg, \ 127 .bit = _bit, \ 128 .mask = _mask, \ 129 } 130 131 #define RK_PINDRIVE(_bank, _subbank, _offset, _value, _ma) \ 132 { \ 133 .bank = _bank, \ 134 .subbank = _subbank, \ 135 .offset = _offset, \ 136 .value = _value, \ 137 .ma = _ma, \ 138 } 139 #define RK_GPIO(_bank, _name) \ 140 { \ 141 .bank = _bank, \ 142 .gpio_name = _name, \ 143 } 144 145 static struct rk_pinctrl_gpio rk3288_gpio_bank[] = { 146 RK_GPIO(0, "gpio0"), 147 RK_GPIO(1, "gpio1"), 148 RK_GPIO(2, "gpio2"), 149 RK_GPIO(3, "gpio3"), 150 RK_GPIO(4, "gpio4"), 151 RK_GPIO(5, "gpio5"), 152 RK_GPIO(6, "gpio6"), 153 RK_GPIO(7, "gpio7"), 154 RK_GPIO(8, "gpio8"), 155 }; 156 157 static struct rk_pinctrl_bank rk3288_iomux_bank[] = { 158 /* bank sub offs nbits */ 159 /* PMU */ 160 RK_IOMUX(0, 0, 0x0084, 2), 161 RK_IOMUX(0, 1, 0x0088, 2), 162 RK_IOMUX(0, 2, 0x008C, 2), 163 /* GFR */ 164 RK_IOMUX(1, 3, 0x000C, 2), 165 RK_IOMUX(2, 0, 0x0010, 2), 166 RK_IOMUX(2, 1, 0x0014, 2), 167 RK_IOMUX(2, 2, 0x0018, 2), 168 RK_IOMUX(2, 3, 0x001C, 2), 169 RK_IOMUX(3, 0, 0x0020, 2), 170 RK_IOMUX(3, 1, 0x0024, 2), 171 RK_IOMUX(3, 2, 0x0028, 2), 172 RK_IOMUX(3, 3, 0x002C, 4), 173 RK_IOMUX(4, 0, 0x0034, 4), 174 RK_IOMUX(4, 1, 0x003C, 4), 175 RK_IOMUX(4, 2, 0x0044, 2), 176 RK_IOMUX(4, 3, 0x0048, 2), 177 /* 5,0 - Empty */ 178 RK_IOMUX(5, 1, 0x0050, 2), 179 RK_IOMUX(5, 2, 0x0054, 2), 180 /* 5,3 - Empty */ 181 RK_IOMUX(6, 0, 0x005C, 2), 182 RK_IOMUX(6, 1, 0x0060, 2), 183 RK_IOMUX(6, 2, 0x0064, 2), 184 /* 6,3 - Empty */ 185 RK_IOMUX(7, 0, 0x006C, 2), 186 RK_IOMUX(7, 1, 0x0070, 2), 187 RK_IOMUX(7, 2, 0x0074, 4), 188 /* 7,3 - Empty */ 189 RK_IOMUX(8, 0, 0x0080, 2), 190 RK_IOMUX(8, 1, 0x0084, 2), 191 /* 8,2 - Empty */ 192 /* 8,3 - Empty */ 193 194 }; 195 196 static struct rk_pinctrl_pin_fixup rk3288_pin_fixup[] = { 197 }; 198 199 static struct rk_pinctrl_pin_drive rk3288_pin_drive[] = { 200 /* bank sub offs val ma */ 201 /* GPIO0A (PMU)*/ 202 RK_PINDRIVE(0, 0, 0x070, 0, 2), 203 RK_PINDRIVE(0, 0, 0x070, 1, 4), 204 RK_PINDRIVE(0, 0, 0x070, 2, 8), 205 RK_PINDRIVE(0, 0, 0x070, 3, 12), 206 207 /* GPIO0B (PMU)*/ 208 RK_PINDRIVE(0, 1, 0x074, 0, 2), 209 RK_PINDRIVE(0, 1, 0x074, 1, 4), 210 RK_PINDRIVE(0, 1, 0x074, 2, 8), 211 RK_PINDRIVE(0, 1, 0x074, 3, 12), 212 213 /* GPIO0C (PMU)*/ 214 RK_PINDRIVE(0, 2, 0x078, 0, 2), 215 RK_PINDRIVE(0, 2, 0x078, 1, 4), 216 RK_PINDRIVE(0, 2, 0x078, 2, 8), 217 RK_PINDRIVE(0, 2, 0x078, 3, 12), 218 219 /* GPIO1D */ 220 RK_PINDRIVE(1, 3, 0x1CC, 0, 2), 221 RK_PINDRIVE(1, 3, 0x1CC, 1, 4), 222 RK_PINDRIVE(1, 3, 0x1CC, 2, 8), 223 RK_PINDRIVE(1, 3, 0x1CC, 3, 12), 224 225 /* GPIO2A */ 226 RK_PINDRIVE(2, 0, 0x1D0, 0, 2), 227 RK_PINDRIVE(2, 0, 0x1D0, 1, 4), 228 RK_PINDRIVE(2, 0, 0x1D0, 2, 8), 229 RK_PINDRIVE(2, 0, 0x1D0, 3, 12), 230 231 /* GPIO2B */ 232 RK_PINDRIVE(2, 1, 0x1D4, 0, 2), 233 RK_PINDRIVE(2, 1, 0x1D4, 1, 4), 234 RK_PINDRIVE(2, 1, 0x1D4, 2, 8), 235 RK_PINDRIVE(2, 1, 0x1D4, 3, 12), 236 237 /* GPIO2C */ 238 RK_PINDRIVE(2, 2, 0x1D8, 0, 2), 239 RK_PINDRIVE(2, 2, 0x1D8, 1, 4), 240 RK_PINDRIVE(2, 2, 0x1D8, 2, 8), 241 RK_PINDRIVE(2, 2, 0x1D8, 3, 12), 242 243 /* GPIO2D */ 244 RK_PINDRIVE(2, 3, 0x1DC, 0, 2), 245 RK_PINDRIVE(2, 3, 0x1DC, 1, 4), 246 RK_PINDRIVE(2, 3, 0x1DC, 2, 8), 247 RK_PINDRIVE(2, 3, 0x1DC, 3, 12), 248 249 /* GPIO3A */ 250 RK_PINDRIVE(3, 0, 0x1E0, 0, 2), 251 RK_PINDRIVE(3, 0, 0x1E0, 1, 4), 252 RK_PINDRIVE(3, 0, 0x1E0, 2, 8), 253 RK_PINDRIVE(3, 0, 0x1E0, 3, 12), 254 255 /* GPIO3B */ 256 RK_PINDRIVE(3, 1, 0x1E4, 0, 2), 257 RK_PINDRIVE(3, 1, 0x1E4, 1, 4), 258 RK_PINDRIVE(3, 1, 0x1E4, 2, 8), 259 RK_PINDRIVE(3, 1, 0x1E4, 3, 12), 260 261 /* GPIO3C */ 262 RK_PINDRIVE(3, 2, 0x1E8, 0, 2), 263 RK_PINDRIVE(3, 2, 0x1E8, 1, 4), 264 RK_PINDRIVE(3, 2, 0x1E8, 2, 8), 265 RK_PINDRIVE(3, 2, 0x1E8, 3, 12), 266 267 /* GPIO3D */ 268 RK_PINDRIVE(3, 3, 0x1EC, 0, 2), 269 RK_PINDRIVE(3, 3, 0x1EC, 1, 4), 270 RK_PINDRIVE(3, 3, 0x1EC, 2, 8), 271 RK_PINDRIVE(3, 3, 0x1EC, 3, 12), 272 273 /* GPIO4A */ 274 RK_PINDRIVE(4, 0, 0x1F0, 0, 2), 275 RK_PINDRIVE(4, 0, 0x1F0, 1, 4), 276 RK_PINDRIVE(4, 0, 0x1F0, 2, 8), 277 RK_PINDRIVE(4, 0, 0x1F0, 3, 12), 278 279 /* GPIO4B */ 280 RK_PINDRIVE(4, 1, 0x1F4, 0, 2), 281 RK_PINDRIVE(4, 1, 0x1F4, 1, 4), 282 RK_PINDRIVE(4, 1, 0x1F4, 2, 8), 283 RK_PINDRIVE(4, 1, 0x1F4, 3, 12), 284 285 /* GPIO4C */ 286 RK_PINDRIVE(4, 2, 0x1F8, 0, 2), 287 RK_PINDRIVE(4, 2, 0x1F8, 1, 4), 288 RK_PINDRIVE(4, 2, 0x1F8, 2, 8), 289 RK_PINDRIVE(4, 2, 0x1F8, 3, 12), 290 291 /* GPIO4D */ 292 RK_PINDRIVE(4, 3, 0x1FC, 0, 2), 293 RK_PINDRIVE(4, 3, 0x1FC, 1, 4), 294 RK_PINDRIVE(4, 3, 0x1FC, 2, 8), 295 RK_PINDRIVE(4, 3, 0x1FC, 3, 12), 296 297 /* GPIO5B */ 298 RK_PINDRIVE(5, 1, 0x204, 0, 2), 299 RK_PINDRIVE(5, 1, 0x204, 1, 4), 300 RK_PINDRIVE(5, 1, 0x204, 2, 8), 301 RK_PINDRIVE(5, 1, 0x204, 3, 12), 302 303 /* GPIO5C */ 304 RK_PINDRIVE(5, 2, 0x208, 0, 2), 305 RK_PINDRIVE(5, 2, 0x208, 1, 4), 306 RK_PINDRIVE(5, 2, 0x208, 2, 8), 307 RK_PINDRIVE(5, 2, 0x208, 3, 12), 308 309 /* GPIO6A */ 310 RK_PINDRIVE(6, 0, 0x210, 0, 2), 311 RK_PINDRIVE(6, 0, 0x210, 1, 4), 312 RK_PINDRIVE(6, 0, 0x210, 2, 8), 313 RK_PINDRIVE(6, 0, 0x210, 3, 12), 314 315 /* GPIO6B */ 316 RK_PINDRIVE(6, 1, 0x214, 0, 2), 317 RK_PINDRIVE(6, 1, 0x214, 1, 4), 318 RK_PINDRIVE(6, 1, 0x214, 2, 8), 319 RK_PINDRIVE(6, 1, 0x214, 3, 12), 320 321 /* GPIO6C */ 322 RK_PINDRIVE(6, 2, 0x218, 0, 2), 323 RK_PINDRIVE(6, 2, 0x218, 1, 4), 324 RK_PINDRIVE(6, 2, 0x218, 2, 8), 325 RK_PINDRIVE(6, 2, 0x218, 3, 12), 326 327 /* GPIO7A */ 328 RK_PINDRIVE(7, 0, 0x220, 0, 2), 329 RK_PINDRIVE(7, 0, 0x220, 1, 4), 330 RK_PINDRIVE(7, 0, 0x220, 2, 8), 331 RK_PINDRIVE(7, 0, 0x220, 3, 12), 332 333 /* GPIO7B */ 334 RK_PINDRIVE(7, 1, 0x224, 0, 2), 335 RK_PINDRIVE(7, 1, 0x224, 1, 4), 336 RK_PINDRIVE(7, 1, 0x224, 2, 8), 337 RK_PINDRIVE(7, 1, 0x224, 3, 12), 338 339 /* GPIO7C */ 340 RK_PINDRIVE(7, 2, 0x228, 0, 2), 341 RK_PINDRIVE(7, 2, 0x228, 1, 4), 342 RK_PINDRIVE(7, 2, 0x228, 2, 8), 343 RK_PINDRIVE(7, 2, 0x228, 3, 12), 344 345 /* GPIO8A */ 346 RK_PINDRIVE(8, 0, 0x230, 0, 2), 347 RK_PINDRIVE(8, 0, 0x230, 1, 4), 348 RK_PINDRIVE(8, 0, 0x230, 2, 8), 349 RK_PINDRIVE(8, 0, 0x230, 3, 12), 350 351 /* GPIO8B */ 352 RK_PINDRIVE(8, 1, 0x234, 0, 2), 353 RK_PINDRIVE(8, 1, 0x234, 1, 4), 354 RK_PINDRIVE(8, 1, 0x234, 2, 8), 355 RK_PINDRIVE(8, 1, 0x234, 3, 12), 356 }; 357 358 static uint32_t 359 rk3288_get_pd_offset(struct rk_pinctrl_softc *sc, uint32_t bank) 360 { 361 if (bank == 0) 362 return (0x064); /* PMU */ 363 return (0x130); 364 } 365 366 static struct syscon * 367 rk3288_get_syscon(struct rk_pinctrl_softc *sc, uint32_t bank) 368 { 369 if (bank == 0) 370 return (sc->pmu); 371 return (sc->grf); 372 } 373 374 static int 375 rk3288_parse_bias(phandle_t node, int bank) 376 { 377 if (OF_hasprop(node, "bias-disable")) 378 return (0); 379 if (OF_hasprop(node, "bias-pull-up")) 380 return (1); 381 if (OF_hasprop(node, "bias-pull-down")) 382 return (2); 383 384 return (-1); 385 } 386 387 struct rk_pinctrl_conf rk3288_conf = { 388 .iomux_conf = rk3288_iomux_bank, 389 .iomux_nbanks = nitems(rk3288_iomux_bank), 390 .pin_fixup = rk3288_pin_fixup, 391 .npin_fixup = nitems(rk3288_pin_fixup), 392 .pin_drive = rk3288_pin_drive, 393 .npin_drive = nitems(rk3288_pin_drive), 394 .gpio_bank = rk3288_gpio_bank, 395 .ngpio_bank = nitems(rk3288_gpio_bank), 396 .get_pd_offset = rk3288_get_pd_offset, 397 .get_syscon = rk3288_get_syscon, 398 .parse_bias = rk3288_parse_bias, 399 }; 400 401 static struct rk_pinctrl_gpio rk3328_gpio_bank[] = { 402 RK_GPIO(0, "gpio0"), 403 RK_GPIO(1, "gpio1"), 404 RK_GPIO(2, "gpio2"), 405 RK_GPIO(3, "gpio3"), 406 }; 407 408 static struct rk_pinctrl_bank rk3328_iomux_bank[] = { 409 /* bank sub offs nbits */ 410 RK_IOMUX(0, 0, 0x0000, 2), 411 RK_IOMUX(0, 1, 0x0004, 2), 412 RK_IOMUX(0, 2, 0x0008, 2), 413 RK_IOMUX(0, 3, 0x000C, 2), 414 RK_IOMUX(1, 0, 0x0010, 2), 415 RK_IOMUX(1, 1, 0x0014, 2), 416 RK_IOMUX(1, 2, 0x0018, 2), 417 RK_IOMUX(1, 3, 0x001C, 2), 418 RK_IOMUX(2, 0, 0x0020, 2), 419 RK_IOMUX(2, 1, 0x0024, 3), 420 RK_IOMUX(2, 2, 0x002c, 3), 421 RK_IOMUX(2, 3, 0x0034, 2), 422 RK_IOMUX(3, 0, 0x0038, 3), 423 RK_IOMUX(3, 1, 0x0040, 3), 424 RK_IOMUX(3, 2, 0x0048, 2), 425 RK_IOMUX(3, 3, 0x004c, 2), 426 }; 427 428 static struct rk_pinctrl_pin_fixup rk3328_pin_fixup[] = { 429 /* bank pin reg bit mask */ 430 RK_PINFIX(2, 12, 0x24, 8, 0x300), 431 RK_PINFIX(2, 15, 0x28, 0, 0x7), 432 RK_PINFIX(2, 23, 0x30, 14, 0x6000), 433 }; 434 435 436 static struct rk_pinctrl_pin_drive rk3328_pin_drive[] = { 437 /* bank sub offs val ma */ 438 RK_PINDRIVE(0, 0, 0x200, 0, 2), 439 RK_PINDRIVE(0, 0, 0x200, 1, 4), 440 RK_PINDRIVE(0, 0, 0x200, 2, 8), 441 RK_PINDRIVE(0, 0, 0x200, 3, 12), 442 443 RK_PINDRIVE(0, 1, 0x204, 0, 2), 444 RK_PINDRIVE(0, 1, 0x204, 1, 4), 445 RK_PINDRIVE(0, 1, 0x204, 2, 8), 446 RK_PINDRIVE(0, 1, 0x204, 3, 12), 447 448 RK_PINDRIVE(0, 2, 0x208, 0, 2), 449 RK_PINDRIVE(0, 2, 0x208, 1, 4), 450 RK_PINDRIVE(0, 2, 0x208, 2, 8), 451 RK_PINDRIVE(0, 2, 0x208, 3, 12), 452 453 RK_PINDRIVE(0, 3, 0x20C, 0, 2), 454 RK_PINDRIVE(0, 3, 0x20C, 1, 4), 455 RK_PINDRIVE(0, 3, 0x20C, 2, 8), 456 RK_PINDRIVE(0, 3, 0x20C, 3, 12), 457 458 RK_PINDRIVE(1, 0, 0x210, 0, 2), 459 RK_PINDRIVE(1, 0, 0x210, 1, 4), 460 RK_PINDRIVE(1, 0, 0x210, 2, 8), 461 RK_PINDRIVE(1, 0, 0x210, 3, 12), 462 463 RK_PINDRIVE(1, 1, 0x214, 0, 2), 464 RK_PINDRIVE(1, 1, 0x214, 1, 4), 465 RK_PINDRIVE(1, 1, 0x214, 2, 8), 466 RK_PINDRIVE(1, 1, 0x214, 3, 12), 467 468 RK_PINDRIVE(1, 2, 0x218, 0, 2), 469 RK_PINDRIVE(1, 2, 0x218, 1, 4), 470 RK_PINDRIVE(1, 2, 0x218, 2, 8), 471 RK_PINDRIVE(1, 2, 0x218, 3, 12), 472 473 RK_PINDRIVE(1, 3, 0x21C, 0, 2), 474 RK_PINDRIVE(1, 3, 0x21C, 1, 4), 475 RK_PINDRIVE(1, 3, 0x21C, 2, 8), 476 RK_PINDRIVE(1, 3, 0x21C, 3, 12), 477 478 RK_PINDRIVE(2, 0, 0x220, 0, 2), 479 RK_PINDRIVE(2, 0, 0x220, 1, 4), 480 RK_PINDRIVE(2, 0, 0x220, 2, 8), 481 RK_PINDRIVE(2, 0, 0x220, 3, 12), 482 483 RK_PINDRIVE(2, 1, 0x224, 0, 2), 484 RK_PINDRIVE(2, 1, 0x224, 1, 4), 485 RK_PINDRIVE(2, 1, 0x224, 2, 8), 486 RK_PINDRIVE(2, 1, 0x224, 3, 12), 487 488 RK_PINDRIVE(2, 2, 0x228, 0, 2), 489 RK_PINDRIVE(2, 2, 0x228, 1, 4), 490 RK_PINDRIVE(2, 2, 0x228, 2, 8), 491 RK_PINDRIVE(2, 2, 0x228, 3, 12), 492 493 RK_PINDRIVE(2, 3, 0x22C, 0, 2), 494 RK_PINDRIVE(2, 3, 0x22C, 1, 4), 495 RK_PINDRIVE(2, 3, 0x22C, 2, 8), 496 RK_PINDRIVE(2, 3, 0x22C, 3, 12), 497 498 RK_PINDRIVE(3, 0, 0x230, 0, 2), 499 RK_PINDRIVE(3, 0, 0x230, 1, 4), 500 RK_PINDRIVE(3, 0, 0x230, 2, 8), 501 RK_PINDRIVE(3, 0, 0x230, 3, 12), 502 503 RK_PINDRIVE(3, 1, 0x234, 0, 2), 504 RK_PINDRIVE(3, 1, 0x234, 1, 4), 505 RK_PINDRIVE(3, 1, 0x234, 2, 8), 506 RK_PINDRIVE(3, 1, 0x234, 3, 12), 507 508 RK_PINDRIVE(3, 2, 0x238, 0, 2), 509 RK_PINDRIVE(3, 2, 0x238, 1, 4), 510 RK_PINDRIVE(3, 2, 0x238, 2, 8), 511 RK_PINDRIVE(3, 2, 0x238, 3, 12), 512 513 RK_PINDRIVE(3, 3, 0x23C, 0, 2), 514 RK_PINDRIVE(3, 3, 0x23C, 1, 4), 515 RK_PINDRIVE(3, 3, 0x23C, 2, 8), 516 RK_PINDRIVE(3, 3, 0x23C, 3, 12), 517 }; 518 519 static uint32_t 520 rk3328_get_pd_offset(struct rk_pinctrl_softc *sc, uint32_t bank) 521 { 522 return (0x100); 523 } 524 525 static struct syscon * 526 rk3328_get_syscon(struct rk_pinctrl_softc *sc, uint32_t bank) 527 { 528 return (sc->grf); 529 } 530 531 struct rk_pinctrl_conf rk3328_conf = { 532 .iomux_conf = rk3328_iomux_bank, 533 .iomux_nbanks = nitems(rk3328_iomux_bank), 534 .pin_fixup = rk3328_pin_fixup, 535 .npin_fixup = nitems(rk3328_pin_fixup), 536 .pin_drive = rk3328_pin_drive, 537 .npin_drive = nitems(rk3328_pin_drive), 538 .gpio_bank = rk3328_gpio_bank, 539 .ngpio_bank = nitems(rk3328_gpio_bank), 540 .get_pd_offset = rk3328_get_pd_offset, 541 .get_syscon = rk3328_get_syscon, 542 .parse_bias = rk3288_parse_bias, 543 }; 544 545 static struct rk_pinctrl_gpio rk3399_gpio_bank[] = { 546 RK_GPIO(0, "gpio0"), 547 RK_GPIO(1, "gpio1"), 548 RK_GPIO(2, "gpio2"), 549 RK_GPIO(3, "gpio3"), 550 RK_GPIO(4, "gpio4"), 551 }; 552 553 static struct rk_pinctrl_bank rk3399_iomux_bank[] = { 554 /* bank sub offs nbits */ 555 RK_IOMUX(0, 0, 0x0000, 2), 556 RK_IOMUX(0, 1, 0x0004, 2), 557 RK_IOMUX(0, 2, 0x0008, 2), 558 RK_IOMUX(0, 3, 0x000C, 2), 559 RK_IOMUX(1, 0, 0x0010, 2), 560 RK_IOMUX(1, 1, 0x0014, 2), 561 RK_IOMUX(1, 2, 0x0018, 2), 562 RK_IOMUX(1, 3, 0x001C, 2), 563 RK_IOMUX(2, 0, 0xE000, 2), 564 RK_IOMUX(2, 1, 0xE004, 2), 565 RK_IOMUX(2, 2, 0xE008, 2), 566 RK_IOMUX(2, 3, 0xE00C, 2), 567 RK_IOMUX(3, 0, 0xE010, 2), 568 RK_IOMUX(3, 1, 0xE014, 2), 569 RK_IOMUX(3, 2, 0xE018, 2), 570 RK_IOMUX(3, 3, 0xE01C, 2), 571 RK_IOMUX(4, 0, 0xE020, 2), 572 RK_IOMUX(4, 1, 0xE024, 2), 573 RK_IOMUX(4, 2, 0xE028, 2), 574 RK_IOMUX(4, 3, 0xE02C, 2), 575 }; 576 577 static struct rk_pinctrl_pin_fixup rk3399_pin_fixup[] = {}; 578 579 static struct rk_pinctrl_pin_drive rk3399_pin_drive[] = { 580 /* bank sub offs val ma */ 581 /* GPIO0A */ 582 RK_PINDRIVE(0, 0, 0x80, 0, 5), 583 RK_PINDRIVE(0, 0, 0x80, 1, 10), 584 RK_PINDRIVE(0, 0, 0x80, 2, 15), 585 RK_PINDRIVE(0, 0, 0x80, 3, 20), 586 587 /* GPIOB */ 588 RK_PINDRIVE(0, 1, 0x88, 0, 5), 589 RK_PINDRIVE(0, 1, 0x88, 1, 10), 590 RK_PINDRIVE(0, 1, 0x88, 2, 15), 591 RK_PINDRIVE(0, 1, 0x88, 3, 20), 592 593 /* GPIO1A */ 594 RK_PINDRIVE(1, 0, 0xA0, 0, 3), 595 RK_PINDRIVE(1, 0, 0xA0, 1, 6), 596 RK_PINDRIVE(1, 0, 0xA0, 2, 9), 597 RK_PINDRIVE(1, 0, 0xA0, 3, 12), 598 599 /* GPIO1B */ 600 RK_PINDRIVE(1, 1, 0xA8, 0, 3), 601 RK_PINDRIVE(1, 1, 0xA8, 1, 6), 602 RK_PINDRIVE(1, 1, 0xA8, 2, 9), 603 RK_PINDRIVE(1, 1, 0xA8, 3, 12), 604 605 /* GPIO1C */ 606 RK_PINDRIVE(1, 2, 0xB0, 0, 3), 607 RK_PINDRIVE(1, 2, 0xB0, 1, 6), 608 RK_PINDRIVE(1, 2, 0xB0, 2, 9), 609 RK_PINDRIVE(1, 2, 0xB0, 3, 12), 610 611 /* GPIO1D */ 612 RK_PINDRIVE(1, 3, 0xB8, 0, 3), 613 RK_PINDRIVE(1, 3, 0xB8, 1, 6), 614 RK_PINDRIVE(1, 3, 0xB8, 2, 9), 615 RK_PINDRIVE(1, 3, 0xB8, 3, 12), 616 }; 617 618 static uint32_t 619 rk3399_get_pd_offset(struct rk_pinctrl_softc *sc, uint32_t bank) 620 { 621 if (bank < 2) 622 return (0x40); 623 624 return (0xE040); 625 } 626 627 static struct syscon * 628 rk3399_get_syscon(struct rk_pinctrl_softc *sc, uint32_t bank) 629 { 630 if (bank < 2) 631 return (sc->pmu); 632 633 return (sc->grf); 634 } 635 636 static int 637 rk3399_parse_bias(phandle_t node, int bank) 638 { 639 int pullup, pulldown; 640 641 if (OF_hasprop(node, "bias-disable")) 642 return (0); 643 644 switch (bank) { 645 case 0: 646 case 2: 647 pullup = 3; 648 pulldown = 1; 649 break; 650 case 1: 651 case 3: 652 case 4: 653 pullup = 1; 654 pulldown = 2; 655 break; 656 } 657 658 if (OF_hasprop(node, "bias-pull-up")) 659 return (pullup); 660 if (OF_hasprop(node, "bias-pull-down")) 661 return (pulldown); 662 663 return (-1); 664 } 665 666 struct rk_pinctrl_conf rk3399_conf = { 667 .iomux_conf = rk3399_iomux_bank, 668 .iomux_nbanks = nitems(rk3399_iomux_bank), 669 .pin_fixup = rk3399_pin_fixup, 670 .npin_fixup = nitems(rk3399_pin_fixup), 671 .pin_drive = rk3399_pin_drive, 672 .npin_drive = nitems(rk3399_pin_drive), 673 .gpio_bank = rk3399_gpio_bank, 674 .ngpio_bank = nitems(rk3399_gpio_bank), 675 .get_pd_offset = rk3399_get_pd_offset, 676 .get_syscon = rk3399_get_syscon, 677 .parse_bias = rk3399_parse_bias, 678 }; 679 680 static struct ofw_compat_data compat_data[] = { 681 {"rockchip,rk3288-pinctrl", (uintptr_t)&rk3288_conf}, 682 {"rockchip,rk3328-pinctrl", (uintptr_t)&rk3328_conf}, 683 {"rockchip,rk3399-pinctrl", (uintptr_t)&rk3399_conf}, 684 {NULL, 0} 685 }; 686 687 static int 688 rk_pinctrl_parse_drive(struct rk_pinctrl_softc *sc, phandle_t node, 689 uint32_t bank, uint32_t subbank, uint32_t *drive, uint32_t *offset) 690 { 691 uint32_t value; 692 int i; 693 694 if (OF_getencprop(node, "drive-strength", &value, 695 sizeof(value)) != 0) 696 return (-1); 697 698 /* Map to the correct drive value */ 699 for (i = 0; i < sc->conf->npin_drive; i++) { 700 if (sc->conf->pin_drive[i].bank != bank && 701 sc->conf->pin_drive[i].subbank != subbank) 702 continue; 703 if (sc->conf->pin_drive[i].ma == value) { 704 *drive = sc->conf->pin_drive[i].value; 705 return (0); 706 } 707 } 708 709 return (-1); 710 } 711 712 static void 713 rk_pinctrl_get_fixup(struct rk_pinctrl_softc *sc, uint32_t bank, uint32_t pin, 714 uint32_t *reg, uint32_t *mask, uint32_t *bit) 715 { 716 int i; 717 718 for (i = 0; i < sc->conf->npin_fixup; i++) 719 if (sc->conf->pin_fixup[i].bank == bank && 720 sc->conf->pin_fixup[i].pin == pin) { 721 *reg = sc->conf->pin_fixup[i].reg; 722 *mask = sc->conf->pin_fixup[i].mask; 723 *bit = sc->conf->pin_fixup[i].bit; 724 725 return; 726 } 727 } 728 729 static int 730 rk_pinctrl_handle_io(struct rk_pinctrl_softc *sc, phandle_t node, uint32_t bank, 731 uint32_t pin) 732 { 733 bool have_cfg, have_direction, have_value; 734 uint32_t direction_value, pin_value; 735 struct rk_pinctrl_gpio *gpio; 736 int i, rv; 737 738 have_cfg = false; 739 have_direction = false; 740 have_value = false; 741 742 /* Get (subset of) GPIO pin properties. */ 743 if (OF_hasprop(node, "output-disable")) { 744 have_cfg = true; 745 have_direction = true; 746 direction_value = GPIO_PIN_INPUT; 747 } 748 749 if (OF_hasprop(node, "output-enable")) { 750 have_cfg = true; 751 have_direction = true; 752 direction_value = GPIO_PIN_OUTPUT; 753 } 754 755 if (OF_hasprop(node, "output-low")) { 756 have_cfg = true; 757 have_direction = true; 758 direction_value = GPIO_PIN_OUTPUT; 759 have_value = true; 760 pin_value = 0; 761 } 762 763 if (OF_hasprop(node, "output-high")) { 764 have_cfg = true; 765 have_direction = true; 766 direction_value = GPIO_PIN_OUTPUT; 767 have_value = true; 768 pin_value = 1; 769 } 770 771 if (!have_cfg) 772 return (0); 773 774 /* Find gpio */ 775 gpio = NULL; 776 for(i = 0; i < sc->conf->ngpio_bank; i++) { 777 if (bank == sc->conf->gpio_bank[i].bank) { 778 gpio = sc->conf->gpio_bank + i; 779 break; 780 } 781 } 782 if (gpio == NULL) { 783 device_printf(sc->dev, "Cannot find GPIO bank %d\n", bank); 784 return (ENXIO); 785 } 786 if (gpio->gpio_dev == NULL) { 787 device_printf(sc->dev, 788 "No GPIO subdevice found for bank %d\n", bank); 789 return (ENXIO); 790 } 791 792 rv = 0; 793 if (have_value) { 794 rv = GPIO_PIN_SET(gpio->gpio_dev, pin, pin_value); 795 if (rv != 0) { 796 device_printf(sc->dev, "Cannot set GPIO value: %d\n", 797 rv); 798 return (rv); 799 } 800 } 801 802 if (have_direction) { 803 rv = GPIO_PIN_SETFLAGS(gpio->gpio_dev, pin, direction_value); 804 if (rv != 0) { 805 device_printf(sc->dev, 806 "Cannot set GPIO direction: %d\n", rv); 807 return (rv); 808 } 809 } 810 811 return (0); 812 } 813 814 static void 815 rk_pinctrl_configure_pin(struct rk_pinctrl_softc *sc, uint32_t *pindata) 816 { 817 phandle_t pin_conf; 818 struct syscon *syscon; 819 uint32_t bank, subbank, pin, function, bias; 820 uint32_t bit, mask, reg, drive; 821 int i, rv; 822 823 bank = pindata[0]; 824 pin = pindata[1]; 825 function = pindata[2]; 826 pin_conf = OF_node_from_xref(pindata[3]); 827 subbank = pin / 8; 828 829 for (i = 0; i < sc->conf->iomux_nbanks; i++) 830 if (sc->conf->iomux_conf[i].bank == bank && 831 sc->conf->iomux_conf[i].subbank == subbank) 832 break; 833 834 if (i == sc->conf->iomux_nbanks) { 835 device_printf(sc->dev, "Unknown pin %d in bank %d\n", pin, 836 bank); 837 return; 838 } 839 840 /* Find syscon */ 841 syscon = sc->conf->get_syscon(sc, bank); 842 843 /* Parse pin function */ 844 reg = sc->conf->iomux_conf[i].offset; 845 switch (sc->conf->iomux_conf[i].nbits) { 846 case 4: 847 if ((pin % 8) >= 4) 848 reg += 0x4; 849 bit = (pin % 4) * 4; 850 mask = (0xF << bit); 851 break; 852 case 3: 853 if ((pin % 8) >= 5) 854 reg += 4; 855 bit = (pin % 8 % 5) * 3; 856 mask = (0x7 << bit); 857 break; 858 case 2: 859 bit = (pin % 8) * 2; 860 mask = (0x3 << bit); 861 break; 862 default: 863 device_printf(sc->dev, 864 "Unknown pin stride width %d in bank %d\n", 865 sc->conf->iomux_conf[i].nbits, bank); 866 return; 867 } 868 rk_pinctrl_get_fixup(sc, bank, pin, ®, &mask, &bit); 869 870 /* 871 * NOTE: not all syscon registers uses hi-word write mask, thus 872 * register modify method should be used. 873 * XXXX We should not pass write mask to syscon register 874 * without hi-word write mask. 875 */ 876 SYSCON_MODIFY_4(syscon, reg, mask, function << bit | (mask << 16)); 877 878 /* Pull-Up/Down */ 879 bias = sc->conf->parse_bias(pin_conf, bank); 880 if (bias >= 0) { 881 reg = sc->conf->get_pd_offset(sc, bank); 882 883 reg += bank * 0x10 + ((pin / 8) * 0x4); 884 bit = (pin % 8) * 2; 885 mask = (0x3 << bit) << 16; 886 SYSCON_MODIFY_4(syscon, reg, mask, bias << bit | (mask << 16)); 887 } 888 889 /* Drive Strength */ 890 rv = rk_pinctrl_parse_drive(sc, pin_conf, bank, subbank, &drive, ®); 891 if (rv == 0) { 892 bit = (pin % 8) * 2; 893 mask = (0x3 << bit) << 16; 894 SYSCON_MODIFY_4(syscon, reg, mask, drive << bit | (mask << 16)); 895 } 896 897 /* Input/Outpot + default level */ 898 rv = rk_pinctrl_handle_io(sc, pin_conf, bank, pin); 899 } 900 901 static int 902 rk_pinctrl_configure_pins(device_t dev, phandle_t cfgxref) 903 { 904 struct rk_pinctrl_softc *sc; 905 phandle_t node; 906 uint32_t *pins; 907 int i, npins; 908 909 sc = device_get_softc(dev); 910 node = OF_node_from_xref(cfgxref); 911 912 npins = OF_getencprop_alloc_multi(node, "rockchip,pins", sizeof(*pins), 913 (void **)&pins); 914 if (npins <= 0) 915 return (ENOENT); 916 917 for (i = 0; i != npins; i += 4) 918 rk_pinctrl_configure_pin(sc, pins + i); 919 920 return (0); 921 } 922 923 924 static int 925 rk_pinctrl_register_gpio(struct rk_pinctrl_softc *sc, char *gpio_name, 926 device_t gpio_dev) 927 { 928 int i; 929 930 for(i = 0; i < sc->conf->ngpio_bank; i++) { 931 if (strcmp(gpio_name, sc->conf->gpio_bank[i].gpio_name) != 0) 932 continue; 933 sc->conf->gpio_bank[i].gpio_dev = gpio_dev; 934 return(0); 935 } 936 return (ENXIO); 937 } 938 939 static int 940 rk_pinctrl_probe(device_t dev) 941 { 942 943 if (!ofw_bus_status_okay(dev)) 944 return (ENXIO); 945 946 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 947 return (ENXIO); 948 949 device_set_desc(dev, "RockChip Pinctrl controller"); 950 return (BUS_PROBE_DEFAULT); 951 } 952 953 static int 954 rk_pinctrl_attach(device_t dev) 955 { 956 struct rk_pinctrl_softc *sc; 957 phandle_t node; 958 device_t cdev; 959 char *gpio_name, *eptr; 960 int rv; 961 962 sc = device_get_softc(dev); 963 sc->dev = dev; 964 965 node = ofw_bus_get_node(dev); 966 967 if (OF_hasprop(node, "rockchip,grf") && 968 syscon_get_by_ofw_property(dev, node, 969 "rockchip,grf", &sc->grf) != 0) { 970 device_printf(dev, "cannot get grf driver handle\n"); 971 return (ENXIO); 972 } 973 974 /* RK3399,RK3288 has banks in PMU. RK3328 does not have a PMU. */ 975 if (ofw_bus_node_is_compatible(node, "rockchip,rk3399-pinctrl") || 976 ofw_bus_node_is_compatible(node, "rockchip,rk3288-pinctrl")) { 977 if (OF_hasprop(node, "rockchip,pmu") && 978 syscon_get_by_ofw_property(dev, node, 979 "rockchip,pmu", &sc->pmu) != 0) { 980 device_printf(dev, "cannot get pmu driver handle\n"); 981 return (ENXIO); 982 } 983 } 984 985 sc->conf = (struct rk_pinctrl_conf *)ofw_bus_search_compatible(dev, 986 compat_data)->ocd_data; 987 988 fdt_pinctrl_register(dev, "rockchip,pins"); 989 990 simplebus_init(dev, node); 991 992 bus_generic_probe(dev); 993 994 /* Attach child devices */ 995 for (node = OF_child(node); node > 0; node = OF_peer(node)) { 996 if (!ofw_bus_node_is_compatible(node, "rockchip,gpio-bank")) 997 continue; 998 999 rv = OF_getprop_alloc(node, "name", (void **)&gpio_name); 1000 if (rv <= 0) { 1001 device_printf(sc->dev, "Cannot GPIO subdevice name.\n"); 1002 continue; 1003 } 1004 1005 cdev = simplebus_add_device(dev, node, 0, NULL, -1, NULL); 1006 if (cdev == NULL) { 1007 device_printf(dev, " Cannot add GPIO subdevice: %s\n", 1008 gpio_name); 1009 OF_prop_free(gpio_name); 1010 continue; 1011 } 1012 1013 rv = device_probe_and_attach(cdev); 1014 if (rv != 0) { 1015 device_printf(sc->dev, 1016 "Cannot attach GPIO subdevice: %s\n", gpio_name); 1017 OF_prop_free(gpio_name); 1018 continue; 1019 } 1020 1021 /* Grep device name from name property */ 1022 eptr = gpio_name; 1023 strsep(&eptr, "@"); 1024 if (gpio_name == eptr) { 1025 device_printf(sc->dev, 1026 "Unrecognized format of GPIO subdevice name: %s\n", 1027 gpio_name); 1028 OF_prop_free(gpio_name); 1029 continue; 1030 } 1031 rv = rk_pinctrl_register_gpio(sc, gpio_name, cdev); 1032 if (rv != 0) { 1033 device_printf(sc->dev, 1034 "Cannot register GPIO subdevice %s: %d\n", 1035 gpio_name, rv); 1036 OF_prop_free(gpio_name); 1037 continue; 1038 } 1039 OF_prop_free(gpio_name); 1040 } 1041 1042 fdt_pinctrl_configure_tree(dev); 1043 1044 return (bus_generic_attach(dev)); 1045 } 1046 1047 static int 1048 rk_pinctrl_detach(device_t dev) 1049 { 1050 1051 return (EBUSY); 1052 } 1053 1054 static device_method_t rk_pinctrl_methods[] = { 1055 /* Device interface */ 1056 DEVMETHOD(device_probe, rk_pinctrl_probe), 1057 DEVMETHOD(device_attach, rk_pinctrl_attach), 1058 DEVMETHOD(device_detach, rk_pinctrl_detach), 1059 1060 /* fdt_pinctrl interface */ 1061 DEVMETHOD(fdt_pinctrl_configure, rk_pinctrl_configure_pins), 1062 1063 DEVMETHOD_END 1064 }; 1065 1066 static devclass_t rk_pinctrl_devclass; 1067 1068 DEFINE_CLASS_1(rk_pinctrl, rk_pinctrl_driver, rk_pinctrl_methods, 1069 sizeof(struct rk_pinctrl_softc), simplebus_driver); 1070 1071 EARLY_DRIVER_MODULE(rk_pinctrl, simplebus, rk_pinctrl_driver, 1072 rk_pinctrl_devclass, 0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE); 1073 MODULE_VERSION(rk_pinctrl, 1); 1074