1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2018 Emmanuel Vadot <manu@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/bus.h> 36 37 #include <sys/gpio.h> 38 #include <sys/kernel.h> 39 #include <sys/lock.h> 40 #include <sys/module.h> 41 #include <sys/mutex.h> 42 #include <sys/rman.h> 43 44 #include <machine/bus.h> 45 #include <machine/resource.h> 46 #include <machine/intr.h> 47 48 #include <dev/fdt/simplebus.h> 49 50 #include <dev/ofw/ofw_bus.h> 51 #include <dev/ofw/ofw_bus_subr.h> 52 53 #include <dev/fdt/fdt_pinctrl.h> 54 55 #include <dev/extres/syscon/syscon.h> 56 57 #include "gpio_if.h" 58 #include "syscon_if.h" 59 60 struct rk_pinctrl_pin_drive { 61 uint32_t bank; 62 uint32_t subbank; 63 uint32_t offset; 64 uint32_t value; 65 uint32_t ma; 66 }; 67 68 struct rk_pinctrl_bank { 69 uint32_t bank; 70 uint32_t subbank; 71 uint32_t offset; 72 uint32_t nbits; 73 }; 74 75 struct rk_pinctrl_pin_fixup { 76 uint32_t bank; 77 uint32_t subbank; 78 uint32_t pin; 79 uint32_t reg; 80 uint32_t bit; 81 uint32_t mask; 82 }; 83 84 struct rk_pinctrl_gpio { 85 uint32_t bank; 86 char *gpio_name; 87 device_t gpio_dev; 88 }; 89 90 91 struct rk_pinctrl_softc; 92 93 struct rk_pinctrl_conf { 94 struct rk_pinctrl_bank *iomux_conf; 95 uint32_t iomux_nbanks; 96 struct rk_pinctrl_pin_fixup *pin_fixup; 97 uint32_t npin_fixup; 98 struct rk_pinctrl_pin_drive *pin_drive; 99 uint32_t npin_drive; 100 struct rk_pinctrl_gpio *gpio_bank; 101 uint32_t ngpio_bank; 102 uint32_t (*get_pd_offset)(struct rk_pinctrl_softc *, uint32_t); 103 struct syscon *(*get_syscon)(struct rk_pinctrl_softc *, uint32_t); 104 }; 105 106 struct rk_pinctrl_softc { 107 struct simplebus_softc simplebus_sc; 108 device_t dev; 109 struct syscon *grf; 110 struct syscon *pmu; 111 struct rk_pinctrl_conf *conf; 112 }; 113 114 #define RK_IOMUX(_bank, _subbank, _offset, _nbits) \ 115 { \ 116 .bank = _bank, \ 117 .subbank = _subbank, \ 118 .offset = _offset, \ 119 .nbits = _nbits, \ 120 } 121 122 #define RK_PINFIX(_bank, _pin, _reg, _bit, _mask) \ 123 { \ 124 .bank = _bank, \ 125 .pin = _pin, \ 126 .reg = _reg, \ 127 .bit = _bit, \ 128 .mask = _mask, \ 129 } 130 131 #define RK_PINDRIVE(_bank, _subbank, _offset, _value, _ma) \ 132 { \ 133 .bank = _bank, \ 134 .subbank = _subbank, \ 135 .offset = _offset, \ 136 .value = _value, \ 137 .ma = _ma, \ 138 } 139 #define RK_GPIO(_bank, _name) \ 140 { \ 141 .bank = _bank, \ 142 .gpio_name = _name, \ 143 } 144 145 static struct rk_pinctrl_gpio rk3288_gpio_bank[] = { 146 RK_GPIO(0, "gpio0"), 147 RK_GPIO(1, "gpio1"), 148 RK_GPIO(2, "gpio2"), 149 RK_GPIO(3, "gpio3"), 150 RK_GPIO(4, "gpio4"), 151 RK_GPIO(5, "gpio5"), 152 RK_GPIO(6, "gpio6"), 153 RK_GPIO(7, "gpio7"), 154 RK_GPIO(8, "gpio8"), 155 }; 156 157 static struct rk_pinctrl_bank rk3288_iomux_bank[] = { 158 /* bank sub offs nbits */ 159 /* PMU */ 160 RK_IOMUX(0, 0, 0x0084, 2), 161 RK_IOMUX(0, 1, 0x0088, 2), 162 RK_IOMUX(0, 2, 0x008C, 2), 163 /* GFR */ 164 RK_IOMUX(1, 3, 0x000C, 2), 165 RK_IOMUX(2, 0, 0x0010, 2), 166 RK_IOMUX(2, 1, 0x0014, 2), 167 RK_IOMUX(2, 2, 0x0018, 2), 168 RK_IOMUX(2, 3, 0x001C, 2), 169 RK_IOMUX(3, 0, 0x0020, 2), 170 RK_IOMUX(3, 1, 0x0024, 2), 171 RK_IOMUX(3, 2, 0x0028, 2), 172 RK_IOMUX(3, 3, 0x002C, 4), 173 RK_IOMUX(4, 0, 0x0034, 4), 174 RK_IOMUX(4, 1, 0x003C, 4), 175 RK_IOMUX(4, 2, 0x0044, 2), 176 RK_IOMUX(4, 3, 0x0048, 2), 177 /* 5,0 - Empty */ 178 RK_IOMUX(5, 1, 0x0050, 2), 179 RK_IOMUX(5, 2, 0x0054, 2), 180 /* 5,3 - Empty */ 181 RK_IOMUX(6, 0, 0x005C, 2), 182 RK_IOMUX(6, 1, 0x0060, 2), 183 RK_IOMUX(6, 2, 0x0064, 2), 184 /* 6,3 - Empty */ 185 RK_IOMUX(7, 0, 0x006C, 2), 186 RK_IOMUX(7, 1, 0x0070, 2), 187 RK_IOMUX(7, 2, 0x0074, 4), 188 /* 7,3 - Empty */ 189 RK_IOMUX(8, 0, 0x0080, 2), 190 RK_IOMUX(8, 1, 0x0084, 2), 191 /* 8,2 - Empty */ 192 /* 8,3 - Empty */ 193 194 }; 195 196 static struct rk_pinctrl_pin_fixup rk3288_pin_fixup[] = { 197 }; 198 199 static struct rk_pinctrl_pin_drive rk3288_pin_drive[] = { 200 /* bank sub offs val ma */ 201 /* GPIO0A (PMU)*/ 202 RK_PINDRIVE(0, 0, 0x070, 0, 2), 203 RK_PINDRIVE(0, 0, 0x070, 1, 4), 204 RK_PINDRIVE(0, 0, 0x070, 2, 8), 205 RK_PINDRIVE(0, 0, 0x070, 3, 12), 206 207 /* GPIO0B (PMU)*/ 208 RK_PINDRIVE(0, 1, 0x074, 0, 2), 209 RK_PINDRIVE(0, 1, 0x074, 1, 4), 210 RK_PINDRIVE(0, 1, 0x074, 2, 8), 211 RK_PINDRIVE(0, 1, 0x074, 3, 12), 212 213 /* GPIO0C (PMU)*/ 214 RK_PINDRIVE(0, 2, 0x078, 0, 2), 215 RK_PINDRIVE(0, 2, 0x078, 1, 4), 216 RK_PINDRIVE(0, 2, 0x078, 2, 8), 217 RK_PINDRIVE(0, 2, 0x078, 3, 12), 218 219 /* GPIO1D */ 220 RK_PINDRIVE(1, 3, 0x1CC, 0, 2), 221 RK_PINDRIVE(1, 3, 0x1CC, 1, 4), 222 RK_PINDRIVE(1, 3, 0x1CC, 2, 8), 223 RK_PINDRIVE(1, 3, 0x1CC, 3, 12), 224 225 /* GPIO2A */ 226 RK_PINDRIVE(2, 0, 0x1D0, 0, 2), 227 RK_PINDRIVE(2, 0, 0x1D0, 1, 4), 228 RK_PINDRIVE(2, 0, 0x1D0, 2, 8), 229 RK_PINDRIVE(2, 0, 0x1D0, 3, 12), 230 231 /* GPIO2B */ 232 RK_PINDRIVE(2, 1, 0x1D4, 0, 2), 233 RK_PINDRIVE(2, 1, 0x1D4, 1, 4), 234 RK_PINDRIVE(2, 1, 0x1D4, 2, 8), 235 RK_PINDRIVE(2, 1, 0x1D4, 3, 12), 236 237 /* GPIO2C */ 238 RK_PINDRIVE(2, 2, 0x1D8, 0, 2), 239 RK_PINDRIVE(2, 2, 0x1D8, 1, 4), 240 RK_PINDRIVE(2, 2, 0x1D8, 2, 8), 241 RK_PINDRIVE(2, 2, 0x1D8, 3, 12), 242 243 /* GPIO2D */ 244 RK_PINDRIVE(2, 3, 0x1DC, 0, 2), 245 RK_PINDRIVE(2, 3, 0x1DC, 1, 4), 246 RK_PINDRIVE(2, 3, 0x1DC, 2, 8), 247 RK_PINDRIVE(2, 3, 0x1DC, 3, 12), 248 249 /* GPIO3A */ 250 RK_PINDRIVE(3, 0, 0x1E0, 0, 2), 251 RK_PINDRIVE(3, 0, 0x1E0, 1, 4), 252 RK_PINDRIVE(3, 0, 0x1E0, 2, 8), 253 RK_PINDRIVE(3, 0, 0x1E0, 3, 12), 254 255 /* GPIO3B */ 256 RK_PINDRIVE(3, 1, 0x1E4, 0, 2), 257 RK_PINDRIVE(3, 1, 0x1E4, 1, 4), 258 RK_PINDRIVE(3, 1, 0x1E4, 2, 8), 259 RK_PINDRIVE(3, 1, 0x1E4, 3, 12), 260 261 /* GPIO3C */ 262 RK_PINDRIVE(3, 2, 0x1E8, 0, 2), 263 RK_PINDRIVE(3, 2, 0x1E8, 1, 4), 264 RK_PINDRIVE(3, 2, 0x1E8, 2, 8), 265 RK_PINDRIVE(3, 2, 0x1E8, 3, 12), 266 267 /* GPIO3D */ 268 RK_PINDRIVE(3, 3, 0x1EC, 0, 2), 269 RK_PINDRIVE(3, 3, 0x1EC, 1, 4), 270 RK_PINDRIVE(3, 3, 0x1EC, 2, 8), 271 RK_PINDRIVE(3, 3, 0x1EC, 3, 12), 272 273 /* GPIO4A */ 274 RK_PINDRIVE(4, 0, 0x1F0, 0, 2), 275 RK_PINDRIVE(4, 0, 0x1F0, 1, 4), 276 RK_PINDRIVE(4, 0, 0x1F0, 2, 8), 277 RK_PINDRIVE(4, 0, 0x1F0, 3, 12), 278 279 /* GPIO4B */ 280 RK_PINDRIVE(4, 1, 0x1F4, 0, 2), 281 RK_PINDRIVE(4, 1, 0x1F4, 1, 4), 282 RK_PINDRIVE(4, 1, 0x1F4, 2, 8), 283 RK_PINDRIVE(4, 1, 0x1F4, 3, 12), 284 285 /* GPIO4C */ 286 RK_PINDRIVE(4, 2, 0x1F8, 0, 2), 287 RK_PINDRIVE(4, 2, 0x1F8, 1, 4), 288 RK_PINDRIVE(4, 2, 0x1F8, 2, 8), 289 RK_PINDRIVE(4, 2, 0x1F8, 3, 12), 290 291 /* GPIO4D */ 292 RK_PINDRIVE(4, 3, 0x1FC, 0, 2), 293 RK_PINDRIVE(4, 3, 0x1FC, 1, 4), 294 RK_PINDRIVE(4, 3, 0x1FC, 2, 8), 295 RK_PINDRIVE(4, 3, 0x1FC, 3, 12), 296 297 /* GPIO5B */ 298 RK_PINDRIVE(5, 1, 0x204, 0, 2), 299 RK_PINDRIVE(5, 1, 0x204, 1, 4), 300 RK_PINDRIVE(5, 1, 0x204, 2, 8), 301 RK_PINDRIVE(5, 1, 0x204, 3, 12), 302 303 /* GPIO5C */ 304 RK_PINDRIVE(5, 2, 0x208, 0, 2), 305 RK_PINDRIVE(5, 2, 0x208, 1, 4), 306 RK_PINDRIVE(5, 2, 0x208, 2, 8), 307 RK_PINDRIVE(5, 2, 0x208, 3, 12), 308 309 /* GPIO6A */ 310 RK_PINDRIVE(6, 0, 0x210, 0, 2), 311 RK_PINDRIVE(6, 0, 0x210, 1, 4), 312 RK_PINDRIVE(6, 0, 0x210, 2, 8), 313 RK_PINDRIVE(6, 0, 0x210, 3, 12), 314 315 /* GPIO6B */ 316 RK_PINDRIVE(6, 1, 0x214, 0, 2), 317 RK_PINDRIVE(6, 1, 0x214, 1, 4), 318 RK_PINDRIVE(6, 1, 0x214, 2, 8), 319 RK_PINDRIVE(6, 1, 0x214, 3, 12), 320 321 /* GPIO6C */ 322 RK_PINDRIVE(6, 2, 0x218, 0, 2), 323 RK_PINDRIVE(6, 2, 0x218, 1, 4), 324 RK_PINDRIVE(6, 2, 0x218, 2, 8), 325 RK_PINDRIVE(6, 2, 0x218, 3, 12), 326 327 /* GPIO7A */ 328 RK_PINDRIVE(7, 0, 0x220, 0, 2), 329 RK_PINDRIVE(7, 0, 0x220, 1, 4), 330 RK_PINDRIVE(7, 0, 0x220, 2, 8), 331 RK_PINDRIVE(7, 0, 0x220, 3, 12), 332 333 /* GPIO7B */ 334 RK_PINDRIVE(7, 1, 0x224, 0, 2), 335 RK_PINDRIVE(7, 1, 0x224, 1, 4), 336 RK_PINDRIVE(7, 1, 0x224, 2, 8), 337 RK_PINDRIVE(7, 1, 0x224, 3, 12), 338 339 /* GPIO7C */ 340 RK_PINDRIVE(7, 2, 0x228, 0, 2), 341 RK_PINDRIVE(7, 2, 0x228, 1, 4), 342 RK_PINDRIVE(7, 2, 0x228, 2, 8), 343 RK_PINDRIVE(7, 2, 0x228, 3, 12), 344 345 /* GPIO8A */ 346 RK_PINDRIVE(8, 0, 0x230, 0, 2), 347 RK_PINDRIVE(8, 0, 0x230, 1, 4), 348 RK_PINDRIVE(8, 0, 0x230, 2, 8), 349 RK_PINDRIVE(8, 0, 0x230, 3, 12), 350 351 /* GPIO8B */ 352 RK_PINDRIVE(8, 1, 0x234, 0, 2), 353 RK_PINDRIVE(8, 1, 0x234, 1, 4), 354 RK_PINDRIVE(8, 1, 0x234, 2, 8), 355 RK_PINDRIVE(8, 1, 0x234, 3, 12), 356 }; 357 358 static uint32_t 359 rk3288_get_pd_offset(struct rk_pinctrl_softc *sc, uint32_t bank) 360 { 361 if (bank == 0) 362 return (0x064); /* PMU */ 363 return (0x130); 364 } 365 366 static struct syscon * 367 rk3288_get_syscon(struct rk_pinctrl_softc *sc, uint32_t bank) 368 { 369 if (bank == 0) 370 return (sc->pmu); 371 return (sc->grf); 372 } 373 374 struct rk_pinctrl_conf rk3288_conf = { 375 .iomux_conf = rk3288_iomux_bank, 376 .iomux_nbanks = nitems(rk3288_iomux_bank), 377 .pin_fixup = rk3288_pin_fixup, 378 .npin_fixup = nitems(rk3288_pin_fixup), 379 .pin_drive = rk3288_pin_drive, 380 .npin_drive = nitems(rk3288_pin_drive), 381 .gpio_bank = rk3288_gpio_bank, 382 .ngpio_bank = nitems(rk3288_gpio_bank), 383 .get_pd_offset = rk3288_get_pd_offset, 384 .get_syscon = rk3288_get_syscon, 385 }; 386 387 static struct rk_pinctrl_bank rk3328_iomux_bank[] = { 388 /* bank sub offs nbits */ 389 RK_IOMUX(0, 0, 0x0000, 2), 390 RK_IOMUX(0, 1, 0x0004, 2), 391 RK_IOMUX(0, 2, 0x0008, 2), 392 RK_IOMUX(0, 3, 0x000C, 2), 393 RK_IOMUX(1, 0, 0x0010, 2), 394 RK_IOMUX(1, 1, 0x0014, 2), 395 RK_IOMUX(1, 2, 0x0018, 2), 396 RK_IOMUX(1, 3, 0x001C, 2), 397 RK_IOMUX(2, 0, 0xE000, 2), 398 RK_IOMUX(2, 1, 0xE004, 2), 399 RK_IOMUX(2, 2, 0xE008, 2), 400 RK_IOMUX(2, 3, 0xE00C, 2), 401 RK_IOMUX(3, 0, 0xE010, 2), 402 RK_IOMUX(3, 1, 0xE014, 2), 403 RK_IOMUX(3, 2, 0xE018, 2), 404 RK_IOMUX(3, 3, 0xE01C, 2), 405 RK_IOMUX(4, 0, 0xE020, 2), 406 RK_IOMUX(4, 1, 0xE024, 2), 407 RK_IOMUX(4, 2, 0xE028, 2), 408 RK_IOMUX(4, 3, 0xE02C, 2), 409 }; 410 411 static struct rk_pinctrl_pin_fixup rk3328_pin_fixup[] = { 412 /* bank pin reg bit mask */ 413 RK_PINFIX(2, 12, 0x24, 8, 0x300), 414 RK_PINFIX(2, 15, 0x28, 0, 0x7), 415 RK_PINFIX(2, 23, 0x30, 14, 0x6000), 416 }; 417 418 419 static struct rk_pinctrl_pin_drive rk3328_pin_drive[] = { 420 /* bank sub offs val ma */ 421 RK_PINDRIVE(0, 0, 0x200, 0, 2), 422 RK_PINDRIVE(0, 0, 0x200, 1, 4), 423 RK_PINDRIVE(0, 0, 0x200, 2, 8), 424 RK_PINDRIVE(0, 0, 0x200, 3, 12), 425 426 RK_PINDRIVE(0, 1, 0x204, 0, 2), 427 RK_PINDRIVE(0, 1, 0x204, 1, 4), 428 RK_PINDRIVE(0, 1, 0x204, 2, 8), 429 RK_PINDRIVE(0, 1, 0x204, 3, 12), 430 431 RK_PINDRIVE(0, 2, 0x208, 0, 2), 432 RK_PINDRIVE(0, 2, 0x208, 1, 4), 433 RK_PINDRIVE(0, 2, 0x208, 2, 8), 434 RK_PINDRIVE(0, 2, 0x208, 3, 12), 435 436 RK_PINDRIVE(0, 3, 0x20C, 0, 2), 437 RK_PINDRIVE(0, 3, 0x20C, 1, 4), 438 RK_PINDRIVE(0, 3, 0x20C, 2, 8), 439 RK_PINDRIVE(0, 3, 0x20C, 3, 12), 440 441 RK_PINDRIVE(1, 0, 0x210, 0, 2), 442 RK_PINDRIVE(1, 0, 0x210, 1, 4), 443 RK_PINDRIVE(1, 0, 0x210, 2, 8), 444 RK_PINDRIVE(1, 0, 0x210, 3, 12), 445 446 RK_PINDRIVE(1, 1, 0x214, 0, 2), 447 RK_PINDRIVE(1, 1, 0x214, 1, 4), 448 RK_PINDRIVE(1, 1, 0x214, 2, 8), 449 RK_PINDRIVE(1, 1, 0x214, 3, 12), 450 451 RK_PINDRIVE(1, 2, 0x218, 0, 2), 452 RK_PINDRIVE(1, 2, 0x218, 1, 4), 453 RK_PINDRIVE(1, 2, 0x218, 2, 8), 454 RK_PINDRIVE(1, 2, 0x218, 3, 12), 455 456 RK_PINDRIVE(1, 3, 0x21C, 0, 2), 457 RK_PINDRIVE(1, 3, 0x21C, 1, 4), 458 RK_PINDRIVE(1, 3, 0x21C, 2, 8), 459 RK_PINDRIVE(1, 3, 0x21C, 3, 12), 460 461 RK_PINDRIVE(2, 0, 0x220, 0, 2), 462 RK_PINDRIVE(2, 0, 0x220, 1, 4), 463 RK_PINDRIVE(2, 0, 0x220, 2, 8), 464 RK_PINDRIVE(2, 0, 0x220, 3, 12), 465 466 RK_PINDRIVE(2, 1, 0x224, 0, 2), 467 RK_PINDRIVE(2, 1, 0x224, 1, 4), 468 RK_PINDRIVE(2, 1, 0x224, 2, 8), 469 RK_PINDRIVE(2, 1, 0x224, 3, 12), 470 471 RK_PINDRIVE(2, 2, 0x228, 0, 2), 472 RK_PINDRIVE(2, 2, 0x228, 1, 4), 473 RK_PINDRIVE(2, 2, 0x228, 2, 8), 474 RK_PINDRIVE(2, 2, 0x228, 3, 12), 475 476 RK_PINDRIVE(2, 3, 0x22C, 0, 2), 477 RK_PINDRIVE(2, 3, 0x22C, 1, 4), 478 RK_PINDRIVE(2, 3, 0x22C, 2, 8), 479 RK_PINDRIVE(2, 3, 0x22C, 3, 12), 480 481 RK_PINDRIVE(3, 0, 0x230, 0, 2), 482 RK_PINDRIVE(3, 0, 0x230, 1, 4), 483 RK_PINDRIVE(3, 0, 0x230, 2, 8), 484 RK_PINDRIVE(3, 0, 0x230, 3, 12), 485 486 RK_PINDRIVE(3, 1, 0x234, 0, 2), 487 RK_PINDRIVE(3, 1, 0x234, 1, 4), 488 RK_PINDRIVE(3, 1, 0x234, 2, 8), 489 RK_PINDRIVE(3, 1, 0x234, 3, 12), 490 491 RK_PINDRIVE(3, 2, 0x238, 0, 2), 492 RK_PINDRIVE(3, 2, 0x238, 1, 4), 493 RK_PINDRIVE(3, 2, 0x238, 2, 8), 494 RK_PINDRIVE(3, 2, 0x238, 3, 12), 495 496 RK_PINDRIVE(3, 3, 0x23C, 0, 2), 497 RK_PINDRIVE(3, 3, 0x23C, 1, 4), 498 RK_PINDRIVE(3, 3, 0x23C, 2, 8), 499 RK_PINDRIVE(3, 3, 0x23C, 3, 12), 500 }; 501 502 static uint32_t 503 rk3328_get_pd_offset(struct rk_pinctrl_softc *sc, uint32_t bank) 504 { 505 return (0x100); 506 } 507 508 static struct syscon * 509 rk3328_get_syscon(struct rk_pinctrl_softc *sc, uint32_t bank) 510 { 511 return (sc->grf); 512 } 513 514 struct rk_pinctrl_conf rk3328_conf = { 515 .iomux_conf = rk3328_iomux_bank, 516 .iomux_nbanks = nitems(rk3328_iomux_bank), 517 .pin_fixup = rk3328_pin_fixup, 518 .npin_fixup = nitems(rk3328_pin_fixup), 519 .pin_drive = rk3328_pin_drive, 520 .npin_drive = nitems(rk3328_pin_drive), 521 .get_pd_offset = rk3328_get_pd_offset, 522 .get_syscon = rk3328_get_syscon, 523 }; 524 525 static struct rk_pinctrl_bank rk3399_iomux_bank[] = { 526 /* bank sub offs nbits */ 527 RK_IOMUX(0, 0, 0x0000, 2), 528 RK_IOMUX(0, 1, 0x0004, 2), 529 RK_IOMUX(0, 2, 0x0008, 2), 530 RK_IOMUX(0, 3, 0x000C, 2), 531 RK_IOMUX(1, 0, 0x0010, 2), 532 RK_IOMUX(1, 1, 0x0014, 2), 533 RK_IOMUX(1, 2, 0x0018, 2), 534 RK_IOMUX(1, 3, 0x000C, 2), 535 RK_IOMUX(2, 0, 0xE000, 2), 536 RK_IOMUX(2, 1, 0xE004, 2), 537 RK_IOMUX(2, 2, 0xE008, 2), 538 RK_IOMUX(2, 3, 0xE00C, 2), 539 RK_IOMUX(3, 0, 0xE010, 2), 540 RK_IOMUX(3, 1, 0xE014, 2), 541 RK_IOMUX(3, 2, 0xE018, 2), 542 RK_IOMUX(3, 3, 0xE01C, 2), 543 RK_IOMUX(4, 0, 0xE020, 2), 544 RK_IOMUX(4, 1, 0xE024, 2), 545 RK_IOMUX(4, 2, 0xE028, 2), 546 RK_IOMUX(4, 3, 0xE02C, 2), 547 }; 548 549 static struct rk_pinctrl_pin_fixup rk3399_pin_fixup[] = {}; 550 551 static struct rk_pinctrl_pin_drive rk3399_pin_drive[] = { 552 /* bank sub offs val ma */ 553 /* GPIO0A */ 554 RK_PINDRIVE(0, 0, 0x80, 0, 5), 555 RK_PINDRIVE(0, 0, 0x80, 1, 10), 556 RK_PINDRIVE(0, 0, 0x80, 2, 15), 557 RK_PINDRIVE(0, 0, 0x80, 3, 20), 558 559 /* GPIOB */ 560 RK_PINDRIVE(0, 1, 0x88, 0, 5), 561 RK_PINDRIVE(0, 1, 0x88, 1, 10), 562 RK_PINDRIVE(0, 1, 0x88, 2, 15), 563 RK_PINDRIVE(0, 1, 0x88, 3, 20), 564 565 /* GPIO1A */ 566 RK_PINDRIVE(1, 0, 0xA0, 0, 3), 567 RK_PINDRIVE(1, 0, 0xA0, 1, 6), 568 RK_PINDRIVE(1, 0, 0xA0, 2, 9), 569 RK_PINDRIVE(1, 0, 0xA0, 3, 12), 570 571 /* GPIO1B */ 572 RK_PINDRIVE(1, 1, 0xA8, 0, 3), 573 RK_PINDRIVE(1, 1, 0xA8, 1, 6), 574 RK_PINDRIVE(1, 1, 0xA8, 2, 9), 575 RK_PINDRIVE(1, 1, 0xA8, 3, 12), 576 577 /* GPIO1C */ 578 RK_PINDRIVE(1, 2, 0xB0, 0, 3), 579 RK_PINDRIVE(1, 2, 0xB0, 1, 6), 580 RK_PINDRIVE(1, 2, 0xB0, 2, 9), 581 RK_PINDRIVE(1, 2, 0xB0, 3, 12), 582 583 /* GPIO1D */ 584 RK_PINDRIVE(1, 3, 0xB8, 0, 3), 585 RK_PINDRIVE(1, 3, 0xB8, 1, 6), 586 RK_PINDRIVE(1, 3, 0xB8, 2, 9), 587 RK_PINDRIVE(1, 3, 0xB8, 3, 12), 588 }; 589 590 static uint32_t 591 rk3399_get_pd_offset(struct rk_pinctrl_softc *sc, uint32_t bank) 592 { 593 if (bank < 2) 594 return (0x40); 595 596 return (0xE040); 597 } 598 599 static struct syscon * 600 rk3399_get_syscon(struct rk_pinctrl_softc *sc, uint32_t bank) 601 { 602 if (bank < 2) 603 return (sc->pmu); 604 605 return (sc->grf); 606 } 607 608 struct rk_pinctrl_conf rk3399_conf = { 609 .iomux_conf = rk3399_iomux_bank, 610 .iomux_nbanks = nitems(rk3399_iomux_bank), 611 .pin_fixup = rk3399_pin_fixup, 612 .npin_fixup = nitems(rk3399_pin_fixup), 613 .pin_drive = rk3399_pin_drive, 614 .npin_drive = nitems(rk3399_pin_drive), 615 .get_pd_offset = rk3399_get_pd_offset, 616 .get_syscon = rk3399_get_syscon, 617 }; 618 619 static struct ofw_compat_data compat_data[] = { 620 {"rockchip,rk3288-pinctrl", (uintptr_t)&rk3288_conf}, 621 {"rockchip,rk3328-pinctrl", (uintptr_t)&rk3328_conf}, 622 {"rockchip,rk3399-pinctrl", (uintptr_t)&rk3399_conf}, 623 {NULL, 0} 624 }; 625 626 static int 627 rk_pinctrl_parse_bias(phandle_t node) 628 { 629 if (OF_hasprop(node, "bias-disable")) 630 return (0); 631 if (OF_hasprop(node, "bias-pull-up")) 632 return (1); 633 if (OF_hasprop(node, "bias-pull-down")) 634 return (2); 635 636 return (-1); 637 } 638 639 static int 640 rk_pinctrl_parse_drive(struct rk_pinctrl_softc *sc, phandle_t node, 641 uint32_t bank, uint32_t subbank, uint32_t *drive, uint32_t *offset) 642 { 643 uint32_t value; 644 int i; 645 646 if (OF_getencprop(node, "drive-strength", &value, 647 sizeof(value)) != 0) 648 return (-1); 649 650 /* Map to the correct drive value */ 651 for (i = 0; i < sc->conf->npin_drive; i++) { 652 if (sc->conf->pin_drive[i].bank != bank && 653 sc->conf->pin_drive[i].subbank != subbank) 654 continue; 655 if (sc->conf->pin_drive[i].ma == value) { 656 *drive = sc->conf->pin_drive[i].value; 657 return (0); 658 } 659 } 660 661 return (-1); 662 } 663 664 static void 665 rk_pinctrl_get_fixup(struct rk_pinctrl_softc *sc, uint32_t bank, uint32_t pin, 666 uint32_t *reg, uint32_t *mask, uint32_t *bit) 667 { 668 int i; 669 670 for (i = 0; i < sc->conf->npin_fixup; i++) 671 if (sc->conf->pin_fixup[i].bank == bank && 672 sc->conf->pin_fixup[i].pin == pin) { 673 *reg = sc->conf->pin_fixup[i].reg; 674 *mask = sc->conf->pin_fixup[i].mask; 675 *bit = sc->conf->pin_fixup[i].bit; 676 677 return; 678 } 679 } 680 681 static int 682 rk_pinctrl_handle_io(struct rk_pinctrl_softc *sc, phandle_t node, uint32_t bank, 683 uint32_t pin) 684 { 685 bool have_cfg, have_direction, have_value; 686 uint32_t direction_value, pin_value; 687 struct rk_pinctrl_gpio *gpio; 688 int i, rv; 689 690 have_cfg = false; 691 have_direction = false; 692 have_value = false; 693 694 /* Get (subset of) GPIO pin properties. */ 695 if (OF_hasprop(node, "output-disable")) { 696 have_cfg = true; 697 have_direction = true; 698 direction_value = GPIO_PIN_INPUT; 699 } 700 701 if (OF_hasprop(node, "output-enable")) { 702 have_cfg = true; 703 have_direction = true; 704 direction_value = GPIO_PIN_OUTPUT; 705 } 706 707 if (OF_hasprop(node, "output-low")) { 708 have_cfg = true; 709 have_direction = true; 710 direction_value = GPIO_PIN_OUTPUT; 711 have_value = true; 712 pin_value = 0; 713 } 714 715 if (OF_hasprop(node, "output-high")) { 716 have_cfg = true; 717 have_direction = true; 718 direction_value = GPIO_PIN_OUTPUT; 719 have_value = true; 720 pin_value = 1; 721 } 722 723 if (!have_cfg) 724 return (0); 725 726 /* Find gpio */ 727 gpio = NULL; 728 for(i = 0; i < sc->conf->ngpio_bank; i++) { 729 if (bank == sc->conf->gpio_bank[i].bank) { 730 gpio = sc->conf->gpio_bank + i; 731 break; 732 } 733 } 734 if (gpio == NULL) { 735 device_printf(sc->dev, "Cannot find GPIO bank %d\n", bank); 736 return (ENXIO); 737 } 738 if (gpio->gpio_dev == NULL) { 739 device_printf(sc->dev, 740 "No GPIO subdevice found for bank %d\n", bank); 741 return (ENXIO); 742 } 743 744 rv = 0; 745 if (have_value) { 746 rv = GPIO_PIN_SET(gpio->gpio_dev, pin, pin_value); 747 if (rv != 0) { 748 device_printf(sc->dev, "Cannot set GPIO value: %d\n", 749 rv); 750 return (rv); 751 } 752 } 753 754 if (have_direction) { 755 rv = GPIO_PIN_SETFLAGS(gpio->gpio_dev, pin, direction_value); 756 if (rv != 0) { 757 device_printf(sc->dev, 758 "Cannot set GPIO direction: %d\n", rv); 759 return (rv); 760 } 761 } 762 763 return (0); 764 } 765 766 static void 767 rk_pinctrl_configure_pin(struct rk_pinctrl_softc *sc, uint32_t *pindata) 768 { 769 phandle_t pin_conf; 770 struct syscon *syscon; 771 uint32_t bank, subbank, pin, function, bias; 772 uint32_t bit, mask, reg, drive; 773 int i, rv; 774 775 bank = pindata[0]; 776 pin = pindata[1]; 777 function = pindata[2]; 778 pin_conf = OF_node_from_xref(pindata[3]); 779 subbank = pin / 8; 780 781 for (i = 0; i < sc->conf->iomux_nbanks; i++) 782 if (sc->conf->iomux_conf[i].bank == bank && 783 sc->conf->iomux_conf[i].subbank == subbank) 784 break; 785 786 if (i == sc->conf->iomux_nbanks) { 787 device_printf(sc->dev, "Unknown pin %d in bank %d\n", pin, 788 bank); 789 return; 790 } 791 792 /* Find syscon */ 793 syscon = sc->conf->get_syscon(sc, bank); 794 795 /* Parse pin function */ 796 reg = sc->conf->iomux_conf[i].offset; 797 switch (sc->conf->iomux_conf[i].nbits) { 798 case 4: 799 if ((pin % 8) >= 4) 800 reg += 0x4; 801 bit = (pin % 4) * 4; 802 mask = (0xF << bit); 803 break; 804 case 3: 805 if ((pin % 8) >= 5) 806 reg += 4; 807 bit = (pin % 8 % 5) * 3; 808 mask = (0x7 << bit); 809 break; 810 case 2: 811 bit = (pin % 8) * 2; 812 mask = (0x3 << bit); 813 break; 814 default: 815 device_printf(sc->dev, 816 "Unknown pin stride width %d in bank %d\n", 817 sc->conf->iomux_conf[i].nbits, bank); 818 return; 819 } 820 rk_pinctrl_get_fixup(sc, bank, pin, ®, &mask, &bit); 821 822 /* 823 * NOTE: not all syscon registers uses hi-word write mask, thus 824 * register modify method should be used. 825 * XXXX We should not pass write mask to syscon register 826 * without hi-word write mask. 827 */ 828 SYSCON_MODIFY_4(syscon, reg, mask, function << bit | (mask << 16)); 829 830 /* Pull-Up/Down */ 831 bias = rk_pinctrl_parse_bias(pin_conf); 832 if (bias >= 0) { 833 reg = sc->conf->get_pd_offset(sc, bank); 834 835 reg += bank * 0x10 + ((pin / 8) * 0x4); 836 bit = (pin % 8) * 2; 837 mask = (0x3 << bit) << 16; 838 SYSCON_MODIFY_4(syscon, reg, mask, bias << bit | (mask << 16)); 839 } 840 841 /* Drive Strength */ 842 rv = rk_pinctrl_parse_drive(sc, pin_conf, bank, subbank, &drive, ®); 843 if (rv == 0) { 844 bit = (pin % 8) * 2; 845 mask = (0x3 << bit) << 16; 846 SYSCON_MODIFY_4(syscon, reg, mask, drive << bit | (mask << 16)); 847 } 848 849 /* Input/Outpot + default level */ 850 rv = rk_pinctrl_handle_io(sc, pin_conf, bank, pin); 851 } 852 853 static int 854 rk_pinctrl_configure_pins(device_t dev, phandle_t cfgxref) 855 { 856 struct rk_pinctrl_softc *sc; 857 phandle_t node; 858 uint32_t *pins; 859 int i, npins; 860 861 sc = device_get_softc(dev); 862 node = OF_node_from_xref(cfgxref); 863 864 npins = OF_getencprop_alloc_multi(node, "rockchip,pins", sizeof(*pins), 865 (void **)&pins); 866 if (npins <= 0) 867 return (ENOENT); 868 869 for (i = 0; i != npins; i += 4) 870 rk_pinctrl_configure_pin(sc, pins + i); 871 872 return (0); 873 } 874 875 876 static int 877 rk_pinctrl_register_gpio(struct rk_pinctrl_softc *sc, char *gpio_name, 878 device_t gpio_dev) 879 { 880 int i; 881 882 for(i = 0; i < sc->conf->ngpio_bank; i++) { 883 if (strcmp(gpio_name, sc->conf->gpio_bank[i].gpio_name) != 0) 884 continue; 885 sc->conf->gpio_bank[i].gpio_dev = gpio_dev; 886 return(0); 887 } 888 return (ENXIO); 889 } 890 891 static int 892 rk_pinctrl_probe(device_t dev) 893 { 894 895 if (!ofw_bus_status_okay(dev)) 896 return (ENXIO); 897 898 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 899 return (ENXIO); 900 901 device_set_desc(dev, "RockChip Pinctrl controller"); 902 return (BUS_PROBE_DEFAULT); 903 } 904 905 static int 906 rk_pinctrl_attach(device_t dev) 907 { 908 struct rk_pinctrl_softc *sc; 909 phandle_t node; 910 device_t cdev; 911 char *gpio_name, *eptr; 912 int rv; 913 914 sc = device_get_softc(dev); 915 sc->dev = dev; 916 917 node = ofw_bus_get_node(dev); 918 919 if (OF_hasprop(node, "rockchip,grf") && 920 syscon_get_by_ofw_property(dev, node, 921 "rockchip,grf", &sc->grf) != 0) { 922 device_printf(dev, "cannot get grf driver handle\n"); 923 return (ENXIO); 924 } 925 926 /* RK3399,RK3288 has banks in PMU. RK3328 does not have a PMU. */ 927 if (ofw_bus_node_is_compatible(node, "rockchip,rk3399-pinctrl") || 928 ofw_bus_node_is_compatible(node, "rockchip,rk3288-pinctrl")) { 929 if (OF_hasprop(node, "rockchip,pmu") && 930 syscon_get_by_ofw_property(dev, node, 931 "rockchip,pmu", &sc->pmu) != 0) { 932 device_printf(dev, "cannot get pmu driver handle\n"); 933 return (ENXIO); 934 } 935 } 936 937 sc->conf = (struct rk_pinctrl_conf *)ofw_bus_search_compatible(dev, 938 compat_data)->ocd_data; 939 940 fdt_pinctrl_register(dev, "rockchip,pins"); 941 942 simplebus_init(dev, node); 943 944 bus_generic_probe(dev); 945 946 /* Attach child devices */ 947 for (node = OF_child(node); node > 0; node = OF_peer(node)) { 948 if (!ofw_bus_node_is_compatible(node, "rockchip,gpio-bank")) 949 continue; 950 951 rv = OF_getprop_alloc(node, "name", (void **)&gpio_name); 952 if (rv <= 0) { 953 device_printf(sc->dev, "Cannot GPIO subdevice name.\n"); 954 continue; 955 } 956 957 cdev = simplebus_add_device(dev, node, 0, NULL, -1, NULL); 958 if (cdev == NULL) { 959 device_printf(dev, " Cannot add GPIO subdevice: %s\n", 960 gpio_name); 961 OF_prop_free(gpio_name); 962 continue; 963 } 964 965 rv = device_probe_and_attach(cdev); 966 if (rv != 0) { 967 device_printf(sc->dev, 968 "Cannot attach GPIO subdevice: %s\n", gpio_name); 969 OF_prop_free(gpio_name); 970 continue; 971 } 972 973 /* Grep device name from name property */ 974 eptr = gpio_name; 975 strsep(&eptr, "@"); 976 if (gpio_name == eptr) { 977 device_printf(sc->dev, 978 "Unrecognized format of GPIO subdevice name: %s\n", 979 gpio_name); 980 OF_prop_free(gpio_name); 981 continue; 982 } 983 rv = rk_pinctrl_register_gpio(sc, gpio_name, cdev); 984 if (rv != 0) { 985 device_printf(sc->dev, 986 "Cannot register GPIO subdevice %s: %d\n", 987 gpio_name, rv); 988 OF_prop_free(gpio_name); 989 continue; 990 } 991 OF_prop_free(gpio_name); 992 } 993 994 fdt_pinctrl_configure_tree(dev); 995 996 return (bus_generic_attach(dev)); 997 } 998 999 static int 1000 rk_pinctrl_detach(device_t dev) 1001 { 1002 1003 return (EBUSY); 1004 } 1005 1006 static device_method_t rk_pinctrl_methods[] = { 1007 /* Device interface */ 1008 DEVMETHOD(device_probe, rk_pinctrl_probe), 1009 DEVMETHOD(device_attach, rk_pinctrl_attach), 1010 DEVMETHOD(device_detach, rk_pinctrl_detach), 1011 1012 /* fdt_pinctrl interface */ 1013 DEVMETHOD(fdt_pinctrl_configure, rk_pinctrl_configure_pins), 1014 1015 DEVMETHOD_END 1016 }; 1017 1018 static devclass_t rk_pinctrl_devclass; 1019 1020 DEFINE_CLASS_1(rk_pinctrl, rk_pinctrl_driver, rk_pinctrl_methods, 1021 sizeof(struct rk_pinctrl_softc), simplebus_driver); 1022 1023 EARLY_DRIVER_MODULE(rk_pinctrl, simplebus, rk_pinctrl_driver, 1024 rk_pinctrl_devclass, 0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE); 1025 MODULE_VERSION(rk_pinctrl, 1); 1026