1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2018 Emmanuel Vadot <manu@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/bus.h> 35 36 #include <sys/gpio.h> 37 #include <sys/kernel.h> 38 #include <sys/lock.h> 39 #include <sys/module.h> 40 #include <sys/mutex.h> 41 #include <sys/rman.h> 42 43 #include <machine/bus.h> 44 #include <machine/resource.h> 45 #include <machine/intr.h> 46 47 #include <dev/fdt/simplebus.h> 48 49 #include <dev/ofw/ofw_bus.h> 50 #include <dev/ofw/ofw_bus_subr.h> 51 52 #include <dev/fdt/fdt_pinctrl.h> 53 54 #include <dev/extres/syscon/syscon.h> 55 56 #include "gpio_if.h" 57 #include "syscon_if.h" 58 #include "fdt_pinctrl_if.h" 59 60 struct rk_pinctrl_pin_drive { 61 uint32_t bank; 62 uint32_t subbank; 63 uint32_t offset; 64 uint32_t value; 65 uint32_t ma; 66 }; 67 68 struct rk_pinctrl_bank { 69 uint32_t bank; 70 uint32_t subbank; 71 uint32_t offset; 72 uint32_t nbits; 73 }; 74 75 struct rk_pinctrl_pin_fixup { 76 uint32_t bank; 77 uint32_t subbank; 78 uint32_t pin; 79 uint32_t reg; 80 uint32_t bit; 81 uint32_t mask; 82 }; 83 84 struct rk_pinctrl_gpio { 85 uint32_t bank; 86 char *gpio_name; 87 device_t gpio_dev; 88 }; 89 90 91 struct rk_pinctrl_softc; 92 93 struct rk_pinctrl_conf { 94 struct rk_pinctrl_bank *iomux_conf; 95 uint32_t iomux_nbanks; 96 struct rk_pinctrl_pin_fixup *pin_fixup; 97 uint32_t npin_fixup; 98 struct rk_pinctrl_pin_drive *pin_drive; 99 uint32_t npin_drive; 100 struct rk_pinctrl_gpio *gpio_bank; 101 uint32_t ngpio_bank; 102 uint32_t (*get_pd_offset)(struct rk_pinctrl_softc *, uint32_t); 103 struct syscon *(*get_syscon)(struct rk_pinctrl_softc *, uint32_t); 104 int (*parse_bias)(phandle_t, int); 105 int (*resolv_bias_value)(int, int); 106 int (*get_bias_value)(int, int); 107 }; 108 109 struct rk_pinctrl_softc { 110 struct simplebus_softc simplebus_sc; 111 device_t dev; 112 struct syscon *grf; 113 struct syscon *pmu; 114 struct rk_pinctrl_conf *conf; 115 struct mtx mtx; 116 }; 117 118 #define RK_PINCTRL_LOCK(_sc) mtx_lock_spin(&(_sc)->mtx) 119 #define RK_PINCTRL_UNLOCK(_sc) mtx_unlock_spin(&(_sc)->mtx) 120 #define RK_PINCTRL_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->mtx, MA_OWNED) 121 122 #define RK_IOMUX(_bank, _subbank, _offset, _nbits) \ 123 { \ 124 .bank = _bank, \ 125 .subbank = _subbank, \ 126 .offset = _offset, \ 127 .nbits = _nbits, \ 128 } 129 130 #define RK_PINFIX(_bank, _pin, _reg, _bit, _mask) \ 131 { \ 132 .bank = _bank, \ 133 .pin = _pin, \ 134 .reg = _reg, \ 135 .bit = _bit, \ 136 .mask = _mask, \ 137 } 138 139 #define RK_PINDRIVE(_bank, _subbank, _offset, _value, _ma) \ 140 { \ 141 .bank = _bank, \ 142 .subbank = _subbank, \ 143 .offset = _offset, \ 144 .value = _value, \ 145 .ma = _ma, \ 146 } 147 #define RK_GPIO(_bank, _name) \ 148 { \ 149 .bank = _bank, \ 150 .gpio_name = _name, \ 151 } 152 153 static struct rk_pinctrl_gpio rk3288_gpio_bank[] = { 154 RK_GPIO(0, "gpio0"), 155 RK_GPIO(1, "gpio1"), 156 RK_GPIO(2, "gpio2"), 157 RK_GPIO(3, "gpio3"), 158 RK_GPIO(4, "gpio4"), 159 RK_GPIO(5, "gpio5"), 160 RK_GPIO(6, "gpio6"), 161 RK_GPIO(7, "gpio7"), 162 RK_GPIO(8, "gpio8"), 163 }; 164 165 static struct rk_pinctrl_bank rk3288_iomux_bank[] = { 166 /* bank sub offs nbits */ 167 /* PMU */ 168 RK_IOMUX(0, 0, 0x0084, 2), 169 RK_IOMUX(0, 1, 0x0088, 2), 170 RK_IOMUX(0, 2, 0x008C, 2), 171 /* GFR */ 172 RK_IOMUX(1, 3, 0x000C, 2), 173 RK_IOMUX(2, 0, 0x0010, 2), 174 RK_IOMUX(2, 1, 0x0014, 2), 175 RK_IOMUX(2, 2, 0x0018, 2), 176 RK_IOMUX(2, 3, 0x001C, 2), 177 RK_IOMUX(3, 0, 0x0020, 2), 178 RK_IOMUX(3, 1, 0x0024, 2), 179 RK_IOMUX(3, 2, 0x0028, 2), 180 RK_IOMUX(3, 3, 0x002C, 4), 181 RK_IOMUX(4, 0, 0x0034, 4), 182 RK_IOMUX(4, 1, 0x003C, 4), 183 RK_IOMUX(4, 2, 0x0044, 2), 184 RK_IOMUX(4, 3, 0x0048, 2), 185 /* 5,0 - Empty */ 186 RK_IOMUX(5, 1, 0x0050, 2), 187 RK_IOMUX(5, 2, 0x0054, 2), 188 /* 5,3 - Empty */ 189 RK_IOMUX(6, 0, 0x005C, 2), 190 RK_IOMUX(6, 1, 0x0060, 2), 191 RK_IOMUX(6, 2, 0x0064, 2), 192 /* 6,3 - Empty */ 193 RK_IOMUX(7, 0, 0x006C, 2), 194 RK_IOMUX(7, 1, 0x0070, 2), 195 RK_IOMUX(7, 2, 0x0074, 4), 196 /* 7,3 - Empty */ 197 RK_IOMUX(8, 0, 0x0080, 2), 198 RK_IOMUX(8, 1, 0x0084, 2), 199 /* 8,2 - Empty */ 200 /* 8,3 - Empty */ 201 202 }; 203 204 static struct rk_pinctrl_pin_fixup rk3288_pin_fixup[] = { 205 }; 206 207 static struct rk_pinctrl_pin_drive rk3288_pin_drive[] = { 208 /* bank sub offs val ma */ 209 /* GPIO0A (PMU)*/ 210 RK_PINDRIVE(0, 0, 0x070, 0, 2), 211 RK_PINDRIVE(0, 0, 0x070, 1, 4), 212 RK_PINDRIVE(0, 0, 0x070, 2, 8), 213 RK_PINDRIVE(0, 0, 0x070, 3, 12), 214 215 /* GPIO0B (PMU)*/ 216 RK_PINDRIVE(0, 1, 0x074, 0, 2), 217 RK_PINDRIVE(0, 1, 0x074, 1, 4), 218 RK_PINDRIVE(0, 1, 0x074, 2, 8), 219 RK_PINDRIVE(0, 1, 0x074, 3, 12), 220 221 /* GPIO0C (PMU)*/ 222 RK_PINDRIVE(0, 2, 0x078, 0, 2), 223 RK_PINDRIVE(0, 2, 0x078, 1, 4), 224 RK_PINDRIVE(0, 2, 0x078, 2, 8), 225 RK_PINDRIVE(0, 2, 0x078, 3, 12), 226 227 /* GPIO1D */ 228 RK_PINDRIVE(1, 3, 0x1CC, 0, 2), 229 RK_PINDRIVE(1, 3, 0x1CC, 1, 4), 230 RK_PINDRIVE(1, 3, 0x1CC, 2, 8), 231 RK_PINDRIVE(1, 3, 0x1CC, 3, 12), 232 233 /* GPIO2A */ 234 RK_PINDRIVE(2, 0, 0x1D0, 0, 2), 235 RK_PINDRIVE(2, 0, 0x1D0, 1, 4), 236 RK_PINDRIVE(2, 0, 0x1D0, 2, 8), 237 RK_PINDRIVE(2, 0, 0x1D0, 3, 12), 238 239 /* GPIO2B */ 240 RK_PINDRIVE(2, 1, 0x1D4, 0, 2), 241 RK_PINDRIVE(2, 1, 0x1D4, 1, 4), 242 RK_PINDRIVE(2, 1, 0x1D4, 2, 8), 243 RK_PINDRIVE(2, 1, 0x1D4, 3, 12), 244 245 /* GPIO2C */ 246 RK_PINDRIVE(2, 2, 0x1D8, 0, 2), 247 RK_PINDRIVE(2, 2, 0x1D8, 1, 4), 248 RK_PINDRIVE(2, 2, 0x1D8, 2, 8), 249 RK_PINDRIVE(2, 2, 0x1D8, 3, 12), 250 251 /* GPIO2D */ 252 RK_PINDRIVE(2, 3, 0x1DC, 0, 2), 253 RK_PINDRIVE(2, 3, 0x1DC, 1, 4), 254 RK_PINDRIVE(2, 3, 0x1DC, 2, 8), 255 RK_PINDRIVE(2, 3, 0x1DC, 3, 12), 256 257 /* GPIO3A */ 258 RK_PINDRIVE(3, 0, 0x1E0, 0, 2), 259 RK_PINDRIVE(3, 0, 0x1E0, 1, 4), 260 RK_PINDRIVE(3, 0, 0x1E0, 2, 8), 261 RK_PINDRIVE(3, 0, 0x1E0, 3, 12), 262 263 /* GPIO3B */ 264 RK_PINDRIVE(3, 1, 0x1E4, 0, 2), 265 RK_PINDRIVE(3, 1, 0x1E4, 1, 4), 266 RK_PINDRIVE(3, 1, 0x1E4, 2, 8), 267 RK_PINDRIVE(3, 1, 0x1E4, 3, 12), 268 269 /* GPIO3C */ 270 RK_PINDRIVE(3, 2, 0x1E8, 0, 2), 271 RK_PINDRIVE(3, 2, 0x1E8, 1, 4), 272 RK_PINDRIVE(3, 2, 0x1E8, 2, 8), 273 RK_PINDRIVE(3, 2, 0x1E8, 3, 12), 274 275 /* GPIO3D */ 276 RK_PINDRIVE(3, 3, 0x1EC, 0, 2), 277 RK_PINDRIVE(3, 3, 0x1EC, 1, 4), 278 RK_PINDRIVE(3, 3, 0x1EC, 2, 8), 279 RK_PINDRIVE(3, 3, 0x1EC, 3, 12), 280 281 /* GPIO4A */ 282 RK_PINDRIVE(4, 0, 0x1F0, 0, 2), 283 RK_PINDRIVE(4, 0, 0x1F0, 1, 4), 284 RK_PINDRIVE(4, 0, 0x1F0, 2, 8), 285 RK_PINDRIVE(4, 0, 0x1F0, 3, 12), 286 287 /* GPIO4B */ 288 RK_PINDRIVE(4, 1, 0x1F4, 0, 2), 289 RK_PINDRIVE(4, 1, 0x1F4, 1, 4), 290 RK_PINDRIVE(4, 1, 0x1F4, 2, 8), 291 RK_PINDRIVE(4, 1, 0x1F4, 3, 12), 292 293 /* GPIO4C */ 294 RK_PINDRIVE(4, 2, 0x1F8, 0, 2), 295 RK_PINDRIVE(4, 2, 0x1F8, 1, 4), 296 RK_PINDRIVE(4, 2, 0x1F8, 2, 8), 297 RK_PINDRIVE(4, 2, 0x1F8, 3, 12), 298 299 /* GPIO4D */ 300 RK_PINDRIVE(4, 3, 0x1FC, 0, 2), 301 RK_PINDRIVE(4, 3, 0x1FC, 1, 4), 302 RK_PINDRIVE(4, 3, 0x1FC, 2, 8), 303 RK_PINDRIVE(4, 3, 0x1FC, 3, 12), 304 305 /* GPIO5B */ 306 RK_PINDRIVE(5, 1, 0x204, 0, 2), 307 RK_PINDRIVE(5, 1, 0x204, 1, 4), 308 RK_PINDRIVE(5, 1, 0x204, 2, 8), 309 RK_PINDRIVE(5, 1, 0x204, 3, 12), 310 311 /* GPIO5C */ 312 RK_PINDRIVE(5, 2, 0x208, 0, 2), 313 RK_PINDRIVE(5, 2, 0x208, 1, 4), 314 RK_PINDRIVE(5, 2, 0x208, 2, 8), 315 RK_PINDRIVE(5, 2, 0x208, 3, 12), 316 317 /* GPIO6A */ 318 RK_PINDRIVE(6, 0, 0x210, 0, 2), 319 RK_PINDRIVE(6, 0, 0x210, 1, 4), 320 RK_PINDRIVE(6, 0, 0x210, 2, 8), 321 RK_PINDRIVE(6, 0, 0x210, 3, 12), 322 323 /* GPIO6B */ 324 RK_PINDRIVE(6, 1, 0x214, 0, 2), 325 RK_PINDRIVE(6, 1, 0x214, 1, 4), 326 RK_PINDRIVE(6, 1, 0x214, 2, 8), 327 RK_PINDRIVE(6, 1, 0x214, 3, 12), 328 329 /* GPIO6C */ 330 RK_PINDRIVE(6, 2, 0x218, 0, 2), 331 RK_PINDRIVE(6, 2, 0x218, 1, 4), 332 RK_PINDRIVE(6, 2, 0x218, 2, 8), 333 RK_PINDRIVE(6, 2, 0x218, 3, 12), 334 335 /* GPIO7A */ 336 RK_PINDRIVE(7, 0, 0x220, 0, 2), 337 RK_PINDRIVE(7, 0, 0x220, 1, 4), 338 RK_PINDRIVE(7, 0, 0x220, 2, 8), 339 RK_PINDRIVE(7, 0, 0x220, 3, 12), 340 341 /* GPIO7B */ 342 RK_PINDRIVE(7, 1, 0x224, 0, 2), 343 RK_PINDRIVE(7, 1, 0x224, 1, 4), 344 RK_PINDRIVE(7, 1, 0x224, 2, 8), 345 RK_PINDRIVE(7, 1, 0x224, 3, 12), 346 347 /* GPIO7C */ 348 RK_PINDRIVE(7, 2, 0x228, 0, 2), 349 RK_PINDRIVE(7, 2, 0x228, 1, 4), 350 RK_PINDRIVE(7, 2, 0x228, 2, 8), 351 RK_PINDRIVE(7, 2, 0x228, 3, 12), 352 353 /* GPIO8A */ 354 RK_PINDRIVE(8, 0, 0x230, 0, 2), 355 RK_PINDRIVE(8, 0, 0x230, 1, 4), 356 RK_PINDRIVE(8, 0, 0x230, 2, 8), 357 RK_PINDRIVE(8, 0, 0x230, 3, 12), 358 359 /* GPIO8B */ 360 RK_PINDRIVE(8, 1, 0x234, 0, 2), 361 RK_PINDRIVE(8, 1, 0x234, 1, 4), 362 RK_PINDRIVE(8, 1, 0x234, 2, 8), 363 RK_PINDRIVE(8, 1, 0x234, 3, 12), 364 }; 365 366 static uint32_t 367 rk3288_get_pd_offset(struct rk_pinctrl_softc *sc, uint32_t bank) 368 { 369 if (bank == 0) 370 return (0x064); /* PMU */ 371 return (0x130); 372 } 373 374 static struct syscon * 375 rk3288_get_syscon(struct rk_pinctrl_softc *sc, uint32_t bank) 376 { 377 if (bank == 0) 378 return (sc->pmu); 379 return (sc->grf); 380 } 381 382 static int 383 rk3288_parse_bias(phandle_t node, int bank) 384 { 385 if (OF_hasprop(node, "bias-disable")) 386 return (0); 387 if (OF_hasprop(node, "bias-pull-up")) 388 return (1); 389 if (OF_hasprop(node, "bias-pull-down")) 390 return (2); 391 392 return (-1); 393 } 394 395 static int 396 rk3288_resolv_bias_value(int bank, int bias) 397 { 398 int rv = 0; 399 400 if (bias == 1) 401 rv = GPIO_PIN_PULLUP; 402 else if (bias == 2) 403 rv = GPIO_PIN_PULLDOWN; 404 405 return (rv); 406 } 407 408 static int 409 rk3288_get_bias_value(int bank, int bias) 410 { 411 int rv = 0; 412 413 if (bias & GPIO_PIN_PULLUP) 414 rv = 1; 415 else if (bias & GPIO_PIN_PULLDOWN) 416 rv = 2; 417 418 return (rv); 419 } 420 421 struct rk_pinctrl_conf rk3288_conf = { 422 .iomux_conf = rk3288_iomux_bank, 423 .iomux_nbanks = nitems(rk3288_iomux_bank), 424 .pin_fixup = rk3288_pin_fixup, 425 .npin_fixup = nitems(rk3288_pin_fixup), 426 .pin_drive = rk3288_pin_drive, 427 .npin_drive = nitems(rk3288_pin_drive), 428 .gpio_bank = rk3288_gpio_bank, 429 .ngpio_bank = nitems(rk3288_gpio_bank), 430 .get_pd_offset = rk3288_get_pd_offset, 431 .get_syscon = rk3288_get_syscon, 432 .parse_bias = rk3288_parse_bias, 433 .resolv_bias_value = rk3288_resolv_bias_value, 434 .get_bias_value = rk3288_get_bias_value, 435 }; 436 437 static struct rk_pinctrl_gpio rk3328_gpio_bank[] = { 438 RK_GPIO(0, "gpio0"), 439 RK_GPIO(1, "gpio1"), 440 RK_GPIO(2, "gpio2"), 441 RK_GPIO(3, "gpio3"), 442 }; 443 444 static struct rk_pinctrl_bank rk3328_iomux_bank[] = { 445 /* bank sub offs nbits */ 446 RK_IOMUX(0, 0, 0x0000, 2), 447 RK_IOMUX(0, 1, 0x0004, 2), 448 RK_IOMUX(0, 2, 0x0008, 2), 449 RK_IOMUX(0, 3, 0x000C, 2), 450 RK_IOMUX(1, 0, 0x0010, 2), 451 RK_IOMUX(1, 1, 0x0014, 2), 452 RK_IOMUX(1, 2, 0x0018, 2), 453 RK_IOMUX(1, 3, 0x001C, 2), 454 RK_IOMUX(2, 0, 0x0020, 2), 455 RK_IOMUX(2, 1, 0x0024, 3), 456 RK_IOMUX(2, 2, 0x002c, 3), 457 RK_IOMUX(2, 3, 0x0034, 2), 458 RK_IOMUX(3, 0, 0x0038, 3), 459 RK_IOMUX(3, 1, 0x0040, 3), 460 RK_IOMUX(3, 2, 0x0048, 2), 461 RK_IOMUX(3, 3, 0x004c, 2), 462 }; 463 464 static struct rk_pinctrl_pin_fixup rk3328_pin_fixup[] = { 465 /* bank pin reg bit mask */ 466 RK_PINFIX(2, 12, 0x24, 8, 0x300), 467 RK_PINFIX(2, 15, 0x28, 0, 0x7), 468 RK_PINFIX(2, 23, 0x30, 14, 0x6000), 469 }; 470 471 472 static struct rk_pinctrl_pin_drive rk3328_pin_drive[] = { 473 /* bank sub offs val ma */ 474 RK_PINDRIVE(0, 0, 0x200, 0, 2), 475 RK_PINDRIVE(0, 0, 0x200, 1, 4), 476 RK_PINDRIVE(0, 0, 0x200, 2, 8), 477 RK_PINDRIVE(0, 0, 0x200, 3, 12), 478 479 RK_PINDRIVE(0, 1, 0x204, 0, 2), 480 RK_PINDRIVE(0, 1, 0x204, 1, 4), 481 RK_PINDRIVE(0, 1, 0x204, 2, 8), 482 RK_PINDRIVE(0, 1, 0x204, 3, 12), 483 484 RK_PINDRIVE(0, 2, 0x208, 0, 2), 485 RK_PINDRIVE(0, 2, 0x208, 1, 4), 486 RK_PINDRIVE(0, 2, 0x208, 2, 8), 487 RK_PINDRIVE(0, 2, 0x208, 3, 12), 488 489 RK_PINDRIVE(0, 3, 0x20C, 0, 2), 490 RK_PINDRIVE(0, 3, 0x20C, 1, 4), 491 RK_PINDRIVE(0, 3, 0x20C, 2, 8), 492 RK_PINDRIVE(0, 3, 0x20C, 3, 12), 493 494 RK_PINDRIVE(1, 0, 0x210, 0, 2), 495 RK_PINDRIVE(1, 0, 0x210, 1, 4), 496 RK_PINDRIVE(1, 0, 0x210, 2, 8), 497 RK_PINDRIVE(1, 0, 0x210, 3, 12), 498 499 RK_PINDRIVE(1, 1, 0x214, 0, 2), 500 RK_PINDRIVE(1, 1, 0x214, 1, 4), 501 RK_PINDRIVE(1, 1, 0x214, 2, 8), 502 RK_PINDRIVE(1, 1, 0x214, 3, 12), 503 504 RK_PINDRIVE(1, 2, 0x218, 0, 2), 505 RK_PINDRIVE(1, 2, 0x218, 1, 4), 506 RK_PINDRIVE(1, 2, 0x218, 2, 8), 507 RK_PINDRIVE(1, 2, 0x218, 3, 12), 508 509 RK_PINDRIVE(1, 3, 0x21C, 0, 2), 510 RK_PINDRIVE(1, 3, 0x21C, 1, 4), 511 RK_PINDRIVE(1, 3, 0x21C, 2, 8), 512 RK_PINDRIVE(1, 3, 0x21C, 3, 12), 513 514 RK_PINDRIVE(2, 0, 0x220, 0, 2), 515 RK_PINDRIVE(2, 0, 0x220, 1, 4), 516 RK_PINDRIVE(2, 0, 0x220, 2, 8), 517 RK_PINDRIVE(2, 0, 0x220, 3, 12), 518 519 RK_PINDRIVE(2, 1, 0x224, 0, 2), 520 RK_PINDRIVE(2, 1, 0x224, 1, 4), 521 RK_PINDRIVE(2, 1, 0x224, 2, 8), 522 RK_PINDRIVE(2, 1, 0x224, 3, 12), 523 524 RK_PINDRIVE(2, 2, 0x228, 0, 2), 525 RK_PINDRIVE(2, 2, 0x228, 1, 4), 526 RK_PINDRIVE(2, 2, 0x228, 2, 8), 527 RK_PINDRIVE(2, 2, 0x228, 3, 12), 528 529 RK_PINDRIVE(2, 3, 0x22C, 0, 2), 530 RK_PINDRIVE(2, 3, 0x22C, 1, 4), 531 RK_PINDRIVE(2, 3, 0x22C, 2, 8), 532 RK_PINDRIVE(2, 3, 0x22C, 3, 12), 533 534 RK_PINDRIVE(3, 0, 0x230, 0, 2), 535 RK_PINDRIVE(3, 0, 0x230, 1, 4), 536 RK_PINDRIVE(3, 0, 0x230, 2, 8), 537 RK_PINDRIVE(3, 0, 0x230, 3, 12), 538 539 RK_PINDRIVE(3, 1, 0x234, 0, 2), 540 RK_PINDRIVE(3, 1, 0x234, 1, 4), 541 RK_PINDRIVE(3, 1, 0x234, 2, 8), 542 RK_PINDRIVE(3, 1, 0x234, 3, 12), 543 544 RK_PINDRIVE(3, 2, 0x238, 0, 2), 545 RK_PINDRIVE(3, 2, 0x238, 1, 4), 546 RK_PINDRIVE(3, 2, 0x238, 2, 8), 547 RK_PINDRIVE(3, 2, 0x238, 3, 12), 548 549 RK_PINDRIVE(3, 3, 0x23C, 0, 2), 550 RK_PINDRIVE(3, 3, 0x23C, 1, 4), 551 RK_PINDRIVE(3, 3, 0x23C, 2, 8), 552 RK_PINDRIVE(3, 3, 0x23C, 3, 12), 553 }; 554 555 static uint32_t 556 rk3328_get_pd_offset(struct rk_pinctrl_softc *sc, uint32_t bank) 557 { 558 return (0x100); 559 } 560 561 static struct syscon * 562 rk3328_get_syscon(struct rk_pinctrl_softc *sc, uint32_t bank) 563 { 564 return (sc->grf); 565 } 566 567 struct rk_pinctrl_conf rk3328_conf = { 568 .iomux_conf = rk3328_iomux_bank, 569 .iomux_nbanks = nitems(rk3328_iomux_bank), 570 .pin_fixup = rk3328_pin_fixup, 571 .npin_fixup = nitems(rk3328_pin_fixup), 572 .pin_drive = rk3328_pin_drive, 573 .npin_drive = nitems(rk3328_pin_drive), 574 .gpio_bank = rk3328_gpio_bank, 575 .ngpio_bank = nitems(rk3328_gpio_bank), 576 .get_pd_offset = rk3328_get_pd_offset, 577 .get_syscon = rk3328_get_syscon, 578 .parse_bias = rk3288_parse_bias, 579 .resolv_bias_value = rk3288_resolv_bias_value, 580 .get_bias_value = rk3288_get_bias_value, 581 }; 582 583 static struct rk_pinctrl_gpio rk3399_gpio_bank[] = { 584 RK_GPIO(0, "gpio0"), 585 RK_GPIO(1, "gpio1"), 586 RK_GPIO(2, "gpio2"), 587 RK_GPIO(3, "gpio3"), 588 RK_GPIO(4, "gpio4"), 589 }; 590 591 static struct rk_pinctrl_bank rk3399_iomux_bank[] = { 592 /* bank sub offs nbits */ 593 RK_IOMUX(0, 0, 0x0000, 2), 594 RK_IOMUX(0, 1, 0x0004, 2), 595 RK_IOMUX(0, 2, 0x0008, 2), 596 RK_IOMUX(0, 3, 0x000C, 2), 597 RK_IOMUX(1, 0, 0x0010, 2), 598 RK_IOMUX(1, 1, 0x0014, 2), 599 RK_IOMUX(1, 2, 0x0018, 2), 600 RK_IOMUX(1, 3, 0x001C, 2), 601 RK_IOMUX(2, 0, 0xE000, 2), 602 RK_IOMUX(2, 1, 0xE004, 2), 603 RK_IOMUX(2, 2, 0xE008, 2), 604 RK_IOMUX(2, 3, 0xE00C, 2), 605 RK_IOMUX(3, 0, 0xE010, 2), 606 RK_IOMUX(3, 1, 0xE014, 2), 607 RK_IOMUX(3, 2, 0xE018, 2), 608 RK_IOMUX(3, 3, 0xE01C, 2), 609 RK_IOMUX(4, 0, 0xE020, 2), 610 RK_IOMUX(4, 1, 0xE024, 2), 611 RK_IOMUX(4, 2, 0xE028, 2), 612 RK_IOMUX(4, 3, 0xE02C, 2), 613 }; 614 615 static struct rk_pinctrl_pin_fixup rk3399_pin_fixup[] = {}; 616 617 static struct rk_pinctrl_pin_drive rk3399_pin_drive[] = { 618 /* bank sub offs val ma */ 619 /* GPIO0A */ 620 RK_PINDRIVE(0, 0, 0x80, 0, 5), 621 RK_PINDRIVE(0, 0, 0x80, 1, 10), 622 RK_PINDRIVE(0, 0, 0x80, 2, 15), 623 RK_PINDRIVE(0, 0, 0x80, 3, 20), 624 625 /* GPIOB */ 626 RK_PINDRIVE(0, 1, 0x88, 0, 5), 627 RK_PINDRIVE(0, 1, 0x88, 1, 10), 628 RK_PINDRIVE(0, 1, 0x88, 2, 15), 629 RK_PINDRIVE(0, 1, 0x88, 3, 20), 630 631 /* GPIO1A */ 632 RK_PINDRIVE(1, 0, 0xA0, 0, 3), 633 RK_PINDRIVE(1, 0, 0xA0, 1, 6), 634 RK_PINDRIVE(1, 0, 0xA0, 2, 9), 635 RK_PINDRIVE(1, 0, 0xA0, 3, 12), 636 637 /* GPIO1B */ 638 RK_PINDRIVE(1, 1, 0xA8, 0, 3), 639 RK_PINDRIVE(1, 1, 0xA8, 1, 6), 640 RK_PINDRIVE(1, 1, 0xA8, 2, 9), 641 RK_PINDRIVE(1, 1, 0xA8, 3, 12), 642 643 /* GPIO1C */ 644 RK_PINDRIVE(1, 2, 0xB0, 0, 3), 645 RK_PINDRIVE(1, 2, 0xB0, 1, 6), 646 RK_PINDRIVE(1, 2, 0xB0, 2, 9), 647 RK_PINDRIVE(1, 2, 0xB0, 3, 12), 648 649 /* GPIO1D */ 650 RK_PINDRIVE(1, 3, 0xB8, 0, 3), 651 RK_PINDRIVE(1, 3, 0xB8, 1, 6), 652 RK_PINDRIVE(1, 3, 0xB8, 2, 9), 653 RK_PINDRIVE(1, 3, 0xB8, 3, 12), 654 }; 655 656 static uint32_t 657 rk3399_get_pd_offset(struct rk_pinctrl_softc *sc, uint32_t bank) 658 { 659 if (bank < 2) 660 return (0x40); 661 662 return (0xE040); 663 } 664 665 static struct syscon * 666 rk3399_get_syscon(struct rk_pinctrl_softc *sc, uint32_t bank) 667 { 668 if (bank < 2) 669 return (sc->pmu); 670 671 return (sc->grf); 672 } 673 674 static int 675 rk3399_parse_bias(phandle_t node, int bank) 676 { 677 int pullup, pulldown; 678 679 if (OF_hasprop(node, "bias-disable")) 680 return (0); 681 682 switch (bank) { 683 case 0: 684 case 2: 685 pullup = 3; 686 pulldown = 1; 687 break; 688 case 1: 689 case 3: 690 case 4: 691 pullup = 1; 692 pulldown = 2; 693 break; 694 } 695 696 if (OF_hasprop(node, "bias-pull-up")) 697 return (pullup); 698 if (OF_hasprop(node, "bias-pull-down")) 699 return (pulldown); 700 701 return (-1); 702 } 703 704 static int 705 rk3399_resolv_bias_value(int bank, int bias) 706 { 707 int rv = 0; 708 709 switch (bank) { 710 case 0: 711 case 2: 712 if (bias == 3) 713 rv = GPIO_PIN_PULLUP; 714 else if (bias == 1) 715 rv = GPIO_PIN_PULLDOWN; 716 break; 717 case 1: 718 case 3: 719 case 4: 720 if (bias == 1) 721 rv = GPIO_PIN_PULLUP; 722 else if (bias == 2) 723 rv = GPIO_PIN_PULLDOWN; 724 break; 725 } 726 727 return (rv); 728 } 729 730 static int 731 rk3399_get_bias_value(int bank, int bias) 732 { 733 int rv = 0; 734 735 switch (bank) { 736 case 0: 737 case 2: 738 if (bias & GPIO_PIN_PULLUP) 739 rv = 3; 740 else if (bias & GPIO_PIN_PULLDOWN) 741 rv = 1; 742 break; 743 case 1: 744 case 3: 745 case 4: 746 if (bias & GPIO_PIN_PULLUP) 747 rv = 1; 748 else if (bias & GPIO_PIN_PULLDOWN) 749 rv = 2; 750 break; 751 } 752 753 return (rv); 754 } 755 756 struct rk_pinctrl_conf rk3399_conf = { 757 .iomux_conf = rk3399_iomux_bank, 758 .iomux_nbanks = nitems(rk3399_iomux_bank), 759 .pin_fixup = rk3399_pin_fixup, 760 .npin_fixup = nitems(rk3399_pin_fixup), 761 .pin_drive = rk3399_pin_drive, 762 .npin_drive = nitems(rk3399_pin_drive), 763 .gpio_bank = rk3399_gpio_bank, 764 .ngpio_bank = nitems(rk3399_gpio_bank), 765 .get_pd_offset = rk3399_get_pd_offset, 766 .get_syscon = rk3399_get_syscon, 767 .parse_bias = rk3399_parse_bias, 768 .resolv_bias_value = rk3399_resolv_bias_value, 769 .get_bias_value = rk3399_get_bias_value, 770 }; 771 772 static struct ofw_compat_data compat_data[] = { 773 {"rockchip,rk3288-pinctrl", (uintptr_t)&rk3288_conf}, 774 {"rockchip,rk3328-pinctrl", (uintptr_t)&rk3328_conf}, 775 {"rockchip,rk3399-pinctrl", (uintptr_t)&rk3399_conf}, 776 {NULL, 0} 777 }; 778 779 static int 780 rk_pinctrl_parse_drive(struct rk_pinctrl_softc *sc, phandle_t node, 781 uint32_t bank, uint32_t subbank, uint32_t *drive, uint32_t *offset) 782 { 783 uint32_t value; 784 int i; 785 786 if (OF_getencprop(node, "drive-strength", &value, 787 sizeof(value)) != 0) 788 return (-1); 789 790 /* Map to the correct drive value */ 791 for (i = 0; i < sc->conf->npin_drive; i++) { 792 if (sc->conf->pin_drive[i].bank != bank && 793 sc->conf->pin_drive[i].subbank != subbank) 794 continue; 795 if (sc->conf->pin_drive[i].ma == value) { 796 *drive = sc->conf->pin_drive[i].value; 797 return (0); 798 } 799 } 800 801 return (-1); 802 } 803 804 static void 805 rk_pinctrl_get_fixup(struct rk_pinctrl_softc *sc, uint32_t bank, uint32_t pin, 806 uint32_t *reg, uint32_t *mask, uint32_t *bit) 807 { 808 int i; 809 810 for (i = 0; i < sc->conf->npin_fixup; i++) 811 if (sc->conf->pin_fixup[i].bank == bank && 812 sc->conf->pin_fixup[i].pin == pin) { 813 *reg = sc->conf->pin_fixup[i].reg; 814 *mask = sc->conf->pin_fixup[i].mask; 815 *bit = sc->conf->pin_fixup[i].bit; 816 817 return; 818 } 819 } 820 821 static int 822 rk_pinctrl_handle_io(struct rk_pinctrl_softc *sc, phandle_t node, uint32_t bank, 823 uint32_t pin) 824 { 825 bool have_cfg, have_direction, have_value; 826 uint32_t direction_value, pin_value; 827 struct rk_pinctrl_gpio *gpio; 828 int i, rv; 829 830 have_cfg = false; 831 have_direction = false; 832 have_value = false; 833 834 /* Get (subset of) GPIO pin properties. */ 835 if (OF_hasprop(node, "output-disable")) { 836 have_cfg = true; 837 have_direction = true; 838 direction_value = GPIO_PIN_INPUT; 839 } 840 841 if (OF_hasprop(node, "output-enable")) { 842 have_cfg = true; 843 have_direction = true; 844 direction_value = GPIO_PIN_OUTPUT; 845 } 846 847 if (OF_hasprop(node, "output-low")) { 848 have_cfg = true; 849 have_direction = true; 850 direction_value = GPIO_PIN_OUTPUT; 851 have_value = true; 852 pin_value = 0; 853 } 854 855 if (OF_hasprop(node, "output-high")) { 856 have_cfg = true; 857 have_direction = true; 858 direction_value = GPIO_PIN_OUTPUT; 859 have_value = true; 860 pin_value = 1; 861 } 862 863 if (!have_cfg) 864 return (0); 865 866 /* Find gpio */ 867 gpio = NULL; 868 for(i = 0; i < sc->conf->ngpio_bank; i++) { 869 if (bank == sc->conf->gpio_bank[i].bank) { 870 gpio = sc->conf->gpio_bank + i; 871 break; 872 } 873 } 874 if (gpio == NULL) { 875 device_printf(sc->dev, "Cannot find GPIO bank %d\n", bank); 876 return (ENXIO); 877 } 878 if (gpio->gpio_dev == NULL) { 879 device_printf(sc->dev, 880 "No GPIO subdevice found for bank %d\n", bank); 881 return (ENXIO); 882 } 883 884 rv = 0; 885 if (have_value) { 886 rv = GPIO_PIN_SET(gpio->gpio_dev, pin, pin_value); 887 if (rv != 0) { 888 device_printf(sc->dev, "Cannot set GPIO value: %d\n", 889 rv); 890 return (rv); 891 } 892 } 893 894 if (have_direction) { 895 rv = GPIO_PIN_SETFLAGS(gpio->gpio_dev, pin, direction_value); 896 if (rv != 0) { 897 device_printf(sc->dev, 898 "Cannot set GPIO direction: %d\n", rv); 899 return (rv); 900 } 901 } 902 903 return (0); 904 } 905 906 static void 907 rk_pinctrl_configure_pin(struct rk_pinctrl_softc *sc, uint32_t *pindata) 908 { 909 phandle_t pin_conf; 910 struct syscon *syscon; 911 uint32_t bank, subbank, pin, function, bias; 912 uint32_t bit, mask, reg, drive; 913 int i, rv; 914 915 bank = pindata[0]; 916 pin = pindata[1]; 917 function = pindata[2]; 918 pin_conf = OF_node_from_xref(pindata[3]); 919 subbank = pin / 8; 920 921 for (i = 0; i < sc->conf->iomux_nbanks; i++) 922 if (sc->conf->iomux_conf[i].bank == bank && 923 sc->conf->iomux_conf[i].subbank == subbank) 924 break; 925 926 if (i == sc->conf->iomux_nbanks) { 927 device_printf(sc->dev, "Unknown pin %d in bank %d\n", pin, 928 bank); 929 return; 930 } 931 932 /* Find syscon */ 933 syscon = sc->conf->get_syscon(sc, bank); 934 935 /* Setup GPIO properties first */ 936 rv = rk_pinctrl_handle_io(sc, pin_conf, bank, pin); 937 938 /* Then pin pull-up/down */ 939 bias = sc->conf->parse_bias(pin_conf, bank); 940 if (bias >= 0) { 941 reg = sc->conf->get_pd_offset(sc, bank); 942 reg += bank * 0x10 + ((pin / 8) * 0x4); 943 bit = (pin % 8) * 2; 944 mask = (0x3 << bit); 945 SYSCON_MODIFY_4(syscon, reg, mask, bias << bit | (mask << 16)); 946 } 947 948 /* Then drive strength */ 949 rv = rk_pinctrl_parse_drive(sc, pin_conf, bank, subbank, &drive, ®); 950 if (rv == 0) { 951 bit = (pin % 8) * 2; 952 mask = (0x3 << bit); 953 SYSCON_MODIFY_4(syscon, reg, mask, drive << bit | (mask << 16)); 954 } 955 956 /* Finally set the pin function */ 957 reg = sc->conf->iomux_conf[i].offset; 958 switch (sc->conf->iomux_conf[i].nbits) { 959 case 4: 960 if ((pin % 8) >= 4) 961 reg += 0x4; 962 bit = (pin % 4) * 4; 963 mask = (0xF << bit); 964 break; 965 case 3: 966 if ((pin % 8) >= 5) 967 reg += 4; 968 bit = (pin % 8 % 5) * 3; 969 mask = (0x7 << bit); 970 break; 971 case 2: 972 bit = (pin % 8) * 2; 973 mask = (0x3 << bit); 974 break; 975 default: 976 device_printf(sc->dev, 977 "Unknown pin stride width %d in bank %d\n", 978 sc->conf->iomux_conf[i].nbits, bank); 979 return; 980 } 981 rk_pinctrl_get_fixup(sc, bank, pin, ®, &mask, &bit); 982 983 /* 984 * NOTE: not all syscon registers uses hi-word write mask, thus 985 * register modify method should be used. 986 * XXXX We should not pass write mask to syscon register 987 * without hi-word write mask. 988 */ 989 SYSCON_MODIFY_4(syscon, reg, mask, function << bit | (mask << 16)); 990 } 991 992 static int 993 rk_pinctrl_configure_pins(device_t dev, phandle_t cfgxref) 994 { 995 struct rk_pinctrl_softc *sc; 996 phandle_t node; 997 uint32_t *pins; 998 int i, npins; 999 1000 sc = device_get_softc(dev); 1001 node = OF_node_from_xref(cfgxref); 1002 1003 npins = OF_getencprop_alloc_multi(node, "rockchip,pins", sizeof(*pins), 1004 (void **)&pins); 1005 if (npins <= 0) 1006 return (ENOENT); 1007 1008 for (i = 0; i != npins; i += 4) 1009 rk_pinctrl_configure_pin(sc, pins + i); 1010 1011 return (0); 1012 } 1013 1014 static int 1015 rk_pinctrl_is_gpio_locked(struct rk_pinctrl_softc *sc, struct syscon *syscon, 1016 int bank, uint32_t pin, bool *is_gpio) 1017 { 1018 uint32_t subbank, bit, mask, reg; 1019 uint32_t pinfunc; 1020 int i; 1021 1022 RK_PINCTRL_LOCK_ASSERT(sc); 1023 1024 subbank = pin / 8; 1025 *is_gpio = false; 1026 1027 for (i = 0; i < sc->conf->iomux_nbanks; i++) 1028 if (sc->conf->iomux_conf[i].bank == bank && 1029 sc->conf->iomux_conf[i].subbank == subbank) 1030 break; 1031 1032 if (i == sc->conf->iomux_nbanks) { 1033 device_printf(sc->dev, "Unknown pin %d in bank %d\n", pin, 1034 bank); 1035 return (EINVAL); 1036 } 1037 1038 syscon = sc->conf->get_syscon(sc, bank); 1039 1040 /* Parse pin function */ 1041 reg = sc->conf->iomux_conf[i].offset; 1042 switch (sc->conf->iomux_conf[i].nbits) { 1043 case 4: 1044 if ((pin % 8) >= 4) 1045 reg += 0x4; 1046 bit = (pin % 4) * 4; 1047 mask = (0xF << bit); 1048 break; 1049 case 3: 1050 if ((pin % 8) >= 5) 1051 reg += 4; 1052 bit = (pin % 8 % 5) * 3; 1053 mask = (0x7 << bit); 1054 break; 1055 case 2: 1056 bit = (pin % 8) * 2; 1057 mask = (0x3 << bit); 1058 break; 1059 default: 1060 device_printf(sc->dev, 1061 "Unknown pin stride width %d in bank %d\n", 1062 sc->conf->iomux_conf[i].nbits, bank); 1063 return (EINVAL); 1064 } 1065 rk_pinctrl_get_fixup(sc, bank, pin, ®, &mask, &bit); 1066 1067 reg = SYSCON_READ_4(syscon, reg); 1068 pinfunc = (reg & mask) >> bit; 1069 1070 /* Test if the pin is in gpio mode */ 1071 if (pinfunc == 0) 1072 *is_gpio = true; 1073 1074 return (0); 1075 } 1076 1077 static int 1078 rk_pinctrl_get_bank(struct rk_pinctrl_softc *sc, device_t gpio, int *bank) 1079 { 1080 int i; 1081 1082 for (i = 0; i < sc->conf->ngpio_bank; i++) { 1083 if (sc->conf->gpio_bank[i].gpio_dev == gpio) 1084 break; 1085 } 1086 if (i == sc->conf->ngpio_bank) 1087 return (EINVAL); 1088 1089 *bank = i; 1090 return (0); 1091 } 1092 1093 static int 1094 rk_pinctrl_is_gpio(device_t pinctrl, device_t gpio, uint32_t pin, bool *is_gpio) 1095 { 1096 struct rk_pinctrl_softc *sc; 1097 struct syscon *syscon; 1098 int bank; 1099 int rv; 1100 1101 sc = device_get_softc(pinctrl); 1102 RK_PINCTRL_LOCK(sc); 1103 1104 rv = rk_pinctrl_get_bank(sc, gpio, &bank); 1105 if (rv != 0) 1106 goto done; 1107 syscon = sc->conf->get_syscon(sc, bank); 1108 rv = rk_pinctrl_is_gpio_locked(sc, syscon, bank, pin, is_gpio); 1109 1110 done: 1111 RK_PINCTRL_UNLOCK(sc); 1112 1113 return (rv); 1114 } 1115 1116 static int 1117 rk_pinctrl_get_flags(device_t pinctrl, device_t gpio, uint32_t pin, 1118 uint32_t *flags) 1119 { 1120 struct rk_pinctrl_softc *sc; 1121 struct syscon *syscon; 1122 uint32_t reg, mask, bit; 1123 uint32_t bias; 1124 int bank; 1125 int rv = 0; 1126 bool is_gpio; 1127 1128 sc = device_get_softc(pinctrl); 1129 RK_PINCTRL_LOCK(sc); 1130 1131 rv = rk_pinctrl_get_bank(sc, gpio, &bank); 1132 if (rv != 0) 1133 goto done; 1134 syscon = sc->conf->get_syscon(sc, bank); 1135 rv = rk_pinctrl_is_gpio_locked(sc, syscon, bank, pin, &is_gpio); 1136 if (rv != 0) 1137 goto done; 1138 if (!is_gpio) { 1139 rv = EINVAL; 1140 goto done; 1141 } 1142 /* Get the pullup/pulldown configuration */ 1143 reg = sc->conf->get_pd_offset(sc, bank); 1144 reg += bank * 0x10 + ((pin / 8) * 0x4); 1145 bit = (pin % 8) * 2; 1146 mask = (0x3 << bit) << 16; 1147 reg = SYSCON_READ_4(syscon, reg); 1148 reg = (reg >> bit) & 0x3; 1149 bias = sc->conf->resolv_bias_value(bank, reg); 1150 *flags = bias; 1151 1152 done: 1153 RK_PINCTRL_UNLOCK(sc); 1154 return (rv); 1155 } 1156 1157 static int 1158 rk_pinctrl_set_flags(device_t pinctrl, device_t gpio, uint32_t pin, 1159 uint32_t flags) 1160 { 1161 struct rk_pinctrl_softc *sc; 1162 struct syscon *syscon; 1163 uint32_t bit, mask, reg; 1164 uint32_t bias; 1165 int bank; 1166 int rv = 0; 1167 bool is_gpio; 1168 1169 sc = device_get_softc(pinctrl); 1170 RK_PINCTRL_LOCK(sc); 1171 1172 rv = rk_pinctrl_get_bank(sc, gpio, &bank); 1173 if (rv != 0) 1174 goto done; 1175 syscon = sc->conf->get_syscon(sc, bank); 1176 rv = rk_pinctrl_is_gpio_locked(sc, syscon, bank, pin, &is_gpio); 1177 if (rv != 0) 1178 goto done; 1179 if (!is_gpio) { 1180 rv = EINVAL; 1181 goto done; 1182 } 1183 /* Get the pullup/pulldown configuration */ 1184 reg = sc->conf->get_pd_offset(sc, bank); 1185 reg += bank * 0x10 + ((pin / 8) * 0x4); 1186 bit = (pin % 8) * 2; 1187 mask = (0x3 << bit); 1188 bias = sc->conf->get_bias_value(bank, flags); 1189 SYSCON_MODIFY_4(syscon, reg, mask, bias << bit | (mask << 16)); 1190 1191 done: 1192 RK_PINCTRL_UNLOCK(sc); 1193 return (rv); 1194 } 1195 1196 static int 1197 rk_pinctrl_register_gpio(struct rk_pinctrl_softc *sc, char *gpio_name, 1198 device_t gpio_dev) 1199 { 1200 int i; 1201 1202 for(i = 0; i < sc->conf->ngpio_bank; i++) { 1203 if (strcmp(gpio_name, sc->conf->gpio_bank[i].gpio_name) != 0) 1204 continue; 1205 sc->conf->gpio_bank[i].gpio_dev = gpio_dev; 1206 return(0); 1207 } 1208 return (ENXIO); 1209 } 1210 1211 static int 1212 rk_pinctrl_probe(device_t dev) 1213 { 1214 1215 if (!ofw_bus_status_okay(dev)) 1216 return (ENXIO); 1217 1218 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 1219 return (ENXIO); 1220 1221 device_set_desc(dev, "RockChip Pinctrl controller"); 1222 return (BUS_PROBE_DEFAULT); 1223 } 1224 1225 static int 1226 rk_pinctrl_attach(device_t dev) 1227 { 1228 struct rk_pinctrl_softc *sc; 1229 phandle_t node; 1230 device_t cdev; 1231 char *gpio_name, *eptr; 1232 int rv; 1233 1234 sc = device_get_softc(dev); 1235 sc->dev = dev; 1236 1237 node = ofw_bus_get_node(dev); 1238 1239 if (OF_hasprop(node, "rockchip,grf") && 1240 syscon_get_by_ofw_property(dev, node, 1241 "rockchip,grf", &sc->grf) != 0) { 1242 device_printf(dev, "cannot get grf driver handle\n"); 1243 return (ENXIO); 1244 } 1245 1246 /* RK3399,RK3288 has banks in PMU. RK3328 does not have a PMU. */ 1247 if (ofw_bus_node_is_compatible(node, "rockchip,rk3399-pinctrl") || 1248 ofw_bus_node_is_compatible(node, "rockchip,rk3288-pinctrl")) { 1249 if (OF_hasprop(node, "rockchip,pmu") && 1250 syscon_get_by_ofw_property(dev, node, 1251 "rockchip,pmu", &sc->pmu) != 0) { 1252 device_printf(dev, "cannot get pmu driver handle\n"); 1253 return (ENXIO); 1254 } 1255 } 1256 1257 mtx_init(&sc->mtx, "rk pinctrl", "pinctrl", MTX_SPIN); 1258 1259 sc->conf = (struct rk_pinctrl_conf *)ofw_bus_search_compatible(dev, 1260 compat_data)->ocd_data; 1261 1262 fdt_pinctrl_register(dev, "rockchip,pins"); 1263 1264 simplebus_init(dev, node); 1265 1266 bus_generic_probe(dev); 1267 1268 /* Attach child devices */ 1269 for (node = OF_child(node); node > 0; node = OF_peer(node)) { 1270 if (!ofw_bus_node_is_compatible(node, "rockchip,gpio-bank")) 1271 continue; 1272 1273 rv = OF_getprop_alloc(node, "name", (void **)&gpio_name); 1274 if (rv <= 0) { 1275 device_printf(sc->dev, "Cannot GPIO subdevice name.\n"); 1276 continue; 1277 } 1278 1279 cdev = simplebus_add_device(dev, node, 0, NULL, -1, NULL); 1280 if (cdev == NULL) { 1281 device_printf(dev, " Cannot add GPIO subdevice: %s\n", 1282 gpio_name); 1283 OF_prop_free(gpio_name); 1284 continue; 1285 } 1286 1287 rv = device_probe_and_attach(cdev); 1288 if (rv != 0) { 1289 device_printf(sc->dev, 1290 "Cannot attach GPIO subdevice: %s\n", gpio_name); 1291 OF_prop_free(gpio_name); 1292 continue; 1293 } 1294 1295 /* Grep device name from name property */ 1296 eptr = gpio_name; 1297 strsep(&eptr, "@"); 1298 if (gpio_name == eptr) { 1299 device_printf(sc->dev, 1300 "Unrecognized format of GPIO subdevice name: %s\n", 1301 gpio_name); 1302 OF_prop_free(gpio_name); 1303 continue; 1304 } 1305 rv = rk_pinctrl_register_gpio(sc, gpio_name, cdev); 1306 if (rv != 0) { 1307 device_printf(sc->dev, 1308 "Cannot register GPIO subdevice %s: %d\n", 1309 gpio_name, rv); 1310 OF_prop_free(gpio_name); 1311 continue; 1312 } 1313 OF_prop_free(gpio_name); 1314 } 1315 1316 fdt_pinctrl_configure_tree(dev); 1317 1318 return (bus_generic_attach(dev)); 1319 } 1320 1321 static int 1322 rk_pinctrl_detach(device_t dev) 1323 { 1324 1325 return (EBUSY); 1326 } 1327 1328 static device_method_t rk_pinctrl_methods[] = { 1329 /* Device interface */ 1330 DEVMETHOD(device_probe, rk_pinctrl_probe), 1331 DEVMETHOD(device_attach, rk_pinctrl_attach), 1332 DEVMETHOD(device_detach, rk_pinctrl_detach), 1333 1334 /* fdt_pinctrl interface */ 1335 DEVMETHOD(fdt_pinctrl_configure, rk_pinctrl_configure_pins), 1336 DEVMETHOD(fdt_pinctrl_is_gpio, rk_pinctrl_is_gpio), 1337 DEVMETHOD(fdt_pinctrl_get_flags, rk_pinctrl_get_flags), 1338 DEVMETHOD(fdt_pinctrl_set_flags, rk_pinctrl_set_flags), 1339 1340 DEVMETHOD_END 1341 }; 1342 1343 static devclass_t rk_pinctrl_devclass; 1344 1345 DEFINE_CLASS_1(rk_pinctrl, rk_pinctrl_driver, rk_pinctrl_methods, 1346 sizeof(struct rk_pinctrl_softc), simplebus_driver); 1347 1348 EARLY_DRIVER_MODULE(rk_pinctrl, simplebus, rk_pinctrl_driver, 1349 rk_pinctrl_devclass, 0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE); 1350 MODULE_VERSION(rk_pinctrl, 1); 1351