1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2018 Emmanuel Vadot <manu@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 */ 28 29 #include <sys/param.h> 30 #include <sys/systm.h> 31 #include <sys/bus.h> 32 33 #include <sys/gpio.h> 34 #include <sys/kernel.h> 35 #include <sys/lock.h> 36 #include <sys/module.h> 37 #include <sys/mutex.h> 38 #include <sys/rman.h> 39 40 #include <machine/bus.h> 41 #include <machine/resource.h> 42 #include <machine/intr.h> 43 44 #include <dev/fdt/simplebus.h> 45 46 #include <dev/ofw/ofw_bus.h> 47 #include <dev/ofw/ofw_bus_subr.h> 48 49 #include <dev/fdt/fdt_pinctrl.h> 50 51 #include <dev/extres/syscon/syscon.h> 52 53 #include "gpio_if.h" 54 #include "syscon_if.h" 55 #include "fdt_pinctrl_if.h" 56 57 struct rk_pinctrl_pin_drive { 58 uint32_t bank; 59 uint32_t subbank; 60 uint32_t offset; 61 uint32_t value; 62 uint32_t ma; 63 }; 64 65 struct rk_pinctrl_bank { 66 uint32_t bank; 67 uint32_t subbank; 68 uint32_t offset; 69 uint32_t nbits; 70 }; 71 72 struct rk_pinctrl_pin_fixup { 73 uint32_t bank; 74 uint32_t subbank; 75 uint32_t pin; 76 uint32_t reg; 77 uint32_t bit; 78 uint32_t mask; 79 }; 80 81 struct rk_pinctrl_gpio { 82 uint32_t bank; 83 char *gpio_name; 84 device_t gpio_dev; 85 }; 86 87 struct rk_pinctrl_softc; 88 89 struct rk_pinctrl_conf { 90 struct rk_pinctrl_bank *iomux_conf; 91 uint32_t iomux_nbanks; 92 struct rk_pinctrl_pin_fixup *pin_fixup; 93 uint32_t npin_fixup; 94 struct rk_pinctrl_pin_drive *pin_drive; 95 uint32_t npin_drive; 96 struct rk_pinctrl_gpio *gpio_bank; 97 uint32_t ngpio_bank; 98 uint32_t (*get_pd_offset)(struct rk_pinctrl_softc *, uint32_t); 99 struct syscon *(*get_syscon)(struct rk_pinctrl_softc *, uint32_t); 100 int (*parse_bias)(phandle_t, int); 101 int (*resolv_bias_value)(int, int); 102 int (*get_bias_value)(int, int); 103 }; 104 105 struct rk_pinctrl_softc { 106 struct simplebus_softc simplebus_sc; 107 device_t dev; 108 struct syscon *grf; 109 struct syscon *pmu; 110 struct rk_pinctrl_conf *conf; 111 struct mtx mtx; 112 }; 113 114 #define RK_PINCTRL_LOCK(_sc) mtx_lock_spin(&(_sc)->mtx) 115 #define RK_PINCTRL_UNLOCK(_sc) mtx_unlock_spin(&(_sc)->mtx) 116 #define RK_PINCTRL_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->mtx, MA_OWNED) 117 118 #define RK_IOMUX(_bank, _subbank, _offset, _nbits) \ 119 { \ 120 .bank = _bank, \ 121 .subbank = _subbank, \ 122 .offset = _offset, \ 123 .nbits = _nbits, \ 124 } 125 126 #define RK_PINFIX(_bank, _pin, _reg, _bit, _mask) \ 127 { \ 128 .bank = _bank, \ 129 .pin = _pin, \ 130 .reg = _reg, \ 131 .bit = _bit, \ 132 .mask = _mask, \ 133 } 134 135 #define RK_PINDRIVE(_bank, _subbank, _offset, _value, _ma) \ 136 { \ 137 .bank = _bank, \ 138 .subbank = _subbank, \ 139 .offset = _offset, \ 140 .value = _value, \ 141 .ma = _ma, \ 142 } 143 #define RK_GPIO(_bank, _name) \ 144 { \ 145 .bank = _bank, \ 146 .gpio_name = _name, \ 147 } 148 149 static struct rk_pinctrl_gpio rk3288_gpio_bank[] = { 150 RK_GPIO(0, "gpio0"), 151 RK_GPIO(1, "gpio1"), 152 RK_GPIO(2, "gpio2"), 153 RK_GPIO(3, "gpio3"), 154 RK_GPIO(4, "gpio4"), 155 RK_GPIO(5, "gpio5"), 156 RK_GPIO(6, "gpio6"), 157 RK_GPIO(7, "gpio7"), 158 RK_GPIO(8, "gpio8"), 159 }; 160 161 static struct rk_pinctrl_bank rk3288_iomux_bank[] = { 162 /* bank sub offs nbits */ 163 /* PMU */ 164 RK_IOMUX(0, 0, 0x0084, 2), 165 RK_IOMUX(0, 1, 0x0088, 2), 166 RK_IOMUX(0, 2, 0x008C, 2), 167 /* GFR */ 168 RK_IOMUX(1, 3, 0x000C, 2), 169 RK_IOMUX(2, 0, 0x0010, 2), 170 RK_IOMUX(2, 1, 0x0014, 2), 171 RK_IOMUX(2, 2, 0x0018, 2), 172 RK_IOMUX(2, 3, 0x001C, 2), 173 RK_IOMUX(3, 0, 0x0020, 2), 174 RK_IOMUX(3, 1, 0x0024, 2), 175 RK_IOMUX(3, 2, 0x0028, 2), 176 RK_IOMUX(3, 3, 0x002C, 4), 177 RK_IOMUX(4, 0, 0x0034, 4), 178 RK_IOMUX(4, 1, 0x003C, 4), 179 RK_IOMUX(4, 2, 0x0044, 2), 180 RK_IOMUX(4, 3, 0x0048, 2), 181 /* 5,0 - Empty */ 182 RK_IOMUX(5, 1, 0x0050, 2), 183 RK_IOMUX(5, 2, 0x0054, 2), 184 /* 5,3 - Empty */ 185 RK_IOMUX(6, 0, 0x005C, 2), 186 RK_IOMUX(6, 1, 0x0060, 2), 187 RK_IOMUX(6, 2, 0x0064, 2), 188 /* 6,3 - Empty */ 189 RK_IOMUX(7, 0, 0x006C, 2), 190 RK_IOMUX(7, 1, 0x0070, 2), 191 RK_IOMUX(7, 2, 0x0074, 4), 192 /* 7,3 - Empty */ 193 RK_IOMUX(8, 0, 0x0080, 2), 194 RK_IOMUX(8, 1, 0x0084, 2), 195 /* 8,2 - Empty */ 196 /* 8,3 - Empty */ 197 198 }; 199 200 static struct rk_pinctrl_pin_fixup rk3288_pin_fixup[] = { 201 }; 202 203 static struct rk_pinctrl_pin_drive rk3288_pin_drive[] = { 204 /* bank sub offs val ma */ 205 /* GPIO0A (PMU)*/ 206 RK_PINDRIVE(0, 0, 0x070, 0, 2), 207 RK_PINDRIVE(0, 0, 0x070, 1, 4), 208 RK_PINDRIVE(0, 0, 0x070, 2, 8), 209 RK_PINDRIVE(0, 0, 0x070, 3, 12), 210 211 /* GPIO0B (PMU)*/ 212 RK_PINDRIVE(0, 1, 0x074, 0, 2), 213 RK_PINDRIVE(0, 1, 0x074, 1, 4), 214 RK_PINDRIVE(0, 1, 0x074, 2, 8), 215 RK_PINDRIVE(0, 1, 0x074, 3, 12), 216 217 /* GPIO0C (PMU)*/ 218 RK_PINDRIVE(0, 2, 0x078, 0, 2), 219 RK_PINDRIVE(0, 2, 0x078, 1, 4), 220 RK_PINDRIVE(0, 2, 0x078, 2, 8), 221 RK_PINDRIVE(0, 2, 0x078, 3, 12), 222 223 /* GPIO1D */ 224 RK_PINDRIVE(1, 3, 0x1CC, 0, 2), 225 RK_PINDRIVE(1, 3, 0x1CC, 1, 4), 226 RK_PINDRIVE(1, 3, 0x1CC, 2, 8), 227 RK_PINDRIVE(1, 3, 0x1CC, 3, 12), 228 229 /* GPIO2A */ 230 RK_PINDRIVE(2, 0, 0x1D0, 0, 2), 231 RK_PINDRIVE(2, 0, 0x1D0, 1, 4), 232 RK_PINDRIVE(2, 0, 0x1D0, 2, 8), 233 RK_PINDRIVE(2, 0, 0x1D0, 3, 12), 234 235 /* GPIO2B */ 236 RK_PINDRIVE(2, 1, 0x1D4, 0, 2), 237 RK_PINDRIVE(2, 1, 0x1D4, 1, 4), 238 RK_PINDRIVE(2, 1, 0x1D4, 2, 8), 239 RK_PINDRIVE(2, 1, 0x1D4, 3, 12), 240 241 /* GPIO2C */ 242 RK_PINDRIVE(2, 2, 0x1D8, 0, 2), 243 RK_PINDRIVE(2, 2, 0x1D8, 1, 4), 244 RK_PINDRIVE(2, 2, 0x1D8, 2, 8), 245 RK_PINDRIVE(2, 2, 0x1D8, 3, 12), 246 247 /* GPIO2D */ 248 RK_PINDRIVE(2, 3, 0x1DC, 0, 2), 249 RK_PINDRIVE(2, 3, 0x1DC, 1, 4), 250 RK_PINDRIVE(2, 3, 0x1DC, 2, 8), 251 RK_PINDRIVE(2, 3, 0x1DC, 3, 12), 252 253 /* GPIO3A */ 254 RK_PINDRIVE(3, 0, 0x1E0, 0, 2), 255 RK_PINDRIVE(3, 0, 0x1E0, 1, 4), 256 RK_PINDRIVE(3, 0, 0x1E0, 2, 8), 257 RK_PINDRIVE(3, 0, 0x1E0, 3, 12), 258 259 /* GPIO3B */ 260 RK_PINDRIVE(3, 1, 0x1E4, 0, 2), 261 RK_PINDRIVE(3, 1, 0x1E4, 1, 4), 262 RK_PINDRIVE(3, 1, 0x1E4, 2, 8), 263 RK_PINDRIVE(3, 1, 0x1E4, 3, 12), 264 265 /* GPIO3C */ 266 RK_PINDRIVE(3, 2, 0x1E8, 0, 2), 267 RK_PINDRIVE(3, 2, 0x1E8, 1, 4), 268 RK_PINDRIVE(3, 2, 0x1E8, 2, 8), 269 RK_PINDRIVE(3, 2, 0x1E8, 3, 12), 270 271 /* GPIO3D */ 272 RK_PINDRIVE(3, 3, 0x1EC, 0, 2), 273 RK_PINDRIVE(3, 3, 0x1EC, 1, 4), 274 RK_PINDRIVE(3, 3, 0x1EC, 2, 8), 275 RK_PINDRIVE(3, 3, 0x1EC, 3, 12), 276 277 /* GPIO4A */ 278 RK_PINDRIVE(4, 0, 0x1F0, 0, 2), 279 RK_PINDRIVE(4, 0, 0x1F0, 1, 4), 280 RK_PINDRIVE(4, 0, 0x1F0, 2, 8), 281 RK_PINDRIVE(4, 0, 0x1F0, 3, 12), 282 283 /* GPIO4B */ 284 RK_PINDRIVE(4, 1, 0x1F4, 0, 2), 285 RK_PINDRIVE(4, 1, 0x1F4, 1, 4), 286 RK_PINDRIVE(4, 1, 0x1F4, 2, 8), 287 RK_PINDRIVE(4, 1, 0x1F4, 3, 12), 288 289 /* GPIO4C */ 290 RK_PINDRIVE(4, 2, 0x1F8, 0, 2), 291 RK_PINDRIVE(4, 2, 0x1F8, 1, 4), 292 RK_PINDRIVE(4, 2, 0x1F8, 2, 8), 293 RK_PINDRIVE(4, 2, 0x1F8, 3, 12), 294 295 /* GPIO4D */ 296 RK_PINDRIVE(4, 3, 0x1FC, 0, 2), 297 RK_PINDRIVE(4, 3, 0x1FC, 1, 4), 298 RK_PINDRIVE(4, 3, 0x1FC, 2, 8), 299 RK_PINDRIVE(4, 3, 0x1FC, 3, 12), 300 301 /* GPIO5B */ 302 RK_PINDRIVE(5, 1, 0x204, 0, 2), 303 RK_PINDRIVE(5, 1, 0x204, 1, 4), 304 RK_PINDRIVE(5, 1, 0x204, 2, 8), 305 RK_PINDRIVE(5, 1, 0x204, 3, 12), 306 307 /* GPIO5C */ 308 RK_PINDRIVE(5, 2, 0x208, 0, 2), 309 RK_PINDRIVE(5, 2, 0x208, 1, 4), 310 RK_PINDRIVE(5, 2, 0x208, 2, 8), 311 RK_PINDRIVE(5, 2, 0x208, 3, 12), 312 313 /* GPIO6A */ 314 RK_PINDRIVE(6, 0, 0x210, 0, 2), 315 RK_PINDRIVE(6, 0, 0x210, 1, 4), 316 RK_PINDRIVE(6, 0, 0x210, 2, 8), 317 RK_PINDRIVE(6, 0, 0x210, 3, 12), 318 319 /* GPIO6B */ 320 RK_PINDRIVE(6, 1, 0x214, 0, 2), 321 RK_PINDRIVE(6, 1, 0x214, 1, 4), 322 RK_PINDRIVE(6, 1, 0x214, 2, 8), 323 RK_PINDRIVE(6, 1, 0x214, 3, 12), 324 325 /* GPIO6C */ 326 RK_PINDRIVE(6, 2, 0x218, 0, 2), 327 RK_PINDRIVE(6, 2, 0x218, 1, 4), 328 RK_PINDRIVE(6, 2, 0x218, 2, 8), 329 RK_PINDRIVE(6, 2, 0x218, 3, 12), 330 331 /* GPIO7A */ 332 RK_PINDRIVE(7, 0, 0x220, 0, 2), 333 RK_PINDRIVE(7, 0, 0x220, 1, 4), 334 RK_PINDRIVE(7, 0, 0x220, 2, 8), 335 RK_PINDRIVE(7, 0, 0x220, 3, 12), 336 337 /* GPIO7B */ 338 RK_PINDRIVE(7, 1, 0x224, 0, 2), 339 RK_PINDRIVE(7, 1, 0x224, 1, 4), 340 RK_PINDRIVE(7, 1, 0x224, 2, 8), 341 RK_PINDRIVE(7, 1, 0x224, 3, 12), 342 343 /* GPIO7C */ 344 RK_PINDRIVE(7, 2, 0x228, 0, 2), 345 RK_PINDRIVE(7, 2, 0x228, 1, 4), 346 RK_PINDRIVE(7, 2, 0x228, 2, 8), 347 RK_PINDRIVE(7, 2, 0x228, 3, 12), 348 349 /* GPIO8A */ 350 RK_PINDRIVE(8, 0, 0x230, 0, 2), 351 RK_PINDRIVE(8, 0, 0x230, 1, 4), 352 RK_PINDRIVE(8, 0, 0x230, 2, 8), 353 RK_PINDRIVE(8, 0, 0x230, 3, 12), 354 355 /* GPIO8B */ 356 RK_PINDRIVE(8, 1, 0x234, 0, 2), 357 RK_PINDRIVE(8, 1, 0x234, 1, 4), 358 RK_PINDRIVE(8, 1, 0x234, 2, 8), 359 RK_PINDRIVE(8, 1, 0x234, 3, 12), 360 }; 361 362 static uint32_t 363 rk3288_get_pd_offset(struct rk_pinctrl_softc *sc, uint32_t bank) 364 { 365 if (bank == 0) 366 return (0x064); /* PMU */ 367 return (0x130); 368 } 369 370 static struct syscon * 371 rk3288_get_syscon(struct rk_pinctrl_softc *sc, uint32_t bank) 372 { 373 if (bank == 0) 374 return (sc->pmu); 375 return (sc->grf); 376 } 377 378 static int 379 rk3288_parse_bias(phandle_t node, int bank) 380 { 381 if (OF_hasprop(node, "bias-disable")) 382 return (0); 383 if (OF_hasprop(node, "bias-pull-up")) 384 return (1); 385 if (OF_hasprop(node, "bias-pull-down")) 386 return (2); 387 388 return (-1); 389 } 390 391 static int 392 rk3288_resolv_bias_value(int bank, int bias) 393 { 394 int rv = 0; 395 396 if (bias == 1) 397 rv = GPIO_PIN_PULLUP; 398 else if (bias == 2) 399 rv = GPIO_PIN_PULLDOWN; 400 401 return (rv); 402 } 403 404 static int 405 rk3288_get_bias_value(int bank, int bias) 406 { 407 int rv = 0; 408 409 if (bias & GPIO_PIN_PULLUP) 410 rv = 1; 411 else if (bias & GPIO_PIN_PULLDOWN) 412 rv = 2; 413 414 return (rv); 415 } 416 417 struct rk_pinctrl_conf rk3288_conf = { 418 .iomux_conf = rk3288_iomux_bank, 419 .iomux_nbanks = nitems(rk3288_iomux_bank), 420 .pin_fixup = rk3288_pin_fixup, 421 .npin_fixup = nitems(rk3288_pin_fixup), 422 .pin_drive = rk3288_pin_drive, 423 .npin_drive = nitems(rk3288_pin_drive), 424 .gpio_bank = rk3288_gpio_bank, 425 .ngpio_bank = nitems(rk3288_gpio_bank), 426 .get_pd_offset = rk3288_get_pd_offset, 427 .get_syscon = rk3288_get_syscon, 428 .parse_bias = rk3288_parse_bias, 429 .resolv_bias_value = rk3288_resolv_bias_value, 430 .get_bias_value = rk3288_get_bias_value, 431 }; 432 433 static struct rk_pinctrl_gpio rk3328_gpio_bank[] = { 434 RK_GPIO(0, "gpio0"), 435 RK_GPIO(1, "gpio1"), 436 RK_GPIO(2, "gpio2"), 437 RK_GPIO(3, "gpio3"), 438 }; 439 440 static struct rk_pinctrl_bank rk3328_iomux_bank[] = { 441 /* bank sub offs nbits */ 442 RK_IOMUX(0, 0, 0x0000, 2), 443 RK_IOMUX(0, 1, 0x0004, 2), 444 RK_IOMUX(0, 2, 0x0008, 2), 445 RK_IOMUX(0, 3, 0x000C, 2), 446 RK_IOMUX(1, 0, 0x0010, 2), 447 RK_IOMUX(1, 1, 0x0014, 2), 448 RK_IOMUX(1, 2, 0x0018, 2), 449 RK_IOMUX(1, 3, 0x001C, 2), 450 RK_IOMUX(2, 0, 0x0020, 2), 451 RK_IOMUX(2, 1, 0x0024, 3), 452 RK_IOMUX(2, 2, 0x002c, 3), 453 RK_IOMUX(2, 3, 0x0034, 2), 454 RK_IOMUX(3, 0, 0x0038, 3), 455 RK_IOMUX(3, 1, 0x0040, 3), 456 RK_IOMUX(3, 2, 0x0048, 2), 457 RK_IOMUX(3, 3, 0x004c, 2), 458 }; 459 460 static struct rk_pinctrl_pin_fixup rk3328_pin_fixup[] = { 461 /* bank pin reg bit mask */ 462 RK_PINFIX(2, 12, 0x24, 8, 0x300), 463 RK_PINFIX(2, 15, 0x28, 0, 0x7), 464 RK_PINFIX(2, 23, 0x30, 14, 0x6000), 465 }; 466 467 static struct rk_pinctrl_pin_drive rk3328_pin_drive[] = { 468 /* bank sub offs val ma */ 469 RK_PINDRIVE(0, 0, 0x200, 0, 2), 470 RK_PINDRIVE(0, 0, 0x200, 1, 4), 471 RK_PINDRIVE(0, 0, 0x200, 2, 8), 472 RK_PINDRIVE(0, 0, 0x200, 3, 12), 473 474 RK_PINDRIVE(0, 1, 0x204, 0, 2), 475 RK_PINDRIVE(0, 1, 0x204, 1, 4), 476 RK_PINDRIVE(0, 1, 0x204, 2, 8), 477 RK_PINDRIVE(0, 1, 0x204, 3, 12), 478 479 RK_PINDRIVE(0, 2, 0x208, 0, 2), 480 RK_PINDRIVE(0, 2, 0x208, 1, 4), 481 RK_PINDRIVE(0, 2, 0x208, 2, 8), 482 RK_PINDRIVE(0, 2, 0x208, 3, 12), 483 484 RK_PINDRIVE(0, 3, 0x20C, 0, 2), 485 RK_PINDRIVE(0, 3, 0x20C, 1, 4), 486 RK_PINDRIVE(0, 3, 0x20C, 2, 8), 487 RK_PINDRIVE(0, 3, 0x20C, 3, 12), 488 489 RK_PINDRIVE(1, 0, 0x210, 0, 2), 490 RK_PINDRIVE(1, 0, 0x210, 1, 4), 491 RK_PINDRIVE(1, 0, 0x210, 2, 8), 492 RK_PINDRIVE(1, 0, 0x210, 3, 12), 493 494 RK_PINDRIVE(1, 1, 0x214, 0, 2), 495 RK_PINDRIVE(1, 1, 0x214, 1, 4), 496 RK_PINDRIVE(1, 1, 0x214, 2, 8), 497 RK_PINDRIVE(1, 1, 0x214, 3, 12), 498 499 RK_PINDRIVE(1, 2, 0x218, 0, 2), 500 RK_PINDRIVE(1, 2, 0x218, 1, 4), 501 RK_PINDRIVE(1, 2, 0x218, 2, 8), 502 RK_PINDRIVE(1, 2, 0x218, 3, 12), 503 504 RK_PINDRIVE(1, 3, 0x21C, 0, 2), 505 RK_PINDRIVE(1, 3, 0x21C, 1, 4), 506 RK_PINDRIVE(1, 3, 0x21C, 2, 8), 507 RK_PINDRIVE(1, 3, 0x21C, 3, 12), 508 509 RK_PINDRIVE(2, 0, 0x220, 0, 2), 510 RK_PINDRIVE(2, 0, 0x220, 1, 4), 511 RK_PINDRIVE(2, 0, 0x220, 2, 8), 512 RK_PINDRIVE(2, 0, 0x220, 3, 12), 513 514 RK_PINDRIVE(2, 1, 0x224, 0, 2), 515 RK_PINDRIVE(2, 1, 0x224, 1, 4), 516 RK_PINDRIVE(2, 1, 0x224, 2, 8), 517 RK_PINDRIVE(2, 1, 0x224, 3, 12), 518 519 RK_PINDRIVE(2, 2, 0x228, 0, 2), 520 RK_PINDRIVE(2, 2, 0x228, 1, 4), 521 RK_PINDRIVE(2, 2, 0x228, 2, 8), 522 RK_PINDRIVE(2, 2, 0x228, 3, 12), 523 524 RK_PINDRIVE(2, 3, 0x22C, 0, 2), 525 RK_PINDRIVE(2, 3, 0x22C, 1, 4), 526 RK_PINDRIVE(2, 3, 0x22C, 2, 8), 527 RK_PINDRIVE(2, 3, 0x22C, 3, 12), 528 529 RK_PINDRIVE(3, 0, 0x230, 0, 2), 530 RK_PINDRIVE(3, 0, 0x230, 1, 4), 531 RK_PINDRIVE(3, 0, 0x230, 2, 8), 532 RK_PINDRIVE(3, 0, 0x230, 3, 12), 533 534 RK_PINDRIVE(3, 1, 0x234, 0, 2), 535 RK_PINDRIVE(3, 1, 0x234, 1, 4), 536 RK_PINDRIVE(3, 1, 0x234, 2, 8), 537 RK_PINDRIVE(3, 1, 0x234, 3, 12), 538 539 RK_PINDRIVE(3, 2, 0x238, 0, 2), 540 RK_PINDRIVE(3, 2, 0x238, 1, 4), 541 RK_PINDRIVE(3, 2, 0x238, 2, 8), 542 RK_PINDRIVE(3, 2, 0x238, 3, 12), 543 544 RK_PINDRIVE(3, 3, 0x23C, 0, 2), 545 RK_PINDRIVE(3, 3, 0x23C, 1, 4), 546 RK_PINDRIVE(3, 3, 0x23C, 2, 8), 547 RK_PINDRIVE(3, 3, 0x23C, 3, 12), 548 }; 549 550 static uint32_t 551 rk3328_get_pd_offset(struct rk_pinctrl_softc *sc, uint32_t bank) 552 { 553 return (0x100); 554 } 555 556 static struct syscon * 557 rk3328_get_syscon(struct rk_pinctrl_softc *sc, uint32_t bank) 558 { 559 return (sc->grf); 560 } 561 562 struct rk_pinctrl_conf rk3328_conf = { 563 .iomux_conf = rk3328_iomux_bank, 564 .iomux_nbanks = nitems(rk3328_iomux_bank), 565 .pin_fixup = rk3328_pin_fixup, 566 .npin_fixup = nitems(rk3328_pin_fixup), 567 .pin_drive = rk3328_pin_drive, 568 .npin_drive = nitems(rk3328_pin_drive), 569 .gpio_bank = rk3328_gpio_bank, 570 .ngpio_bank = nitems(rk3328_gpio_bank), 571 .get_pd_offset = rk3328_get_pd_offset, 572 .get_syscon = rk3328_get_syscon, 573 .parse_bias = rk3288_parse_bias, 574 .resolv_bias_value = rk3288_resolv_bias_value, 575 .get_bias_value = rk3288_get_bias_value, 576 }; 577 578 static struct rk_pinctrl_gpio rk3399_gpio_bank[] = { 579 RK_GPIO(0, "gpio0"), 580 RK_GPIO(1, "gpio1"), 581 RK_GPIO(2, "gpio2"), 582 RK_GPIO(3, "gpio3"), 583 RK_GPIO(4, "gpio4"), 584 }; 585 586 static struct rk_pinctrl_bank rk3399_iomux_bank[] = { 587 /* bank sub offs nbits */ 588 RK_IOMUX(0, 0, 0x0000, 2), 589 RK_IOMUX(0, 1, 0x0004, 2), 590 RK_IOMUX(0, 2, 0x0008, 2), 591 RK_IOMUX(0, 3, 0x000C, 2), 592 RK_IOMUX(1, 0, 0x0010, 2), 593 RK_IOMUX(1, 1, 0x0014, 2), 594 RK_IOMUX(1, 2, 0x0018, 2), 595 RK_IOMUX(1, 3, 0x001C, 2), 596 RK_IOMUX(2, 0, 0xE000, 2), 597 RK_IOMUX(2, 1, 0xE004, 2), 598 RK_IOMUX(2, 2, 0xE008, 2), 599 RK_IOMUX(2, 3, 0xE00C, 2), 600 RK_IOMUX(3, 0, 0xE010, 2), 601 RK_IOMUX(3, 1, 0xE014, 2), 602 RK_IOMUX(3, 2, 0xE018, 2), 603 RK_IOMUX(3, 3, 0xE01C, 2), 604 RK_IOMUX(4, 0, 0xE020, 2), 605 RK_IOMUX(4, 1, 0xE024, 2), 606 RK_IOMUX(4, 2, 0xE028, 2), 607 RK_IOMUX(4, 3, 0xE02C, 2), 608 }; 609 610 static struct rk_pinctrl_pin_fixup rk3399_pin_fixup[] = {}; 611 612 static struct rk_pinctrl_pin_drive rk3399_pin_drive[] = { 613 /* bank sub offs val ma */ 614 /* GPIO0A */ 615 RK_PINDRIVE(0, 0, 0x80, 0, 5), 616 RK_PINDRIVE(0, 0, 0x80, 1, 10), 617 RK_PINDRIVE(0, 0, 0x80, 2, 15), 618 RK_PINDRIVE(0, 0, 0x80, 3, 20), 619 620 /* GPIOB */ 621 RK_PINDRIVE(0, 1, 0x88, 0, 5), 622 RK_PINDRIVE(0, 1, 0x88, 1, 10), 623 RK_PINDRIVE(0, 1, 0x88, 2, 15), 624 RK_PINDRIVE(0, 1, 0x88, 3, 20), 625 626 /* GPIO1A */ 627 RK_PINDRIVE(1, 0, 0xA0, 0, 3), 628 RK_PINDRIVE(1, 0, 0xA0, 1, 6), 629 RK_PINDRIVE(1, 0, 0xA0, 2, 9), 630 RK_PINDRIVE(1, 0, 0xA0, 3, 12), 631 632 /* GPIO1B */ 633 RK_PINDRIVE(1, 1, 0xA8, 0, 3), 634 RK_PINDRIVE(1, 1, 0xA8, 1, 6), 635 RK_PINDRIVE(1, 1, 0xA8, 2, 9), 636 RK_PINDRIVE(1, 1, 0xA8, 3, 12), 637 638 /* GPIO1C */ 639 RK_PINDRIVE(1, 2, 0xB0, 0, 3), 640 RK_PINDRIVE(1, 2, 0xB0, 1, 6), 641 RK_PINDRIVE(1, 2, 0xB0, 2, 9), 642 RK_PINDRIVE(1, 2, 0xB0, 3, 12), 643 644 /* GPIO1D */ 645 RK_PINDRIVE(1, 3, 0xB8, 0, 3), 646 RK_PINDRIVE(1, 3, 0xB8, 1, 6), 647 RK_PINDRIVE(1, 3, 0xB8, 2, 9), 648 RK_PINDRIVE(1, 3, 0xB8, 3, 12), 649 }; 650 651 static uint32_t 652 rk3399_get_pd_offset(struct rk_pinctrl_softc *sc, uint32_t bank) 653 { 654 if (bank < 2) 655 return (0x40); 656 657 return (0xE040); 658 } 659 660 static struct syscon * 661 rk3399_get_syscon(struct rk_pinctrl_softc *sc, uint32_t bank) 662 { 663 if (bank < 2) 664 return (sc->pmu); 665 666 return (sc->grf); 667 } 668 669 static int 670 rk3399_parse_bias(phandle_t node, int bank) 671 { 672 int pullup, pulldown; 673 674 if (OF_hasprop(node, "bias-disable")) 675 return (0); 676 677 switch (bank) { 678 case 0: 679 case 2: 680 pullup = 3; 681 pulldown = 1; 682 break; 683 case 1: 684 case 3: 685 case 4: 686 pullup = 1; 687 pulldown = 2; 688 break; 689 } 690 691 if (OF_hasprop(node, "bias-pull-up")) 692 return (pullup); 693 if (OF_hasprop(node, "bias-pull-down")) 694 return (pulldown); 695 696 return (-1); 697 } 698 699 static int 700 rk3399_resolv_bias_value(int bank, int bias) 701 { 702 int rv = 0; 703 704 switch (bank) { 705 case 0: 706 case 2: 707 if (bias == 3) 708 rv = GPIO_PIN_PULLUP; 709 else if (bias == 1) 710 rv = GPIO_PIN_PULLDOWN; 711 break; 712 case 1: 713 case 3: 714 case 4: 715 if (bias == 1) 716 rv = GPIO_PIN_PULLUP; 717 else if (bias == 2) 718 rv = GPIO_PIN_PULLDOWN; 719 break; 720 } 721 722 return (rv); 723 } 724 725 static int 726 rk3399_get_bias_value(int bank, int bias) 727 { 728 int rv = 0; 729 730 switch (bank) { 731 case 0: 732 case 2: 733 if (bias & GPIO_PIN_PULLUP) 734 rv = 3; 735 else if (bias & GPIO_PIN_PULLDOWN) 736 rv = 1; 737 break; 738 case 1: 739 case 3: 740 case 4: 741 if (bias & GPIO_PIN_PULLUP) 742 rv = 1; 743 else if (bias & GPIO_PIN_PULLDOWN) 744 rv = 2; 745 break; 746 } 747 748 return (rv); 749 } 750 751 struct rk_pinctrl_conf rk3399_conf = { 752 .iomux_conf = rk3399_iomux_bank, 753 .iomux_nbanks = nitems(rk3399_iomux_bank), 754 .pin_fixup = rk3399_pin_fixup, 755 .npin_fixup = nitems(rk3399_pin_fixup), 756 .pin_drive = rk3399_pin_drive, 757 .npin_drive = nitems(rk3399_pin_drive), 758 .gpio_bank = rk3399_gpio_bank, 759 .ngpio_bank = nitems(rk3399_gpio_bank), 760 .get_pd_offset = rk3399_get_pd_offset, 761 .get_syscon = rk3399_get_syscon, 762 .parse_bias = rk3399_parse_bias, 763 .resolv_bias_value = rk3399_resolv_bias_value, 764 .get_bias_value = rk3399_get_bias_value, 765 }; 766 767 #define GRF_IOFUNC_SEL0 0x0300 768 #define GMAC1_IOMUX_SEL_M0 0x01000000 769 #define GMAC1_IOMUX_SEL_M1 0x01000100 770 771 static struct rk_pinctrl_gpio rk3568_gpio_bank[] = { 772 RK_GPIO(0, "gpio0"), 773 RK_GPIO(1, "gpio1"), 774 RK_GPIO(2, "gpio2"), 775 RK_GPIO(3, "gpio3"), 776 RK_GPIO(4, "gpio4"), 777 }; 778 779 static struct rk_pinctrl_bank rk3568_iomux_bank[] = { 780 /* bank sub offs nbits */ 781 RK_IOMUX(0, 0, 0x0000, 4), /* PMU_GRF */ 782 RK_IOMUX(0, 1, 0x0008, 4), 783 RK_IOMUX(0, 2, 0x0010, 4), 784 RK_IOMUX(0, 3, 0x0018, 4), 785 786 RK_IOMUX(1, 0, 0x0000, 4), /* SYS_GRF */ 787 RK_IOMUX(1, 1, 0x0008, 4), 788 RK_IOMUX(1, 2, 0x0010, 4), 789 RK_IOMUX(1, 3, 0x0018, 4), 790 RK_IOMUX(2, 0, 0x0020, 4), 791 RK_IOMUX(2, 1, 0x0028, 4), 792 RK_IOMUX(2, 2, 0x0030, 4), 793 RK_IOMUX(2, 3, 0x0038, 4), 794 RK_IOMUX(3, 0, 0x0040, 4), 795 RK_IOMUX(3, 1, 0x0048, 4), 796 RK_IOMUX(3, 2, 0x0050, 4), 797 RK_IOMUX(3, 3, 0x0058, 4), 798 RK_IOMUX(4, 0, 0x0060, 4), 799 RK_IOMUX(4, 1, 0x0068, 4), 800 RK_IOMUX(4, 2, 0x0070, 4), 801 RK_IOMUX(4, 3, 0x0078, 4), 802 }; 803 804 static struct rk_pinctrl_pin_fixup rk3568_pin_fixup[] = {}; 805 806 static struct rk_pinctrl_pin_drive rk3568_pin_drive[] = { 807 /* bank sub offs val ma */ 808 /* GPIO0A */ 809 RK_PINDRIVE(0, 0, 0x0020, 0, 2), 810 RK_PINDRIVE(0, 0, 0x0020, 1, 4), 811 RK_PINDRIVE(0, 0, 0x0020, 2, 8), 812 RK_PINDRIVE(0, 0, 0x0020, 3, 12), 813 814 /* GPIO0B */ 815 RK_PINDRIVE(0, 1, 0x0024, 0, 2), 816 RK_PINDRIVE(0, 1, 0x0024, 1, 4), 817 RK_PINDRIVE(0, 1, 0x0024, 2, 8), 818 RK_PINDRIVE(0, 1, 0x0024, 3, 12), 819 820 /* GPIO0C */ 821 RK_PINDRIVE(0, 1, 0x0028, 0, 2), 822 RK_PINDRIVE(0, 1, 0x0028, 1, 4), 823 RK_PINDRIVE(0, 1, 0x0028, 2, 8), 824 RK_PINDRIVE(0, 1, 0x0028, 3, 12), 825 826 /* GPIO0D */ 827 RK_PINDRIVE(0, 1, 0x002c, 0, 2), 828 RK_PINDRIVE(0, 1, 0x002c, 1, 4), 829 RK_PINDRIVE(0, 1, 0x002c, 2, 8), 830 RK_PINDRIVE(0, 1, 0x002c, 3, 12), 831 832 /* GPIO1A */ 833 RK_PINDRIVE(1, 0, 0x0080, 0, 2), 834 RK_PINDRIVE(1, 0, 0x0080, 1, 4), 835 RK_PINDRIVE(1, 0, 0x0080, 2, 8), 836 RK_PINDRIVE(1, 0, 0x0080, 3, 12), 837 838 /* GPIO1B */ 839 RK_PINDRIVE(1, 1, 0x0084, 0, 2), 840 RK_PINDRIVE(1, 1, 0x0084, 1, 4), 841 RK_PINDRIVE(1, 1, 0x0084, 2, 8), 842 RK_PINDRIVE(1, 1, 0x0084, 3, 12), 843 844 /* GPIO1C */ 845 RK_PINDRIVE(1, 2, 0x0088, 0, 2), 846 RK_PINDRIVE(1, 2, 0x0088, 1, 4), 847 RK_PINDRIVE(1, 2, 0x0088, 2, 8), 848 RK_PINDRIVE(1, 2, 0x0088, 3, 12), 849 850 /* GPIO1D */ 851 RK_PINDRIVE(1, 3, 0x008c, 0, 2), 852 RK_PINDRIVE(1, 3, 0x008c, 1, 4), 853 RK_PINDRIVE(1, 3, 0x008c, 2, 8), 854 RK_PINDRIVE(1, 3, 0x008c, 3, 12), 855 856 /* GPIO2A */ 857 RK_PINDRIVE(2, 0, 0x0090, 0, 2), 858 RK_PINDRIVE(2, 0, 0x0090, 1, 4), 859 RK_PINDRIVE(2, 0, 0x0090, 2, 8), 860 RK_PINDRIVE(2, 0, 0x0090, 3, 12), 861 862 /* GPIO2B */ 863 RK_PINDRIVE(2, 1, 0x0094, 0, 2), 864 RK_PINDRIVE(2, 1, 0x0094, 1, 4), 865 RK_PINDRIVE(2, 1, 0x0094, 2, 8), 866 RK_PINDRIVE(2, 1, 0x0094, 3, 12), 867 868 /* GPIO2C */ 869 RK_PINDRIVE(2, 2, 0x0098, 0, 2), 870 RK_PINDRIVE(2, 2, 0x0098, 1, 4), 871 RK_PINDRIVE(2, 2, 0x0098, 2, 8), 872 RK_PINDRIVE(2, 2, 0x0098, 3, 12), 873 874 /* GPIO2D */ 875 RK_PINDRIVE(2, 3, 0x009c, 0, 2), 876 RK_PINDRIVE(2, 3, 0x009c, 1, 4), 877 RK_PINDRIVE(2, 3, 0x009c, 2, 8), 878 RK_PINDRIVE(2, 3, 0x009c, 3, 12), 879 880 /* GPIO3A */ 881 RK_PINDRIVE(3, 0, 0x00a0, 0, 2), 882 RK_PINDRIVE(3, 0, 0x00a0, 1, 4), 883 RK_PINDRIVE(3, 0, 0x00a0, 2, 8), 884 RK_PINDRIVE(3, 0, 0x00a0, 3, 12), 885 886 /* GPIO3B */ 887 RK_PINDRIVE(3, 1, 0x00a4, 0, 2), 888 RK_PINDRIVE(3, 1, 0x00a4, 1, 4), 889 RK_PINDRIVE(3, 1, 0x00a4, 2, 8), 890 RK_PINDRIVE(3, 1, 0x00a4, 3, 12), 891 892 /* GPIO3C */ 893 RK_PINDRIVE(3, 2, 0x00a8, 0, 2), 894 RK_PINDRIVE(3, 2, 0x00a8, 1, 4), 895 RK_PINDRIVE(3, 2, 0x00a8, 2, 8), 896 RK_PINDRIVE(3, 2, 0x00a8, 3, 12), 897 898 /* GPIO3D */ 899 RK_PINDRIVE(3, 3, 0x00ac, 0, 2), 900 RK_PINDRIVE(3, 3, 0x00ac, 1, 4), 901 RK_PINDRIVE(3, 3, 0x00ac, 2, 8), 902 RK_PINDRIVE(3, 3, 0x00ac, 3, 12), 903 904 /* GPIO4A */ 905 RK_PINDRIVE(4, 0, 0x00b0, 0, 2), 906 RK_PINDRIVE(4, 0, 0x00b0, 1, 4), 907 RK_PINDRIVE(4, 0, 0x00b0, 2, 8), 908 RK_PINDRIVE(4, 0, 0x00b0, 3, 12), 909 910 /* GPIO4B */ 911 RK_PINDRIVE(4, 1, 0x00b4, 0, 2), 912 RK_PINDRIVE(4, 1, 0x00b4, 1, 4), 913 RK_PINDRIVE(4, 1, 0x00b4, 2, 8), 914 RK_PINDRIVE(4, 1, 0x00b4, 3, 12), 915 916 /* GPIO4C */ 917 RK_PINDRIVE(4, 2, 0x00b8, 0, 2), 918 RK_PINDRIVE(4, 2, 0x00b8, 1, 4), 919 RK_PINDRIVE(4, 2, 0x00b8, 2, 8), 920 RK_PINDRIVE(4, 2, 0x00b8, 3, 12), 921 922 /* GPIO4D */ 923 RK_PINDRIVE(4, 3, 0x00bc, 0, 2), 924 RK_PINDRIVE(4, 3, 0x00bc, 1, 4), 925 RK_PINDRIVE(4, 3, 0x00bc, 2, 8), 926 RK_PINDRIVE(4, 3, 0x00bc, 3, 12), 927 }; 928 929 static uint32_t 930 rk3568_get_pd_offset(struct rk_pinctrl_softc *sc, uint32_t bank) 931 { 932 933 if (bank == 0) 934 return (0x20); 935 936 /* 937 * Registers start at 0x80, but bank index starts at 1. Return 0x70 938 * so later calculations get the correct offset. 939 */ 940 return (0x70); 941 } 942 943 static struct syscon * 944 rk3568_get_syscon(struct rk_pinctrl_softc *sc, uint32_t bank) 945 { 946 947 if (bank) 948 return (sc->grf); 949 else 950 return (sc->pmu); 951 } 952 953 static int 954 rk3568_parse_bias(phandle_t node, int bank) 955 { 956 957 if (OF_hasprop(node, "bias-disable")) 958 return (0); 959 if (OF_hasprop(node, "bias-pull-up")) 960 return (1); 961 if (OF_hasprop(node, "bias-pull-down")) 962 return (2); 963 return (-1); 964 } 965 966 static int 967 rk3568_resolv_bias_value(int bank, int bias) 968 { 969 970 if (bias == 1) 971 return (GPIO_PIN_PULLUP); 972 if (bias == 2) 973 return (GPIO_PIN_PULLDOWN); 974 return (0); 975 } 976 977 static int 978 rk3568_get_bias_value(int bank, int bias) 979 { 980 981 if (bias & GPIO_PIN_PULLUP) 982 return (1); 983 if (bias & GPIO_PIN_PULLDOWN) 984 return (2); 985 return (0); 986 } 987 988 struct rk_pinctrl_conf rk3568_conf = { 989 .iomux_conf = rk3568_iomux_bank, 990 .iomux_nbanks = nitems(rk3568_iomux_bank), 991 .pin_fixup = rk3568_pin_fixup, 992 .npin_fixup = nitems(rk3568_pin_fixup), 993 .pin_drive = rk3568_pin_drive, 994 .npin_drive = nitems(rk3568_pin_drive), 995 .gpio_bank = rk3568_gpio_bank, 996 .ngpio_bank = nitems(rk3568_gpio_bank), 997 .get_pd_offset = rk3568_get_pd_offset, 998 .get_syscon = rk3568_get_syscon, 999 .parse_bias = rk3568_parse_bias, 1000 .resolv_bias_value = rk3568_resolv_bias_value, 1001 .get_bias_value = rk3568_get_bias_value, 1002 }; 1003 1004 static struct ofw_compat_data compat_data[] = { 1005 {"rockchip,rk3288-pinctrl", (uintptr_t)&rk3288_conf}, 1006 {"rockchip,rk3328-pinctrl", (uintptr_t)&rk3328_conf}, 1007 {"rockchip,rk3399-pinctrl", (uintptr_t)&rk3399_conf}, 1008 {"rockchip,rk3568-pinctrl", (uintptr_t)&rk3568_conf}, 1009 {NULL, 0} 1010 }; 1011 1012 static int 1013 rk_pinctrl_parse_drive(struct rk_pinctrl_softc *sc, phandle_t node, 1014 uint32_t bank, uint32_t subbank, uint32_t *drive, uint32_t *offset) 1015 { 1016 uint32_t value; 1017 int i; 1018 1019 if (OF_getencprop(node, "drive-strength", &value, 1020 sizeof(value)) != 0) 1021 return (-1); 1022 1023 /* Map to the correct drive value */ 1024 for (i = 0; i < sc->conf->npin_drive; i++) { 1025 if (sc->conf->pin_drive[i].bank != bank && 1026 sc->conf->pin_drive[i].subbank != subbank) 1027 continue; 1028 if (sc->conf->pin_drive[i].ma == value) { 1029 *drive = sc->conf->pin_drive[i].value; 1030 return (0); 1031 } 1032 } 1033 1034 return (-1); 1035 } 1036 1037 static void 1038 rk_pinctrl_get_fixup(struct rk_pinctrl_softc *sc, uint32_t bank, uint32_t pin, 1039 uint32_t *reg, uint32_t *mask, uint32_t *bit) 1040 { 1041 int i; 1042 1043 for (i = 0; i < sc->conf->npin_fixup; i++) 1044 if (sc->conf->pin_fixup[i].bank == bank && 1045 sc->conf->pin_fixup[i].pin == pin) { 1046 *reg = sc->conf->pin_fixup[i].reg; 1047 *mask = sc->conf->pin_fixup[i].mask; 1048 *bit = sc->conf->pin_fixup[i].bit; 1049 1050 return; 1051 } 1052 } 1053 1054 static int 1055 rk_pinctrl_handle_io(struct rk_pinctrl_softc *sc, phandle_t node, uint32_t bank, 1056 uint32_t pin) 1057 { 1058 bool have_cfg, have_direction, have_value; 1059 uint32_t direction_value, pin_value; 1060 struct rk_pinctrl_gpio *gpio; 1061 int i, rv; 1062 1063 have_cfg = false; 1064 have_direction = false; 1065 have_value = false; 1066 1067 /* Get (subset of) GPIO pin properties. */ 1068 if (OF_hasprop(node, "output-disable")) { 1069 have_cfg = true; 1070 have_direction = true; 1071 direction_value = GPIO_PIN_INPUT; 1072 } 1073 1074 if (OF_hasprop(node, "output-enable")) { 1075 have_cfg = true; 1076 have_direction = true; 1077 direction_value = GPIO_PIN_OUTPUT; 1078 } 1079 1080 if (OF_hasprop(node, "output-low")) { 1081 have_cfg = true; 1082 have_direction = true; 1083 direction_value = GPIO_PIN_OUTPUT; 1084 have_value = true; 1085 pin_value = 0; 1086 } 1087 1088 if (OF_hasprop(node, "output-high")) { 1089 have_cfg = true; 1090 have_direction = true; 1091 direction_value = GPIO_PIN_OUTPUT; 1092 have_value = true; 1093 pin_value = 1; 1094 } 1095 1096 if (!have_cfg) 1097 return (0); 1098 1099 /* Find gpio */ 1100 gpio = NULL; 1101 for(i = 0; i < sc->conf->ngpio_bank; i++) { 1102 if (bank == sc->conf->gpio_bank[i].bank) { 1103 gpio = sc->conf->gpio_bank + i; 1104 break; 1105 } 1106 } 1107 if (gpio == NULL) { 1108 device_printf(sc->dev, "Cannot find GPIO bank %d\n", bank); 1109 return (ENXIO); 1110 } 1111 if (gpio->gpio_dev == NULL) { 1112 device_printf(sc->dev, 1113 "No GPIO subdevice found for bank %d\n", bank); 1114 return (ENXIO); 1115 } 1116 1117 rv = 0; 1118 if (have_value) { 1119 rv = GPIO_PIN_SET(gpio->gpio_dev, pin, pin_value); 1120 if (rv != 0) { 1121 device_printf(sc->dev, "Cannot set GPIO value: %d\n", 1122 rv); 1123 return (rv); 1124 } 1125 } 1126 1127 if (have_direction) { 1128 rv = GPIO_PIN_SETFLAGS(gpio->gpio_dev, pin, direction_value); 1129 if (rv != 0) { 1130 device_printf(sc->dev, 1131 "Cannot set GPIO direction: %d\n", rv); 1132 return (rv); 1133 } 1134 } 1135 1136 return (0); 1137 } 1138 1139 static void 1140 rk_pinctrl_configure_pin(struct rk_pinctrl_softc *sc, uint32_t *pindata) 1141 { 1142 phandle_t pin_conf; 1143 struct syscon *syscon; 1144 uint32_t bank, subbank, pin, function, bias; 1145 uint32_t bit, mask, reg, drive; 1146 int i, rv; 1147 1148 bank = pindata[0]; 1149 pin = pindata[1]; 1150 function = pindata[2]; 1151 pin_conf = OF_node_from_xref(pindata[3]); 1152 subbank = pin / 8; 1153 1154 for (i = 0; i < sc->conf->iomux_nbanks; i++) 1155 if (sc->conf->iomux_conf[i].bank == bank && 1156 sc->conf->iomux_conf[i].subbank == subbank) 1157 break; 1158 1159 if (i == sc->conf->iomux_nbanks) { 1160 device_printf(sc->dev, "Unknown pin %d in bank %d\n", pin, 1161 bank); 1162 return; 1163 } 1164 1165 /* Find syscon */ 1166 syscon = sc->conf->get_syscon(sc, bank); 1167 1168 /* Setup GPIO properties first */ 1169 rv = rk_pinctrl_handle_io(sc, pin_conf, bank, pin); 1170 1171 /* Then pin pull-up/down */ 1172 bias = sc->conf->parse_bias(pin_conf, bank); 1173 if (bias >= 0) { 1174 reg = sc->conf->get_pd_offset(sc, bank); 1175 reg += bank * 0x10 + ((pin / 8) * 0x4); 1176 bit = (pin % 8) * 2; 1177 mask = (0x3 << bit); 1178 SYSCON_MODIFY_4(syscon, reg, mask, bias << bit | (mask << 16)); 1179 } 1180 1181 /* Then drive strength */ 1182 if (ofw_bus_node_is_compatible(ofw_bus_get_node(sc->dev), 1183 "rockchip,rk3568-pinctrl")) { 1184 uint32_t value; 1185 if (OF_getencprop(pin_conf, "drive-strength", &value, 1186 sizeof(value)) == 0) { 1187 if (bank) 1188 reg = 0x01c0 + (bank * 0x40) + (pin / 2 * 4); 1189 else 1190 reg = 0x0070 + (pin / 2 * 4); 1191 1192 drive = ((1 << (value + 1)) - 1) << (pin % 2); 1193 1194 mask = 0x3f << (pin % 2);; 1195 1196 SYSCON_WRITE_4(syscon, reg, drive | (mask << 16)); 1197 } 1198 } else { 1199 rv = rk_pinctrl_parse_drive(sc, pin_conf, bank, subbank, &drive, 1200 ®); 1201 if (rv == 0) { 1202 bit = (pin % 8) * 2; 1203 mask = (0x3 << bit); 1204 SYSCON_MODIFY_4(syscon, reg, mask, 1205 drive << bit | (mask << 16)); 1206 } 1207 } 1208 1209 /* Finally set the pin function */ 1210 reg = sc->conf->iomux_conf[i].offset; 1211 switch (sc->conf->iomux_conf[i].nbits) { 1212 case 4: 1213 if ((pin % 8) >= 4) 1214 reg += 0x4; 1215 bit = (pin % 4) * 4; 1216 mask = (0xF << bit); 1217 break; 1218 case 3: 1219 if ((pin % 8) >= 5) 1220 reg += 4; 1221 bit = (pin % 8 % 5) * 3; 1222 mask = (0x7 << bit); 1223 break; 1224 case 2: 1225 bit = (pin % 8) * 2; 1226 mask = (0x3 << bit); 1227 break; 1228 default: 1229 device_printf(sc->dev, 1230 "Unknown pin stride width %d in bank %d\n", 1231 sc->conf->iomux_conf[i].nbits, bank); 1232 return; 1233 } 1234 rk_pinctrl_get_fixup(sc, bank, pin, ®, &mask, &bit); 1235 1236 /* 1237 * NOTE: not all syscon registers uses hi-word write mask, thus 1238 * register modify method should be used. 1239 * XXXX We should not pass write mask to syscon register 1240 * without hi-word write mask. 1241 */ 1242 SYSCON_MODIFY_4(syscon, reg, mask, function << bit | (mask << 16)); 1243 1244 /* RK3568 specific pin mux for various functionalities */ 1245 if (ofw_bus_node_is_compatible(ofw_bus_get_node(sc->dev), 1246 "rockchip,rk3568-pinctrl")) { 1247 if (bank == 3 && pin == 9 && function == 3) 1248 SYSCON_WRITE_4(sc->grf, 1249 GRF_IOFUNC_SEL0, GMAC1_IOMUX_SEL_M0); 1250 if (bank == 4 && pin == 7 && function == 3) 1251 SYSCON_WRITE_4(sc->grf, 1252 GRF_IOFUNC_SEL0, GMAC1_IOMUX_SEL_M1); 1253 } 1254 } 1255 1256 static int 1257 rk_pinctrl_configure_pins(device_t dev, phandle_t cfgxref) 1258 { 1259 struct rk_pinctrl_softc *sc; 1260 phandle_t node; 1261 uint32_t *pins; 1262 int i, npins; 1263 1264 sc = device_get_softc(dev); 1265 node = OF_node_from_xref(cfgxref); 1266 1267 npins = OF_getencprop_alloc_multi(node, "rockchip,pins", sizeof(*pins), 1268 (void **)&pins); 1269 if (npins <= 0) 1270 return (ENOENT); 1271 1272 for (i = 0; i != npins; i += 4) 1273 rk_pinctrl_configure_pin(sc, pins + i); 1274 1275 return (0); 1276 } 1277 1278 static int 1279 rk_pinctrl_is_gpio_locked(struct rk_pinctrl_softc *sc, struct syscon *syscon, 1280 int bank, uint32_t pin, bool *is_gpio) 1281 { 1282 uint32_t subbank, bit, mask, reg; 1283 uint32_t pinfunc; 1284 int i; 1285 1286 RK_PINCTRL_LOCK_ASSERT(sc); 1287 1288 subbank = pin / 8; 1289 *is_gpio = false; 1290 1291 for (i = 0; i < sc->conf->iomux_nbanks; i++) 1292 if (sc->conf->iomux_conf[i].bank == bank && 1293 sc->conf->iomux_conf[i].subbank == subbank) 1294 break; 1295 1296 if (i == sc->conf->iomux_nbanks) { 1297 device_printf(sc->dev, "Unknown pin %d in bank %d\n", pin, 1298 bank); 1299 return (EINVAL); 1300 } 1301 1302 syscon = sc->conf->get_syscon(sc, bank); 1303 1304 /* Parse pin function */ 1305 reg = sc->conf->iomux_conf[i].offset; 1306 switch (sc->conf->iomux_conf[i].nbits) { 1307 case 4: 1308 if ((pin % 8) >= 4) 1309 reg += 0x4; 1310 bit = (pin % 4) * 4; 1311 mask = (0xF << bit); 1312 break; 1313 case 3: 1314 if ((pin % 8) >= 5) 1315 reg += 4; 1316 bit = (pin % 8 % 5) * 3; 1317 mask = (0x7 << bit); 1318 break; 1319 case 2: 1320 bit = (pin % 8) * 2; 1321 mask = (0x3 << bit); 1322 break; 1323 default: 1324 device_printf(sc->dev, 1325 "Unknown pin stride width %d in bank %d\n", 1326 sc->conf->iomux_conf[i].nbits, bank); 1327 return (EINVAL); 1328 } 1329 rk_pinctrl_get_fixup(sc, bank, pin, ®, &mask, &bit); 1330 1331 reg = SYSCON_READ_4(syscon, reg); 1332 pinfunc = (reg & mask) >> bit; 1333 1334 /* Test if the pin is in gpio mode */ 1335 if (pinfunc == 0) 1336 *is_gpio = true; 1337 1338 return (0); 1339 } 1340 1341 static int 1342 rk_pinctrl_get_bank(struct rk_pinctrl_softc *sc, device_t gpio, int *bank) 1343 { 1344 int i; 1345 1346 for (i = 0; i < sc->conf->ngpio_bank; i++) { 1347 if (sc->conf->gpio_bank[i].gpio_dev == gpio) 1348 break; 1349 } 1350 if (i == sc->conf->ngpio_bank) 1351 return (EINVAL); 1352 1353 *bank = i; 1354 return (0); 1355 } 1356 1357 static int 1358 rk_pinctrl_is_gpio(device_t pinctrl, device_t gpio, uint32_t pin, bool *is_gpio) 1359 { 1360 struct rk_pinctrl_softc *sc; 1361 struct syscon *syscon; 1362 int bank; 1363 int rv; 1364 1365 sc = device_get_softc(pinctrl); 1366 RK_PINCTRL_LOCK(sc); 1367 1368 rv = rk_pinctrl_get_bank(sc, gpio, &bank); 1369 if (rv != 0) 1370 goto done; 1371 syscon = sc->conf->get_syscon(sc, bank); 1372 rv = rk_pinctrl_is_gpio_locked(sc, syscon, bank, pin, is_gpio); 1373 1374 done: 1375 RK_PINCTRL_UNLOCK(sc); 1376 1377 return (rv); 1378 } 1379 1380 static int 1381 rk_pinctrl_get_flags(device_t pinctrl, device_t gpio, uint32_t pin, 1382 uint32_t *flags) 1383 { 1384 struct rk_pinctrl_softc *sc; 1385 struct syscon *syscon; 1386 uint32_t reg, bit; 1387 uint32_t bias; 1388 int bank; 1389 int rv = 0; 1390 bool is_gpio; 1391 1392 sc = device_get_softc(pinctrl); 1393 RK_PINCTRL_LOCK(sc); 1394 1395 rv = rk_pinctrl_get_bank(sc, gpio, &bank); 1396 if (rv != 0) 1397 goto done; 1398 syscon = sc->conf->get_syscon(sc, bank); 1399 rv = rk_pinctrl_is_gpio_locked(sc, syscon, bank, pin, &is_gpio); 1400 if (rv != 0) 1401 goto done; 1402 if (!is_gpio) { 1403 rv = EINVAL; 1404 goto done; 1405 } 1406 /* Get the pullup/pulldown configuration */ 1407 reg = sc->conf->get_pd_offset(sc, bank); 1408 reg += bank * 0x10 + ((pin / 8) * 0x4); 1409 bit = (pin % 8) * 2; 1410 reg = SYSCON_READ_4(syscon, reg); 1411 reg = (reg >> bit) & 0x3; 1412 bias = sc->conf->resolv_bias_value(bank, reg); 1413 *flags = bias; 1414 1415 done: 1416 RK_PINCTRL_UNLOCK(sc); 1417 return (rv); 1418 } 1419 1420 static int 1421 rk_pinctrl_set_flags(device_t pinctrl, device_t gpio, uint32_t pin, 1422 uint32_t flags) 1423 { 1424 struct rk_pinctrl_softc *sc; 1425 struct syscon *syscon; 1426 uint32_t bit, mask, reg; 1427 uint32_t bias; 1428 int bank; 1429 int rv = 0; 1430 bool is_gpio; 1431 1432 sc = device_get_softc(pinctrl); 1433 RK_PINCTRL_LOCK(sc); 1434 1435 rv = rk_pinctrl_get_bank(sc, gpio, &bank); 1436 if (rv != 0) 1437 goto done; 1438 syscon = sc->conf->get_syscon(sc, bank); 1439 rv = rk_pinctrl_is_gpio_locked(sc, syscon, bank, pin, &is_gpio); 1440 if (rv != 0) 1441 goto done; 1442 if (!is_gpio) { 1443 rv = EINVAL; 1444 goto done; 1445 } 1446 /* Get the pullup/pulldown configuration */ 1447 reg = sc->conf->get_pd_offset(sc, bank); 1448 reg += bank * 0x10 + ((pin / 8) * 0x4); 1449 bit = (pin % 8) * 2; 1450 mask = (0x3 << bit); 1451 bias = sc->conf->get_bias_value(bank, flags); 1452 SYSCON_MODIFY_4(syscon, reg, mask, bias << bit | (mask << 16)); 1453 1454 done: 1455 RK_PINCTRL_UNLOCK(sc); 1456 return (rv); 1457 } 1458 1459 static int 1460 rk_pinctrl_probe(device_t dev) 1461 { 1462 1463 if (!ofw_bus_status_okay(dev)) 1464 return (ENXIO); 1465 1466 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 1467 return (ENXIO); 1468 1469 device_set_desc(dev, "RockChip Pinctrl controller"); 1470 return (BUS_PROBE_DEFAULT); 1471 } 1472 1473 static int 1474 rk_pinctrl_attach(device_t dev) 1475 { 1476 struct rk_pinctrl_softc *sc; 1477 phandle_t node; 1478 device_t cdev; 1479 int rv, gpio_unit; 1480 1481 sc = device_get_softc(dev); 1482 sc->dev = dev; 1483 1484 node = ofw_bus_get_node(dev); 1485 1486 if (OF_hasprop(node, "rockchip,grf") && 1487 syscon_get_by_ofw_property(dev, node, 1488 "rockchip,grf", &sc->grf) != 0) { 1489 device_printf(dev, "cannot get grf driver handle\n"); 1490 return (ENXIO); 1491 } 1492 1493 /* RK3568,RK3399,RK3288 have banks in PMU. RK3328 doesn't have a PMU. */ 1494 if (ofw_bus_node_is_compatible(node, "rockchip,rk3568-pinctrl") || 1495 ofw_bus_node_is_compatible(node, "rockchip,rk3399-pinctrl") || 1496 ofw_bus_node_is_compatible(node, "rockchip,rk3288-pinctrl")) { 1497 if (OF_hasprop(node, "rockchip,pmu") && 1498 syscon_get_by_ofw_property(dev, node, 1499 "rockchip,pmu", &sc->pmu) != 0) { 1500 device_printf(dev, "cannot get pmu driver handle\n"); 1501 return (ENXIO); 1502 } 1503 } 1504 1505 mtx_init(&sc->mtx, "rk pinctrl", "pinctrl", MTX_SPIN); 1506 1507 sc->conf = (struct rk_pinctrl_conf *)ofw_bus_search_compatible(dev, 1508 compat_data)->ocd_data; 1509 1510 fdt_pinctrl_register(dev, "rockchip,pins"); 1511 1512 simplebus_init(dev, node); 1513 1514 bus_generic_probe(dev); 1515 1516 /* Attach child devices */ 1517 for (node = OF_child(node), gpio_unit = 0; node > 0; 1518 node = OF_peer(node)) { 1519 if (!ofw_bus_node_is_compatible(node, "rockchip,gpio-bank")) 1520 continue; 1521 cdev = simplebus_add_device(dev, node, 0, NULL, -1, NULL); 1522 if (cdev == NULL) { 1523 device_printf(dev, " Cannot add GPIO subdevice\n"); 1524 gpio_unit += 1; 1525 continue; 1526 } 1527 rv = device_probe_and_attach(cdev); 1528 if (rv != 0) { 1529 device_printf(sc->dev, 1530 "Cannot attach GPIO subdevice\n"); 1531 gpio_unit += 1; 1532 continue; 1533 } 1534 sc->conf->gpio_bank[gpio_unit].gpio_dev = cdev; 1535 gpio_unit += 1; 1536 } 1537 1538 fdt_pinctrl_configure_tree(dev); 1539 1540 return (bus_generic_attach(dev)); 1541 } 1542 1543 static int 1544 rk_pinctrl_detach(device_t dev) 1545 { 1546 1547 return (EBUSY); 1548 } 1549 1550 static device_method_t rk_pinctrl_methods[] = { 1551 /* Device interface */ 1552 DEVMETHOD(device_probe, rk_pinctrl_probe), 1553 DEVMETHOD(device_attach, rk_pinctrl_attach), 1554 DEVMETHOD(device_detach, rk_pinctrl_detach), 1555 1556 /* fdt_pinctrl interface */ 1557 DEVMETHOD(fdt_pinctrl_configure, rk_pinctrl_configure_pins), 1558 DEVMETHOD(fdt_pinctrl_is_gpio, rk_pinctrl_is_gpio), 1559 DEVMETHOD(fdt_pinctrl_get_flags, rk_pinctrl_get_flags), 1560 DEVMETHOD(fdt_pinctrl_set_flags, rk_pinctrl_set_flags), 1561 1562 DEVMETHOD_END 1563 }; 1564 1565 DEFINE_CLASS_1(rk_pinctrl, rk_pinctrl_driver, rk_pinctrl_methods, 1566 sizeof(struct rk_pinctrl_softc), simplebus_driver); 1567 1568 EARLY_DRIVER_MODULE(rk_pinctrl, simplebus, rk_pinctrl_driver, 0, 0, 1569 BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE); 1570 MODULE_VERSION(rk_pinctrl, 1); 1571