1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2019 Michal Meloun <mmel@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 */ 28 29 /* Rockchip PCIe controller driver */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/bus.h> 37 #include <sys/gpio.h> 38 #include <sys/proc.h> 39 #include <sys/kernel.h> 40 #include <sys/lock.h> 41 #include <sys/malloc.h> 42 #include <sys/module.h> 43 #include <sys/mutex.h> 44 #include <sys/rman.h> 45 46 #include <machine/bus.h> 47 #include <machine/intr.h> 48 #include <machine/resource.h> 49 50 #include <dev/extres/clk/clk.h> 51 #include <dev/extres/hwreset/hwreset.h> 52 #include <dev/extres/phy/phy.h> 53 #include <dev/extres/regulator/regulator.h> 54 #include <dev/gpio/gpiobusvar.h> 55 #include <dev/ofw/ofw_bus.h> 56 #include <dev/ofw/ofw_bus_subr.h> 57 #include <dev/ofw/ofw_pci.h> 58 #include <dev/ofw/ofwpci.h> 59 #include <dev/pci/pcivar.h> 60 #include <dev/pci/pcireg.h> 61 #include <dev/pci/pcib_private.h> 62 63 #include <dev/ofw/ofw_bus.h> 64 65 #include "pcib_if.h" 66 67 #define ATU_CFG_BUS(x) (((x) & 0x0ff) << 20) 68 #define ATU_CFG_SLOT(x) (((x) & 0x01f) << 15) 69 #define ATU_CFG_FUNC(x) (((x) & 0x007) << 12) 70 #define ATU_CFG_REG(x) (((x) & 0xfff) << 0) 71 72 #define ATU_TYPE_MEM 0x2 73 #define ATU_TYPE_IO 0x6 74 #define ATU_TYPE_CFG0 0xA 75 #define ATU_TYPE_CFG1 0xB 76 #define ATY_TYPE_NOR_MSG 0xC 77 78 #define ATU_OB_REGIONS 33 79 #define ATU_OB_REGION_SHIFT 20 80 #define ATU_OB_REGION_SIZE (1 << ATU_OB_REGION_SHIFT) 81 #define ATU_OB_REGION_0_SIZE (( ATU_OB_REGIONS - 1) * ATU_OB_REGION_SIZE) 82 83 #define ATU_IB_REGIONS 3 84 85 #define PCIE_CLIENT_BASIC_STRAP_CONF 0x000000 86 #define STRAP_CONF_GEN_2 (1 << 7) 87 #define STRAP_CONF_MODE_RC (1 << 6) 88 #define STRAP_CONF_LANES(n) ((((n) / 2) & 0x3) << 4) 89 #define STRAP_CONF_ARI_EN (1 << 3) 90 #define STRAP_CONF_SR_IOV_EN (1 << 2) 91 #define STRAP_CONF_LINK_TRAIN_EN (1 << 1) 92 #define STRAP_CONF_CONF_EN (1 << 0) 93 #define PCIE_CLIENT_HOT_RESET_CTRL 0x000018 94 #define HOT_RESET_CTRL_LINK_DOWN_RESET (1 << 1) 95 #define HOT_RESET_CTRL_HOT_RESET_IN (1 << 0) 96 #define PCIE_CLIENT_BASIC_STATUS0 0x000044 97 #define PCIE_CLIENT_BASIC_STATUS1 0x000048 98 #define STATUS1_LINK_ST_GET(x) (((x) >> 20) & 0x3) 99 #define STATUS1_LINK_ST_UP 3 100 #define PCIE_CLIENT_INT_MASK 0x00004C 101 #define PCIE_CLIENT_INT_STATUS 0x000050 102 #define PCIE_CLIENT_INT_LEGACY_DONE (1 << 15) 103 #define PCIE_CLIENT_INT_MSG (1 << 14) 104 #define PCIE_CLIENT_INT_HOT_RST (1 << 13) 105 #define PCIE_CLIENT_INT_DPA (1 << 12) 106 #define PCIE_CLIENT_INT_FATAL_ERR (1 << 11) 107 #define PCIE_CLIENT_INT_NFATAL_ERR (1 << 10) 108 #define PCIE_CLIENT_INT_CORR_ERR (1 << 9) 109 #define PCIE_CLIENT_INT_INTD (1 << 8) 110 #define PCIE_CLIENT_INT_INTC (1 << 7) 111 #define PCIE_CLIENT_INT_INTB (1 << 6) 112 #define PCIE_CLIENT_INT_INTA (1 << 5) 113 #define PCIE_CLIENT_INT_LOCAL (1 << 4) 114 #define PCIE_CLIENT_INT_UDMA (1 << 3) 115 #define PCIE_CLIENT_INT_PHY (1 << 2) 116 #define PCIE_CLIENT_INT_HOT_PLUG (1 << 1) 117 #define PCIE_CLIENT_INT_PWR_STCG (1 << 0) 118 #define PCIE_CLIENT_INT_LEGACY (PCIE_CLIENT_INT_INTA | \ 119 PCIE_CLIENT_INT_INTB | \ 120 PCIE_CLIENT_INT_INTC | \ 121 PCIE_CLIENT_INT_INTD) 122 123 #define PCIE_CORE_CTRL0 0x900000 124 #define CORE_CTRL_LANES_GET(x) (((x) >> 20) & 0x3) 125 #define PCIE_CORE_CTRL1 0x900004 126 #define PCIE_CORE_CONFIG_VENDOR 0x900044 127 #define PCIE_CORE_INT_STATUS 0x90020c 128 #define PCIE_CORE_INT_PRFPE (1 << 0) 129 #define PCIE_CORE_INT_CRFPE (1 << 1) 130 #define PCIE_CORE_INT_RRPE (1 << 2) 131 #define PCIE_CORE_INT_PRFO (1 << 3) 132 #define PCIE_CORE_INT_CRFO (1 << 4) 133 #define PCIE_CORE_INT_RT (1 << 5) 134 #define PCIE_CORE_INT_RTR (1 << 6) 135 #define PCIE_CORE_INT_PE (1 << 7) 136 #define PCIE_CORE_INT_MTR (1 << 8) 137 #define PCIE_CORE_INT_UCR (1 << 9) 138 #define PCIE_CORE_INT_FCE (1 << 10) 139 #define PCIE_CORE_INT_CT (1 << 11) 140 #define PCIE_CORE_INT_UTC (1 << 18) 141 #define PCIE_CORE_INT_MMVC (1 << 19) 142 #define PCIE_CORE_INT_MASK 0x900210 143 #define PCIE_CORE_PHY_FUNC_CONF 0x9002C0 144 #define PCIE_CORE_RC_BAR_CONF 0x900300 145 146 #define PCIE_RC_CONFIG_STD_BASE 0x800000 147 #define PCIE_RC_CONFIG_PRIV_BASE 0xA00000 148 #define PCIE_RC_CONFIG_DCSR 0xA000C8 149 #define PCIE_RC_CONFIG_DCSR_MPS_MASK (0x7 << 5) 150 #define PCIE_RC_CONFIG_DCSR_MPS_128 (0 << 5) 151 #define PCIE_RC_CONFIG_DCSR_MPS_256 (1 << 5) 152 #define PCIE_RC_CONFIG_LINK_CAP 0xA00CC 153 #define PCIE_RC_CONFIG_LINK_CAP_L0S (1 << 10) 154 155 #define PCIE_RC_CONFIG_LCS 0xA000D0 156 #define PCIE_RC_CONFIG_THP_CAP 0xA00274 157 #define PCIE_RC_CONFIG_THP_CAP_NEXT_MASK 0xFFF00000 158 159 #define PCIE_CORE_OB_ADDR0(n) (0xC00000 + 0x20 * (n) + 0x00) 160 #define PCIE_CORE_OB_ADDR1(n) (0xC00000 + 0x20 * (n) + 0x04) 161 #define PCIE_CORE_OB_DESC0(n) (0xC00000 + 0x20 * (n) + 0x08) 162 #define PCIE_CORE_OB_DESC1(n) (0xC00000 + 0x20 * (n) + 0x0C) 163 #define PCIE_CORE_OB_DESC2(n) (0xC00000 + 0x20 * (n) + 0x10) 164 #define PCIE_CORE_OB_DESC3(n) (0xC00000 + 0x20 * (n) + 0x14) 165 166 #define PCIE_CORE_IB_ADDR0(n) (0xC00800 + 0x8 * (n) + 0x00) 167 #define PCIE_CORE_IB_ADDR1(n) (0xC00800 + 0x8 * (n) + 0x04) 168 169 #define PRIV_CFG_RD4(sc, reg) \ 170 (uint32_t)rk_pcie_local_cfg_read(sc, true, reg, 4) 171 #define PRIV_CFG_RD2(sc, reg) \ 172 (uint16_t)rk_pcie_local_cfg_read(sc, true, reg, 2) 173 #define PRIV_CFG_RD1(sc, reg) \ 174 (uint8_t)rk_pcie_local_cfg_read(sc, true, reg, 1) 175 #define PRIV_CFG_WR4(sc, reg, val) \ 176 rk_pcie_local_cfg_write(sc, true, reg, val, 4) 177 #define PRIV_CFG_WR2(sc, reg, val) \ 178 rk_pcie_local_cfg_write(sc, true, reg, val, 2) 179 #define PRIV_CFG_WR1(sc, reg, val) \ 180 rk_pcie_local_cfg_write(sc, true, reg, val, 1) 181 182 #define APB_WR4(_sc, _r, _v) bus_write_4((_sc)->apb_mem_res, (_r), (_v)) 183 #define APB_RD4(_sc, _r) bus_read_4((_sc)->apb_mem_res, (_r)) 184 185 #define MAX_LANES 4 186 187 #define RK_PCIE_ENABLE_MSI 188 #define RK_PCIE_ENABLE_MSIX 189 190 struct rk_pcie_softc { 191 struct ofw_pci_softc ofw_pci; /* Must be first */ 192 193 struct resource *axi_mem_res; 194 struct resource *apb_mem_res; 195 struct resource *client_irq_res; 196 struct resource *legacy_irq_res; 197 struct resource *sys_irq_res; 198 void *client_irq_cookie; 199 void *legacy_irq_cookie; 200 void *sys_irq_cookie; 201 202 device_t dev; 203 phandle_t node; 204 struct mtx mtx; 205 206 struct ofw_pci_range mem_range; 207 struct ofw_pci_range pref_mem_range; 208 struct ofw_pci_range io_range; 209 210 bool coherent; 211 bus_dma_tag_t dmat; 212 213 int num_lanes; 214 bool link_is_gen2; 215 bool no_l0s; 216 217 u_int bus_start; 218 u_int bus_end; 219 u_int root_bus; 220 u_int sub_bus; 221 222 regulator_t supply_12v; 223 regulator_t supply_3v3; 224 regulator_t supply_1v8; 225 regulator_t supply_0v9; 226 hwreset_t hwreset_core; 227 hwreset_t hwreset_mgmt; 228 hwreset_t hwreset_mgmt_sticky; 229 hwreset_t hwreset_pipe; 230 hwreset_t hwreset_pm; 231 hwreset_t hwreset_aclk; 232 hwreset_t hwreset_pclk; 233 clk_t clk_aclk; 234 clk_t clk_aclk_perf; 235 clk_t clk_hclk; 236 clk_t clk_pm; 237 phy_t phys[MAX_LANES]; 238 gpio_pin_t gpio_ep; 239 }; 240 241 /* Compatible devices. */ 242 static struct ofw_compat_data compat_data[] = { 243 {"rockchip,rk3399-pcie", 1}, 244 {NULL, 0}, 245 }; 246 247 static uint32_t 248 rk_pcie_local_cfg_read(struct rk_pcie_softc *sc, bool priv, u_int reg, 249 int bytes) 250 { 251 uint32_t val; 252 bus_addr_t base; 253 254 if (priv) 255 base = PCIE_RC_CONFIG_PRIV_BASE; 256 else 257 base = PCIE_RC_CONFIG_STD_BASE; 258 259 switch (bytes) { 260 case 4: 261 val = bus_read_4(sc->apb_mem_res, base + reg); 262 break; 263 case 2: 264 val = bus_read_2(sc->apb_mem_res, base + reg); 265 break; 266 case 1: 267 val = bus_read_1(sc->apb_mem_res, base + reg); 268 break; 269 default: 270 val = 0xFFFFFFFF; 271 } 272 return (val); 273 } 274 275 static void 276 rk_pcie_local_cfg_write(struct rk_pcie_softc *sc, bool priv, u_int reg, 277 uint32_t val, int bytes) 278 { 279 uint32_t val2; 280 bus_addr_t base; 281 282 if (priv) 283 base = PCIE_RC_CONFIG_PRIV_BASE; 284 else 285 base = PCIE_RC_CONFIG_STD_BASE; 286 287 switch (bytes) { 288 case 4: 289 bus_write_4(sc->apb_mem_res, base + reg, val); 290 break; 291 case 2: 292 val2 = bus_read_4(sc->apb_mem_res, base + (reg & ~3)); 293 val2 &= ~(0xffff << ((reg & 3) << 3)); 294 val2 |= ((val & 0xffff) << ((reg & 3) << 3)); 295 bus_write_4(sc->apb_mem_res, base + (reg & ~3), val2); 296 break; 297 case 1: 298 val2 = bus_read_4(sc->apb_mem_res, base + (reg & ~3)); 299 val2 &= ~(0xff << ((reg & 3) << 3)); 300 val2 |= ((val & 0xff) << ((reg & 3) << 3)); 301 bus_write_4(sc->apb_mem_res, base + (reg & ~3), val2); 302 break; 303 } 304 } 305 306 static bool 307 rk_pcie_check_dev(struct rk_pcie_softc *sc, u_int bus, u_int slot, u_int func, 308 u_int reg) 309 { 310 uint32_t val; 311 312 if (bus < sc->bus_start || bus > sc->bus_end || slot > PCI_SLOTMAX || 313 func > PCI_FUNCMAX || reg > PCI_REGMAX) 314 return (false); 315 316 if (bus == sc->root_bus) { 317 /* we have only 1 device with 1 function root port */ 318 if (slot > 0 || func > 0) 319 return (false); 320 return (true); 321 } 322 323 /* link is needed for accessing non-root busses */ 324 val = APB_RD4(sc, PCIE_CLIENT_BASIC_STATUS1); 325 if (STATUS1_LINK_ST_GET(val) != STATUS1_LINK_ST_UP) 326 return (false); 327 328 /* only one device is on first subordinate bus */ 329 if (bus == sc->sub_bus && slot) 330 return (false); 331 return (true); 332 } 333 334 static void 335 rk_pcie_map_out_atu(struct rk_pcie_softc *sc, int idx, int type, 336 int num_bits, uint64_t pa) 337 { 338 uint32_t addr0; 339 uint64_t max_size; 340 341 /* Check HW constrains */ 342 max_size = idx == 0 ? ATU_OB_REGION_0_SIZE: ATU_OB_REGION_SIZE; 343 KASSERT(idx < ATU_OB_REGIONS, ("Invalid region index: %d\n", idx)); 344 KASSERT(num_bits >= 7 && num_bits <= 63, 345 ("Bit width of region is invalid: %d\n", num_bits)); 346 KASSERT(max_size <= (1ULL << (num_bits + 1)), 347 ("Bit width is invalid for given region[%d]: %d\n", idx, num_bits)); 348 349 addr0 = (uint32_t)pa & 0xFFFFFF00; 350 addr0 |= num_bits; 351 APB_WR4(sc, PCIE_CORE_OB_ADDR0(idx), addr0); 352 APB_WR4(sc, PCIE_CORE_OB_ADDR1(idx), (uint32_t)(pa >> 32)); 353 APB_WR4(sc, PCIE_CORE_OB_DESC0(idx), 1 << 23 | type); 354 APB_WR4(sc, PCIE_CORE_OB_DESC1(idx), sc->root_bus); 355 356 /* Readback for sync */ 357 APB_RD4(sc, PCIE_CORE_OB_DESC1(idx)); 358 } 359 360 static void 361 rk_pcie_map_cfg_atu(struct rk_pcie_softc *sc, int idx, int type) 362 { 363 364 /* Check HW constrains */ 365 KASSERT(idx < ATU_OB_REGIONS, ("Invalid region index: %d\n", idx)); 366 367 /* 368 * Config window is only 25 bits width, so we cannot encode full bus 369 * range into it. Remaining bits of bus number should be taken from 370 * DESC1 field. 371 */ 372 APB_WR4(sc, PCIE_CORE_OB_ADDR0(idx), 25 - 1); 373 APB_WR4(sc, PCIE_CORE_OB_ADDR1(idx), 0); 374 APB_WR4(sc, PCIE_CORE_OB_DESC0(idx), 1 << 23 | type); 375 APB_WR4(sc, PCIE_CORE_OB_DESC1(idx), sc->root_bus); 376 377 /* Readback for sync */ 378 APB_RD4(sc, PCIE_CORE_OB_DESC1(idx)); 379 380 } 381 382 static void 383 rk_pcie_map_in_atu(struct rk_pcie_softc *sc, int idx, int num_bits, uint64_t pa) 384 { 385 uint32_t addr0; 386 387 /* Check HW constrains */ 388 KASSERT(idx < ATU_IB_REGIONS, ("Invalid region index: %d\n", idx)); 389 KASSERT(num_bits >= 7 && num_bits <= 63, 390 ("Bit width of region is invalid: %d\n", num_bits)); 391 392 addr0 = (uint32_t)pa & 0xFFFFFF00; 393 addr0 |= num_bits; 394 APB_WR4(sc, PCIE_CORE_IB_ADDR0(idx), addr0); 395 APB_WR4(sc, PCIE_CORE_IB_ADDR1(idx), (uint32_t)(pa >> 32)); 396 397 /* Readback for sync */ 398 APB_RD4(sc, PCIE_CORE_IB_ADDR1(idx)); 399 } 400 401 static int 402 rk_pcie_decode_ranges(struct rk_pcie_softc *sc, struct ofw_pci_range *ranges, 403 int nranges) 404 { 405 int i; 406 407 for (i = 0; i < nranges; i++) { 408 if ((ranges[i].pci_hi & OFW_PCI_PHYS_HI_SPACEMASK) == 409 OFW_PCI_PHYS_HI_SPACE_IO) { 410 if (sc->io_range.size != 0) { 411 device_printf(sc->dev, 412 "Duplicated IO range found in DT\n"); 413 return (ENXIO); 414 } 415 sc->io_range = ranges[i]; 416 } 417 if (((ranges[i].pci_hi & OFW_PCI_PHYS_HI_SPACEMASK) == 418 OFW_PCI_PHYS_HI_SPACE_MEM64)) { 419 if (ranges[i].pci_hi & OFW_PCI_PHYS_HI_PREFETCHABLE) { 420 if (sc->pref_mem_range.size != 0) { 421 device_printf(sc->dev, 422 "Duplicated memory range found " 423 "in DT\n"); 424 return (ENXIO); 425 } 426 sc->pref_mem_range = ranges[i]; 427 } else { 428 if (sc->mem_range.size != 0) { 429 device_printf(sc->dev, 430 "Duplicated memory range found " 431 "in DT\n"); 432 return (ENXIO); 433 } 434 sc->mem_range = ranges[i]; 435 } 436 } 437 } 438 if (sc->mem_range.size == 0) { 439 device_printf(sc->dev, 440 " At least memory range should be defined in DT.\n"); 441 return (ENXIO); 442 } 443 return (0); 444 } 445 446 /*----------------------------------------------------------------------------- 447 * 448 * P C I B I N T E R F A C E 449 */ 450 static uint32_t 451 rk_pcie_read_config(device_t dev, u_int bus, u_int slot, 452 u_int func, u_int reg, int bytes) 453 { 454 struct rk_pcie_softc *sc; 455 uint32_t data; 456 uint64_t addr; 457 int type; 458 459 sc = device_get_softc(dev); 460 461 if (!rk_pcie_check_dev(sc, bus, slot, func, reg)) 462 return (0xFFFFFFFFU); 463 464 if (bus == sc->root_bus) 465 return (rk_pcie_local_cfg_read(sc, false, reg, bytes)); 466 467 addr = ATU_CFG_BUS(bus) | ATU_CFG_SLOT(slot) | ATU_CFG_FUNC(func) | 468 ATU_CFG_REG(reg); 469 if (bus == sc->sub_bus) { 470 type = ATU_TYPE_CFG0; 471 } else { 472 type = ATU_TYPE_CFG1; 473 /* 474 * XXX FIXME: any attempt to generate type1 configuration 475 * access causes external data abort 476 */ 477 return (0xFFFFFFFFU); 478 } 479 rk_pcie_map_cfg_atu(sc, 0, type); 480 481 switch (bytes) { 482 case 1: 483 data = bus_read_1(sc->axi_mem_res, addr); 484 break; 485 case 2: 486 data = bus_read_2(sc->axi_mem_res, addr); 487 break; 488 case 4: 489 data = bus_read_4(sc->axi_mem_res, addr); 490 break; 491 default: 492 data = 0xFFFFFFFFU; 493 } 494 return (data); 495 } 496 497 static void 498 rk_pcie_write_config(device_t dev, u_int bus, u_int slot, 499 u_int func, u_int reg, uint32_t val, int bytes) 500 { 501 struct rk_pcie_softc *sc; 502 uint64_t addr; 503 int type; 504 505 sc = device_get_softc(dev); 506 507 if (!rk_pcie_check_dev(sc, bus, slot, func, reg)) 508 return; 509 510 if (bus == sc->root_bus) 511 return (rk_pcie_local_cfg_write(sc, false, reg, val, bytes)); 512 513 addr = ATU_CFG_BUS(bus) | ATU_CFG_SLOT(slot) | ATU_CFG_FUNC(func) | 514 ATU_CFG_REG(reg); 515 if (bus == sc->sub_bus){ 516 type = ATU_TYPE_CFG0; 517 } else { 518 type = ATU_TYPE_CFG1; 519 /* 520 * XXX FIXME: any attempt to generate type1 configuration 521 * access causes external data abort 522 */ 523 return; 524 } 525 rk_pcie_map_cfg_atu(sc, 0, type); 526 527 switch (bytes) { 528 case 1: 529 bus_write_1(sc->axi_mem_res, addr, val); 530 break; 531 case 2: 532 bus_write_2(sc->axi_mem_res, addr, val); 533 break; 534 case 4: 535 bus_write_4(sc->axi_mem_res, addr, val); 536 break; 537 default: 538 break; 539 } 540 } 541 542 #ifdef RK_PCIE_ENABLE_MSI 543 static int 544 rk_pcie_alloc_msi(device_t pci, device_t child, int count, 545 int maxcount, int *irqs) 546 { 547 phandle_t msi_parent; 548 int rv; 549 550 rv = ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), 551 &msi_parent, NULL); 552 if (rv != 0) 553 return (rv); 554 555 rv = intr_alloc_msi(pci, child, msi_parent, count, maxcount,irqs); 556 return (rv); 557 } 558 559 static int 560 rk_pcie_release_msi(device_t pci, device_t child, int count, int *irqs) 561 { 562 phandle_t msi_parent; 563 int rv; 564 565 rv = ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), 566 &msi_parent, NULL); 567 if (rv != 0) 568 return (rv); 569 rv = intr_release_msi(pci, child, msi_parent, count, irqs); 570 return (rv); 571 } 572 #endif 573 574 static int 575 rk_pcie_map_msi(device_t pci, device_t child, int irq, uint64_t *addr, 576 uint32_t *data) 577 { 578 phandle_t msi_parent; 579 int rv; 580 581 rv = ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), 582 &msi_parent, NULL); 583 if (rv != 0) 584 return (rv); 585 rv = intr_map_msi(pci, child, msi_parent, irq, addr, data); 586 return (rv); 587 } 588 589 #ifdef RK_PCIE_ENABLE_MSIX 590 static int 591 rk_pcie_alloc_msix(device_t pci, device_t child, int *irq) 592 { 593 phandle_t msi_parent; 594 int rv; 595 596 rv = ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), 597 &msi_parent, NULL); 598 if (rv != 0) 599 return (rv); 600 rv = intr_alloc_msix(pci, child, msi_parent, irq); 601 return (rv); 602 } 603 604 static int 605 rk_pcie_release_msix(device_t pci, device_t child, int irq) 606 { 607 phandle_t msi_parent; 608 int rv; 609 610 rv = ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), 611 &msi_parent, NULL); 612 if (rv != 0) 613 return (rv); 614 rv = intr_release_msix(pci, child, msi_parent, irq); 615 return (rv); 616 } 617 #endif 618 619 static int 620 rk_pcie_get_id(device_t pci, device_t child, enum pci_id_type type, 621 uintptr_t *id) 622 { 623 phandle_t node; 624 int rv; 625 uint32_t rid; 626 uint16_t pci_rid; 627 628 if (type != PCI_ID_MSI) 629 return (pcib_get_id(pci, child, type, id)); 630 631 node = ofw_bus_get_node(pci); 632 pci_rid = pci_get_rid(child); 633 634 rv = ofw_bus_msimap(node, pci_rid, NULL, &rid); 635 if (rv != 0) 636 return (rv); 637 638 *id = rid; 639 return (0); 640 } 641 642 static int 643 rk_pcie_route_interrupt(device_t bus, device_t dev, int pin) 644 { 645 struct rk_pcie_softc *sc; 646 u_int irq; 647 648 sc = device_get_softc(bus); 649 irq = intr_map_clone_irq(rman_get_start(sc->legacy_irq_res)); 650 device_printf(bus, "route pin %d for device %d.%d to %u\n", 651 pin, pci_get_slot(dev), pci_get_function(dev), irq); 652 653 return (irq); 654 } 655 656 /*----------------------------------------------------------------------------- 657 * 658 * B U S / D E V I C E I N T E R F A C E 659 */ 660 static int 661 rk_pcie_parse_fdt_resources(struct rk_pcie_softc *sc) 662 { 663 int i, rv; 664 char buf[16]; 665 666 /* Regulators. All are optional. */ 667 rv = regulator_get_by_ofw_property(sc->dev, 0, 668 "vpcie12v-supply", &sc->supply_12v); 669 if (rv != 0 && rv != ENOENT) { 670 device_printf(sc->dev,"Cannot get 'vpcie12' regulator\n"); 671 return (ENXIO); 672 } 673 rv = regulator_get_by_ofw_property(sc->dev, 0, 674 "vpcie3v3-supply", &sc->supply_3v3); 675 if (rv != 0 && rv != ENOENT) { 676 device_printf(sc->dev,"Cannot get 'vpcie3v3' regulator\n"); 677 return (ENXIO); 678 } 679 rv = regulator_get_by_ofw_property(sc->dev, 0, 680 "vpcie1v8-supply", &sc->supply_1v8); 681 if (rv != 0 && rv != ENOENT) { 682 device_printf(sc->dev,"Cannot get 'vpcie1v8' regulator\n"); 683 return (ENXIO); 684 } 685 rv = regulator_get_by_ofw_property(sc->dev, 0, 686 "vpcie0v9-supply", &sc->supply_0v9); 687 if (rv != 0 && rv != ENOENT) { 688 device_printf(sc->dev,"Cannot get 'vpcie0v9' regulator\n"); 689 return (ENXIO); 690 } 691 692 /* Resets. */ 693 rv = hwreset_get_by_ofw_name(sc->dev, 0, "core", &sc->hwreset_core); 694 if (rv != 0) { 695 device_printf(sc->dev, "Cannot get 'core' reset\n"); 696 return (ENXIO); 697 } 698 rv = hwreset_get_by_ofw_name(sc->dev, 0, "mgmt", &sc->hwreset_mgmt); 699 if (rv != 0) { 700 device_printf(sc->dev, "Cannot get 'mgmt' reset\n"); 701 return (ENXIO); 702 } 703 rv = hwreset_get_by_ofw_name(sc->dev, 0, "mgmt-sticky", 704 &sc->hwreset_mgmt_sticky); 705 if (rv != 0) { 706 device_printf(sc->dev, "Cannot get 'mgmt-sticky' reset\n"); 707 return (ENXIO); 708 } 709 rv = hwreset_get_by_ofw_name(sc->dev, 0, "pipe", &sc->hwreset_pipe); 710 if (rv != 0) { 711 device_printf(sc->dev, "Cannot get 'pipe' reset\n"); 712 return (ENXIO); 713 } 714 rv = hwreset_get_by_ofw_name(sc->dev, 0, "pm", &sc->hwreset_pm); 715 if (rv != 0) { 716 device_printf(sc->dev, "Cannot get 'pm' reset\n"); 717 return (ENXIO); 718 } 719 rv = hwreset_get_by_ofw_name(sc->dev, 0, "aclk", &sc->hwreset_aclk); 720 if (rv != 0) { 721 device_printf(sc->dev, "Cannot get 'aclk' reset\n"); 722 return (ENXIO); 723 } 724 rv = hwreset_get_by_ofw_name(sc->dev, 0, "pclk", &sc->hwreset_pclk); 725 if (rv != 0) { 726 device_printf(sc->dev, "Cannot get 'pclk' reset\n"); 727 return (ENXIO); 728 } 729 730 /* Clocks. */ 731 rv = clk_get_by_ofw_name(sc->dev, 0, "aclk", &sc->clk_aclk); 732 if (rv != 0) { 733 device_printf(sc->dev, "Cannot get 'aclk' clock\n"); 734 return (ENXIO); 735 } 736 rv = clk_get_by_ofw_name(sc->dev, 0, "aclk-perf", &sc->clk_aclk_perf); 737 if (rv != 0) { 738 device_printf(sc->dev, "Cannot get 'aclk-perf' clock\n"); 739 return (ENXIO); 740 } 741 rv = clk_get_by_ofw_name(sc->dev, 0, "hclk", &sc->clk_hclk); 742 if (rv != 0) { 743 device_printf(sc->dev, "Cannot get 'hclk' clock\n"); 744 return (ENXIO); 745 } 746 rv = clk_get_by_ofw_name(sc->dev, 0, "pm", &sc->clk_pm); 747 if (rv != 0) { 748 device_printf(sc->dev, "Cannot get 'pm' clock\n"); 749 return (ENXIO); 750 } 751 752 /* Phys. */ 753 for (i = 0; i < MAX_LANES; i++ ) { 754 sprintf (buf, "pcie-phy-%d", i); 755 rv = phy_get_by_ofw_name(sc->dev, 0, buf, sc->phys + i); 756 if (rv != 0) { 757 device_printf(sc->dev, "Cannot get '%s' phy\n", buf); 758 return (ENXIO); 759 } 760 } 761 762 /* GPIO for PERST#. Optional */ 763 rv = gpio_pin_get_by_ofw_property(sc->dev, sc->node, "ep-gpios", 764 &sc->gpio_ep); 765 if (rv != 0 && rv != ENOENT) { 766 device_printf(sc->dev, "Cannot get 'ep-gpios' gpio\n"); 767 return (ENXIO); 768 } 769 770 return (0); 771 } 772 773 static int 774 rk_pcie_enable_resources(struct rk_pcie_softc *sc) 775 { 776 int i, rv; 777 uint32_t val; 778 779 /* Assert all resets */ 780 rv = hwreset_assert(sc->hwreset_pclk); 781 if (rv != 0) { 782 device_printf(sc->dev, "Cannot assert 'pclk' reset\n"); 783 return (rv); 784 } 785 rv = hwreset_assert(sc->hwreset_aclk); 786 if (rv != 0) { 787 device_printf(sc->dev, "Cannot assert 'aclk' reset\n"); 788 return (rv); 789 } 790 rv = hwreset_assert(sc->hwreset_pm); 791 if (rv != 0) { 792 device_printf(sc->dev, "Cannot assert 'pm' reset\n"); 793 return (rv); 794 } 795 rv = hwreset_assert(sc->hwreset_pipe); 796 if (rv != 0) { 797 device_printf(sc->dev, "Cannot assert 'pipe' reset\n"); 798 return (rv); 799 } 800 rv = hwreset_assert(sc->hwreset_mgmt_sticky); 801 if (rv != 0) { 802 device_printf(sc->dev, "Cannot assert 'mgmt_sticky' reset\n"); 803 return (rv); 804 } 805 rv = hwreset_assert(sc->hwreset_mgmt); 806 if (rv != 0) { 807 device_printf(sc->dev, "Cannot assert 'hmgmt' reset\n"); 808 return (rv); 809 } 810 rv = hwreset_assert(sc->hwreset_core); 811 if (rv != 0) { 812 device_printf(sc->dev, "Cannot assert 'hcore' reset\n"); 813 return (rv); 814 } 815 DELAY(10000); 816 817 /* Enable clockls */ 818 rv = clk_enable(sc->clk_aclk); 819 if (rv != 0) { 820 device_printf(sc->dev, "Cannot enable 'aclk' clock\n"); 821 return (rv); 822 } 823 rv = clk_enable(sc->clk_aclk_perf); 824 if (rv != 0) { 825 device_printf(sc->dev, "Cannot enable 'aclk_perf' clock\n"); 826 return (rv); 827 } 828 rv = clk_enable(sc->clk_hclk); 829 if (rv != 0) { 830 device_printf(sc->dev, "Cannot enable 'hclk' clock\n"); 831 return (rv); 832 } 833 rv = clk_enable(sc->clk_pm); 834 if (rv != 0) { 835 device_printf(sc->dev, "Cannot enable 'pm' clock\n"); 836 return (rv); 837 } 838 839 /* Power up regulators */ 840 if (sc->supply_12v != NULL) { 841 rv = regulator_enable(sc->supply_12v); 842 if (rv != 0) { 843 device_printf(sc->dev, 844 "Cannot enable 'vpcie12' regulator\n"); 845 return (rv); 846 } 847 } 848 if (sc->supply_3v3 != NULL) { 849 rv = regulator_enable(sc->supply_3v3); 850 if (rv != 0) { 851 device_printf(sc->dev, 852 "Cannot enable 'vpcie3v3' regulator\n"); 853 return (rv); 854 } 855 } 856 if (sc->supply_1v8 != NULL) { 857 rv = regulator_enable(sc->supply_1v8); 858 if (rv != 0) { 859 device_printf(sc->dev, 860 "Cannot enable 'vpcie1v8' regulator\n"); 861 return (rv); 862 } 863 } 864 if (sc->supply_0v9 != NULL) { 865 rv = regulator_enable(sc->supply_0v9); 866 if (rv != 0) { 867 device_printf(sc->dev, 868 "Cannot enable 'vpcie1v8' regulator\n"); 869 return (rv); 870 } 871 } 872 DELAY(1000); 873 874 /* Deassert basic resets*/ 875 rv = hwreset_deassert(sc->hwreset_pm); 876 if (rv != 0) { 877 device_printf(sc->dev, "Cannot deassert 'pm' reset\n"); 878 return (rv); 879 } 880 rv = hwreset_deassert(sc->hwreset_aclk); 881 if (rv != 0) { 882 device_printf(sc->dev, "Cannot deassert 'aclk' reset\n"); 883 return (rv); 884 } 885 rv = hwreset_deassert(sc->hwreset_pclk); 886 if (rv != 0) { 887 device_printf(sc->dev, "Cannot deassert 'pclk' reset\n"); 888 return (rv); 889 } 890 891 /* Set basic PCIe core mode (RC, lanes, gen1 or 2) */ 892 val = STRAP_CONF_GEN_2 << 16 | 893 (sc->link_is_gen2 ? STRAP_CONF_GEN_2: 0); 894 val |= STRAP_CONF_MODE_RC << 16 | STRAP_CONF_MODE_RC; 895 val |= STRAP_CONF_LANES(~0) << 16 | STRAP_CONF_LANES(sc->num_lanes); 896 val |= STRAP_CONF_ARI_EN << 16 | STRAP_CONF_ARI_EN; 897 val |= STRAP_CONF_CONF_EN << 16 | STRAP_CONF_CONF_EN; 898 APB_WR4(sc, PCIE_CLIENT_BASIC_STRAP_CONF, val); 899 900 for (i = 0; i < MAX_LANES; i++) { 901 rv = phy_enable(sc->phys[i]); 902 if (rv != 0) { 903 device_printf(sc->dev, "Cannot enable phy %d\n", i); 904 return (rv); 905 } 906 } 907 908 /* Deassert rest of resets - order is important ! */ 909 rv = hwreset_deassert(sc->hwreset_mgmt_sticky); 910 if (rv != 0) { 911 device_printf(sc->dev, "Cannot deassert 'mgmt_sticky' reset\n"); 912 return (rv); 913 } 914 rv = hwreset_deassert(sc->hwreset_core); 915 if (rv != 0) { 916 device_printf(sc->dev, "Cannot deassert 'core' reset\n"); 917 return (rv); 918 } 919 rv = hwreset_deassert(sc->hwreset_mgmt); 920 if (rv != 0) { 921 device_printf(sc->dev, "Cannot deassert 'mgmt' reset\n"); 922 return (rv); 923 } 924 rv = hwreset_deassert(sc->hwreset_pipe); 925 if (rv != 0) { 926 device_printf(sc->dev, "Cannot deassert 'pipe' reset\n"); 927 return (rv); 928 } 929 return (0); 930 } 931 932 static int 933 rk_pcie_setup_hw(struct rk_pcie_softc *sc) 934 { 935 uint32_t val; 936 int i, rv; 937 938 /* Assert PERST# if defined */ 939 if (sc->gpio_ep != NULL) { 940 rv = gpio_pin_set_active(sc->gpio_ep, 0); 941 if (rv != 0) { 942 device_printf(sc->dev, 943 "Cannot clear 'gpio-ep' gpio\n"); 944 return (rv); 945 } 946 } 947 948 rv = rk_pcie_enable_resources(sc); 949 if (rv != 0) 950 return(rv); 951 952 /* Fix wrong default value for transmited FTS for L0s exit */ 953 val = APB_RD4(sc, PCIE_CORE_CTRL1); 954 val |= 0xFFFF << 8; 955 APB_WR4(sc, PCIE_CORE_CTRL1, val); 956 957 /* Setup PCIE Link Status & Control register */ 958 val = APB_RD4(sc, PCIE_RC_CONFIG_LCS); 959 val |= PCIEM_LINK_CTL_COMMON_CLOCK; 960 APB_WR4(sc, PCIE_RC_CONFIG_LCS, val); 961 val = APB_RD4(sc, PCIE_RC_CONFIG_LCS); 962 val |= PCIEM_LINK_CTL_RCB; 963 APB_WR4(sc, PCIE_RC_CONFIG_LCS, val); 964 965 /* Enable training for GEN1 */ 966 APB_WR4(sc, PCIE_CLIENT_BASIC_STRAP_CONF, 967 STRAP_CONF_LINK_TRAIN_EN << 16 | STRAP_CONF_LINK_TRAIN_EN); 968 969 /* Deassert PERST# if defined */ 970 if (sc->gpio_ep != NULL) { 971 rv = gpio_pin_set_active(sc->gpio_ep, 1); 972 if (rv != 0) { 973 device_printf(sc->dev, "Cannot set 'gpio-ep' gpio\n"); 974 return (rv); 975 } 976 } 977 978 /* Wait for link */ 979 for (i = 500; i > 0; i--) { 980 val = APB_RD4(sc, PCIE_CLIENT_BASIC_STATUS1); 981 if (STATUS1_LINK_ST_GET(val) == STATUS1_LINK_ST_UP) 982 break; 983 DELAY(1000); 984 } 985 if (i <= 0) { 986 device_printf(sc->dev, 987 "Gen1 link training timeouted: 0x%08X.\n", val); 988 return (0); 989 } 990 991 if (sc->link_is_gen2) { 992 val = APB_RD4(sc, PCIE_RC_CONFIG_LCS); 993 val |= PCIEM_LINK_CTL_RETRAIN_LINK; 994 APB_WR4(sc, PCIE_RC_CONFIG_LCS, val); 995 996 /* Wait for link */ 997 for (i = 500; i > 0; i--) { 998 val = APB_RD4(sc, PCIE_CLIENT_BASIC_STATUS1); 999 if (STATUS1_LINK_ST_GET(val) == 1000 STATUS1_LINK_ST_UP) 1001 break; 1002 DELAY(1000); 1003 } 1004 if (i <= 0) 1005 device_printf(sc->dev, "Gen2 link training " 1006 "timeouted: 0x%08X.\n", val); 1007 } 1008 1009 val = APB_RD4(sc, PCIE_CORE_CTRL0); 1010 val = CORE_CTRL_LANES_GET(val); 1011 if (bootverbose) 1012 device_printf(sc->dev, "Link width: %d\n", 1 << val); 1013 1014 return (0); 1015 } 1016 1017 static int 1018 rk_pcie_setup_sw(struct rk_pcie_softc *sc) 1019 { 1020 uint32_t val; 1021 int i, region; 1022 1023 pcib_bridge_init(sc->dev); 1024 1025 /* Setup config registers */ 1026 APB_WR4(sc, PCIE_CORE_CONFIG_VENDOR, 0x1D87); /* Rockchip vendor ID*/ 1027 PRIV_CFG_WR1(sc, PCIR_CLASS, PCIC_BRIDGE); 1028 PRIV_CFG_WR1(sc, PCIR_SUBCLASS, PCIS_BRIDGE_PCI); 1029 PRIV_CFG_WR1(sc, PCIR_PRIBUS_1, sc->root_bus); 1030 PRIV_CFG_WR1(sc, PCIR_SECBUS_1, sc->sub_bus); 1031 PRIV_CFG_WR1(sc, PCIR_SUBBUS_1, sc->bus_end); 1032 PRIV_CFG_WR2(sc, PCIR_COMMAND, PCIM_CMD_MEMEN | 1033 PCIM_CMD_BUSMASTEREN | PCIM_CMD_SERRESPEN); 1034 1035 /* Don't advertise L1 power substate */ 1036 val = APB_RD4(sc, PCIE_RC_CONFIG_THP_CAP); 1037 val &= ~PCIE_RC_CONFIG_THP_CAP_NEXT_MASK; 1038 APB_WR4(sc, PCIE_RC_CONFIG_THP_CAP, val); 1039 1040 /* Don't advertise L0s */ 1041 if (sc->no_l0s) { 1042 val = APB_RD4(sc, PCIE_RC_CONFIG_LINK_CAP); 1043 val &= ~PCIE_RC_CONFIG_THP_CAP_NEXT_MASK; 1044 APB_WR4(sc, PCIE_RC_CONFIG_LINK_CAP_L0S, val); 1045 } 1046 1047 /*Adjust maximum payload size*/ 1048 val = APB_RD4(sc, PCIE_RC_CONFIG_DCSR); 1049 val &= ~PCIE_RC_CONFIG_DCSR_MPS_MASK; 1050 val |= PCIE_RC_CONFIG_DCSR_MPS_128; 1051 APB_WR4(sc, PCIE_RC_CONFIG_DCSR, val); 1052 1053 /* 1054 * Prepare IB ATU 1055 * map whole address range in 1:1 mappings 1056 */ 1057 rk_pcie_map_in_atu(sc, 2, 64 - 1, 0); 1058 1059 /* Prepare OB ATU */ 1060 /* - region 0 (32 MB) is used for config access */ 1061 region = 0; 1062 rk_pcie_map_out_atu(sc, region++, ATU_TYPE_CFG0, 25 - 1, 0); 1063 1064 /* - then map memory (by using 1MB regions */ 1065 for (i = 0; i < sc->mem_range.size / ATU_OB_REGION_SIZE; i++) { 1066 rk_pcie_map_out_atu(sc, region++, ATU_TYPE_MEM, 1067 ATU_OB_REGION_SHIFT - 1, 1068 sc->mem_range.pci + ATU_OB_REGION_SIZE * i); 1069 } 1070 1071 /* - IO space is next, one region typically*/ 1072 for (i = 0; i < sc->io_range.size / ATU_OB_REGION_SIZE; i++) { 1073 rk_pcie_map_out_atu(sc, region++, ATU_TYPE_IO, 1074 ATU_OB_REGION_SHIFT - 1, 1075 sc->io_range.pci + ATU_OB_REGION_SIZE * i); 1076 } 1077 APB_WR4(sc, PCIE_CORE_RC_BAR_CONF, 0); 1078 return (0); 1079 } 1080 1081 static int 1082 rk_pcie_sys_irq(void *arg) 1083 { 1084 struct rk_pcie_softc *sc; 1085 uint32_t irq; 1086 1087 sc = (struct rk_pcie_softc *)arg; 1088 irq = APB_RD4(sc, PCIE_CLIENT_INT_STATUS); 1089 if (irq & PCIE_CLIENT_INT_LOCAL) { 1090 irq = APB_RD4(sc, PCIE_CORE_INT_STATUS); 1091 APB_WR4(sc, PCIE_CORE_INT_STATUS, irq); 1092 APB_WR4(sc, PCIE_CLIENT_INT_STATUS, PCIE_CLIENT_INT_LOCAL); 1093 1094 device_printf(sc->dev, "'sys' interrupt received: 0x%04X\n", 1095 irq); 1096 } 1097 1098 return (FILTER_HANDLED); 1099 } 1100 1101 static int 1102 rk_pcie_client_irq(void *arg) 1103 { 1104 struct rk_pcie_softc *sc; 1105 uint32_t irq; 1106 1107 sc = (struct rk_pcie_softc *)arg; 1108 irq = APB_RD4(sc, PCIE_CLIENT_INT_STATUS); 1109 /* Clear causes handled by other interrups */ 1110 irq &= ~PCIE_CLIENT_INT_LOCAL; 1111 irq &= ~PCIE_CLIENT_INT_LEGACY; 1112 APB_WR4(sc, PCIE_CLIENT_INT_STATUS, irq); 1113 1114 device_printf(sc->dev, "'client' interrupt received: 0x%04X\n", irq); 1115 1116 return (FILTER_HANDLED); 1117 } 1118 1119 static int 1120 rk_pcie_legacy_irq(void *arg) 1121 { 1122 struct rk_pcie_softc *sc; 1123 uint32_t irq; 1124 1125 sc = (struct rk_pcie_softc *)arg; 1126 irq = APB_RD4(sc, PCIE_CLIENT_INT_STATUS); 1127 irq &= PCIE_CLIENT_INT_LEGACY; 1128 APB_WR4(sc, PCIE_CLIENT_INT_STATUS, irq); 1129 1130 /* all legacy interrupt are shared, do nothing */ 1131 return (FILTER_STRAY); 1132 } 1133 1134 static bus_dma_tag_t 1135 rk_pcie_get_dma_tag(device_t dev, device_t child) 1136 { 1137 struct rk_pcie_softc *sc; 1138 1139 sc = device_get_softc(dev); 1140 return (sc->dmat); 1141 } 1142 1143 static int 1144 rk_pcie_probe(device_t dev) 1145 { 1146 1147 if (!ofw_bus_status_okay(dev)) 1148 return (ENXIO); 1149 1150 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 1151 return (ENXIO); 1152 1153 device_set_desc(dev, "Rockchip PCIe controller"); 1154 return (BUS_PROBE_DEFAULT); 1155 } 1156 1157 static int 1158 rk_pcie_attach(device_t dev) 1159 { struct rk_pcie_softc *sc; 1160 uint32_t val; 1161 int rv, rid, max_speed; 1162 1163 sc = device_get_softc(dev); 1164 sc->dev = dev; 1165 sc->node = ofw_bus_get_node(dev); 1166 1167 mtx_init(&sc->mtx, "rk_pcie_mtx", NULL, MTX_DEF); 1168 1169 /* XXX Should not be this configurable ? */ 1170 sc->bus_start = 0; 1171 sc->bus_end = 0x1F; 1172 sc->root_bus = sc->bus_start; 1173 sc->sub_bus = 1; 1174 1175 /* Read FDT properties */ 1176 rv = rk_pcie_parse_fdt_resources(sc); 1177 if (rv != 0) 1178 return (rv); 1179 1180 sc->coherent = OF_hasprop(sc->node, "dma-coherent"); 1181 sc->no_l0s = OF_hasprop(sc->node, "aspm-no-l0s"); 1182 rv = OF_getencprop(sc->node, "num-lanes", &sc->num_lanes, 1183 sizeof(sc->num_lanes)); 1184 if (rv != sizeof(sc->num_lanes)) 1185 sc->num_lanes = 1; 1186 if (sc->num_lanes != 1 && sc->num_lanes != 2 && sc->num_lanes != 4) { 1187 device_printf(dev, 1188 "invalid number of lanes: %d\n",sc->num_lanes); 1189 sc->num_lanes = 0; 1190 rv = ENXIO; 1191 goto out; 1192 } 1193 1194 rv = OF_getencprop(sc->node, "max-link-speed", &max_speed, 1195 sizeof(max_speed)); 1196 if (rv != sizeof(max_speed) || max_speed != 1) 1197 sc->link_is_gen2 = true; 1198 else 1199 sc->link_is_gen2 = false; 1200 1201 rv = ofw_bus_find_string_index(sc->node, "reg-names", "axi-base", &rid); 1202 if (rv != 0) { 1203 device_printf(dev, "Cannot get 'axi-base' memory\n"); 1204 rv = ENXIO; 1205 goto out; 1206 } 1207 sc->axi_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1208 RF_ACTIVE); 1209 if (sc->axi_mem_res == NULL) { 1210 device_printf(dev, "Cannot allocate 'axi-base' (rid: %d)\n", 1211 rid); 1212 rv = ENXIO; 1213 goto out; 1214 } 1215 rv = ofw_bus_find_string_index(sc->node, "reg-names", "apb-base", &rid); 1216 if (rv != 0) { 1217 device_printf(dev, "Cannot get 'apb-base' memory\n"); 1218 rv = ENXIO; 1219 goto out; 1220 } 1221 sc->apb_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1222 RF_ACTIVE); 1223 if (sc->apb_mem_res == NULL) { 1224 device_printf(dev, "Cannot allocate 'apb-base' (rid: %d)\n", 1225 rid); 1226 rv = ENXIO; 1227 goto out; 1228 } 1229 1230 rv = ofw_bus_find_string_index(sc->node, "interrupt-names", 1231 "client", &rid); 1232 if (rv != 0) { 1233 device_printf(dev, "Cannot get 'client' IRQ\n"); 1234 rv = ENXIO; 1235 goto out; 1236 } 1237 sc->client_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1238 RF_ACTIVE | RF_SHAREABLE); 1239 if (sc->client_irq_res == NULL) { 1240 device_printf(dev, "Cannot allocate 'client' IRQ resource\n"); 1241 rv = ENXIO; 1242 goto out; 1243 } 1244 1245 rv = ofw_bus_find_string_index(sc->node, "interrupt-names", 1246 "legacy", &rid); 1247 if (rv != 0) { 1248 device_printf(dev, "Cannot get 'legacy' IRQ\n"); 1249 rv = ENXIO; 1250 goto out; 1251 } 1252 sc->legacy_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1253 RF_ACTIVE | RF_SHAREABLE); 1254 if (sc->legacy_irq_res == NULL) { 1255 device_printf(dev, "Cannot allocate 'legacy' IRQ resource\n"); 1256 rv = ENXIO; 1257 goto out; 1258 } 1259 1260 rv = ofw_bus_find_string_index(sc->node, "interrupt-names", 1261 "sys", &rid); 1262 if (rv != 0) { 1263 device_printf(dev, "Cannot get 'sys' IRQ\n"); 1264 rv = ENXIO; 1265 goto out; 1266 } 1267 sc->sys_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1268 RF_ACTIVE | RF_SHAREABLE); 1269 if (sc->sys_irq_res == NULL) { 1270 device_printf(dev, "Cannot allocate 'sys' IRQ resource\n"); 1271 rv = ENXIO; 1272 goto out; 1273 } 1274 1275 if (bootverbose) 1276 device_printf(dev, "Bus is%s cache-coherent\n", 1277 sc->coherent ? "" : " not"); 1278 rv = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1279 1, 0, /* alignment, bounds */ 1280 BUS_SPACE_MAXADDR, /* lowaddr */ 1281 BUS_SPACE_MAXADDR, /* highaddr */ 1282 NULL, NULL, /* filter, filterarg */ 1283 BUS_SPACE_MAXSIZE, /* maxsize */ 1284 BUS_SPACE_UNRESTRICTED, /* nsegments */ 1285 BUS_SPACE_MAXSIZE, /* maxsegsize */ 1286 sc->coherent ? BUS_DMA_COHERENT : 0, /* flags */ 1287 NULL, NULL, /* lockfunc, lockarg */ 1288 &sc->dmat); 1289 if (rv != 0) 1290 goto out; 1291 1292 rv = ofw_pci_init(dev); 1293 if (rv != 0) 1294 goto out; 1295 1296 rv = rk_pcie_decode_ranges(sc, sc->ofw_pci.sc_range, 1297 sc->ofw_pci.sc_nrange); 1298 if (rv != 0) 1299 goto out; 1300 rv = rk_pcie_setup_hw(sc); 1301 if (rv != 0) 1302 goto out; 1303 1304 rv = rk_pcie_setup_sw(sc); 1305 if (rv != 0) 1306 goto out; 1307 1308 rv = bus_setup_intr(dev, sc->client_irq_res, INTR_TYPE_BIO | INTR_MPSAFE, 1309 rk_pcie_client_irq, NULL, sc, &sc->client_irq_cookie); 1310 if (rv != 0) { 1311 device_printf(dev, "cannot setup client interrupt handler\n"); 1312 rv = ENXIO; 1313 goto out; 1314 } 1315 1316 rv = bus_setup_intr(dev, sc->legacy_irq_res, INTR_TYPE_BIO | INTR_MPSAFE, 1317 rk_pcie_legacy_irq, NULL, sc, &sc->legacy_irq_cookie); 1318 if (rv != 0) { 1319 device_printf(dev, "cannot setup client interrupt handler\n"); 1320 rv = ENXIO; 1321 goto out; 1322 } 1323 1324 rv = bus_setup_intr(dev, sc->sys_irq_res, INTR_TYPE_BIO | INTR_MPSAFE, 1325 rk_pcie_sys_irq, NULL, sc, &sc->sys_irq_cookie); 1326 if (rv != 0) { 1327 device_printf(dev, "cannot setup client interrupt handler\n"); 1328 rv = ENXIO; 1329 goto out; 1330 } 1331 1332 /* Enable interrupts */ 1333 val = 1334 PCIE_CLIENT_INT_CORR_ERR | PCIE_CLIENT_INT_NFATAL_ERR | 1335 PCIE_CLIENT_INT_FATAL_ERR | PCIE_CLIENT_INT_DPA | 1336 PCIE_CLIENT_INT_HOT_RST | PCIE_CLIENT_INT_MSG | 1337 PCIE_CLIENT_INT_LEGACY_DONE | PCIE_CLIENT_INT_INTA | 1338 PCIE_CLIENT_INT_INTB | PCIE_CLIENT_INT_INTC | 1339 PCIE_CLIENT_INT_INTD | PCIE_CLIENT_INT_PHY; 1340 1341 APB_WR4(sc, PCIE_CLIENT_INT_MASK, (val << 16) & ~val); 1342 1343 val = 1344 PCIE_CORE_INT_PRFPE | PCIE_CORE_INT_CRFPE | 1345 PCIE_CORE_INT_RRPE | PCIE_CORE_INT_CRFO | 1346 PCIE_CORE_INT_RT | PCIE_CORE_INT_RTR | 1347 PCIE_CORE_INT_PE | PCIE_CORE_INT_MTR | 1348 PCIE_CORE_INT_UCR | PCIE_CORE_INT_FCE | 1349 PCIE_CORE_INT_CT | PCIE_CORE_INT_UTC | 1350 PCIE_CORE_INT_MMVC; 1351 APB_WR4(sc, PCIE_CORE_INT_MASK, ~(val)); 1352 1353 val = APB_RD4(sc, PCIE_RC_CONFIG_LCS); 1354 val |= PCIEM_LINK_CTL_LBMIE | PCIEM_LINK_CTL_LABIE; 1355 APB_WR4(sc, PCIE_RC_CONFIG_LCS, val); 1356 1357 DELAY(250000); 1358 device_add_child(dev, "pci", -1); 1359 return (bus_generic_attach(dev)); 1360 out: 1361 /* XXX Cleanup */ 1362 return (rv); 1363 } 1364 1365 static device_method_t rk_pcie_methods[] = { 1366 /* Device interface */ 1367 DEVMETHOD(device_probe, rk_pcie_probe), 1368 DEVMETHOD(device_attach, rk_pcie_attach), 1369 1370 /* Bus interface */ 1371 DEVMETHOD(bus_get_dma_tag, rk_pcie_get_dma_tag), 1372 1373 /* pcib interface */ 1374 DEVMETHOD(pcib_read_config, rk_pcie_read_config), 1375 DEVMETHOD(pcib_write_config, rk_pcie_write_config), 1376 DEVMETHOD(pcib_route_interrupt, rk_pcie_route_interrupt), 1377 #ifdef RK_PCIE_ENABLE_MSI 1378 DEVMETHOD(pcib_alloc_msi, rk_pcie_alloc_msi), 1379 DEVMETHOD(pcib_release_msi, rk_pcie_release_msi), 1380 #endif 1381 #ifdef RK_PCIE_ENABLE_MSIX 1382 DEVMETHOD(pcib_alloc_msix, rk_pcie_alloc_msix), 1383 DEVMETHOD(pcib_release_msix, rk_pcie_release_msix), 1384 #endif 1385 DEVMETHOD(pcib_map_msi, rk_pcie_map_msi), 1386 DEVMETHOD(pcib_get_id, rk_pcie_get_id), 1387 1388 /* OFW bus interface */ 1389 DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat), 1390 DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model), 1391 DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name), 1392 DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node), 1393 DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type), 1394 1395 DEVMETHOD_END 1396 }; 1397 1398 DEFINE_CLASS_1(pcib, rk_pcie_driver, rk_pcie_methods, 1399 sizeof(struct rk_pcie_softc), ofw_pci_driver); 1400 static devclass_t rk_pcie_devclass; 1401 DRIVER_MODULE( rk_pcie, simplebus, rk_pcie_driver, rk_pcie_devclass, 1402 NULL, NULL); 1403