1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2019 Oleksandr Tymoshenko <gonzo@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 20 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 21 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 22 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 23 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/param.h> 29 #include <sys/systm.h> 30 #include <sys/bus.h> 31 #include <sys/kernel.h> 32 #include <sys/lock.h> 33 #include <sys/module.h> 34 #include <sys/mutex.h> 35 #include <sys/rman.h> 36 #include <sys/resource.h> 37 #include <machine/bus.h> 38 39 #include <dev/ofw/ofw_bus.h> 40 #include <dev/ofw/ofw_bus_subr.h> 41 42 #include <dev/clk/clk.h> 43 #include <dev/hwreset/hwreset.h> 44 #include <dev/syscon/syscon.h> 45 46 #include "syscon_if.h" 47 48 #include "opt_snd.h" 49 #include <dev/sound/pcm/sound.h> 50 #include <dev/sound/fdt/audio_dai.h> 51 #include "audio_dai_if.h" 52 53 #define AUDIO_BUFFER_SIZE 48000 * 4 54 55 #define I2S_TXCR 0x0000 56 #define I2S_CSR_2 (0 << 15) 57 #define I2S_CSR_4 (1 << 15) 58 #define I2S_CSR_6 (2 << 15) 59 #define I2S_CSR_8 (3 << 15) 60 #define I2S_TXCR_IBM_NORMAL (0 << 9) 61 #define I2S_TXCR_IBM_LJ (1 << 9) 62 #define I2S_TXCR_IBM_RJ (2 << 9) 63 #define I2S_TXCR_PBM_NODELAY (0 << 7) 64 #define I2S_TXCR_PBM_1 (1 << 7) 65 #define I2S_TXCR_PBM_2 (2 << 7) 66 #define I2S_TXCR_PBM_3 (3 << 7) 67 #define I2S_TXCR_TFS_I2S (0 << 5) 68 #define I2S_TXCR_TFS_PCM (1 << 5) 69 #define I2S_TXCR_VDW_16 (0xf << 0) 70 #define I2S_RXCR 0x0004 71 #define I2S_RXCR_IBM_NORMAL (0 << 9) 72 #define I2S_RXCR_IBM_LJ (1 << 9) 73 #define I2S_RXCR_IBM_RJ (2 << 9) 74 #define I2S_RXCR_PBM_NODELAY (0 << 7) 75 #define I2S_RXCR_PBM_1 (1 << 7) 76 #define I2S_RXCR_PBM_2 (2 << 7) 77 #define I2S_RXCR_PBM_3 (3 << 7) 78 #define I2S_RXCR_TFS_I2S (0 << 5) 79 #define I2S_RXCR_TFS_PCM (1 << 5) 80 #define I2S_RXCR_VDW_16 (0xf << 0) 81 #define I2S_CKR 0x0008 82 #define I2S_CKR_MSS_MASK (1 << 27) 83 #define I2S_CKR_MSS_MASTER (0 << 27) 84 #define I2S_CKR_MSS_SLAVE (1 << 27) 85 #define I2S_CKR_CKP (1 << 26) 86 #define I2S_CKR_MDIV(n) (((n) - 1) << 16) 87 #define I2S_CKR_MDIV_MASK (0xff << 16) 88 #define I2S_CKR_RSD(n) (((n) - 1) << 8) 89 #define I2S_CKR_RSD_MASK (0xff << 8) 90 #define I2S_CKR_TSD(n) (((n) - 1) << 0) 91 #define I2S_CKR_TSD_MASK (0xff << 0) 92 #define I2S_TXFIFOLR 0x000c 93 #define TXFIFO0LR_MASK 0x3f 94 #define I2S_DMACR 0x0010 95 #define I2S_DMACR_RDE_ENABLE (1 << 24) 96 #define I2S_DMACR_RDL(n) ((n) << 16) 97 #define I2S_DMACR_TDE_ENABLE (1 << 8) 98 #define I2S_DMACR_TDL(n) ((n) << 0) 99 #define I2S_INTCR 0x0014 100 #define I2S_INTCR_RFT(n) (((n) - 1) << 20) 101 #define I2S_INTCR_TFT(n) (((n) - 1) << 4) 102 #define I2S_INTCR_RXFIE (1 << 16) 103 #define I2S_INTCR_TXUIC (1 << 2) 104 #define I2S_INTCR_TXEIE (1 << 0) 105 #define I2S_INTSR 0x0018 106 #define I2S_INTSR_RXFI (1 << 16) 107 #define I2S_INTSR_TXUI (1 << 1) 108 #define I2S_INTSR_TXEI (1 << 0) 109 #define I2S_XFER 0x001c 110 #define I2S_XFER_RXS_START (1 << 1) 111 #define I2S_XFER_TXS_START (1 << 0) 112 #define I2S_CLR 0x0020 113 #define I2S_CLR_RXC (1 << 1) 114 #define I2S_CLR_TXC (1 << 0) 115 #define I2S_TXDR 0x0024 116 #define I2S_RXDR 0x0028 117 #define I2S_RXFIFOLR 0x002c 118 #define RXFIFO0LR_MASK 0x3f 119 120 /* syscon */ 121 #define GRF_SOC_CON8 0xe220 122 #define I2S_IO_DIRECTION_MASK 7 123 #define I2S_IO_DIRECTION_SHIFT 11 124 #define I2S_IO_8CH_OUT_2CH_IN 0 125 #define I2S_IO_6CH_OUT_4CH_IN 4 126 #define I2S_IO_4CH_OUT_6CH_IN 6 127 #define I2S_IO_2CH_OUT_8CH_IN 7 128 129 #define DIV_ROUND_CLOSEST(n,d) (((n) + (d) / 2) / (d)) 130 131 #define RK_I2S_SAMPLING_RATE 48000 132 #define FIFO_SIZE 32 133 134 static struct ofw_compat_data compat_data[] = { 135 { "rockchip,rk3066-i2s", 1 }, 136 { "rockchip,rk3399-i2s", 1 }, 137 { NULL, 0 } 138 }; 139 140 static struct resource_spec rk_i2s_spec[] = { 141 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 142 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 143 { -1, 0 } 144 }; 145 146 struct rk_i2s_softc { 147 device_t dev; 148 struct resource *res[2]; 149 struct mtx mtx; 150 clk_t clk; 151 clk_t hclk; 152 void * intrhand; 153 struct syscon *grf; 154 /* pointers to playback/capture buffers */ 155 uint32_t play_ptr; 156 uint32_t rec_ptr; 157 }; 158 159 #define RK_I2S_LOCK(sc) mtx_lock(&(sc)->mtx) 160 #define RK_I2S_UNLOCK(sc) mtx_unlock(&(sc)->mtx) 161 #define RK_I2S_READ_4(sc, reg) bus_read_4((sc)->res[0], (reg)) 162 #define RK_I2S_WRITE_4(sc, reg, val) bus_write_4((sc)->res[0], (reg), (val)) 163 164 static int rk_i2s_probe(device_t dev); 165 static int rk_i2s_attach(device_t dev); 166 static int rk_i2s_detach(device_t dev); 167 168 static uint32_t sc_fmt[] = { 169 SND_FORMAT(AFMT_S16_LE, 2, 0), 170 0 171 }; 172 static struct pcmchan_caps rk_i2s_caps = {RK_I2S_SAMPLING_RATE, RK_I2S_SAMPLING_RATE, sc_fmt, 0}; 173 174 175 static int 176 rk_i2s_init(struct rk_i2s_softc *sc) 177 { 178 uint32_t val; 179 int error; 180 181 clk_set_freq(sc->clk, RK_I2S_SAMPLING_RATE * 256, 182 CLK_SET_ROUND_DOWN); 183 error = clk_enable(sc->clk); 184 if (error != 0) { 185 device_printf(sc->dev, "cannot enable i2s_clk clock\n"); 186 return (ENXIO); 187 } 188 189 val = I2S_INTCR_TFT(FIFO_SIZE/2); 190 val |= I2S_INTCR_RFT(FIFO_SIZE/2); 191 RK_I2S_WRITE_4(sc, I2S_INTCR, val); 192 193 if (sc->grf && ofw_bus_is_compatible(sc->dev, "rockchip,rk3399-i2s")) { 194 val = (I2S_IO_2CH_OUT_8CH_IN << I2S_IO_DIRECTION_SHIFT); 195 val |= (I2S_IO_DIRECTION_MASK << I2S_IO_DIRECTION_SHIFT) << 16; 196 SYSCON_WRITE_4(sc->grf, GRF_SOC_CON8, val); 197 198 #if 0 199 // HACK: enable IO domain 200 val = (1 << 1); 201 val |= (1 << 1) << 16; 202 SYSCON_WRITE_4(sc->grf, 0xe640, val); 203 #endif 204 } 205 206 RK_I2S_WRITE_4(sc, I2S_XFER, 0); 207 208 return (0); 209 } 210 211 static int 212 rk_i2s_probe(device_t dev) 213 { 214 if (!ofw_bus_status_okay(dev)) 215 return (ENXIO); 216 217 if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data) 218 return (ENXIO); 219 220 device_set_desc(dev, "Rockchip I2S"); 221 return (BUS_PROBE_DEFAULT); 222 } 223 224 static int 225 rk_i2s_attach(device_t dev) 226 { 227 struct rk_i2s_softc *sc; 228 int error; 229 phandle_t node; 230 231 sc = device_get_softc(dev); 232 sc->dev = dev; 233 234 mtx_init(&sc->mtx, device_get_nameunit(dev), NULL, MTX_DEF); 235 236 if (bus_alloc_resources(dev, rk_i2s_spec, sc->res) != 0) { 237 device_printf(dev, "cannot allocate resources for device\n"); 238 error = ENXIO; 239 goto fail; 240 } 241 242 error = clk_get_by_ofw_name(dev, 0, "i2s_hclk", &sc->hclk); 243 if (error != 0) { 244 device_printf(dev, "cannot get i2s_hclk clock\n"); 245 goto fail; 246 } 247 248 error = clk_get_by_ofw_name(dev, 0, "i2s_clk", &sc->clk); 249 if (error != 0) { 250 device_printf(dev, "cannot get i2s_clk clock\n"); 251 goto fail; 252 } 253 254 /* Activate the module clock. */ 255 error = clk_enable(sc->hclk); 256 if (error != 0) { 257 device_printf(dev, "cannot enable i2s_hclk clock\n"); 258 goto fail; 259 } 260 261 node = ofw_bus_get_node(dev); 262 if (OF_hasprop(node, "rockchip,grf") && 263 syscon_get_by_ofw_property(dev, node, 264 "rockchip,grf", &sc->grf) != 0) { 265 device_printf(dev, "cannot get grf driver handle\n"); 266 return (ENXIO); 267 } 268 269 rk_i2s_init(sc); 270 271 OF_device_register_xref(OF_xref_from_node(node), dev); 272 273 return (0); 274 275 fail: 276 rk_i2s_detach(dev); 277 return (error); 278 } 279 280 static int 281 rk_i2s_detach(device_t dev) 282 { 283 struct rk_i2s_softc *i2s; 284 285 i2s = device_get_softc(dev); 286 287 if (i2s->hclk != NULL) 288 clk_release(i2s->hclk); 289 if (i2s->clk) 290 clk_release(i2s->clk); 291 292 if (i2s->intrhand != NULL) 293 bus_teardown_intr(i2s->dev, i2s->res[1], i2s->intrhand); 294 295 bus_release_resources(dev, rk_i2s_spec, i2s->res); 296 mtx_destroy(&i2s->mtx); 297 298 return (0); 299 } 300 301 static int 302 rk_i2s_dai_init(device_t dev, uint32_t format) 303 { 304 uint32_t val, txcr, rxcr; 305 struct rk_i2s_softc *sc; 306 int fmt, pol, clk; 307 308 sc = device_get_softc(dev); 309 310 fmt = AUDIO_DAI_FORMAT_FORMAT(format); 311 pol = AUDIO_DAI_FORMAT_POLARITY(format); 312 clk = AUDIO_DAI_FORMAT_CLOCK(format); 313 314 /* Set format */ 315 val = RK_I2S_READ_4(sc, I2S_CKR); 316 317 val &= ~(I2S_CKR_MSS_MASK); 318 switch (clk) { 319 case AUDIO_DAI_CLOCK_CBM_CFM: 320 val |= I2S_CKR_MSS_MASTER; 321 break; 322 case AUDIO_DAI_CLOCK_CBS_CFS: 323 val |= I2S_CKR_MSS_SLAVE; 324 break; 325 default: 326 return (EINVAL); 327 } 328 329 switch (pol) { 330 case AUDIO_DAI_POLARITY_IB_NF: 331 val |= I2S_CKR_CKP; 332 break; 333 case AUDIO_DAI_POLARITY_NB_NF: 334 val &= ~I2S_CKR_CKP; 335 break; 336 default: 337 return (EINVAL); 338 } 339 340 RK_I2S_WRITE_4(sc, I2S_CKR, val); 341 342 txcr = I2S_TXCR_VDW_16 | I2S_CSR_2; 343 rxcr = I2S_RXCR_VDW_16 | I2S_CSR_2; 344 345 switch (fmt) { 346 case AUDIO_DAI_FORMAT_I2S: 347 txcr |= I2S_TXCR_IBM_NORMAL; 348 rxcr |= I2S_RXCR_IBM_NORMAL; 349 break; 350 case AUDIO_DAI_FORMAT_LJ: 351 txcr |= I2S_TXCR_IBM_LJ; 352 rxcr |= I2S_RXCR_IBM_LJ; 353 break; 354 case AUDIO_DAI_FORMAT_RJ: 355 txcr |= I2S_TXCR_IBM_RJ; 356 rxcr |= I2S_RXCR_IBM_RJ; 357 break; 358 case AUDIO_DAI_FORMAT_DSPA: 359 txcr |= I2S_TXCR_TFS_PCM; 360 rxcr |= I2S_RXCR_TFS_PCM; 361 txcr |= I2S_TXCR_PBM_1; 362 rxcr |= I2S_RXCR_PBM_1; 363 break; 364 case AUDIO_DAI_FORMAT_DSPB: 365 txcr |= I2S_TXCR_TFS_PCM; 366 rxcr |= I2S_RXCR_TFS_PCM; 367 txcr |= I2S_TXCR_PBM_2; 368 rxcr |= I2S_RXCR_PBM_2; 369 break; 370 default: 371 return EINVAL; 372 } 373 374 RK_I2S_WRITE_4(sc, I2S_TXCR, txcr); 375 RK_I2S_WRITE_4(sc, I2S_RXCR, rxcr); 376 377 RK_I2S_WRITE_4(sc, I2S_XFER, 0); 378 379 return (0); 380 } 381 382 383 static int 384 rk_i2s_dai_intr(device_t dev, struct snd_dbuf *play_buf, struct snd_dbuf *rec_buf) 385 { 386 struct rk_i2s_softc *sc; 387 uint32_t status; 388 uint32_t level; 389 uint32_t val = 0x00; 390 int ret = 0; 391 392 sc = device_get_softc(dev); 393 394 RK_I2S_LOCK(sc); 395 status = RK_I2S_READ_4(sc, I2S_INTSR); 396 397 if (status & I2S_INTSR_TXEI) { 398 level = RK_I2S_READ_4(sc, I2S_TXFIFOLR) & TXFIFO0LR_MASK; 399 uint8_t *samples; 400 uint32_t count, size, readyptr, written; 401 count = sndbuf_getready(play_buf); 402 if (count > FIFO_SIZE - 1) 403 count = FIFO_SIZE - 1; 404 size = sndbuf_getsize(play_buf); 405 readyptr = sndbuf_getreadyptr(play_buf); 406 407 samples = (uint8_t*)sndbuf_getbuf(play_buf); 408 written = 0; 409 for (; level < count; level++) { 410 val = (samples[readyptr++ % size] << 0); 411 val |= (samples[readyptr++ % size] << 8); 412 val |= (samples[readyptr++ % size] << 16); 413 val |= (samples[readyptr++ % size] << 24); 414 written += 4; 415 RK_I2S_WRITE_4(sc, I2S_TXDR, val); 416 } 417 sc->play_ptr += written; 418 sc->play_ptr %= size; 419 ret |= AUDIO_DAI_PLAY_INTR; 420 } 421 422 if (status & I2S_INTSR_RXFI) { 423 level = RK_I2S_READ_4(sc, I2S_RXFIFOLR) & RXFIFO0LR_MASK; 424 uint8_t *samples; 425 uint32_t count, size, freeptr, recorded; 426 count = sndbuf_getfree(rec_buf); 427 size = sndbuf_getsize(rec_buf); 428 freeptr = sndbuf_getfreeptr(rec_buf); 429 samples = (uint8_t*)sndbuf_getbuf(rec_buf); 430 recorded = 0; 431 if (level > count / 4) 432 level = count / 4; 433 434 for (; level > 0; level--) { 435 val = RK_I2S_READ_4(sc, I2S_RXDR); 436 samples[freeptr++ % size] = val & 0xff; 437 samples[freeptr++ % size] = (val >> 8) & 0xff; 438 samples[freeptr++ % size] = (val >> 16) & 0xff; 439 samples[freeptr++ % size] = (val >> 24) & 0xff; 440 recorded += 4; 441 } 442 sc->rec_ptr += recorded; 443 sc->rec_ptr %= size; 444 ret |= AUDIO_DAI_REC_INTR; 445 } 446 447 RK_I2S_UNLOCK(sc); 448 449 return (ret); 450 } 451 452 static struct pcmchan_caps * 453 rk_i2s_dai_get_caps(device_t dev) 454 { 455 return (&rk_i2s_caps); 456 } 457 458 static int 459 rk_i2s_dai_trigger(device_t dev, int go, int pcm_dir) 460 { 461 struct rk_i2s_softc *sc = device_get_softc(dev); 462 uint32_t val; 463 uint32_t clear_bit; 464 465 if ((pcm_dir != PCMDIR_PLAY) && (pcm_dir != PCMDIR_REC)) 466 return (EINVAL); 467 468 switch (go) { 469 case PCMTRIG_START: 470 val = RK_I2S_READ_4(sc, I2S_INTCR); 471 if (pcm_dir == PCMDIR_PLAY) 472 val |= I2S_INTCR_TXEIE; 473 else if (pcm_dir == PCMDIR_REC) 474 val |= I2S_INTCR_RXFIE; 475 RK_I2S_WRITE_4(sc, I2S_INTCR, val); 476 477 val = I2S_XFER_TXS_START | I2S_XFER_RXS_START; 478 RK_I2S_WRITE_4(sc, I2S_XFER, val); 479 break; 480 481 case PCMTRIG_STOP: 482 case PCMTRIG_ABORT: 483 val = RK_I2S_READ_4(sc, I2S_INTCR); 484 if (pcm_dir == PCMDIR_PLAY) 485 val &= ~I2S_INTCR_TXEIE; 486 else if (pcm_dir == PCMDIR_REC) 487 val &= ~I2S_INTCR_RXFIE; 488 RK_I2S_WRITE_4(sc, I2S_INTCR, val); 489 490 /* 491 * If there is no other activity going on, stop transfers 492 */ 493 if ((val & (I2S_INTCR_TXEIE | I2S_INTCR_RXFIE)) == 0) { 494 RK_I2S_WRITE_4(sc, I2S_XFER, 0); 495 496 if (pcm_dir == PCMDIR_PLAY) 497 clear_bit = I2S_CLR_TXC; 498 else if (pcm_dir == PCMDIR_REC) 499 clear_bit = I2S_CLR_RXC; 500 else 501 return (EINVAL); 502 503 val = RK_I2S_READ_4(sc, I2S_CLR); 504 val |= clear_bit; 505 RK_I2S_WRITE_4(sc, I2S_CLR, val); 506 507 while ((RK_I2S_READ_4(sc, I2S_CLR) & clear_bit) != 0) 508 DELAY(1); 509 } 510 511 RK_I2S_LOCK(sc); 512 if (pcm_dir == PCMDIR_PLAY) 513 sc->play_ptr = 0; 514 else 515 sc->rec_ptr = 0; 516 RK_I2S_UNLOCK(sc); 517 break; 518 } 519 520 return (0); 521 } 522 523 static uint32_t 524 rk_i2s_dai_get_ptr(device_t dev, int pcm_dir) 525 { 526 struct rk_i2s_softc *sc; 527 uint32_t ptr; 528 529 sc = device_get_softc(dev); 530 531 RK_I2S_LOCK(sc); 532 if (pcm_dir == PCMDIR_PLAY) 533 ptr = sc->play_ptr; 534 else 535 ptr = sc->rec_ptr; 536 RK_I2S_UNLOCK(sc); 537 538 return ptr; 539 } 540 541 static int 542 rk_i2s_dai_setup_intr(device_t dev, driver_intr_t intr_handler, void *intr_arg) 543 { 544 struct rk_i2s_softc *sc = device_get_softc(dev); 545 546 if (bus_setup_intr(dev, sc->res[1], 547 INTR_TYPE_MISC | INTR_MPSAFE, NULL, intr_handler, intr_arg, 548 &sc->intrhand)) { 549 device_printf(dev, "cannot setup interrupt handler\n"); 550 return (ENXIO); 551 } 552 553 return (0); 554 } 555 556 static uint32_t 557 rk_i2s_dai_set_chanformat(device_t dev, uint32_t format) 558 { 559 560 return (0); 561 } 562 563 static int 564 rk_i2s_dai_set_sysclk(device_t dev, unsigned int rate, int dai_dir) 565 { 566 struct rk_i2s_softc *sc; 567 int error; 568 569 sc = device_get_softc(dev); 570 error = clk_disable(sc->clk); 571 if (error != 0) { 572 device_printf(sc->dev, "could not disable i2s_clk clock\n"); 573 return (error); 574 } 575 576 error = clk_set_freq(sc->clk, rate, CLK_SET_ROUND_DOWN); 577 if (error != 0) 578 device_printf(sc->dev, "could not set i2s_clk freq\n"); 579 580 error = clk_enable(sc->clk); 581 if (error != 0) { 582 device_printf(sc->dev, "could not enable i2s_clk clock\n"); 583 return (error); 584 } 585 586 return (0); 587 } 588 589 static uint32_t 590 rk_i2s_dai_set_chanspeed(device_t dev, uint32_t speed) 591 { 592 struct rk_i2s_softc *sc; 593 int error; 594 uint32_t val; 595 uint32_t bus_clock_div, lr_clock_div; 596 uint64_t bus_clk_freq; 597 uint64_t clk_freq; 598 599 sc = device_get_softc(dev); 600 601 /* Set format */ 602 val = RK_I2S_READ_4(sc, I2S_CKR); 603 604 if ((val & I2S_CKR_MSS_SLAVE) == 0) { 605 error = clk_get_freq(sc->clk, &clk_freq); 606 if (error != 0) { 607 device_printf(sc->dev, "failed to get clk frequency: err=%d\n", error); 608 return (error); 609 } 610 bus_clk_freq = 2 * 32 * speed; 611 bus_clock_div = DIV_ROUND_CLOSEST(clk_freq, bus_clk_freq); 612 lr_clock_div = bus_clk_freq / speed; 613 614 val &= ~(I2S_CKR_MDIV_MASK | I2S_CKR_RSD_MASK | I2S_CKR_TSD_MASK); 615 val |= I2S_CKR_MDIV(bus_clock_div); 616 val |= I2S_CKR_RSD(lr_clock_div); 617 val |= I2S_CKR_TSD(lr_clock_div); 618 619 RK_I2S_WRITE_4(sc, I2S_CKR, val); 620 } 621 622 return (speed); 623 } 624 625 static device_method_t rk_i2s_methods[] = { 626 /* Device interface */ 627 DEVMETHOD(device_probe, rk_i2s_probe), 628 DEVMETHOD(device_attach, rk_i2s_attach), 629 DEVMETHOD(device_detach, rk_i2s_detach), 630 631 DEVMETHOD(audio_dai_init, rk_i2s_dai_init), 632 DEVMETHOD(audio_dai_setup_intr, rk_i2s_dai_setup_intr), 633 DEVMETHOD(audio_dai_set_sysclk, rk_i2s_dai_set_sysclk), 634 DEVMETHOD(audio_dai_set_chanspeed, rk_i2s_dai_set_chanspeed), 635 DEVMETHOD(audio_dai_set_chanformat, rk_i2s_dai_set_chanformat), 636 DEVMETHOD(audio_dai_intr, rk_i2s_dai_intr), 637 DEVMETHOD(audio_dai_get_caps, rk_i2s_dai_get_caps), 638 DEVMETHOD(audio_dai_trigger, rk_i2s_dai_trigger), 639 DEVMETHOD(audio_dai_get_ptr, rk_i2s_dai_get_ptr), 640 641 DEVMETHOD_END 642 }; 643 644 static driver_t rk_i2s_driver = { 645 "i2s", 646 rk_i2s_methods, 647 sizeof(struct rk_i2s_softc), 648 }; 649 650 DRIVER_MODULE(rk_i2s, simplebus, rk_i2s_driver, 0, 0); 651 SIMPLEBUS_PNP_INFO(compat_data); 652