1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2019 Oleksandr Tymoshenko <gonzo@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 20 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 21 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 22 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 23 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/param.h> 29 #include <sys/systm.h> 30 #include <sys/bus.h> 31 #include <sys/kernel.h> 32 #include <sys/lock.h> 33 #include <sys/module.h> 34 #include <sys/mutex.h> 35 #include <sys/rman.h> 36 #include <sys/resource.h> 37 #include <machine/bus.h> 38 39 #include <dev/ofw/ofw_bus.h> 40 #include <dev/ofw/ofw_bus_subr.h> 41 42 #include <dev/clk/clk.h> 43 #include <dev/hwreset/hwreset.h> 44 #include <dev/syscon/syscon.h> 45 46 #include "syscon_if.h" 47 48 #include "opt_snd.h" 49 #include <dev/sound/pcm/sound.h> 50 #include <dev/sound/fdt/audio_dai.h> 51 #include "audio_dai_if.h" 52 53 #define I2S_TXCR 0x0000 54 #define I2S_CSR_2 (0 << 15) 55 #define I2S_CSR_4 (1 << 15) 56 #define I2S_CSR_6 (2 << 15) 57 #define I2S_CSR_8 (3 << 15) 58 #define I2S_TXCR_IBM_NORMAL (0 << 9) 59 #define I2S_TXCR_IBM_LJ (1 << 9) 60 #define I2S_TXCR_IBM_RJ (2 << 9) 61 #define I2S_TXCR_PBM_NODELAY (0 << 7) 62 #define I2S_TXCR_PBM_1 (1 << 7) 63 #define I2S_TXCR_PBM_2 (2 << 7) 64 #define I2S_TXCR_PBM_3 (3 << 7) 65 #define I2S_TXCR_TFS_I2S (0 << 5) 66 #define I2S_TXCR_TFS_PCM (1 << 5) 67 #define I2S_TXCR_VDW_16 (0xf << 0) 68 #define I2S_RXCR 0x0004 69 #define I2S_RXCR_IBM_NORMAL (0 << 9) 70 #define I2S_RXCR_IBM_LJ (1 << 9) 71 #define I2S_RXCR_IBM_RJ (2 << 9) 72 #define I2S_RXCR_PBM_NODELAY (0 << 7) 73 #define I2S_RXCR_PBM_1 (1 << 7) 74 #define I2S_RXCR_PBM_2 (2 << 7) 75 #define I2S_RXCR_PBM_3 (3 << 7) 76 #define I2S_RXCR_TFS_I2S (0 << 5) 77 #define I2S_RXCR_TFS_PCM (1 << 5) 78 #define I2S_RXCR_VDW_16 (0xf << 0) 79 #define I2S_CKR 0x0008 80 #define I2S_CKR_MSS_MASK (1 << 27) 81 #define I2S_CKR_MSS_MASTER (0 << 27) 82 #define I2S_CKR_MSS_SLAVE (1 << 27) 83 #define I2S_CKR_CKP (1 << 26) 84 #define I2S_CKR_MDIV(n) (((n) - 1) << 16) 85 #define I2S_CKR_MDIV_MASK (0xff << 16) 86 #define I2S_CKR_RSD(n) (((n) - 1) << 8) 87 #define I2S_CKR_RSD_MASK (0xff << 8) 88 #define I2S_CKR_TSD(n) (((n) - 1) << 0) 89 #define I2S_CKR_TSD_MASK (0xff << 0) 90 #define I2S_TXFIFOLR 0x000c 91 #define TXFIFO0LR_MASK 0x3f 92 #define I2S_DMACR 0x0010 93 #define I2S_DMACR_RDE_ENABLE (1 << 24) 94 #define I2S_DMACR_RDL(n) (((n) - 1) << 16) 95 #define I2S_DMACR_TDE_ENABLE (1 << 8) 96 #define I2S_DMACR_TDL(n) ((n) << 0) 97 #define I2S_INTCR 0x0014 98 #define I2S_INTCR_RFT(n) (((n) - 1) << 20) 99 #define I2S_INTCR_TFT(n) ((n) << 4) 100 #define I2S_INTCR_RXOIC (1 << 18) 101 #define I2S_INTCR_RXOIE (1 << 17) 102 #define I2S_INTCR_RXFIE (1 << 16) 103 #define I2S_INTCR_TXUIC (1 << 2) 104 #define I2S_INTCR_TXUIE (1 << 1) 105 #define I2S_INTCR_TXEIE (1 << 0) 106 #define I2S_INTSR 0x0018 107 #define I2S_INTSR_RXOI (1 << 17) 108 #define I2S_INTSR_RXFI (1 << 16) 109 #define I2S_INTSR_TXUI (1 << 1) 110 #define I2S_INTSR_TXEI (1 << 0) 111 #define I2S_XFER 0x001c 112 #define I2S_XFER_RXS_START (1 << 1) 113 #define I2S_XFER_TXS_START (1 << 0) 114 #define I2S_CLR 0x0020 115 #define I2S_CLR_RXC (1 << 1) 116 #define I2S_CLR_TXC (1 << 0) 117 #define I2S_TXDR 0x0024 118 #define I2S_RXDR 0x0028 119 #define I2S_RXFIFOLR 0x002c 120 #define RXFIFO0LR_MASK 0x3f 121 122 /* syscon */ 123 #define GRF_SOC_CON8 0xe220 124 #define I2S_IO_DIRECTION_MASK 7 125 #define I2S_IO_DIRECTION_SHIFT 11 126 #define I2S_IO_8CH_OUT_2CH_IN 0 127 #define I2S_IO_6CH_OUT_4CH_IN 4 128 #define I2S_IO_4CH_OUT_6CH_IN 6 129 #define I2S_IO_2CH_OUT_8CH_IN 7 130 131 #define DIV_ROUND_CLOSEST(n,d) (((n) + (d) / 2) / (d)) 132 133 #define RK_I2S_SAMPLING_RATE 48000 134 #define FIFO_SIZE 32 135 136 static struct ofw_compat_data compat_data[] = { 137 { "rockchip,rk3066-i2s", 1 }, 138 { "rockchip,rk3399-i2s", 1 }, 139 { NULL, 0 } 140 }; 141 142 static struct resource_spec rk_i2s_spec[] = { 143 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 144 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 145 { -1, 0 } 146 }; 147 148 struct rk_i2s_softc { 149 device_t dev; 150 struct resource *res[2]; 151 struct mtx mtx; 152 clk_t clk; 153 clk_t hclk; 154 void * intrhand; 155 struct syscon *grf; 156 /* pointers to playback/capture buffers */ 157 uint32_t play_ptr; 158 uint32_t rec_ptr; 159 }; 160 161 #define RK_I2S_LOCK(sc) mtx_lock(&(sc)->mtx) 162 #define RK_I2S_UNLOCK(sc) mtx_unlock(&(sc)->mtx) 163 #define RK_I2S_READ_4(sc, reg) bus_read_4((sc)->res[0], (reg)) 164 #define RK_I2S_WRITE_4(sc, reg, val) bus_write_4((sc)->res[0], (reg), (val)) 165 166 static int rk_i2s_probe(device_t dev); 167 static int rk_i2s_attach(device_t dev); 168 static int rk_i2s_detach(device_t dev); 169 170 static uint32_t sc_fmt[] = { 171 SND_FORMAT(AFMT_S16_LE, 2, 0), 172 0 173 }; 174 static struct pcmchan_caps rk_i2s_caps = {RK_I2S_SAMPLING_RATE, RK_I2S_SAMPLING_RATE, sc_fmt, 0}; 175 176 177 static int 178 rk_i2s_init(struct rk_i2s_softc *sc) 179 { 180 uint32_t val; 181 int error; 182 183 clk_set_freq(sc->clk, RK_I2S_SAMPLING_RATE * 256, 184 CLK_SET_ROUND_DOWN); 185 error = clk_enable(sc->clk); 186 if (error != 0) { 187 device_printf(sc->dev, "cannot enable i2s_clk clock\n"); 188 return (ENXIO); 189 } 190 191 val = I2S_INTCR_TFT(FIFO_SIZE/2); 192 val |= I2S_INTCR_RFT(FIFO_SIZE/2); 193 RK_I2S_WRITE_4(sc, I2S_INTCR, val); 194 195 if (sc->grf && ofw_bus_is_compatible(sc->dev, "rockchip,rk3399-i2s")) { 196 val = (I2S_IO_2CH_OUT_8CH_IN << I2S_IO_DIRECTION_SHIFT); 197 val |= (I2S_IO_DIRECTION_MASK << I2S_IO_DIRECTION_SHIFT) << 16; 198 SYSCON_WRITE_4(sc->grf, GRF_SOC_CON8, val); 199 200 #if 0 201 // HACK: enable IO domain 202 val = (1 << 1); 203 val |= (1 << 1) << 16; 204 SYSCON_WRITE_4(sc->grf, 0xe640, val); 205 #endif 206 } 207 208 RK_I2S_WRITE_4(sc, I2S_XFER, 0); 209 210 return (0); 211 } 212 213 static int 214 rk_i2s_probe(device_t dev) 215 { 216 if (!ofw_bus_status_okay(dev)) 217 return (ENXIO); 218 219 if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data) 220 return (ENXIO); 221 222 device_set_desc(dev, "Rockchip I2S"); 223 return (BUS_PROBE_DEFAULT); 224 } 225 226 static int 227 rk_i2s_attach(device_t dev) 228 { 229 struct rk_i2s_softc *sc; 230 int error; 231 phandle_t node; 232 233 sc = device_get_softc(dev); 234 sc->dev = dev; 235 236 mtx_init(&sc->mtx, device_get_nameunit(dev), NULL, MTX_DEF); 237 238 if (bus_alloc_resources(dev, rk_i2s_spec, sc->res) != 0) { 239 device_printf(dev, "cannot allocate resources for device\n"); 240 error = ENXIO; 241 goto fail; 242 } 243 244 error = clk_get_by_ofw_name(dev, 0, "i2s_hclk", &sc->hclk); 245 if (error != 0) { 246 device_printf(dev, "cannot get i2s_hclk clock\n"); 247 goto fail; 248 } 249 250 error = clk_get_by_ofw_name(dev, 0, "i2s_clk", &sc->clk); 251 if (error != 0) { 252 device_printf(dev, "cannot get i2s_clk clock\n"); 253 goto fail; 254 } 255 256 /* Activate the module clock. */ 257 error = clk_enable(sc->hclk); 258 if (error != 0) { 259 device_printf(dev, "cannot enable i2s_hclk clock\n"); 260 goto fail; 261 } 262 263 node = ofw_bus_get_node(dev); 264 if (OF_hasprop(node, "rockchip,grf") && 265 syscon_get_by_ofw_property(dev, node, 266 "rockchip,grf", &sc->grf) != 0) { 267 device_printf(dev, "cannot get grf driver handle\n"); 268 return (ENXIO); 269 } 270 271 rk_i2s_init(sc); 272 273 OF_device_register_xref(OF_xref_from_node(node), dev); 274 275 return (0); 276 277 fail: 278 rk_i2s_detach(dev); 279 return (error); 280 } 281 282 static int 283 rk_i2s_detach(device_t dev) 284 { 285 struct rk_i2s_softc *i2s; 286 287 i2s = device_get_softc(dev); 288 289 if (i2s->hclk != NULL) 290 clk_release(i2s->hclk); 291 if (i2s->clk) 292 clk_release(i2s->clk); 293 294 if (i2s->intrhand != NULL) 295 bus_teardown_intr(i2s->dev, i2s->res[1], i2s->intrhand); 296 297 bus_release_resources(dev, rk_i2s_spec, i2s->res); 298 mtx_destroy(&i2s->mtx); 299 300 return (0); 301 } 302 303 static int 304 rk_i2s_dai_init(device_t dev, uint32_t format) 305 { 306 uint32_t val, txcr, rxcr; 307 struct rk_i2s_softc *sc; 308 int fmt, pol, clk; 309 310 sc = device_get_softc(dev); 311 312 fmt = AUDIO_DAI_FORMAT_FORMAT(format); 313 pol = AUDIO_DAI_FORMAT_POLARITY(format); 314 clk = AUDIO_DAI_FORMAT_CLOCK(format); 315 316 /* Set format */ 317 val = RK_I2S_READ_4(sc, I2S_CKR); 318 319 val &= ~(I2S_CKR_MSS_MASK); 320 switch (clk) { 321 case AUDIO_DAI_CLOCK_CBM_CFM: 322 val |= I2S_CKR_MSS_MASTER; 323 break; 324 case AUDIO_DAI_CLOCK_CBS_CFS: 325 val |= I2S_CKR_MSS_SLAVE; 326 break; 327 default: 328 return (EINVAL); 329 } 330 331 switch (pol) { 332 case AUDIO_DAI_POLARITY_IB_NF: 333 val |= I2S_CKR_CKP; 334 break; 335 case AUDIO_DAI_POLARITY_NB_NF: 336 val &= ~I2S_CKR_CKP; 337 break; 338 default: 339 return (EINVAL); 340 } 341 342 RK_I2S_WRITE_4(sc, I2S_CKR, val); 343 344 txcr = I2S_TXCR_VDW_16 | I2S_CSR_2; 345 rxcr = I2S_RXCR_VDW_16 | I2S_CSR_2; 346 347 switch (fmt) { 348 case AUDIO_DAI_FORMAT_I2S: 349 txcr |= I2S_TXCR_IBM_NORMAL; 350 rxcr |= I2S_RXCR_IBM_NORMAL; 351 break; 352 case AUDIO_DAI_FORMAT_LJ: 353 txcr |= I2S_TXCR_IBM_LJ; 354 rxcr |= I2S_RXCR_IBM_LJ; 355 break; 356 case AUDIO_DAI_FORMAT_RJ: 357 txcr |= I2S_TXCR_IBM_RJ; 358 rxcr |= I2S_RXCR_IBM_RJ; 359 break; 360 case AUDIO_DAI_FORMAT_DSPA: 361 txcr |= I2S_TXCR_TFS_PCM; 362 rxcr |= I2S_RXCR_TFS_PCM; 363 txcr |= I2S_TXCR_PBM_1; 364 rxcr |= I2S_RXCR_PBM_1; 365 break; 366 case AUDIO_DAI_FORMAT_DSPB: 367 txcr |= I2S_TXCR_TFS_PCM; 368 rxcr |= I2S_RXCR_TFS_PCM; 369 txcr |= I2S_TXCR_PBM_2; 370 rxcr |= I2S_RXCR_PBM_2; 371 break; 372 default: 373 return EINVAL; 374 } 375 376 RK_I2S_WRITE_4(sc, I2S_TXCR, txcr); 377 RK_I2S_WRITE_4(sc, I2S_RXCR, rxcr); 378 379 RK_I2S_WRITE_4(sc, I2S_XFER, 0); 380 381 return (0); 382 } 383 384 385 static int 386 rk_i2s_dai_intr(device_t dev, struct snd_dbuf *play_buf, struct snd_dbuf *rec_buf) 387 { 388 struct rk_i2s_softc *sc; 389 uint32_t status; 390 uint32_t level; 391 uint32_t val = 0x00; 392 int ret = 0; 393 394 sc = device_get_softc(dev); 395 396 RK_I2S_LOCK(sc); 397 status = RK_I2S_READ_4(sc, I2S_INTSR); 398 399 if (status & I2S_INTSR_TXEI) { 400 level = RK_I2S_READ_4(sc, I2S_TXFIFOLR) & TXFIFO0LR_MASK; 401 uint8_t *samples; 402 uint32_t count, size, readyptr, written; 403 count = sndbuf_getready(play_buf); 404 if (count > FIFO_SIZE - 1) 405 count = FIFO_SIZE - 1; 406 size = sndbuf_getsize(play_buf); 407 readyptr = sndbuf_getreadyptr(play_buf); 408 409 samples = (uint8_t*)sndbuf_getbuf(play_buf); 410 written = 0; 411 for (; level < count; level++) { 412 val = (samples[readyptr++ % size] << 0); 413 val |= (samples[readyptr++ % size] << 8); 414 val |= (samples[readyptr++ % size] << 16); 415 val |= (samples[readyptr++ % size] << 24); 416 written += 4; 417 RK_I2S_WRITE_4(sc, I2S_TXDR, val); 418 } 419 sc->play_ptr += written; 420 sc->play_ptr %= size; 421 ret |= AUDIO_DAI_PLAY_INTR; 422 } 423 424 if (status & I2S_INTSR_RXFI) { 425 level = RK_I2S_READ_4(sc, I2S_RXFIFOLR) & RXFIFO0LR_MASK; 426 uint8_t *samples; 427 uint32_t count, size, freeptr, recorded; 428 count = sndbuf_getfree(rec_buf); 429 size = sndbuf_getsize(rec_buf); 430 freeptr = sndbuf_getfreeptr(rec_buf); 431 samples = (uint8_t*)sndbuf_getbuf(rec_buf); 432 recorded = 0; 433 if (level > count / 4) 434 level = count / 4; 435 436 for (; level > 0; level--) { 437 val = RK_I2S_READ_4(sc, I2S_RXDR); 438 samples[freeptr++ % size] = val & 0xff; 439 samples[freeptr++ % size] = (val >> 8) & 0xff; 440 samples[freeptr++ % size] = (val >> 16) & 0xff; 441 samples[freeptr++ % size] = (val >> 24) & 0xff; 442 recorded += 4; 443 } 444 sc->rec_ptr += recorded; 445 sc->rec_ptr %= size; 446 ret |= AUDIO_DAI_REC_INTR; 447 } 448 449 RK_I2S_UNLOCK(sc); 450 451 return (ret); 452 } 453 454 static struct pcmchan_caps * 455 rk_i2s_dai_get_caps(device_t dev) 456 { 457 return (&rk_i2s_caps); 458 } 459 460 static int 461 rk_i2s_dai_trigger(device_t dev, int go, int pcm_dir) 462 { 463 struct rk_i2s_softc *sc = device_get_softc(dev); 464 uint32_t val; 465 uint32_t clear_bit; 466 467 if ((pcm_dir != PCMDIR_PLAY) && (pcm_dir != PCMDIR_REC)) 468 return (EINVAL); 469 470 switch (go) { 471 case PCMTRIG_START: 472 val = RK_I2S_READ_4(sc, I2S_INTCR); 473 if (pcm_dir == PCMDIR_PLAY) 474 val |= I2S_INTCR_TXEIE; 475 else if (pcm_dir == PCMDIR_REC) 476 val |= I2S_INTCR_RXFIE; 477 RK_I2S_WRITE_4(sc, I2S_INTCR, val); 478 479 val = I2S_XFER_TXS_START | I2S_XFER_RXS_START; 480 RK_I2S_WRITE_4(sc, I2S_XFER, val); 481 break; 482 483 case PCMTRIG_STOP: 484 case PCMTRIG_ABORT: 485 val = RK_I2S_READ_4(sc, I2S_INTCR); 486 if (pcm_dir == PCMDIR_PLAY) 487 val &= ~I2S_INTCR_TXEIE; 488 else if (pcm_dir == PCMDIR_REC) 489 val &= ~I2S_INTCR_RXFIE; 490 RK_I2S_WRITE_4(sc, I2S_INTCR, val); 491 492 /* 493 * If there is no other activity going on, stop transfers 494 */ 495 if ((val & (I2S_INTCR_TXEIE | I2S_INTCR_RXFIE)) == 0) { 496 RK_I2S_WRITE_4(sc, I2S_XFER, 0); 497 498 if (pcm_dir == PCMDIR_PLAY) 499 clear_bit = I2S_CLR_TXC; 500 else if (pcm_dir == PCMDIR_REC) 501 clear_bit = I2S_CLR_RXC; 502 else 503 return (EINVAL); 504 505 val = RK_I2S_READ_4(sc, I2S_CLR); 506 val |= clear_bit; 507 RK_I2S_WRITE_4(sc, I2S_CLR, val); 508 509 while ((RK_I2S_READ_4(sc, I2S_CLR) & clear_bit) != 0) 510 DELAY(1); 511 } 512 513 RK_I2S_LOCK(sc); 514 if (pcm_dir == PCMDIR_PLAY) 515 sc->play_ptr = 0; 516 else 517 sc->rec_ptr = 0; 518 RK_I2S_UNLOCK(sc); 519 break; 520 } 521 522 return (0); 523 } 524 525 static uint32_t 526 rk_i2s_dai_get_ptr(device_t dev, int pcm_dir) 527 { 528 struct rk_i2s_softc *sc; 529 uint32_t ptr; 530 531 sc = device_get_softc(dev); 532 533 RK_I2S_LOCK(sc); 534 if (pcm_dir == PCMDIR_PLAY) 535 ptr = sc->play_ptr; 536 else 537 ptr = sc->rec_ptr; 538 RK_I2S_UNLOCK(sc); 539 540 return ptr; 541 } 542 543 static int 544 rk_i2s_dai_setup_intr(device_t dev, driver_intr_t intr_handler, void *intr_arg) 545 { 546 struct rk_i2s_softc *sc = device_get_softc(dev); 547 548 if (bus_setup_intr(dev, sc->res[1], 549 INTR_TYPE_AV | INTR_MPSAFE, NULL, intr_handler, intr_arg, 550 &sc->intrhand)) { 551 device_printf(dev, "cannot setup interrupt handler\n"); 552 return (ENXIO); 553 } 554 555 return (0); 556 } 557 558 static uint32_t 559 rk_i2s_dai_set_chanformat(device_t dev, uint32_t format) 560 { 561 562 return (0); 563 } 564 565 static int 566 rk_i2s_dai_set_sysclk(device_t dev, unsigned int rate, int dai_dir) 567 { 568 struct rk_i2s_softc *sc; 569 int error; 570 571 sc = device_get_softc(dev); 572 error = clk_disable(sc->clk); 573 if (error != 0) { 574 device_printf(sc->dev, "could not disable i2s_clk clock\n"); 575 return (error); 576 } 577 578 error = clk_set_freq(sc->clk, rate, CLK_SET_ROUND_DOWN); 579 if (error != 0) 580 device_printf(sc->dev, "could not set i2s_clk freq\n"); 581 582 error = clk_enable(sc->clk); 583 if (error != 0) { 584 device_printf(sc->dev, "could not enable i2s_clk clock\n"); 585 return (error); 586 } 587 588 return (0); 589 } 590 591 static uint32_t 592 rk_i2s_dai_set_chanspeed(device_t dev, uint32_t speed) 593 { 594 struct rk_i2s_softc *sc; 595 int error; 596 uint32_t val; 597 uint32_t bus_clock_div, lr_clock_div; 598 uint64_t bus_clk_freq; 599 uint64_t clk_freq; 600 601 sc = device_get_softc(dev); 602 603 /* Set format */ 604 val = RK_I2S_READ_4(sc, I2S_CKR); 605 606 if ((val & I2S_CKR_MSS_SLAVE) == 0) { 607 error = clk_get_freq(sc->clk, &clk_freq); 608 if (error != 0) { 609 device_printf(sc->dev, "failed to get clk frequency: err=%d\n", error); 610 return (error); 611 } 612 bus_clk_freq = 2 * 32 * speed; 613 bus_clock_div = DIV_ROUND_CLOSEST(clk_freq, bus_clk_freq); 614 lr_clock_div = bus_clk_freq / speed; 615 616 val &= ~(I2S_CKR_MDIV_MASK | I2S_CKR_RSD_MASK | I2S_CKR_TSD_MASK); 617 val |= I2S_CKR_MDIV(bus_clock_div); 618 val |= I2S_CKR_RSD(lr_clock_div); 619 val |= I2S_CKR_TSD(lr_clock_div); 620 621 RK_I2S_WRITE_4(sc, I2S_CKR, val); 622 } 623 624 return (speed); 625 } 626 627 static device_method_t rk_i2s_methods[] = { 628 /* Device interface */ 629 DEVMETHOD(device_probe, rk_i2s_probe), 630 DEVMETHOD(device_attach, rk_i2s_attach), 631 DEVMETHOD(device_detach, rk_i2s_detach), 632 633 DEVMETHOD(audio_dai_init, rk_i2s_dai_init), 634 DEVMETHOD(audio_dai_setup_intr, rk_i2s_dai_setup_intr), 635 DEVMETHOD(audio_dai_set_sysclk, rk_i2s_dai_set_sysclk), 636 DEVMETHOD(audio_dai_set_chanspeed, rk_i2s_dai_set_chanspeed), 637 DEVMETHOD(audio_dai_set_chanformat, rk_i2s_dai_set_chanformat), 638 DEVMETHOD(audio_dai_intr, rk_i2s_dai_intr), 639 DEVMETHOD(audio_dai_get_caps, rk_i2s_dai_get_caps), 640 DEVMETHOD(audio_dai_trigger, rk_i2s_dai_trigger), 641 DEVMETHOD(audio_dai_get_ptr, rk_i2s_dai_get_ptr), 642 643 DEVMETHOD_END 644 }; 645 646 static driver_t rk_i2s_driver = { 647 "i2s", 648 rk_i2s_methods, 649 sizeof(struct rk_i2s_softc), 650 }; 651 652 DRIVER_MODULE(rk_i2s, simplebus, rk_i2s_driver, 0, 0); 653 SIMPLEBUS_PNP_INFO(compat_data); 654