1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2019 Oleksandr Tymoshenko <gonzo@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 20 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 21 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 22 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 23 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 #include <sys/param.h> 30 #include <sys/systm.h> 31 #include <sys/bus.h> 32 #include <sys/kernel.h> 33 #include <sys/lock.h> 34 #include <sys/module.h> 35 #include <sys/mutex.h> 36 #include <sys/rman.h> 37 #include <sys/resource.h> 38 #include <machine/bus.h> 39 40 #include <dev/ofw/ofw_bus.h> 41 #include <dev/ofw/ofw_bus_subr.h> 42 43 #include <dev/extres/clk/clk.h> 44 #include <dev/extres/hwreset/hwreset.h> 45 #include <dev/extres/syscon/syscon.h> 46 47 #include "syscon_if.h" 48 49 #include "opt_snd.h" 50 #include <dev/sound/pcm/sound.h> 51 #include <dev/sound/fdt/audio_dai.h> 52 #include "audio_dai_if.h" 53 54 #define AUDIO_BUFFER_SIZE 48000 * 4 55 56 #define I2S_TXCR 0x0000 57 #define I2S_CSR_2 (0 << 15) 58 #define I2S_CSR_4 (1 << 15) 59 #define I2S_CSR_6 (2 << 15) 60 #define I2S_CSR_8 (3 << 15) 61 #define I2S_TXCR_IBM_NORMAL (0 << 9) 62 #define I2S_TXCR_IBM_LJ (1 << 9) 63 #define I2S_TXCR_IBM_RJ (2 << 9) 64 #define I2S_TXCR_PBM_NODELAY (0 << 7) 65 #define I2S_TXCR_PBM_1 (1 << 7) 66 #define I2S_TXCR_PBM_2 (2 << 7) 67 #define I2S_TXCR_PBM_3 (3 << 7) 68 #define I2S_TXCR_TFS_I2S (0 << 5) 69 #define I2S_TXCR_TFS_PCM (1 << 5) 70 #define I2S_TXCR_VDW_16 (0xf << 0) 71 #define I2S_RXCR 0x0004 72 #define I2S_RXCR_IBM_NORMAL (0 << 9) 73 #define I2S_RXCR_IBM_LJ (1 << 9) 74 #define I2S_RXCR_IBM_RJ (2 << 9) 75 #define I2S_RXCR_PBM_NODELAY (0 << 7) 76 #define I2S_RXCR_PBM_1 (1 << 7) 77 #define I2S_RXCR_PBM_2 (2 << 7) 78 #define I2S_RXCR_PBM_3 (3 << 7) 79 #define I2S_RXCR_TFS_I2S (0 << 5) 80 #define I2S_RXCR_TFS_PCM (1 << 5) 81 #define I2S_RXCR_VDW_16 (0xf << 0) 82 #define I2S_CKR 0x0008 83 #define I2S_CKR_MSS_MASK (1 << 27) 84 #define I2S_CKR_MSS_MASTER (0 << 27) 85 #define I2S_CKR_MSS_SLAVE (1 << 27) 86 #define I2S_CKR_CKP (1 << 26) 87 #define I2S_CKR_MDIV(n) (((n) - 1) << 16) 88 #define I2S_CKR_MDIV_MASK (0xff << 16) 89 #define I2S_CKR_RSD(n) (((n) - 1) << 8) 90 #define I2S_CKR_RSD_MASK (0xff << 8) 91 #define I2S_CKR_TSD(n) (((n) - 1) << 0) 92 #define I2S_CKR_TSD_MASK (0xff << 0) 93 #define I2S_TXFIFOLR 0x000c 94 #define TXFIFO0LR_MASK 0x3f 95 #define I2S_DMACR 0x0010 96 #define I2S_DMACR_RDE_ENABLE (1 << 24) 97 #define I2S_DMACR_RDL(n) ((n) << 16) 98 #define I2S_DMACR_TDE_ENABLE (1 << 8) 99 #define I2S_DMACR_TDL(n) ((n) << 0) 100 #define I2S_INTCR 0x0014 101 #define I2S_INTCR_RFT(n) (((n) - 1) << 20) 102 #define I2S_INTCR_TFT(n) (((n) - 1) << 4) 103 #define I2S_INTCR_RXFIE (1 << 16) 104 #define I2S_INTCR_TXUIC (1 << 2) 105 #define I2S_INTCR_TXEIE (1 << 0) 106 #define I2S_INTSR 0x0018 107 #define I2S_INTSR_RXFI (1 << 16) 108 #define I2S_INTSR_TXUI (1 << 1) 109 #define I2S_INTSR_TXEI (1 << 0) 110 #define I2S_XFER 0x001c 111 #define I2S_XFER_RXS_START (1 << 1) 112 #define I2S_XFER_TXS_START (1 << 0) 113 #define I2S_CLR 0x0020 114 #define I2S_CLR_RXC (1 << 1) 115 #define I2S_CLR_TXC (1 << 0) 116 #define I2S_TXDR 0x0024 117 #define I2S_RXDR 0x0028 118 #define I2S_RXFIFOLR 0x002c 119 #define RXFIFO0LR_MASK 0x3f 120 121 /* syscon */ 122 #define GRF_SOC_CON8 0xe220 123 #define I2S_IO_DIRECTION_MASK 7 124 #define I2S_IO_DIRECTION_SHIFT 11 125 #define I2S_IO_8CH_OUT_2CH_IN 0 126 #define I2S_IO_6CH_OUT_4CH_IN 4 127 #define I2S_IO_4CH_OUT_6CH_IN 6 128 #define I2S_IO_2CH_OUT_8CH_IN 7 129 130 #define DIV_ROUND_CLOSEST(n,d) (((n) + (d) / 2) / (d)) 131 132 #define RK_I2S_SAMPLING_RATE 48000 133 #define FIFO_SIZE 32 134 135 static struct ofw_compat_data compat_data[] = { 136 { "rockchip,rk3066-i2s", 1 }, 137 { "rockchip,rk3399-i2s", 1 }, 138 { NULL, 0 } 139 }; 140 141 static struct resource_spec rk_i2s_spec[] = { 142 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 143 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 144 { -1, 0 } 145 }; 146 147 struct rk_i2s_softc { 148 device_t dev; 149 struct resource *res[2]; 150 struct mtx mtx; 151 clk_t clk; 152 clk_t hclk; 153 void * intrhand; 154 struct syscon *grf; 155 /* pointers to playback/capture buffers */ 156 uint32_t play_ptr; 157 uint32_t rec_ptr; 158 }; 159 160 #define RK_I2S_LOCK(sc) mtx_lock(&(sc)->mtx) 161 #define RK_I2S_UNLOCK(sc) mtx_unlock(&(sc)->mtx) 162 #define RK_I2S_READ_4(sc, reg) bus_read_4((sc)->res[0], (reg)) 163 #define RK_I2S_WRITE_4(sc, reg, val) bus_write_4((sc)->res[0], (reg), (val)) 164 165 static int rk_i2s_probe(device_t dev); 166 static int rk_i2s_attach(device_t dev); 167 static int rk_i2s_detach(device_t dev); 168 169 static uint32_t sc_fmt[] = { 170 SND_FORMAT(AFMT_S16_LE, 2, 0), 171 0 172 }; 173 static struct pcmchan_caps rk_i2s_caps = {RK_I2S_SAMPLING_RATE, RK_I2S_SAMPLING_RATE, sc_fmt, 0}; 174 175 176 static int 177 rk_i2s_init(struct rk_i2s_softc *sc) 178 { 179 uint32_t val; 180 int error; 181 182 clk_set_freq(sc->clk, RK_I2S_SAMPLING_RATE * 256, 183 CLK_SET_ROUND_DOWN); 184 error = clk_enable(sc->clk); 185 if (error != 0) { 186 device_printf(sc->dev, "cannot enable i2s_clk clock\n"); 187 return (ENXIO); 188 } 189 190 val = I2S_INTCR_TFT(FIFO_SIZE/2); 191 val |= I2S_INTCR_RFT(FIFO_SIZE/2); 192 RK_I2S_WRITE_4(sc, I2S_INTCR, val); 193 194 if (sc->grf && ofw_bus_is_compatible(sc->dev, "rockchip,rk3399-i2s")) { 195 val = (I2S_IO_2CH_OUT_8CH_IN << I2S_IO_DIRECTION_SHIFT); 196 val |= (I2S_IO_DIRECTION_MASK << I2S_IO_DIRECTION_SHIFT) << 16; 197 SYSCON_WRITE_4(sc->grf, GRF_SOC_CON8, val); 198 199 #if 0 200 // HACK: enable IO domain 201 val = (1 << 1); 202 val |= (1 << 1) << 16; 203 SYSCON_WRITE_4(sc->grf, 0xe640, val); 204 #endif 205 } 206 207 RK_I2S_WRITE_4(sc, I2S_XFER, 0); 208 209 return (0); 210 } 211 212 static int 213 rk_i2s_probe(device_t dev) 214 { 215 if (!ofw_bus_status_okay(dev)) 216 return (ENXIO); 217 218 if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data) 219 return (ENXIO); 220 221 device_set_desc(dev, "Rockchip I2S"); 222 return (BUS_PROBE_DEFAULT); 223 } 224 225 static int 226 rk_i2s_attach(device_t dev) 227 { 228 struct rk_i2s_softc *sc; 229 int error; 230 phandle_t node; 231 232 sc = device_get_softc(dev); 233 sc->dev = dev; 234 235 mtx_init(&sc->mtx, device_get_nameunit(dev), NULL, MTX_DEF); 236 237 if (bus_alloc_resources(dev, rk_i2s_spec, sc->res) != 0) { 238 device_printf(dev, "cannot allocate resources for device\n"); 239 error = ENXIO; 240 goto fail; 241 } 242 243 error = clk_get_by_ofw_name(dev, 0, "i2s_hclk", &sc->hclk); 244 if (error != 0) { 245 device_printf(dev, "cannot get i2s_hclk clock\n"); 246 goto fail; 247 } 248 249 error = clk_get_by_ofw_name(dev, 0, "i2s_clk", &sc->clk); 250 if (error != 0) { 251 device_printf(dev, "cannot get i2s_clk clock\n"); 252 goto fail; 253 } 254 255 /* Activate the module clock. */ 256 error = clk_enable(sc->hclk); 257 if (error != 0) { 258 device_printf(dev, "cannot enable i2s_hclk clock\n"); 259 goto fail; 260 } 261 262 node = ofw_bus_get_node(dev); 263 if (OF_hasprop(node, "rockchip,grf") && 264 syscon_get_by_ofw_property(dev, node, 265 "rockchip,grf", &sc->grf) != 0) { 266 device_printf(dev, "cannot get grf driver handle\n"); 267 return (ENXIO); 268 } 269 270 rk_i2s_init(sc); 271 272 OF_device_register_xref(OF_xref_from_node(node), dev); 273 274 return (0); 275 276 fail: 277 rk_i2s_detach(dev); 278 return (error); 279 } 280 281 static int 282 rk_i2s_detach(device_t dev) 283 { 284 struct rk_i2s_softc *i2s; 285 286 i2s = device_get_softc(dev); 287 288 if (i2s->hclk != NULL) 289 clk_release(i2s->hclk); 290 if (i2s->clk) 291 clk_release(i2s->clk); 292 293 if (i2s->intrhand != NULL) 294 bus_teardown_intr(i2s->dev, i2s->res[1], i2s->intrhand); 295 296 bus_release_resources(dev, rk_i2s_spec, i2s->res); 297 mtx_destroy(&i2s->mtx); 298 299 return (0); 300 } 301 302 static int 303 rk_i2s_dai_init(device_t dev, uint32_t format) 304 { 305 uint32_t val, txcr, rxcr; 306 struct rk_i2s_softc *sc; 307 int fmt, pol, clk; 308 309 sc = device_get_softc(dev); 310 311 fmt = AUDIO_DAI_FORMAT_FORMAT(format); 312 pol = AUDIO_DAI_FORMAT_POLARITY(format); 313 clk = AUDIO_DAI_FORMAT_CLOCK(format); 314 315 /* Set format */ 316 val = RK_I2S_READ_4(sc, I2S_CKR); 317 318 val &= ~(I2S_CKR_MSS_MASK); 319 switch (clk) { 320 case AUDIO_DAI_CLOCK_CBM_CFM: 321 val |= I2S_CKR_MSS_MASTER; 322 break; 323 case AUDIO_DAI_CLOCK_CBS_CFS: 324 val |= I2S_CKR_MSS_SLAVE; 325 break; 326 default: 327 return (EINVAL); 328 } 329 330 switch (pol) { 331 case AUDIO_DAI_POLARITY_IB_NF: 332 val |= I2S_CKR_CKP; 333 break; 334 case AUDIO_DAI_POLARITY_NB_NF: 335 val &= ~I2S_CKR_CKP; 336 break; 337 default: 338 return (EINVAL); 339 } 340 341 RK_I2S_WRITE_4(sc, I2S_CKR, val); 342 343 txcr = I2S_TXCR_VDW_16 | I2S_CSR_2; 344 rxcr = I2S_RXCR_VDW_16 | I2S_CSR_2; 345 346 switch (fmt) { 347 case AUDIO_DAI_FORMAT_I2S: 348 txcr |= I2S_TXCR_IBM_NORMAL; 349 rxcr |= I2S_RXCR_IBM_NORMAL; 350 break; 351 case AUDIO_DAI_FORMAT_LJ: 352 txcr |= I2S_TXCR_IBM_LJ; 353 rxcr |= I2S_RXCR_IBM_LJ; 354 break; 355 case AUDIO_DAI_FORMAT_RJ: 356 txcr |= I2S_TXCR_IBM_RJ; 357 rxcr |= I2S_RXCR_IBM_RJ; 358 break; 359 case AUDIO_DAI_FORMAT_DSPA: 360 txcr |= I2S_TXCR_TFS_PCM; 361 rxcr |= I2S_RXCR_TFS_PCM; 362 txcr |= I2S_TXCR_PBM_1; 363 rxcr |= I2S_RXCR_PBM_1; 364 break; 365 case AUDIO_DAI_FORMAT_DSPB: 366 txcr |= I2S_TXCR_TFS_PCM; 367 rxcr |= I2S_RXCR_TFS_PCM; 368 txcr |= I2S_TXCR_PBM_2; 369 rxcr |= I2S_RXCR_PBM_2; 370 break; 371 default: 372 return EINVAL; 373 } 374 375 RK_I2S_WRITE_4(sc, I2S_TXCR, txcr); 376 RK_I2S_WRITE_4(sc, I2S_RXCR, rxcr); 377 378 RK_I2S_WRITE_4(sc, I2S_XFER, 0); 379 380 return (0); 381 } 382 383 384 static int 385 rk_i2s_dai_intr(device_t dev, struct snd_dbuf *play_buf, struct snd_dbuf *rec_buf) 386 { 387 struct rk_i2s_softc *sc; 388 uint32_t status; 389 uint32_t level; 390 uint32_t val = 0x00; 391 int ret = 0; 392 393 sc = device_get_softc(dev); 394 395 RK_I2S_LOCK(sc); 396 status = RK_I2S_READ_4(sc, I2S_INTSR); 397 398 if (status & I2S_INTSR_TXEI) { 399 level = RK_I2S_READ_4(sc, I2S_TXFIFOLR) & TXFIFO0LR_MASK; 400 uint8_t *samples; 401 uint32_t count, size, readyptr, written; 402 count = sndbuf_getready(play_buf); 403 if (count > FIFO_SIZE - 1) 404 count = FIFO_SIZE - 1; 405 size = sndbuf_getsize(play_buf); 406 readyptr = sndbuf_getreadyptr(play_buf); 407 408 samples = (uint8_t*)sndbuf_getbuf(play_buf); 409 written = 0; 410 for (; level < count; level++) { 411 val = (samples[readyptr++ % size] << 0); 412 val |= (samples[readyptr++ % size] << 8); 413 val |= (samples[readyptr++ % size] << 16); 414 val |= (samples[readyptr++ % size] << 24); 415 written += 4; 416 RK_I2S_WRITE_4(sc, I2S_TXDR, val); 417 } 418 sc->play_ptr += written; 419 sc->play_ptr %= size; 420 ret |= AUDIO_DAI_PLAY_INTR; 421 } 422 423 if (status & I2S_INTSR_RXFI) { 424 level = RK_I2S_READ_4(sc, I2S_RXFIFOLR) & RXFIFO0LR_MASK; 425 uint8_t *samples; 426 uint32_t count, size, freeptr, recorded; 427 count = sndbuf_getfree(rec_buf); 428 size = sndbuf_getsize(rec_buf); 429 freeptr = sndbuf_getfreeptr(rec_buf); 430 samples = (uint8_t*)sndbuf_getbuf(rec_buf); 431 recorded = 0; 432 if (level > count / 4) 433 level = count / 4; 434 435 for (; level > 0; level--) { 436 val = RK_I2S_READ_4(sc, I2S_RXDR); 437 samples[freeptr++ % size] = val & 0xff; 438 samples[freeptr++ % size] = (val >> 8) & 0xff; 439 samples[freeptr++ % size] = (val >> 16) & 0xff; 440 samples[freeptr++ % size] = (val >> 24) & 0xff; 441 recorded += 4; 442 } 443 sc->rec_ptr += recorded; 444 sc->rec_ptr %= size; 445 ret |= AUDIO_DAI_REC_INTR; 446 } 447 448 RK_I2S_UNLOCK(sc); 449 450 return (ret); 451 } 452 453 static struct pcmchan_caps * 454 rk_i2s_dai_get_caps(device_t dev) 455 { 456 return (&rk_i2s_caps); 457 } 458 459 static int 460 rk_i2s_dai_trigger(device_t dev, int go, int pcm_dir) 461 { 462 struct rk_i2s_softc *sc = device_get_softc(dev); 463 uint32_t val; 464 uint32_t clear_bit; 465 466 if ((pcm_dir != PCMDIR_PLAY) && (pcm_dir != PCMDIR_REC)) 467 return (EINVAL); 468 469 switch (go) { 470 case PCMTRIG_START: 471 val = RK_I2S_READ_4(sc, I2S_INTCR); 472 if (pcm_dir == PCMDIR_PLAY) 473 val |= I2S_INTCR_TXEIE; 474 else if (pcm_dir == PCMDIR_REC) 475 val |= I2S_INTCR_RXFIE; 476 RK_I2S_WRITE_4(sc, I2S_INTCR, val); 477 478 val = I2S_XFER_TXS_START | I2S_XFER_RXS_START; 479 RK_I2S_WRITE_4(sc, I2S_XFER, val); 480 break; 481 482 case PCMTRIG_STOP: 483 case PCMTRIG_ABORT: 484 val = RK_I2S_READ_4(sc, I2S_INTCR); 485 if (pcm_dir == PCMDIR_PLAY) 486 val &= ~I2S_INTCR_TXEIE; 487 else if (pcm_dir == PCMDIR_REC) 488 val &= ~I2S_INTCR_RXFIE; 489 RK_I2S_WRITE_4(sc, I2S_INTCR, val); 490 491 /* 492 * If there is no other activity going on, stop transfers 493 */ 494 if ((val & (I2S_INTCR_TXEIE | I2S_INTCR_RXFIE)) == 0) { 495 RK_I2S_WRITE_4(sc, I2S_XFER, 0); 496 497 if (pcm_dir == PCMDIR_PLAY) 498 clear_bit = I2S_CLR_TXC; 499 else if (pcm_dir == PCMDIR_REC) 500 clear_bit = I2S_CLR_RXC; 501 else 502 return (EINVAL); 503 504 val = RK_I2S_READ_4(sc, I2S_CLR); 505 val |= clear_bit; 506 RK_I2S_WRITE_4(sc, I2S_CLR, val); 507 508 while ((RK_I2S_READ_4(sc, I2S_CLR) & clear_bit) != 0) 509 DELAY(1); 510 } 511 512 RK_I2S_LOCK(sc); 513 if (pcm_dir == PCMDIR_PLAY) 514 sc->play_ptr = 0; 515 else 516 sc->rec_ptr = 0; 517 RK_I2S_UNLOCK(sc); 518 break; 519 } 520 521 return (0); 522 } 523 524 static uint32_t 525 rk_i2s_dai_get_ptr(device_t dev, int pcm_dir) 526 { 527 struct rk_i2s_softc *sc; 528 uint32_t ptr; 529 530 sc = device_get_softc(dev); 531 532 RK_I2S_LOCK(sc); 533 if (pcm_dir == PCMDIR_PLAY) 534 ptr = sc->play_ptr; 535 else 536 ptr = sc->rec_ptr; 537 RK_I2S_UNLOCK(sc); 538 539 return ptr; 540 } 541 542 static int 543 rk_i2s_dai_setup_intr(device_t dev, driver_intr_t intr_handler, void *intr_arg) 544 { 545 struct rk_i2s_softc *sc = device_get_softc(dev); 546 547 if (bus_setup_intr(dev, sc->res[1], 548 INTR_TYPE_MISC | INTR_MPSAFE, NULL, intr_handler, intr_arg, 549 &sc->intrhand)) { 550 device_printf(dev, "cannot setup interrupt handler\n"); 551 return (ENXIO); 552 } 553 554 return (0); 555 } 556 557 static uint32_t 558 rk_i2s_dai_set_chanformat(device_t dev, uint32_t format) 559 { 560 561 return (0); 562 } 563 564 static int 565 rk_i2s_dai_set_sysclk(device_t dev, unsigned int rate, int dai_dir) 566 { 567 struct rk_i2s_softc *sc; 568 int error; 569 570 sc = device_get_softc(dev); 571 error = clk_disable(sc->clk); 572 if (error != 0) { 573 device_printf(sc->dev, "could not disable i2s_clk clock\n"); 574 return (error); 575 } 576 577 error = clk_set_freq(sc->clk, rate, CLK_SET_ROUND_DOWN); 578 if (error != 0) 579 device_printf(sc->dev, "could not set i2s_clk freq\n"); 580 581 error = clk_enable(sc->clk); 582 if (error != 0) { 583 device_printf(sc->dev, "could not enable i2s_clk clock\n"); 584 return (error); 585 } 586 587 return (0); 588 } 589 590 static uint32_t 591 rk_i2s_dai_set_chanspeed(device_t dev, uint32_t speed) 592 { 593 struct rk_i2s_softc *sc; 594 int error; 595 uint32_t val; 596 uint32_t bus_clock_div, lr_clock_div; 597 uint64_t bus_clk_freq; 598 uint64_t clk_freq; 599 600 sc = device_get_softc(dev); 601 602 /* Set format */ 603 val = RK_I2S_READ_4(sc, I2S_CKR); 604 605 if ((val & I2S_CKR_MSS_SLAVE) == 0) { 606 error = clk_get_freq(sc->clk, &clk_freq); 607 if (error != 0) { 608 device_printf(sc->dev, "failed to get clk frequency: err=%d\n", error); 609 return (error); 610 } 611 bus_clk_freq = 2 * 32 * speed; 612 bus_clock_div = DIV_ROUND_CLOSEST(clk_freq, bus_clk_freq); 613 lr_clock_div = bus_clk_freq / speed; 614 615 val &= ~(I2S_CKR_MDIV_MASK | I2S_CKR_RSD_MASK | I2S_CKR_TSD_MASK); 616 val |= I2S_CKR_MDIV(bus_clock_div); 617 val |= I2S_CKR_RSD(lr_clock_div); 618 val |= I2S_CKR_TSD(lr_clock_div); 619 620 RK_I2S_WRITE_4(sc, I2S_CKR, val); 621 } 622 623 return (speed); 624 } 625 626 static device_method_t rk_i2s_methods[] = { 627 /* Device interface */ 628 DEVMETHOD(device_probe, rk_i2s_probe), 629 DEVMETHOD(device_attach, rk_i2s_attach), 630 DEVMETHOD(device_detach, rk_i2s_detach), 631 632 DEVMETHOD(audio_dai_init, rk_i2s_dai_init), 633 DEVMETHOD(audio_dai_setup_intr, rk_i2s_dai_setup_intr), 634 DEVMETHOD(audio_dai_set_sysclk, rk_i2s_dai_set_sysclk), 635 DEVMETHOD(audio_dai_set_chanspeed, rk_i2s_dai_set_chanspeed), 636 DEVMETHOD(audio_dai_set_chanformat, rk_i2s_dai_set_chanformat), 637 DEVMETHOD(audio_dai_intr, rk_i2s_dai_intr), 638 DEVMETHOD(audio_dai_get_caps, rk_i2s_dai_get_caps), 639 DEVMETHOD(audio_dai_trigger, rk_i2s_dai_trigger), 640 DEVMETHOD(audio_dai_get_ptr, rk_i2s_dai_get_ptr), 641 642 DEVMETHOD_END 643 }; 644 645 static driver_t rk_i2s_driver = { 646 "i2s", 647 rk_i2s_methods, 648 sizeof(struct rk_i2s_softc), 649 }; 650 651 DRIVER_MODULE(rk_i2s, simplebus, rk_i2s_driver, 0, 0); 652 SIMPLEBUS_PNP_INFO(compat_data); 653