1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2018 Emmanuel Vadot <manu@FreeBSD.org> 5 * Copyright (c) 2021 Soren Schmidt <sos@deepcore.dk> 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 */ 29 30 #include <sys/cdefs.h> 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/bus.h> 34 35 #include <sys/kernel.h> 36 #include <sys/module.h> 37 #include <sys/proc.h> 38 #include <sys/rman.h> 39 #include <sys/lock.h> 40 #include <sys/mutex.h> 41 #include <sys/gpio.h> 42 43 #include <machine/bus.h> 44 #include <machine/resource.h> 45 #include <machine/intr.h> 46 47 #include <dev/gpio/gpiobusvar.h> 48 #include <dev/ofw/ofw_bus.h> 49 #include <dev/ofw/ofw_bus_subr.h> 50 #include <dev/extres/clk/clk.h> 51 52 #include "gpio_if.h" 53 #include "pic_if.h" 54 55 #include "fdt_pinctrl_if.h" 56 57 enum gpio_regs { 58 RK_GPIO_SWPORTA_DR = 1, /* Data register */ 59 RK_GPIO_SWPORTA_DDR, /* Data direction register */ 60 RK_GPIO_INTEN, /* Interrupt enable register */ 61 RK_GPIO_INTMASK, /* Interrupt mask register */ 62 RK_GPIO_INTTYPE_LEVEL, /* Interrupt level register */ 63 RK_GPIO_INTTYPE_BOTH, /* Both rise and falling edge */ 64 RK_GPIO_INT_POLARITY, /* Interrupt polarity register */ 65 RK_GPIO_INT_STATUS, /* Interrupt status register */ 66 RK_GPIO_INT_RAWSTATUS, /* Raw Interrupt status register */ 67 RK_GPIO_DEBOUNCE, /* Debounce enable register */ 68 RK_GPIO_PORTA_EOI, /* Clear interrupt register */ 69 RK_GPIO_EXT_PORTA, /* External port register */ 70 RK_GPIO_REGNUM 71 }; 72 73 #define RK_GPIO_LS_SYNC 0x60 /* Level sensitive syncronization enable register */ 74 75 #define RK_GPIO_DEFAULT_CAPS (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | \ 76 GPIO_PIN_PULLUP | GPIO_PIN_PULLDOWN | GPIO_INTR_EDGE_BOTH | \ 77 GPIO_INTR_EDGE_RISING | GPIO_INTR_EDGE_FALLING | \ 78 GPIO_INTR_LEVEL_HIGH | GPIO_INTR_LEVEL_LOW) 79 80 #define GPIO_FLAGS_PINCTRL GPIO_PIN_PULLUP | GPIO_PIN_PULLDOWN 81 #define RK_GPIO_MAX_PINS 32 82 83 struct pin_cached { 84 uint8_t is_gpio; 85 uint32_t flags; 86 }; 87 88 struct rk_pin_irqsrc { 89 struct intr_irqsrc isrc; 90 uint32_t irq; 91 uint32_t mode; 92 }; 93 94 struct rk_gpio_softc { 95 device_t sc_dev; 96 device_t sc_busdev; 97 struct mtx sc_mtx; 98 struct resource *sc_res[2]; 99 bus_space_tag_t sc_bst; 100 bus_space_handle_t sc_bsh; 101 clk_t clk; 102 device_t pinctrl; 103 uint32_t swporta; 104 uint32_t swporta_ddr; 105 uint32_t version; 106 struct pin_cached pin_cached[RK_GPIO_MAX_PINS]; 107 uint8_t regs[RK_GPIO_REGNUM]; 108 void *ihandle; 109 struct rk_pin_irqsrc isrcs[RK_GPIO_MAX_PINS]; 110 }; 111 112 static struct ofw_compat_data compat_data[] = { 113 {"rockchip,gpio-bank", 1}, 114 {NULL, 0} 115 }; 116 117 static struct resource_spec rk_gpio_spec[] = { 118 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 119 { SYS_RES_IRQ, 0, RF_ACTIVE }, 120 { -1, 0 } 121 }; 122 123 #define RK_GPIO_VERSION 0x78 124 #define RK_GPIO_TYPE_V1 0x00000000 125 #define RK_GPIO_TYPE_V2 0x01000c2b 126 #define RK_GPIO_ISRC(sc, irq) (&(sc->isrcs[irq].isrc)) 127 128 static int rk_gpio_detach(device_t dev); 129 130 #define RK_GPIO_LOCK(_sc) mtx_lock_spin(&(_sc)->sc_mtx) 131 #define RK_GPIO_UNLOCK(_sc) mtx_unlock_spin(&(_sc)->sc_mtx) 132 #define RK_GPIO_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) 133 134 #define RK_GPIO_WRITE(_sc, _off, _val) \ 135 bus_space_write_4(_sc->sc_bst, _sc->sc_bsh, _off, _val) 136 #define RK_GPIO_READ(_sc, _off) \ 137 bus_space_read_4(_sc->sc_bst, _sc->sc_bsh, _off) 138 139 static int 140 rk_gpio_read_bit(struct rk_gpio_softc *sc, int reg, int bit) 141 { 142 int offset = sc->regs[reg]; 143 uint32_t value; 144 145 if (sc->version == RK_GPIO_TYPE_V1) { 146 value = RK_GPIO_READ(sc, offset); 147 value >>= bit; 148 } else { 149 value = RK_GPIO_READ(sc, bit > 15 ? offset + 4 : offset); 150 value >>= (bit % 16); 151 } 152 return (value & 1); 153 } 154 155 static void 156 rk_gpio_write_bit(struct rk_gpio_softc *sc, int reg, int bit, int data) 157 { 158 int offset = sc->regs[reg]; 159 uint32_t value; 160 161 if (sc->version == RK_GPIO_TYPE_V1) { 162 value = RK_GPIO_READ(sc, offset); 163 if (data) 164 value |= (1 << bit); 165 else 166 value &= ~(1 << bit); 167 RK_GPIO_WRITE(sc, offset, value); 168 } else { 169 if (data) 170 value = (1 << (bit % 16)); 171 else 172 value = 0; 173 value |= (1 << ((bit % 16) + 16)); 174 RK_GPIO_WRITE(sc, bit > 15 ? offset + 4 : offset, value); 175 } 176 } 177 178 static uint32_t 179 rk_gpio_read_4(struct rk_gpio_softc *sc, int reg) 180 { 181 int offset = sc->regs[reg]; 182 uint32_t value; 183 184 if (sc->version == RK_GPIO_TYPE_V1) 185 value = RK_GPIO_READ(sc, offset); 186 else 187 value = (RK_GPIO_READ(sc, offset) & 0xffff) | 188 (RK_GPIO_READ(sc, offset + 4) << 16); 189 return (value); 190 } 191 192 static void 193 rk_gpio_write_4(struct rk_gpio_softc *sc, int reg, uint32_t value) 194 { 195 int offset = sc->regs[reg]; 196 197 if (sc->version == RK_GPIO_TYPE_V1) 198 RK_GPIO_WRITE(sc, offset, value); 199 else { 200 RK_GPIO_WRITE(sc, offset, (value & 0xffff) | 0xffff0000); 201 RK_GPIO_WRITE(sc, offset + 4, (value >> 16) | 0xffff0000); 202 } 203 } 204 205 static int 206 rk_gpio_intr(void *arg) 207 { 208 struct rk_gpio_softc *sc = (struct rk_gpio_softc *)arg;; 209 struct trapframe *tf = curthread->td_intr_frame; 210 uint32_t status; 211 212 RK_GPIO_LOCK(sc); 213 status = rk_gpio_read_4(sc, RK_GPIO_INT_STATUS); 214 rk_gpio_write_4(sc, RK_GPIO_PORTA_EOI, status); 215 RK_GPIO_UNLOCK(sc); 216 217 while (status) { 218 int pin = ffs(status) - 1; 219 220 status &= ~(1 << pin); 221 if (intr_isrc_dispatch(RK_GPIO_ISRC(sc, pin), tf)) { 222 device_printf(sc->sc_dev, "Interrupt pin=%d unhandled\n", 223 pin); 224 continue; 225 } 226 227 if ((sc->version == RK_GPIO_TYPE_V1) && 228 (sc->isrcs[pin].mode & GPIO_INTR_EDGE_BOTH)) { 229 RK_GPIO_LOCK(sc); 230 if (rk_gpio_read_bit(sc, RK_GPIO_EXT_PORTA, pin)) 231 rk_gpio_write_bit(sc, RK_GPIO_INT_POLARITY, 232 (1 << pin), 0); 233 else 234 rk_gpio_write_bit(sc, RK_GPIO_INT_POLARITY, 235 (1 << pin), 1); 236 RK_GPIO_UNLOCK(sc); 237 } 238 } 239 return (FILTER_HANDLED); 240 } 241 242 static int 243 rk_gpio_probe(device_t dev) 244 { 245 246 if (!ofw_bus_status_okay(dev)) 247 return (ENXIO); 248 249 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 250 return (ENXIO); 251 252 device_set_desc(dev, "RockChip GPIO Bank controller"); 253 return (BUS_PROBE_DEFAULT); 254 } 255 256 static int 257 rk_gpio_attach(device_t dev) 258 { 259 struct rk_gpio_softc *sc; 260 phandle_t parent_node, node; 261 int err, i; 262 263 sc = device_get_softc(dev); 264 sc->sc_dev = dev; 265 sc->pinctrl = device_get_parent(dev); 266 parent_node = ofw_bus_get_node(sc->pinctrl); 267 268 node = ofw_bus_get_node(sc->sc_dev); 269 if (!OF_hasprop(node, "gpio-controller")) 270 return (ENXIO); 271 272 mtx_init(&sc->sc_mtx, "rk gpio", "gpio", MTX_SPIN); 273 274 if (bus_alloc_resources(dev, rk_gpio_spec, sc->sc_res)) { 275 device_printf(dev, "could not allocate resources\n"); 276 bus_release_resources(dev, rk_gpio_spec, sc->sc_res); 277 mtx_destroy(&sc->sc_mtx); 278 return (ENXIO); 279 } 280 281 sc->sc_bst = rman_get_bustag(sc->sc_res[0]); 282 sc->sc_bsh = rman_get_bushandle(sc->sc_res[0]); 283 284 if (clk_get_by_ofw_index(dev, 0, 0, &sc->clk) != 0) { 285 device_printf(dev, "Cannot get clock\n"); 286 rk_gpio_detach(dev); 287 return (ENXIO); 288 } 289 err = clk_enable(sc->clk); 290 if (err != 0) { 291 device_printf(dev, "Could not enable clock %s\n", 292 clk_get_name(sc->clk)); 293 rk_gpio_detach(dev); 294 return (ENXIO); 295 } 296 297 if ((err = bus_setup_intr(dev, sc->sc_res[1], 298 INTR_TYPE_MISC | INTR_MPSAFE, rk_gpio_intr, NULL, 299 sc, &sc->ihandle))) { 300 device_printf(dev, "Can not setup IRQ\n"); 301 rk_gpio_detach(dev); 302 return (ENXIO); 303 } 304 305 /* 306 * RK3568 has GPIO_VER_ID register, however both 307 * RK3328 and RK3399 doesn't have. So choose the 308 * version based on parent's compat string. 309 */ 310 if (ofw_bus_node_is_compatible(parent_node, "rockchip,rk3568-pinctrl")) 311 sc->version = RK_GPIO_TYPE_V2; 312 else 313 sc->version = RK_GPIO_TYPE_V1; 314 315 switch (sc->version) { 316 case RK_GPIO_TYPE_V1: 317 sc->regs[RK_GPIO_SWPORTA_DR] = 0x00; 318 sc->regs[RK_GPIO_SWPORTA_DDR] = 0x04; 319 sc->regs[RK_GPIO_INTEN] = 0x30; 320 sc->regs[RK_GPIO_INTMASK] = 0x34; 321 sc->regs[RK_GPIO_INTTYPE_LEVEL] = 0x38; 322 sc->regs[RK_GPIO_INT_POLARITY] = 0x3c; 323 sc->regs[RK_GPIO_INT_STATUS] = 0x40; 324 sc->regs[RK_GPIO_INT_RAWSTATUS] = 0x44; 325 sc->regs[RK_GPIO_DEBOUNCE] = 0x48; 326 sc->regs[RK_GPIO_PORTA_EOI] = 0x4c; 327 sc->regs[RK_GPIO_EXT_PORTA] = 0x50; 328 break; 329 case RK_GPIO_TYPE_V2: 330 sc->regs[RK_GPIO_SWPORTA_DR] = 0x00; 331 sc->regs[RK_GPIO_SWPORTA_DDR] = 0x08; 332 sc->regs[RK_GPIO_INTEN] = 0x10; 333 sc->regs[RK_GPIO_INTMASK] = 0x18; 334 sc->regs[RK_GPIO_INTTYPE_LEVEL] = 0x20; 335 sc->regs[RK_GPIO_INTTYPE_BOTH] = 0x30; 336 sc->regs[RK_GPIO_INT_POLARITY] = 0x28; 337 sc->regs[RK_GPIO_INT_STATUS] = 0x50; 338 sc->regs[RK_GPIO_INT_RAWSTATUS] = 0x58; 339 sc->regs[RK_GPIO_DEBOUNCE] = 0x38; 340 sc->regs[RK_GPIO_PORTA_EOI] = 0x60; 341 sc->regs[RK_GPIO_EXT_PORTA] = 0x70; 342 break; 343 default: 344 device_printf(dev, "Unknown gpio version %08x\n", sc->version); 345 rk_gpio_detach(dev); 346 return (ENXIO); 347 } 348 349 for (i = 0; i < RK_GPIO_MAX_PINS; i++) { 350 sc->isrcs[i].irq = i; 351 sc->isrcs[i].mode = GPIO_INTR_CONFORM; 352 if ((err = intr_isrc_register(RK_GPIO_ISRC(sc, i), 353 dev, 0, "%s", device_get_nameunit(dev)))) { 354 device_printf(dev, "Can not register isrc %d\n", err); 355 rk_gpio_detach(dev); 356 return (ENXIO); 357 } 358 } 359 360 if (intr_pic_register(dev, OF_xref_from_node(node)) == NULL) { 361 device_printf(dev, "Can not register pic\n"); 362 rk_gpio_detach(dev); 363 return (ENXIO); 364 } 365 366 sc->sc_busdev = gpiobus_attach_bus(dev); 367 if (sc->sc_busdev == NULL) { 368 rk_gpio_detach(dev); 369 return (ENXIO); 370 } 371 372 /* Set the cached value to unknown */ 373 for (i = 0; i < RK_GPIO_MAX_PINS; i++) 374 sc->pin_cached[i].is_gpio = 2; 375 376 RK_GPIO_LOCK(sc); 377 sc->swporta = rk_gpio_read_4(sc, RK_GPIO_SWPORTA_DR); 378 sc->swporta_ddr = rk_gpio_read_4(sc, RK_GPIO_SWPORTA_DDR); 379 RK_GPIO_UNLOCK(sc); 380 381 return (0); 382 } 383 384 static int 385 rk_gpio_detach(device_t dev) 386 { 387 struct rk_gpio_softc *sc; 388 389 sc = device_get_softc(dev); 390 391 if (sc->sc_busdev) 392 gpiobus_detach_bus(dev); 393 bus_release_resources(dev, rk_gpio_spec, sc->sc_res); 394 mtx_destroy(&sc->sc_mtx); 395 clk_disable(sc->clk); 396 397 return(0); 398 } 399 400 static device_t 401 rk_gpio_get_bus(device_t dev) 402 { 403 struct rk_gpio_softc *sc; 404 405 sc = device_get_softc(dev); 406 407 return (sc->sc_busdev); 408 } 409 410 static int 411 rk_gpio_pin_max(device_t dev, int *maxpin) 412 { 413 414 /* Each bank have always 32 pins */ 415 /* XXX not true*/ 416 *maxpin = 31; 417 return (0); 418 } 419 420 static int 421 rk_gpio_pin_getname(device_t dev, uint32_t pin, char *name) 422 { 423 struct rk_gpio_softc *sc; 424 uint32_t bank; 425 426 sc = device_get_softc(dev); 427 428 if (pin >= 32) 429 return (EINVAL); 430 431 bank = pin / 8; 432 pin = pin - (bank * 8); 433 RK_GPIO_LOCK(sc); 434 snprintf(name, GPIOMAXNAME, "P%c%d", bank + 'A', pin); 435 RK_GPIO_UNLOCK(sc); 436 437 return (0); 438 } 439 440 static int 441 rk_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags) 442 { 443 struct rk_gpio_softc *sc; 444 int rv; 445 446 sc = device_get_softc(dev); 447 448 if (__predict_false(sc->pin_cached[pin].is_gpio != 1)) { 449 rv = FDT_PINCTRL_IS_GPIO(sc->pinctrl, dev, pin, (bool *)&sc->pin_cached[pin].is_gpio); 450 if (rv != 0) 451 return (rv); 452 if (sc->pin_cached[pin].is_gpio == 0) 453 return (EINVAL); 454 } 455 *flags = 0; 456 rv = FDT_PINCTRL_GET_FLAGS(sc->pinctrl, dev, pin, flags); 457 if (rv != 0) 458 return (rv); 459 sc->pin_cached[pin].flags = *flags; 460 461 if (sc->swporta_ddr & (1 << pin)) 462 *flags |= GPIO_PIN_OUTPUT; 463 else 464 *flags |= GPIO_PIN_INPUT; 465 466 return (0); 467 } 468 469 static int 470 rk_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps) 471 { 472 473 if (pin >= RK_GPIO_MAX_PINS) 474 return EINVAL; 475 476 *caps = RK_GPIO_DEFAULT_CAPS; 477 return (0); 478 } 479 480 static int 481 rk_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags) 482 { 483 struct rk_gpio_softc *sc; 484 int rv; 485 486 sc = device_get_softc(dev); 487 488 if (pin >= RK_GPIO_MAX_PINS) 489 return (EINVAL); 490 491 if (__predict_false(sc->pin_cached[pin].is_gpio != 1)) { 492 rv = FDT_PINCTRL_IS_GPIO(sc->pinctrl, dev, pin, (bool *)&sc->pin_cached[pin].is_gpio); 493 if (rv != 0) 494 return (rv); 495 if (sc->pin_cached[pin].is_gpio == 0) 496 return (EINVAL); 497 } 498 499 if (__predict_false((flags & GPIO_PIN_INPUT) && ((flags & GPIO_FLAGS_PINCTRL) != sc->pin_cached[pin].flags))) { 500 rv = FDT_PINCTRL_SET_FLAGS(sc->pinctrl, dev, pin, flags); 501 sc->pin_cached[pin].flags = flags & GPIO_FLAGS_PINCTRL; 502 if (rv != 0) 503 return (rv); 504 } 505 506 RK_GPIO_LOCK(sc); 507 if (flags & GPIO_PIN_INPUT) 508 sc->swporta_ddr &= ~(1 << pin); 509 else if (flags & GPIO_PIN_OUTPUT) 510 sc->swporta_ddr |= (1 << pin); 511 512 rk_gpio_write_4(sc, RK_GPIO_SWPORTA_DDR, sc->swporta_ddr); 513 RK_GPIO_UNLOCK(sc); 514 515 return (0); 516 } 517 518 static int 519 rk_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val) 520 { 521 struct rk_gpio_softc *sc; 522 523 sc = device_get_softc(dev); 524 525 if (pin >= RK_GPIO_MAX_PINS) 526 return (EINVAL); 527 528 RK_GPIO_LOCK(sc); 529 *val = rk_gpio_read_bit(sc, RK_GPIO_EXT_PORTA, pin); 530 RK_GPIO_UNLOCK(sc); 531 532 return (0); 533 } 534 535 static int 536 rk_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value) 537 { 538 struct rk_gpio_softc *sc; 539 540 sc = device_get_softc(dev); 541 542 if (pin >= RK_GPIO_MAX_PINS) 543 return (EINVAL); 544 545 RK_GPIO_LOCK(sc); 546 if (value) 547 sc->swporta |= (1 << pin); 548 else 549 sc->swporta &= ~(1 << pin); 550 rk_gpio_write_4(sc, RK_GPIO_SWPORTA_DR, sc->swporta); 551 RK_GPIO_UNLOCK(sc); 552 553 return (0); 554 } 555 556 static int 557 rk_gpio_pin_toggle(device_t dev, uint32_t pin) 558 { 559 struct rk_gpio_softc *sc; 560 561 sc = device_get_softc(dev); 562 563 if (pin >= RK_GPIO_MAX_PINS) 564 return (EINVAL); 565 566 RK_GPIO_LOCK(sc); 567 if (sc->swporta & (1 << pin)) 568 sc->swporta &= ~(1 << pin); 569 else 570 sc->swporta |= (1 << pin); 571 rk_gpio_write_4(sc, RK_GPIO_SWPORTA_DR, sc->swporta); 572 RK_GPIO_UNLOCK(sc); 573 574 return (0); 575 } 576 577 static int 578 rk_gpio_pin_access_32(device_t dev, uint32_t first_pin, uint32_t clear_pins, 579 uint32_t change_pins, uint32_t *orig_pins) 580 { 581 struct rk_gpio_softc *sc; 582 uint32_t reg; 583 584 sc = device_get_softc(dev); 585 586 RK_GPIO_LOCK(sc); 587 reg = rk_gpio_read_4(sc, RK_GPIO_SWPORTA_DR); 588 if (orig_pins) 589 *orig_pins = reg; 590 sc->swporta = reg; 591 592 if ((clear_pins | change_pins) != 0) { 593 reg = (reg & ~clear_pins) ^ change_pins; 594 rk_gpio_write_4(sc, RK_GPIO_SWPORTA_DR, reg); 595 } 596 RK_GPIO_UNLOCK(sc); 597 598 return (0); 599 } 600 601 static int 602 rk_gpio_pin_config_32(device_t dev, uint32_t first_pin, uint32_t num_pins, 603 uint32_t *pin_flags) 604 { 605 struct rk_gpio_softc *sc; 606 uint32_t reg, set, mask, flags; 607 int i; 608 609 sc = device_get_softc(dev); 610 611 if (first_pin != 0 || num_pins > 32) 612 return (EINVAL); 613 614 set = 0; 615 mask = 0; 616 for (i = 0; i < num_pins; i++) { 617 mask = (mask << 1) | 1; 618 flags = pin_flags[i]; 619 if (flags & GPIO_PIN_INPUT) { 620 set &= ~(1 << i); 621 } else if (flags & GPIO_PIN_OUTPUT) { 622 set |= (1 << i); 623 } 624 } 625 626 RK_GPIO_LOCK(sc); 627 reg = rk_gpio_read_4(sc, RK_GPIO_SWPORTA_DDR); 628 reg &= ~mask; 629 reg |= set; 630 rk_gpio_write_4(sc, RK_GPIO_SWPORTA_DDR, reg); 631 sc->swporta_ddr = reg; 632 RK_GPIO_UNLOCK(sc); 633 634 return (0); 635 } 636 637 static int 638 rk_gpio_map_gpios(device_t bus, phandle_t dev, phandle_t gparent, int gcells, 639 pcell_t *gpios, uint32_t *pin, uint32_t *flags) 640 { 641 642 /* The gpios are mapped as <pin flags> */ 643 *pin = gpios[0]; 644 *flags = gpios[1]; 645 return (0); 646 } 647 648 static phandle_t 649 rk_gpio_get_node(device_t bus, device_t dev) 650 { 651 652 /* We only have one child, the GPIO bus, which needs our own node. */ 653 return (ofw_bus_get_node(bus)); 654 } 655 656 static int 657 rk_pic_map_intr(device_t dev, struct intr_map_data *data, 658 struct intr_irqsrc **isrcp) 659 { 660 struct rk_gpio_softc *sc = device_get_softc(dev); 661 struct intr_map_data_gpio *gdata; 662 uint32_t irq; 663 664 if (data->type != INTR_MAP_DATA_GPIO) { 665 device_printf(dev, "Wrong type\n"); 666 return (ENOTSUP); 667 } 668 gdata = (struct intr_map_data_gpio *)data; 669 irq = gdata->gpio_pin_num; 670 if (irq >= RK_GPIO_MAX_PINS) { 671 device_printf(dev, "Invalid interrupt %u\n", irq); 672 return (EINVAL); 673 } 674 *isrcp = RK_GPIO_ISRC(sc, irq); 675 return (0); 676 } 677 678 static int 679 rk_pic_setup_intr(device_t dev, struct intr_irqsrc *isrc, 680 struct resource *res, struct intr_map_data *data) 681 { 682 struct rk_gpio_softc *sc = device_get_softc(dev); 683 struct rk_pin_irqsrc *rkisrc = (struct rk_pin_irqsrc *)isrc; 684 struct intr_map_data_gpio *gdata; 685 uint32_t mode; 686 uint8_t pin; 687 688 if (!data) { 689 device_printf(dev, "No map data\n"); 690 return (ENOTSUP); 691 } 692 gdata = (struct intr_map_data_gpio *)data; 693 mode = gdata->gpio_intr_mode; 694 pin = gdata->gpio_pin_num; 695 696 if (rkisrc->irq != gdata->gpio_pin_num) { 697 device_printf(dev, "Interrupts don't match\n"); 698 return (EINVAL); 699 } 700 701 if (isrc->isrc_handlers != 0) { 702 device_printf(dev, "Handler already attached\n"); 703 return (rkisrc->mode == mode ? 0 : EINVAL); 704 } 705 rkisrc->mode = mode; 706 707 RK_GPIO_LOCK(sc); 708 709 switch (mode & GPIO_INTR_MASK) { 710 case GPIO_INTR_EDGE_RISING: 711 rk_gpio_write_bit(sc, RK_GPIO_SWPORTA_DDR, pin, 0); 712 rk_gpio_write_bit(sc, RK_GPIO_INTTYPE_LEVEL, pin, 1); 713 rk_gpio_write_bit(sc, RK_GPIO_INT_POLARITY, pin, 1); 714 break; 715 case GPIO_INTR_EDGE_FALLING: 716 rk_gpio_write_bit(sc, RK_GPIO_SWPORTA_DDR, pin, 0); 717 rk_gpio_write_bit(sc, RK_GPIO_INTTYPE_LEVEL, pin, 1); 718 rk_gpio_write_bit(sc, RK_GPIO_INT_POLARITY, pin, 0); 719 break; 720 case GPIO_INTR_EDGE_BOTH: 721 rk_gpio_write_bit(sc, RK_GPIO_SWPORTA_DDR, pin, 0); 722 rk_gpio_write_bit(sc, RK_GPIO_INTTYPE_LEVEL, pin, 1); 723 if (sc->version == RK_GPIO_TYPE_V1) { 724 if (rk_gpio_read_bit(sc, RK_GPIO_EXT_PORTA, pin)) 725 rk_gpio_write_bit(sc, RK_GPIO_INT_POLARITY, 726 pin, 0); 727 else 728 rk_gpio_write_bit(sc, RK_GPIO_INT_POLARITY, 729 pin, 1); 730 } else 731 rk_gpio_write_bit(sc, RK_GPIO_INTTYPE_BOTH, pin, 1); 732 break; 733 case GPIO_INTR_LEVEL_HIGH: 734 rk_gpio_write_bit(sc, RK_GPIO_SWPORTA_DDR, pin, 0); 735 rk_gpio_write_bit(sc, RK_GPIO_INTTYPE_LEVEL, pin, 0); 736 rk_gpio_write_bit(sc, RK_GPIO_INT_POLARITY, pin, 1); 737 break; 738 case GPIO_INTR_LEVEL_LOW: 739 rk_gpio_write_bit(sc, RK_GPIO_SWPORTA_DDR, pin, 0); 740 rk_gpio_write_bit(sc, RK_GPIO_INTTYPE_LEVEL, pin, 0); 741 rk_gpio_write_bit(sc, RK_GPIO_INT_POLARITY, pin, 0); 742 break; 743 default: 744 rk_gpio_write_bit(sc, RK_GPIO_INTMASK, pin, 1); 745 rk_gpio_write_bit(sc, RK_GPIO_INTEN, pin, 0); 746 RK_GPIO_UNLOCK(sc); 747 return (EINVAL); 748 } 749 rk_gpio_write_bit(sc, RK_GPIO_DEBOUNCE, pin, 1); 750 rk_gpio_write_bit(sc, RK_GPIO_INTMASK, pin, 0); 751 rk_gpio_write_bit(sc, RK_GPIO_INTEN, pin, 1); 752 RK_GPIO_UNLOCK(sc); 753 754 return (0); 755 } 756 757 static int 758 rk_pic_teardown_intr(device_t dev, struct intr_irqsrc *isrc, 759 struct resource *res, struct intr_map_data *data) 760 { 761 struct rk_gpio_softc *sc = device_get_softc(dev); 762 struct rk_pin_irqsrc *irqsrc; 763 764 irqsrc = (struct rk_pin_irqsrc *)isrc; 765 766 if (isrc->isrc_handlers == 0) { 767 irqsrc->mode = GPIO_INTR_CONFORM; 768 RK_GPIO_LOCK(sc); 769 rk_gpio_write_bit(sc, RK_GPIO_INTEN, irqsrc->irq, 0); 770 rk_gpio_write_bit(sc, RK_GPIO_INTMASK, irqsrc->irq, 0); 771 rk_gpio_write_bit(sc, RK_GPIO_DEBOUNCE, irqsrc->irq, 0); 772 RK_GPIO_UNLOCK(sc); 773 } 774 return (0); 775 } 776 777 static device_method_t rk_gpio_methods[] = { 778 /* Device interface */ 779 DEVMETHOD(device_probe, rk_gpio_probe), 780 DEVMETHOD(device_attach, rk_gpio_attach), 781 DEVMETHOD(device_detach, rk_gpio_detach), 782 783 /* GPIO protocol */ 784 DEVMETHOD(gpio_get_bus, rk_gpio_get_bus), 785 DEVMETHOD(gpio_pin_max, rk_gpio_pin_max), 786 DEVMETHOD(gpio_pin_getname, rk_gpio_pin_getname), 787 DEVMETHOD(gpio_pin_getflags, rk_gpio_pin_getflags), 788 DEVMETHOD(gpio_pin_getcaps, rk_gpio_pin_getcaps), 789 DEVMETHOD(gpio_pin_setflags, rk_gpio_pin_setflags), 790 DEVMETHOD(gpio_pin_get, rk_gpio_pin_get), 791 DEVMETHOD(gpio_pin_set, rk_gpio_pin_set), 792 DEVMETHOD(gpio_pin_toggle, rk_gpio_pin_toggle), 793 DEVMETHOD(gpio_pin_access_32, rk_gpio_pin_access_32), 794 DEVMETHOD(gpio_pin_config_32, rk_gpio_pin_config_32), 795 DEVMETHOD(gpio_map_gpios, rk_gpio_map_gpios), 796 797 /* Interrupt controller interface */ 798 DEVMETHOD(pic_map_intr, rk_pic_map_intr), 799 DEVMETHOD(pic_setup_intr, rk_pic_setup_intr), 800 DEVMETHOD(pic_teardown_intr, rk_pic_teardown_intr), 801 802 /* ofw_bus interface */ 803 DEVMETHOD(ofw_bus_get_node, rk_gpio_get_node), 804 805 DEVMETHOD_END 806 }; 807 808 static driver_t rk_gpio_driver = { 809 "gpio", 810 rk_gpio_methods, 811 sizeof(struct rk_gpio_softc), 812 }; 813 814 /* 815 * GPIO driver is always a child of rk_pinctrl driver and should be probed 816 * and attached within rk_pinctrl_attach function. Due to this, bus pass order 817 * must be same as bus pass order of rk_pinctrl driver. 818 */ 819 EARLY_DRIVER_MODULE(rk_gpio, simplebus, rk_gpio_driver, 0, 0, 820 BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE); 821