1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2018 Emmanuel Vadot <manu@FreeBSD.org> 5 * Copyright (c) 2021 Soren Schmidt <sos@deepcore.dk> 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 */ 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/bus.h> 33 34 #include <sys/kernel.h> 35 #include <sys/module.h> 36 #include <sys/proc.h> 37 #include <sys/rman.h> 38 #include <sys/lock.h> 39 #include <sys/mutex.h> 40 #include <sys/gpio.h> 41 42 #include <machine/bus.h> 43 #include <machine/resource.h> 44 #include <machine/intr.h> 45 46 #include <dev/gpio/gpiobusvar.h> 47 #include <dev/ofw/ofw_bus.h> 48 #include <dev/ofw/ofw_bus_subr.h> 49 #include <dev/clk/clk.h> 50 51 #include "gpio_if.h" 52 #include "pic_if.h" 53 54 #include "fdt_pinctrl_if.h" 55 56 enum gpio_regs { 57 RK_GPIO_SWPORTA_DR = 1, /* Data register */ 58 RK_GPIO_SWPORTA_DDR, /* Data direction register */ 59 RK_GPIO_INTEN, /* Interrupt enable register */ 60 RK_GPIO_INTMASK, /* Interrupt mask register */ 61 RK_GPIO_INTTYPE_LEVEL, /* Interrupt level register */ 62 RK_GPIO_INTTYPE_BOTH, /* Both rise and falling edge */ 63 RK_GPIO_INT_POLARITY, /* Interrupt polarity register */ 64 RK_GPIO_INT_STATUS, /* Interrupt status register */ 65 RK_GPIO_INT_RAWSTATUS, /* Raw Interrupt status register */ 66 RK_GPIO_DEBOUNCE, /* Debounce enable register */ 67 RK_GPIO_PORTA_EOI, /* Clear interrupt register */ 68 RK_GPIO_EXT_PORTA, /* External port register */ 69 RK_GPIO_REGNUM 70 }; 71 72 #define RK_GPIO_LS_SYNC 0x60 /* Level sensitive syncronization enable register */ 73 74 #define RK_GPIO_DEFAULT_CAPS (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | \ 75 GPIO_PIN_PULLUP | GPIO_PIN_PULLDOWN | GPIO_INTR_EDGE_BOTH | \ 76 GPIO_INTR_EDGE_RISING | GPIO_INTR_EDGE_FALLING | \ 77 GPIO_INTR_LEVEL_HIGH | GPIO_INTR_LEVEL_LOW) 78 79 #define GPIO_FLAGS_PINCTRL (GPIO_PIN_PULLUP | GPIO_PIN_PULLDOWN) 80 #define RK_GPIO_MAX_PINS 32 81 82 struct pin_cached { 83 uint8_t is_gpio; 84 uint32_t flags; 85 }; 86 87 struct rk_pin_irqsrc { 88 struct intr_irqsrc isrc; 89 uint32_t irq; 90 uint32_t mode; 91 }; 92 93 struct rk_gpio_reg { 94 uint8_t single; 95 uint8_t offset; 96 }; 97 98 struct rk_gpio_softc { 99 device_t sc_dev; 100 device_t sc_busdev; 101 struct mtx sc_mtx; 102 struct resource *sc_res[2]; 103 bus_space_tag_t sc_bst; 104 bus_space_handle_t sc_bsh; 105 clk_t clk; 106 device_t pinctrl; 107 uint32_t swporta; 108 uint32_t swporta_ddr; 109 uint32_t version; 110 struct pin_cached pin_cached[RK_GPIO_MAX_PINS]; 111 struct rk_gpio_reg regs[RK_GPIO_REGNUM]; 112 void *ihandle; 113 struct rk_pin_irqsrc isrcs[RK_GPIO_MAX_PINS]; 114 }; 115 116 static struct ofw_compat_data compat_data[] = { 117 {"rockchip,gpio-bank", 1}, 118 {NULL, 0} 119 }; 120 121 static struct resource_spec rk_gpio_spec[] = { 122 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 123 { SYS_RES_IRQ, 0, RF_ACTIVE }, 124 { -1, 0 } 125 }; 126 127 #define RK_GPIO_VERSION 0x78 128 #define RK_GPIO_TYPE_V1 0x00000000 129 #define RK_GPIO_TYPE_V2 0x01000c2b 130 #define RK_GPIO_ISRC(sc, irq) (&(sc->isrcs[irq].isrc)) 131 132 static int rk_gpio_detach(device_t dev); 133 134 #define RK_GPIO_LOCK(_sc) mtx_lock_spin(&(_sc)->sc_mtx) 135 #define RK_GPIO_UNLOCK(_sc) mtx_unlock_spin(&(_sc)->sc_mtx) 136 #define RK_GPIO_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) 137 138 #define RK_GPIO_WRITE(_sc, _off, _val) \ 139 bus_space_write_4(_sc->sc_bst, _sc->sc_bsh, _off, _val) 140 #define RK_GPIO_READ(_sc, _off) \ 141 bus_space_read_4(_sc->sc_bst, _sc->sc_bsh, _off) 142 143 static int 144 rk_gpio_read_bit(struct rk_gpio_softc *sc, int reg, int bit) 145 { 146 struct rk_gpio_reg *rk_reg = &sc->regs[reg]; 147 uint32_t value; 148 149 if (rk_reg->single) { 150 value = RK_GPIO_READ(sc, rk_reg->offset); 151 value >>= bit; 152 } else { 153 value = RK_GPIO_READ(sc, bit > 15 ? 154 rk_reg->offset + 4 : rk_reg->offset); 155 value >>= (bit % 16); 156 } 157 return (value & 1); 158 } 159 160 static void 161 rk_gpio_write_bit(struct rk_gpio_softc *sc, int reg, int bit, int data) 162 { 163 struct rk_gpio_reg *rk_reg = &sc->regs[reg]; 164 uint32_t value; 165 166 if (rk_reg->single) { 167 value = RK_GPIO_READ(sc, rk_reg->offset); 168 if (data) 169 value |= (1 << bit); 170 else 171 value &= ~(1 << bit); 172 RK_GPIO_WRITE(sc, rk_reg->offset, value); 173 } else { 174 if (data) 175 value = (1 << (bit % 16)); 176 else 177 value = 0; 178 value |= (1 << ((bit % 16) + 16)); 179 RK_GPIO_WRITE(sc, bit > 15 ? 180 rk_reg->offset + 4 : rk_reg->offset, value); 181 } 182 } 183 184 static uint32_t 185 rk_gpio_read_4(struct rk_gpio_softc *sc, int reg) 186 { 187 struct rk_gpio_reg *rk_reg = &sc->regs[reg]; 188 uint32_t value; 189 190 if (rk_reg->single) 191 value = RK_GPIO_READ(sc, rk_reg->offset); 192 else 193 value = (RK_GPIO_READ(sc, rk_reg->offset) & 0xffff) | 194 (RK_GPIO_READ(sc, rk_reg->offset + 4) << 16); 195 return (value); 196 } 197 198 static void 199 rk_gpio_write_4(struct rk_gpio_softc *sc, int reg, uint32_t value) 200 { 201 struct rk_gpio_reg *rk_reg = &sc->regs[reg]; 202 203 if (rk_reg->single) 204 RK_GPIO_WRITE(sc, rk_reg->offset, value); 205 else { 206 RK_GPIO_WRITE(sc, rk_reg->offset, 207 (value & 0xffff) | 0xffff0000); 208 RK_GPIO_WRITE(sc, rk_reg->offset + 4, 209 (value >> 16) | 0xffff0000); 210 } 211 } 212 213 static int 214 rk_gpio_intr(void *arg) 215 { 216 struct rk_gpio_softc *sc = (struct rk_gpio_softc *)arg; 217 struct trapframe *tf = curthread->td_intr_frame; 218 uint32_t status; 219 220 RK_GPIO_LOCK(sc); 221 status = rk_gpio_read_4(sc, RK_GPIO_INT_STATUS); 222 rk_gpio_write_4(sc, RK_GPIO_PORTA_EOI, status); 223 RK_GPIO_UNLOCK(sc); 224 225 while (status) { 226 int pin = ffs(status) - 1; 227 228 status &= ~(1 << pin); 229 if (intr_isrc_dispatch(RK_GPIO_ISRC(sc, pin), tf)) { 230 device_printf(sc->sc_dev, "Interrupt pin=%d unhandled\n", 231 pin); 232 continue; 233 } 234 235 if ((sc->version == RK_GPIO_TYPE_V1) && 236 (sc->isrcs[pin].mode & GPIO_INTR_EDGE_BOTH)) { 237 RK_GPIO_LOCK(sc); 238 if (rk_gpio_read_bit(sc, RK_GPIO_EXT_PORTA, pin)) 239 rk_gpio_write_bit(sc, RK_GPIO_INT_POLARITY, 240 (1 << pin), 0); 241 else 242 rk_gpio_write_bit(sc, RK_GPIO_INT_POLARITY, 243 (1 << pin), 1); 244 RK_GPIO_UNLOCK(sc); 245 } 246 } 247 return (FILTER_HANDLED); 248 } 249 250 static int 251 rk_gpio_probe(device_t dev) 252 { 253 254 if (!ofw_bus_status_okay(dev)) 255 return (ENXIO); 256 257 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 258 return (ENXIO); 259 260 device_set_desc(dev, "RockChip GPIO Bank controller"); 261 return (BUS_PROBE_DEFAULT); 262 } 263 264 static int 265 rk_gpio_attach(device_t dev) 266 { 267 struct rk_gpio_softc *sc; 268 phandle_t parent_node, node; 269 int err, i; 270 271 sc = device_get_softc(dev); 272 sc->sc_dev = dev; 273 sc->pinctrl = device_get_parent(dev); 274 parent_node = ofw_bus_get_node(sc->pinctrl); 275 276 node = ofw_bus_get_node(sc->sc_dev); 277 if (!OF_hasprop(node, "gpio-controller")) 278 return (ENXIO); 279 280 mtx_init(&sc->sc_mtx, "rk gpio", "gpio", MTX_SPIN); 281 282 if (bus_alloc_resources(dev, rk_gpio_spec, sc->sc_res)) { 283 device_printf(dev, "could not allocate resources\n"); 284 bus_release_resources(dev, rk_gpio_spec, sc->sc_res); 285 mtx_destroy(&sc->sc_mtx); 286 return (ENXIO); 287 } 288 289 sc->sc_bst = rman_get_bustag(sc->sc_res[0]); 290 sc->sc_bsh = rman_get_bushandle(sc->sc_res[0]); 291 292 if (clk_get_by_ofw_index(dev, 0, 0, &sc->clk) != 0) { 293 device_printf(dev, "Cannot get clock\n"); 294 rk_gpio_detach(dev); 295 return (ENXIO); 296 } 297 err = clk_enable(sc->clk); 298 if (err != 0) { 299 device_printf(dev, "Could not enable clock %s\n", 300 clk_get_name(sc->clk)); 301 rk_gpio_detach(dev); 302 return (ENXIO); 303 } 304 305 if ((err = bus_setup_intr(dev, sc->sc_res[1], 306 INTR_TYPE_MISC | INTR_MPSAFE, rk_gpio_intr, NULL, 307 sc, &sc->ihandle))) { 308 device_printf(dev, "Can not setup IRQ\n"); 309 rk_gpio_detach(dev); 310 return (ENXIO); 311 } 312 313 /* 314 * RK3568 has GPIO_VER_ID register, however both 315 * RK3328 and RK3399 doesn't have. So choose the 316 * version based on parent's compat string. 317 */ 318 if (ofw_bus_node_is_compatible(parent_node, "rockchip,rk3568-pinctrl")) 319 sc->version = RK_GPIO_TYPE_V2; 320 else 321 sc->version = RK_GPIO_TYPE_V1; 322 323 switch (sc->version) { 324 case RK_GPIO_TYPE_V1: 325 sc->regs[RK_GPIO_SWPORTA_DR] = (struct rk_gpio_reg){ 1, 0x00 }; 326 sc->regs[RK_GPIO_SWPORTA_DDR] = (struct rk_gpio_reg){ 1, 0x04 }; 327 sc->regs[RK_GPIO_INTEN] = (struct rk_gpio_reg){ 1, 0x30 }; 328 sc->regs[RK_GPIO_INTMASK] = (struct rk_gpio_reg){ 1, 0x34 }; 329 sc->regs[RK_GPIO_INTTYPE_LEVEL] = (struct rk_gpio_reg){ 1, 0x38 }; 330 sc->regs[RK_GPIO_INT_POLARITY] = (struct rk_gpio_reg){ 1, 0x3c }; 331 sc->regs[RK_GPIO_INT_STATUS] = (struct rk_gpio_reg){ 1, 0x40 }; 332 sc->regs[RK_GPIO_INT_RAWSTATUS] = (struct rk_gpio_reg){ 1, 0x44 }; 333 sc->regs[RK_GPIO_DEBOUNCE] = (struct rk_gpio_reg){ 1, 0x48 }; 334 sc->regs[RK_GPIO_PORTA_EOI] = (struct rk_gpio_reg){ 1, 0x4c }; 335 sc->regs[RK_GPIO_EXT_PORTA] = (struct rk_gpio_reg){ 1, 0x50 }; 336 break; 337 case RK_GPIO_TYPE_V2: 338 sc->regs[RK_GPIO_SWPORTA_DR] = (struct rk_gpio_reg){ 0, 0x00 }; 339 sc->regs[RK_GPIO_SWPORTA_DDR] = (struct rk_gpio_reg){ 0, 0x08 }; 340 sc->regs[RK_GPIO_INTEN] = (struct rk_gpio_reg){ 0, 0x10 }; 341 sc->regs[RK_GPIO_INTMASK] = (struct rk_gpio_reg){ 0, 0x18 }; 342 sc->regs[RK_GPIO_INTTYPE_LEVEL] = (struct rk_gpio_reg){ 0, 0x20 }; 343 sc->regs[RK_GPIO_INTTYPE_BOTH] = (struct rk_gpio_reg){ 0, 0x30 }; 344 sc->regs[RK_GPIO_INT_POLARITY] = (struct rk_gpio_reg){ 0, 0x28 }; 345 sc->regs[RK_GPIO_INT_STATUS] = (struct rk_gpio_reg){ 1, 0x50 }; 346 sc->regs[RK_GPIO_INT_RAWSTATUS] = (struct rk_gpio_reg){ 1, 0x58 }; 347 sc->regs[RK_GPIO_DEBOUNCE] = (struct rk_gpio_reg){ 0, 0x38 }; 348 sc->regs[RK_GPIO_PORTA_EOI] = (struct rk_gpio_reg){ 0, 0x60 }; 349 sc->regs[RK_GPIO_EXT_PORTA] = (struct rk_gpio_reg){ 1, 0x70 }; 350 break; 351 default: 352 device_printf(dev, "Unknown gpio version %08x\n", sc->version); 353 rk_gpio_detach(dev); 354 return (ENXIO); 355 } 356 357 for (i = 0; i < RK_GPIO_MAX_PINS; i++) { 358 sc->isrcs[i].irq = i; 359 sc->isrcs[i].mode = GPIO_INTR_CONFORM; 360 if ((err = intr_isrc_register(RK_GPIO_ISRC(sc, i), 361 dev, 0, "%s", device_get_nameunit(dev)))) { 362 device_printf(dev, "Can not register isrc %d\n", err); 363 rk_gpio_detach(dev); 364 return (ENXIO); 365 } 366 } 367 368 if (intr_pic_register(dev, OF_xref_from_node(node)) == NULL) { 369 device_printf(dev, "Can not register pic\n"); 370 rk_gpio_detach(dev); 371 return (ENXIO); 372 } 373 374 /* Set the cached value to unknown */ 375 for (i = 0; i < RK_GPIO_MAX_PINS; i++) 376 sc->pin_cached[i].is_gpio = 2; 377 378 RK_GPIO_LOCK(sc); 379 sc->swporta = rk_gpio_read_4(sc, RK_GPIO_SWPORTA_DR); 380 sc->swporta_ddr = rk_gpio_read_4(sc, RK_GPIO_SWPORTA_DDR); 381 RK_GPIO_UNLOCK(sc); 382 383 sc->sc_busdev = gpiobus_add_bus(dev); 384 if (sc->sc_busdev == NULL) { 385 rk_gpio_detach(dev); 386 return (ENXIO); 387 } 388 389 bus_attach_children(dev); 390 return (0); 391 } 392 393 static int 394 rk_gpio_detach(device_t dev) 395 { 396 struct rk_gpio_softc *sc; 397 398 sc = device_get_softc(dev); 399 400 if (sc->sc_busdev) 401 gpiobus_detach_bus(dev); 402 bus_release_resources(dev, rk_gpio_spec, sc->sc_res); 403 mtx_destroy(&sc->sc_mtx); 404 clk_disable(sc->clk); 405 406 return (0); 407 } 408 409 static device_t 410 rk_gpio_get_bus(device_t dev) 411 { 412 struct rk_gpio_softc *sc; 413 414 sc = device_get_softc(dev); 415 416 return (sc->sc_busdev); 417 } 418 419 static int 420 rk_gpio_pin_max(device_t dev, int *maxpin) 421 { 422 423 /* Each bank have always 32 pins */ 424 /* XXX not true*/ 425 *maxpin = 31; 426 return (0); 427 } 428 429 static int 430 rk_gpio_pin_getname(device_t dev, uint32_t pin, char *name) 431 { 432 struct rk_gpio_softc *sc; 433 uint32_t bank; 434 435 sc = device_get_softc(dev); 436 437 if (pin >= 32) 438 return (EINVAL); 439 440 bank = pin / 8; 441 pin = pin - (bank * 8); 442 RK_GPIO_LOCK(sc); 443 snprintf(name, GPIOMAXNAME, "P%c%d", bank + 'A', pin); 444 RK_GPIO_UNLOCK(sc); 445 446 return (0); 447 } 448 449 static int 450 rk_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags) 451 { 452 struct rk_gpio_softc *sc; 453 int rv; 454 455 sc = device_get_softc(dev); 456 457 if (__predict_false(sc->pin_cached[pin].is_gpio != 1)) { 458 rv = FDT_PINCTRL_IS_GPIO(sc->pinctrl, dev, pin, (bool *)&sc->pin_cached[pin].is_gpio); 459 if (rv != 0) 460 return (rv); 461 if (sc->pin_cached[pin].is_gpio == 0) 462 return (EINVAL); 463 } 464 *flags = 0; 465 rv = FDT_PINCTRL_GET_FLAGS(sc->pinctrl, dev, pin, flags); 466 if (rv != 0) 467 return (rv); 468 sc->pin_cached[pin].flags = *flags; 469 470 if (sc->swporta_ddr & (1 << pin)) 471 *flags |= GPIO_PIN_OUTPUT; 472 else 473 *flags |= GPIO_PIN_INPUT; 474 475 return (0); 476 } 477 478 static int 479 rk_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps) 480 { 481 482 if (pin >= RK_GPIO_MAX_PINS) 483 return (EINVAL); 484 485 *caps = RK_GPIO_DEFAULT_CAPS; 486 return (0); 487 } 488 489 static int 490 rk_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags) 491 { 492 struct rk_gpio_softc *sc; 493 int rv; 494 495 sc = device_get_softc(dev); 496 497 if (pin >= RK_GPIO_MAX_PINS) 498 return (EINVAL); 499 500 if (__predict_false(sc->pin_cached[pin].is_gpio != 1)) { 501 rv = FDT_PINCTRL_IS_GPIO(sc->pinctrl, dev, pin, (bool *)&sc->pin_cached[pin].is_gpio); 502 if (rv != 0) 503 return (rv); 504 if (sc->pin_cached[pin].is_gpio == 0) 505 return (EINVAL); 506 } 507 508 if (__predict_false((flags & GPIO_PIN_INPUT) && ((flags & GPIO_FLAGS_PINCTRL) != sc->pin_cached[pin].flags))) { 509 rv = FDT_PINCTRL_SET_FLAGS(sc->pinctrl, dev, pin, flags); 510 sc->pin_cached[pin].flags = flags & GPIO_FLAGS_PINCTRL; 511 if (rv != 0) 512 return (rv); 513 } 514 515 RK_GPIO_LOCK(sc); 516 if (flags & GPIO_PIN_INPUT) 517 sc->swporta_ddr &= ~(1 << pin); 518 else if (flags & GPIO_PIN_OUTPUT) 519 sc->swporta_ddr |= (1 << pin); 520 521 rk_gpio_write_4(sc, RK_GPIO_SWPORTA_DDR, sc->swporta_ddr); 522 RK_GPIO_UNLOCK(sc); 523 524 return (0); 525 } 526 527 static int 528 rk_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val) 529 { 530 struct rk_gpio_softc *sc; 531 532 sc = device_get_softc(dev); 533 534 if (pin >= RK_GPIO_MAX_PINS) 535 return (EINVAL); 536 537 RK_GPIO_LOCK(sc); 538 *val = rk_gpio_read_bit(sc, RK_GPIO_EXT_PORTA, pin); 539 RK_GPIO_UNLOCK(sc); 540 541 return (0); 542 } 543 544 static int 545 rk_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value) 546 { 547 struct rk_gpio_softc *sc; 548 549 sc = device_get_softc(dev); 550 551 if (pin >= RK_GPIO_MAX_PINS) 552 return (EINVAL); 553 554 RK_GPIO_LOCK(sc); 555 if (value) 556 sc->swporta |= (1 << pin); 557 else 558 sc->swporta &= ~(1 << pin); 559 rk_gpio_write_4(sc, RK_GPIO_SWPORTA_DR, sc->swporta); 560 RK_GPIO_UNLOCK(sc); 561 562 return (0); 563 } 564 565 static int 566 rk_gpio_pin_toggle(device_t dev, uint32_t pin) 567 { 568 struct rk_gpio_softc *sc; 569 570 sc = device_get_softc(dev); 571 572 if (pin >= RK_GPIO_MAX_PINS) 573 return (EINVAL); 574 575 RK_GPIO_LOCK(sc); 576 if (sc->swporta & (1 << pin)) 577 sc->swporta &= ~(1 << pin); 578 else 579 sc->swporta |= (1 << pin); 580 rk_gpio_write_4(sc, RK_GPIO_SWPORTA_DR, sc->swporta); 581 RK_GPIO_UNLOCK(sc); 582 583 return (0); 584 } 585 586 static int 587 rk_gpio_pin_access_32(device_t dev, uint32_t first_pin, uint32_t clear_pins, 588 uint32_t change_pins, uint32_t *orig_pins) 589 { 590 struct rk_gpio_softc *sc; 591 uint32_t reg; 592 593 sc = device_get_softc(dev); 594 595 RK_GPIO_LOCK(sc); 596 reg = rk_gpio_read_4(sc, RK_GPIO_SWPORTA_DR); 597 if (orig_pins) 598 *orig_pins = reg; 599 sc->swporta = reg; 600 601 if ((clear_pins | change_pins) != 0) { 602 reg = (reg & ~clear_pins) ^ change_pins; 603 rk_gpio_write_4(sc, RK_GPIO_SWPORTA_DR, reg); 604 } 605 RK_GPIO_UNLOCK(sc); 606 607 return (0); 608 } 609 610 static int 611 rk_gpio_pin_config_32(device_t dev, uint32_t first_pin, uint32_t num_pins, 612 uint32_t *pin_flags) 613 { 614 struct rk_gpio_softc *sc; 615 uint32_t reg, set, mask, flags; 616 int i; 617 618 sc = device_get_softc(dev); 619 620 if (first_pin != 0 || num_pins > 32) 621 return (EINVAL); 622 623 set = 0; 624 mask = 0; 625 for (i = 0; i < num_pins; i++) { 626 mask = (mask << 1) | 1; 627 flags = pin_flags[i]; 628 if (flags & GPIO_PIN_INPUT) { 629 set &= ~(1 << i); 630 } else if (flags & GPIO_PIN_OUTPUT) { 631 set |= (1 << i); 632 } 633 } 634 635 RK_GPIO_LOCK(sc); 636 reg = rk_gpio_read_4(sc, RK_GPIO_SWPORTA_DDR); 637 reg &= ~mask; 638 reg |= set; 639 rk_gpio_write_4(sc, RK_GPIO_SWPORTA_DDR, reg); 640 sc->swporta_ddr = reg; 641 RK_GPIO_UNLOCK(sc); 642 643 return (0); 644 } 645 646 static int 647 rk_gpio_map_gpios(device_t bus, phandle_t dev, phandle_t gparent, int gcells, 648 pcell_t *gpios, uint32_t *pin, uint32_t *flags) 649 { 650 651 /* The gpios are mapped as <pin flags> */ 652 *pin = gpios[0]; 653 *flags = gpios[1]; 654 return (0); 655 } 656 657 static phandle_t 658 rk_gpio_get_node(device_t bus, device_t dev) 659 { 660 661 /* We only have one child, the GPIO bus, which needs our own node. */ 662 return (ofw_bus_get_node(bus)); 663 } 664 665 static int 666 rk_gpio_pic_map_fdt(struct rk_gpio_softc *sc, 667 struct intr_map_data_fdt *daf, 668 u_int *irqp, uint32_t *modep) 669 { 670 uint32_t irq; 671 uint32_t mode; 672 673 if (daf->ncells != 2) 674 return (EINVAL); 675 676 irq = daf->cells[0]; 677 if (irq >= RK_GPIO_MAX_PINS) 678 return (EINVAL); 679 680 /* Only reasonable modes are supported. */ 681 if (daf->cells[1] == 1) 682 mode = GPIO_INTR_EDGE_RISING; 683 else if (daf->cells[1] == 2) 684 mode = GPIO_INTR_EDGE_FALLING; 685 else if (daf->cells[1] == 3) 686 mode = GPIO_INTR_EDGE_BOTH; 687 else if (daf->cells[1] == 4) 688 mode = GPIO_INTR_LEVEL_HIGH; 689 else if (daf->cells[1] == 8) 690 mode = GPIO_INTR_LEVEL_LOW; 691 else 692 return (EINVAL); 693 694 *irqp = irq; 695 if (modep != NULL) 696 *modep = mode; 697 return (0); 698 } 699 700 static int 701 rk_gpio_pic_map_gpio(struct rk_gpio_softc *sc, 702 struct intr_map_data_gpio *dag, 703 u_int *irqp, uint32_t *modep) 704 { 705 uint32_t irq; 706 irq = dag->gpio_pin_num; 707 if (irq >= RK_GPIO_MAX_PINS) { 708 device_printf(sc->sc_dev, "Invalid interrupt %u\n", 709 irq); 710 return (EINVAL); 711 } 712 713 *irqp = irq; 714 if (modep != NULL) 715 *modep = dag->gpio_intr_mode; 716 return (0); 717 } 718 719 static int 720 rk_gpio_pic_map(struct rk_gpio_softc *sc, struct intr_map_data *data, 721 u_int *irqp, uint32_t *modep) 722 { 723 switch (data->type) { 724 case INTR_MAP_DATA_FDT: 725 return (rk_gpio_pic_map_fdt(sc, 726 (struct intr_map_data_fdt *)data, irqp, modep)); 727 case INTR_MAP_DATA_GPIO: 728 return (rk_gpio_pic_map_gpio(sc, 729 (struct intr_map_data_gpio *)data, irqp, modep)); 730 default: 731 device_printf(sc->sc_dev, "Wrong type\n"); 732 return (ENOTSUP); 733 } 734 } 735 736 static int 737 rk_pic_map_intr(device_t dev, struct intr_map_data *data, 738 struct intr_irqsrc **isrcp) 739 { 740 int error; 741 struct rk_gpio_softc *sc = device_get_softc(dev); 742 uint32_t irq; 743 744 error = rk_gpio_pic_map(sc, data, &irq, NULL); 745 if (error == 0) 746 *isrcp = RK_GPIO_ISRC(sc, irq); 747 return (error); 748 } 749 750 static int 751 rk_pic_setup_intr(device_t dev, struct intr_irqsrc *isrc, 752 struct resource *res, struct intr_map_data *data) 753 { 754 struct rk_gpio_softc *sc = device_get_softc(dev); 755 struct rk_pin_irqsrc *rkisrc = (struct rk_pin_irqsrc *)isrc; 756 uint32_t mode; 757 uint32_t pin; 758 759 if (!data) { 760 device_printf(dev, "No map data\n"); 761 return (ENOTSUP); 762 } 763 764 if (rk_gpio_pic_map(sc, data, &pin, &mode) != 0) 765 return (EINVAL); 766 767 if (rkisrc->irq != pin) { 768 device_printf(dev, "Interrupts don't match\n"); 769 return (EINVAL); 770 } 771 772 if (isrc->isrc_handlers != 0) { 773 device_printf(dev, "Handler already attached\n"); 774 return (rkisrc->mode == mode ? 0 : EINVAL); 775 } 776 rkisrc->mode = mode; 777 778 RK_GPIO_LOCK(sc); 779 780 switch (mode & GPIO_INTR_MASK) { 781 case GPIO_INTR_EDGE_RISING: 782 rk_gpio_write_bit(sc, RK_GPIO_SWPORTA_DDR, pin, 0); 783 rk_gpio_write_bit(sc, RK_GPIO_INTTYPE_LEVEL, pin, 1); 784 rk_gpio_write_bit(sc, RK_GPIO_INT_POLARITY, pin, 1); 785 break; 786 case GPIO_INTR_EDGE_FALLING: 787 rk_gpio_write_bit(sc, RK_GPIO_SWPORTA_DDR, pin, 0); 788 rk_gpio_write_bit(sc, RK_GPIO_INTTYPE_LEVEL, pin, 1); 789 rk_gpio_write_bit(sc, RK_GPIO_INT_POLARITY, pin, 0); 790 break; 791 case GPIO_INTR_EDGE_BOTH: 792 rk_gpio_write_bit(sc, RK_GPIO_SWPORTA_DDR, pin, 0); 793 rk_gpio_write_bit(sc, RK_GPIO_INTTYPE_LEVEL, pin, 1); 794 if (sc->version == RK_GPIO_TYPE_V1) { 795 if (rk_gpio_read_bit(sc, RK_GPIO_EXT_PORTA, pin)) 796 rk_gpio_write_bit(sc, RK_GPIO_INT_POLARITY, 797 pin, 0); 798 else 799 rk_gpio_write_bit(sc, RK_GPIO_INT_POLARITY, 800 pin, 1); 801 } else 802 rk_gpio_write_bit(sc, RK_GPIO_INTTYPE_BOTH, pin, 1); 803 break; 804 case GPIO_INTR_LEVEL_HIGH: 805 rk_gpio_write_bit(sc, RK_GPIO_SWPORTA_DDR, pin, 0); 806 rk_gpio_write_bit(sc, RK_GPIO_INTTYPE_LEVEL, pin, 0); 807 rk_gpio_write_bit(sc, RK_GPIO_INT_POLARITY, pin, 1); 808 break; 809 case GPIO_INTR_LEVEL_LOW: 810 rk_gpio_write_bit(sc, RK_GPIO_SWPORTA_DDR, pin, 0); 811 rk_gpio_write_bit(sc, RK_GPIO_INTTYPE_LEVEL, pin, 0); 812 rk_gpio_write_bit(sc, RK_GPIO_INT_POLARITY, pin, 0); 813 break; 814 default: 815 rk_gpio_write_bit(sc, RK_GPIO_INTMASK, pin, 1); 816 rk_gpio_write_bit(sc, RK_GPIO_INTEN, pin, 0); 817 RK_GPIO_UNLOCK(sc); 818 return (EINVAL); 819 } 820 rk_gpio_write_bit(sc, RK_GPIO_DEBOUNCE, pin, 1); 821 rk_gpio_write_bit(sc, RK_GPIO_INTMASK, pin, 0); 822 rk_gpio_write_bit(sc, RK_GPIO_INTEN, pin, 1); 823 RK_GPIO_UNLOCK(sc); 824 825 return (0); 826 } 827 828 static int 829 rk_pic_teardown_intr(device_t dev, struct intr_irqsrc *isrc, 830 struct resource *res, struct intr_map_data *data) 831 { 832 struct rk_gpio_softc *sc = device_get_softc(dev); 833 struct rk_pin_irqsrc *irqsrc; 834 835 irqsrc = (struct rk_pin_irqsrc *)isrc; 836 837 if (isrc->isrc_handlers == 0) { 838 irqsrc->mode = GPIO_INTR_CONFORM; 839 RK_GPIO_LOCK(sc); 840 rk_gpio_write_bit(sc, RK_GPIO_INTEN, irqsrc->irq, 0); 841 rk_gpio_write_bit(sc, RK_GPIO_INTMASK, irqsrc->irq, 0); 842 rk_gpio_write_bit(sc, RK_GPIO_DEBOUNCE, irqsrc->irq, 0); 843 RK_GPIO_UNLOCK(sc); 844 } 845 return (0); 846 } 847 848 static device_method_t rk_gpio_methods[] = { 849 /* Device interface */ 850 DEVMETHOD(device_probe, rk_gpio_probe), 851 DEVMETHOD(device_attach, rk_gpio_attach), 852 DEVMETHOD(device_detach, rk_gpio_detach), 853 854 /* Bus interface */ 855 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 856 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 857 858 /* GPIO protocol */ 859 DEVMETHOD(gpio_get_bus, rk_gpio_get_bus), 860 DEVMETHOD(gpio_pin_max, rk_gpio_pin_max), 861 DEVMETHOD(gpio_pin_getname, rk_gpio_pin_getname), 862 DEVMETHOD(gpio_pin_getflags, rk_gpio_pin_getflags), 863 DEVMETHOD(gpio_pin_getcaps, rk_gpio_pin_getcaps), 864 DEVMETHOD(gpio_pin_setflags, rk_gpio_pin_setflags), 865 DEVMETHOD(gpio_pin_get, rk_gpio_pin_get), 866 DEVMETHOD(gpio_pin_set, rk_gpio_pin_set), 867 DEVMETHOD(gpio_pin_toggle, rk_gpio_pin_toggle), 868 DEVMETHOD(gpio_pin_access_32, rk_gpio_pin_access_32), 869 DEVMETHOD(gpio_pin_config_32, rk_gpio_pin_config_32), 870 DEVMETHOD(gpio_map_gpios, rk_gpio_map_gpios), 871 872 /* Interrupt controller interface */ 873 DEVMETHOD(pic_map_intr, rk_pic_map_intr), 874 DEVMETHOD(pic_setup_intr, rk_pic_setup_intr), 875 DEVMETHOD(pic_teardown_intr, rk_pic_teardown_intr), 876 877 /* ofw_bus interface */ 878 DEVMETHOD(ofw_bus_get_node, rk_gpio_get_node), 879 880 DEVMETHOD_END 881 }; 882 883 static driver_t rk_gpio_driver = { 884 "gpio", 885 rk_gpio_methods, 886 sizeof(struct rk_gpio_softc), 887 }; 888 889 /* 890 * GPIO driver is always a child of rk_pinctrl driver and should be probed 891 * and attached within rk_pinctrl_attach function. Due to this, bus pass order 892 * must be same as bus pass order of rk_pinctrl driver. 893 */ 894 EARLY_DRIVER_MODULE(rk_gpio, simplebus, rk_gpio_driver, 0, 0, 895 BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE); 896