1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2018 Emmanuel Vadot <manu@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/bus.h> 35 36 #include <sys/kernel.h> 37 #include <sys/module.h> 38 #include <sys/rman.h> 39 #include <sys/lock.h> 40 #include <sys/mutex.h> 41 #include <sys/gpio.h> 42 43 #include <machine/bus.h> 44 #include <machine/resource.h> 45 #include <machine/intr.h> 46 47 #include <dev/gpio/gpiobusvar.h> 48 #include <dev/ofw/ofw_bus.h> 49 #include <dev/ofw/ofw_bus_subr.h> 50 #include <dev/extres/clk/clk.h> 51 52 #include "gpio_if.h" 53 54 #define RK_GPIO_SWPORTA_DR 0x00 /* Data register */ 55 #define RK_GPIO_SWPORTA_DDR 0x04 /* Data direction register */ 56 57 #define RK_GPIO_INTEN 0x30 /* Interrupt enable register */ 58 #define RK_GPIO_INTMASK 0x34 /* Interrupt mask register */ 59 #define RK_GPIO_INTTYPE_LEVEL 0x38 /* Interrupt level register */ 60 #define RK_GPIO_INT_POLARITY 0x3C /* Interrupt polarity register */ 61 #define RK_GPIO_INT_STATUS 0x40 /* Interrupt status register */ 62 #define RK_GPIO_INT_RAWSTATUS 0x44 /* Raw Interrupt status register */ 63 64 #define RK_GPIO_DEBOUNCE 0x48 /* Debounce enable register */ 65 66 #define RK_GPIO_PORTA_EOI 0x4C /* Clear interrupt register */ 67 #define RK_GPIO_EXT_PORTA 0x50 /* External port register */ 68 69 #define RK_GPIO_LS_SYNC 0x60 /* Level sensitive syncronization enable register */ 70 71 struct rk_gpio_softc { 72 device_t sc_dev; 73 device_t sc_busdev; 74 struct mtx sc_mtx; 75 struct resource *sc_res[2]; 76 bus_space_tag_t sc_bst; 77 bus_space_handle_t sc_bsh; 78 clk_t clk; 79 }; 80 81 static struct ofw_compat_data compat_data[] = { 82 {"rockchip,gpio-bank", 1}, 83 {NULL, 0} 84 }; 85 86 static struct resource_spec rk_gpio_spec[] = { 87 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 88 { SYS_RES_IRQ, 0, RF_ACTIVE }, 89 { -1, 0 } 90 }; 91 92 static int rk_gpio_detach(device_t dev); 93 94 #define RK_GPIO_LOCK(_sc) mtx_lock_spin(&(_sc)->sc_mtx) 95 #define RK_GPIO_UNLOCK(_sc) mtx_unlock_spin(&(_sc)->sc_mtx) 96 #define RK_GPIO_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) 97 98 #define RK_GPIO_WRITE(_sc, _off, _val) \ 99 bus_space_write_4(_sc->sc_bst, _sc->sc_bsh, _off, _val) 100 #define RK_GPIO_READ(_sc, _off) \ 101 bus_space_read_4(_sc->sc_bst, _sc->sc_bsh, _off) 102 103 static int 104 rk_gpio_probe(device_t dev) 105 { 106 107 if (!ofw_bus_status_okay(dev)) 108 return (ENXIO); 109 110 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 111 return (ENXIO); 112 113 device_set_desc(dev, "RockChip GPIO Bank controller"); 114 return (BUS_PROBE_DEFAULT); 115 } 116 117 static int 118 rk_gpio_attach(device_t dev) 119 { 120 struct rk_gpio_softc *sc; 121 phandle_t node; 122 int err; 123 124 sc = device_get_softc(dev); 125 sc->sc_dev = dev; 126 127 node = ofw_bus_get_node(sc->sc_dev); 128 if (!OF_hasprop(node, "gpio-controller")) 129 return (ENXIO); 130 131 mtx_init(&sc->sc_mtx, "rk gpio", "gpio", MTX_SPIN); 132 133 if (bus_alloc_resources(dev, rk_gpio_spec, sc->sc_res)) { 134 device_printf(dev, "could not allocate resources\n"); 135 bus_release_resources(dev, rk_gpio_spec, sc->sc_res); 136 mtx_destroy(&sc->sc_mtx); 137 return (ENXIO); 138 } 139 140 sc->sc_bst = rman_get_bustag(sc->sc_res[0]); 141 sc->sc_bsh = rman_get_bushandle(sc->sc_res[0]); 142 143 if (clk_get_by_ofw_index(dev, 0, 0, &sc->clk) != 0) { 144 device_printf(dev, "Cannot get clock\n"); 145 rk_gpio_detach(dev); 146 return (ENXIO); 147 } 148 err = clk_enable(sc->clk); 149 if (err != 0) { 150 device_printf(dev, "Could not enable clock %s\n", 151 clk_get_name(sc->clk)); 152 rk_gpio_detach(dev); 153 return (ENXIO); 154 } 155 156 sc->sc_busdev = gpiobus_attach_bus(dev); 157 if (sc->sc_busdev == NULL) { 158 rk_gpio_detach(dev); 159 return (ENXIO); 160 } 161 162 return (0); 163 } 164 165 static int 166 rk_gpio_detach(device_t dev) 167 { 168 struct rk_gpio_softc *sc; 169 170 sc = device_get_softc(dev); 171 172 if (sc->sc_busdev) 173 gpiobus_detach_bus(dev); 174 bus_release_resources(dev, rk_gpio_spec, sc->sc_res); 175 mtx_destroy(&sc->sc_mtx); 176 clk_disable(sc->clk); 177 178 return(0); 179 } 180 181 static device_t 182 rk_gpio_get_bus(device_t dev) 183 { 184 struct rk_gpio_softc *sc; 185 186 sc = device_get_softc(dev); 187 188 return (sc->sc_busdev); 189 } 190 191 static int 192 rk_gpio_pin_max(device_t dev, int *maxpin) 193 { 194 195 /* Each bank have always 32 pins */ 196 /* XXX not true*/ 197 *maxpin = 31; 198 return (0); 199 } 200 201 static int 202 rk_gpio_pin_getname(device_t dev, uint32_t pin, char *name) 203 { 204 struct rk_gpio_softc *sc; 205 206 sc = device_get_softc(dev); 207 208 if (pin >= 32) 209 return (EINVAL); 210 211 RK_GPIO_LOCK(sc); 212 snprintf(name, GPIOMAXNAME, "gpio%d", pin); 213 RK_GPIO_UNLOCK(sc); 214 215 return (0); 216 } 217 218 static int 219 rk_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags) 220 { 221 struct rk_gpio_softc *sc; 222 uint32_t reg; 223 224 sc = device_get_softc(dev); 225 226 /* XXX Combine this with parent (pinctrl) */ 227 RK_GPIO_LOCK(sc); 228 reg = RK_GPIO_READ(sc, RK_GPIO_SWPORTA_DDR); 229 RK_GPIO_UNLOCK(sc); 230 231 if (reg & (1 << pin)) 232 *flags = GPIO_PIN_OUTPUT; 233 else 234 *flags = GPIO_PIN_INPUT; 235 236 return (0); 237 } 238 239 static int 240 rk_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps) 241 { 242 243 /* Caps are managed by the pinctrl device */ 244 /* XXX Pass this to parent (pinctrl) */ 245 *caps = 0; 246 return (0); 247 } 248 249 static int 250 rk_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags) 251 { 252 struct rk_gpio_softc *sc; 253 uint32_t reg; 254 255 sc = device_get_softc(dev); 256 257 /* XXX Combine this with parent (pinctrl) */ 258 RK_GPIO_LOCK(sc); 259 260 reg = RK_GPIO_READ(sc, RK_GPIO_SWPORTA_DDR); 261 if (flags & GPIO_PIN_INPUT) 262 reg &= ~(1 << pin); 263 else if (flags & GPIO_PIN_OUTPUT) 264 reg |= (1 << pin); 265 266 RK_GPIO_WRITE(sc, RK_GPIO_SWPORTA_DDR, reg); 267 RK_GPIO_UNLOCK(sc); 268 269 return (0); 270 } 271 272 static int 273 rk_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val) 274 { 275 struct rk_gpio_softc *sc; 276 uint32_t reg; 277 278 sc = device_get_softc(dev); 279 280 RK_GPIO_LOCK(sc); 281 reg = RK_GPIO_READ(sc, RK_GPIO_EXT_PORTA); 282 RK_GPIO_UNLOCK(sc); 283 284 *val = reg & (1 << pin) ? 1 : 0; 285 286 return (0); 287 } 288 289 static int 290 rk_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value) 291 { 292 struct rk_gpio_softc *sc; 293 uint32_t reg; 294 295 sc = device_get_softc(dev); 296 297 RK_GPIO_LOCK(sc); 298 reg = RK_GPIO_READ(sc, RK_GPIO_SWPORTA_DR); 299 if (value) 300 reg |= (1 << pin); 301 else 302 reg &= ~(1 << pin); 303 RK_GPIO_WRITE(sc, RK_GPIO_SWPORTA_DR, reg); 304 RK_GPIO_UNLOCK(sc); 305 306 return (0); 307 } 308 309 static int 310 rk_gpio_pin_toggle(device_t dev, uint32_t pin) 311 { 312 struct rk_gpio_softc *sc; 313 uint32_t reg; 314 315 sc = device_get_softc(dev); 316 317 RK_GPIO_LOCK(sc); 318 reg = RK_GPIO_READ(sc, RK_GPIO_SWPORTA_DR); 319 if (reg & (1 << pin)) 320 reg &= ~(1 << pin); 321 else 322 reg |= (1 << pin); 323 RK_GPIO_WRITE(sc, RK_GPIO_SWPORTA_DR, reg); 324 RK_GPIO_UNLOCK(sc); 325 326 return (0); 327 } 328 329 static int 330 rk_gpio_pin_access_32(device_t dev, uint32_t first_pin, uint32_t clear_pins, 331 uint32_t change_pins, uint32_t *orig_pins) 332 { 333 struct rk_gpio_softc *sc; 334 uint32_t reg; 335 336 sc = device_get_softc(dev); 337 338 RK_GPIO_LOCK(sc); 339 reg = RK_GPIO_READ(sc, RK_GPIO_SWPORTA_DR); 340 if (orig_pins) 341 *orig_pins = reg; 342 343 if ((clear_pins | change_pins) != 0) { 344 reg = (reg & ~clear_pins) ^ change_pins; 345 RK_GPIO_WRITE(sc, RK_GPIO_SWPORTA_DR, reg); 346 } 347 RK_GPIO_UNLOCK(sc); 348 349 return (0); 350 } 351 352 static int 353 rk_gpio_pin_config_32(device_t dev, uint32_t first_pin, uint32_t num_pins, 354 uint32_t *pin_flags) 355 { 356 struct rk_gpio_softc *sc; 357 uint32_t reg, set, mask, flags; 358 int i; 359 360 sc = device_get_softc(dev); 361 362 if (first_pin != 0 || num_pins > 32) 363 return (EINVAL); 364 365 set = 0; 366 mask = 0; 367 for (i = 0; i < num_pins; i++) { 368 mask = (mask << 1) | 1; 369 flags = pin_flags[i]; 370 if (flags & GPIO_PIN_INPUT) { 371 set &= ~(1 << i); 372 } else if (flags & GPIO_PIN_OUTPUT) { 373 set |= (1 << i); 374 } 375 } 376 377 RK_GPIO_LOCK(sc); 378 reg = RK_GPIO_READ(sc, RK_GPIO_SWPORTA_DDR); 379 reg &= ~mask; 380 reg |= set; 381 RK_GPIO_WRITE(sc, RK_GPIO_SWPORTA_DDR, reg); 382 RK_GPIO_UNLOCK(sc); 383 384 return (0); 385 } 386 387 static int 388 rk_gpio_map_gpios(device_t bus, phandle_t dev, phandle_t gparent, int gcells, 389 pcell_t *gpios, uint32_t *pin, uint32_t *flags) 390 { 391 392 /* The gpios are mapped as <pin flags> */ 393 *pin = gpios[0]; 394 *flags = gpios[1]; 395 return (0); 396 } 397 398 static phandle_t 399 rk_gpio_get_node(device_t bus, device_t dev) 400 { 401 402 /* We only have one child, the GPIO bus, which needs our own node. */ 403 return (ofw_bus_get_node(bus)); 404 } 405 406 static device_method_t rk_gpio_methods[] = { 407 /* Device interface */ 408 DEVMETHOD(device_probe, rk_gpio_probe), 409 DEVMETHOD(device_attach, rk_gpio_attach), 410 DEVMETHOD(device_detach, rk_gpio_detach), 411 412 /* GPIO protocol */ 413 DEVMETHOD(gpio_get_bus, rk_gpio_get_bus), 414 DEVMETHOD(gpio_pin_max, rk_gpio_pin_max), 415 DEVMETHOD(gpio_pin_getname, rk_gpio_pin_getname), 416 DEVMETHOD(gpio_pin_getflags, rk_gpio_pin_getflags), 417 DEVMETHOD(gpio_pin_getcaps, rk_gpio_pin_getcaps), 418 DEVMETHOD(gpio_pin_setflags, rk_gpio_pin_setflags), 419 DEVMETHOD(gpio_pin_get, rk_gpio_pin_get), 420 DEVMETHOD(gpio_pin_set, rk_gpio_pin_set), 421 DEVMETHOD(gpio_pin_toggle, rk_gpio_pin_toggle), 422 DEVMETHOD(gpio_pin_access_32, rk_gpio_pin_access_32), 423 DEVMETHOD(gpio_pin_config_32, rk_gpio_pin_config_32), 424 DEVMETHOD(gpio_map_gpios, rk_gpio_map_gpios), 425 426 /* ofw_bus interface */ 427 DEVMETHOD(ofw_bus_get_node, rk_gpio_get_node), 428 429 DEVMETHOD_END 430 }; 431 432 static driver_t rk_gpio_driver = { 433 "gpio", 434 rk_gpio_methods, 435 sizeof(struct rk_gpio_softc), 436 }; 437 438 static devclass_t rk_gpio_devclass; 439 440 /* 441 * GPIO driver is always a child of rk_pinctrl driver and should be probed 442 * and attached within rk_pinctrl_attach function. Due to this, bus pass order 443 * must be same as bus pass order of rk_pinctrl driver. 444 */ 445 EARLY_DRIVER_MODULE(rk_gpio, simplebus, rk_gpio_driver, 446 rk_gpio_devclass, 0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE); 447