1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2018 Emmanuel Vadot <manu@FreeBSD.org> 5 * Copyright (c) 2021 Soren Schmidt <sos@deepcore.dk> 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/bus.h> 36 37 #include <sys/kernel.h> 38 #include <sys/module.h> 39 #include <sys/proc.h> 40 #include <sys/rman.h> 41 #include <sys/lock.h> 42 #include <sys/mutex.h> 43 #include <sys/gpio.h> 44 45 #include <machine/bus.h> 46 #include <machine/resource.h> 47 #include <machine/intr.h> 48 49 #include <dev/gpio/gpiobusvar.h> 50 #include <dev/ofw/ofw_bus.h> 51 #include <dev/ofw/ofw_bus_subr.h> 52 #include <dev/extres/clk/clk.h> 53 54 #include "gpio_if.h" 55 #include "pic_if.h" 56 57 #include "fdt_pinctrl_if.h" 58 59 enum gpio_regs { 60 RK_GPIO_SWPORTA_DR = 1, /* Data register */ 61 RK_GPIO_SWPORTA_DDR, /* Data direction register */ 62 RK_GPIO_INTEN, /* Interrupt enable register */ 63 RK_GPIO_INTMASK, /* Interrupt mask register */ 64 RK_GPIO_INTTYPE_LEVEL, /* Interrupt level register */ 65 RK_GPIO_INTTYPE_BOTH, /* Both rise and falling edge */ 66 RK_GPIO_INT_POLARITY, /* Interrupt polarity register */ 67 RK_GPIO_INT_STATUS, /* Interrupt status register */ 68 RK_GPIO_INT_RAWSTATUS, /* Raw Interrupt status register */ 69 RK_GPIO_DEBOUNCE, /* Debounce enable register */ 70 RK_GPIO_PORTA_EOI, /* Clear interrupt register */ 71 RK_GPIO_EXT_PORTA, /* External port register */ 72 RK_GPIO_REGNUM 73 }; 74 75 #define RK_GPIO_LS_SYNC 0x60 /* Level sensitive syncronization enable register */ 76 77 #define RK_GPIO_DEFAULT_CAPS (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | \ 78 GPIO_PIN_PULLUP | GPIO_PIN_PULLDOWN | GPIO_INTR_EDGE_BOTH | \ 79 GPIO_INTR_EDGE_RISING | GPIO_INTR_EDGE_FALLING | \ 80 GPIO_INTR_LEVEL_HIGH | GPIO_INTR_LEVEL_LOW) 81 82 #define GPIO_FLAGS_PINCTRL GPIO_PIN_PULLUP | GPIO_PIN_PULLDOWN 83 #define RK_GPIO_MAX_PINS 32 84 85 struct pin_cached { 86 uint8_t is_gpio; 87 uint32_t flags; 88 }; 89 90 struct rk_pin_irqsrc { 91 struct intr_irqsrc isrc; 92 uint32_t irq; 93 uint32_t mode; 94 }; 95 96 struct rk_gpio_softc { 97 device_t sc_dev; 98 device_t sc_busdev; 99 struct mtx sc_mtx; 100 struct resource *sc_res[2]; 101 bus_space_tag_t sc_bst; 102 bus_space_handle_t sc_bsh; 103 clk_t clk; 104 device_t pinctrl; 105 uint32_t swporta; 106 uint32_t swporta_ddr; 107 uint32_t version; 108 struct pin_cached pin_cached[RK_GPIO_MAX_PINS]; 109 uint8_t regs[RK_GPIO_REGNUM]; 110 void *ihandle; 111 struct rk_pin_irqsrc isrcs[RK_GPIO_MAX_PINS]; 112 }; 113 114 static struct ofw_compat_data compat_data[] = { 115 {"rockchip,gpio-bank", 1}, 116 {NULL, 0} 117 }; 118 119 static struct resource_spec rk_gpio_spec[] = { 120 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 121 { SYS_RES_IRQ, 0, RF_ACTIVE }, 122 { -1, 0 } 123 }; 124 125 #define RK_GPIO_VERSION 0x78 126 #define RK_GPIO_TYPE_V1 0x00000000 127 #define RK_GPIO_TYPE_V2 0x01000c2b 128 #define RK_GPIO_ISRC(sc, irq) (&(sc->isrcs[irq].isrc)) 129 130 static int rk_gpio_detach(device_t dev); 131 132 #define RK_GPIO_LOCK(_sc) mtx_lock_spin(&(_sc)->sc_mtx) 133 #define RK_GPIO_UNLOCK(_sc) mtx_unlock_spin(&(_sc)->sc_mtx) 134 #define RK_GPIO_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) 135 136 #define RK_GPIO_WRITE(_sc, _off, _val) \ 137 bus_space_write_4(_sc->sc_bst, _sc->sc_bsh, _off, _val) 138 #define RK_GPIO_READ(_sc, _off) \ 139 bus_space_read_4(_sc->sc_bst, _sc->sc_bsh, _off) 140 141 static int 142 rk_gpio_read_bit(struct rk_gpio_softc *sc, int reg, int bit) 143 { 144 int offset = sc->regs[reg]; 145 uint32_t value; 146 147 if (sc->version == RK_GPIO_TYPE_V1) { 148 value = RK_GPIO_READ(sc, offset); 149 value >>= bit; 150 } else { 151 value = RK_GPIO_READ(sc, bit > 15 ? offset + 4 : offset); 152 value >>= (bit % 16); 153 } 154 return (value & 1); 155 } 156 157 static void 158 rk_gpio_write_bit(struct rk_gpio_softc *sc, int reg, int bit, int data) 159 { 160 int offset = sc->regs[reg]; 161 uint32_t value; 162 163 if (sc->version == RK_GPIO_TYPE_V1) { 164 value = RK_GPIO_READ(sc, offset); 165 if (data) 166 value |= (1 << bit); 167 else 168 value &= ~(1 << bit); 169 RK_GPIO_WRITE(sc, offset, value); 170 } else { 171 if (data) 172 value = (1 << (bit % 16)); 173 else 174 value = 0; 175 value |= (1 << ((bit % 16) + 16)); 176 RK_GPIO_WRITE(sc, bit > 15 ? offset + 4 : offset, value); 177 } 178 } 179 180 static uint32_t 181 rk_gpio_read_4(struct rk_gpio_softc *sc, int reg) 182 { 183 int offset = sc->regs[reg]; 184 uint32_t value; 185 186 if (sc->version == RK_GPIO_TYPE_V1) 187 value = RK_GPIO_READ(sc, offset); 188 else 189 value = (RK_GPIO_READ(sc, offset) & 0xffff) | 190 (RK_GPIO_READ(sc, offset + 4) << 16); 191 return (value); 192 } 193 194 static void 195 rk_gpio_write_4(struct rk_gpio_softc *sc, int reg, uint32_t value) 196 { 197 int offset = sc->regs[reg]; 198 199 if (sc->version == RK_GPIO_TYPE_V1) 200 RK_GPIO_WRITE(sc, offset, value); 201 else { 202 RK_GPIO_WRITE(sc, offset, (value & 0xffff) | 0xffff0000); 203 RK_GPIO_WRITE(sc, offset + 4, (value >> 16) | 0xffff0000); 204 } 205 } 206 207 static int 208 rk_gpio_intr(void *arg) 209 { 210 struct rk_gpio_softc *sc = (struct rk_gpio_softc *)arg;; 211 struct trapframe *tf = curthread->td_intr_frame; 212 uint32_t status; 213 214 RK_GPIO_LOCK(sc); 215 status = rk_gpio_read_4(sc, RK_GPIO_INT_STATUS); 216 rk_gpio_write_4(sc, RK_GPIO_PORTA_EOI, status); 217 RK_GPIO_UNLOCK(sc); 218 219 while (status) { 220 int pin = ffs(status) - 1; 221 222 status &= ~(1 << pin); 223 if (intr_isrc_dispatch(RK_GPIO_ISRC(sc, pin), tf)) { 224 device_printf(sc->sc_dev, "Interrupt pin=%d unhandled\n", 225 pin); 226 continue; 227 } 228 229 if ((sc->version == RK_GPIO_TYPE_V1) && 230 (sc->isrcs[pin].mode & GPIO_INTR_EDGE_BOTH)) { 231 RK_GPIO_LOCK(sc); 232 if (rk_gpio_read_bit(sc, RK_GPIO_EXT_PORTA, pin)) 233 rk_gpio_write_bit(sc, RK_GPIO_INT_POLARITY, 234 (1 << pin), 0); 235 else 236 rk_gpio_write_bit(sc, RK_GPIO_INT_POLARITY, 237 (1 << pin), 1); 238 RK_GPIO_UNLOCK(sc); 239 } 240 } 241 return (FILTER_HANDLED); 242 } 243 244 static int 245 rk_gpio_probe(device_t dev) 246 { 247 248 if (!ofw_bus_status_okay(dev)) 249 return (ENXIO); 250 251 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 252 return (ENXIO); 253 254 device_set_desc(dev, "RockChip GPIO Bank controller"); 255 return (BUS_PROBE_DEFAULT); 256 } 257 258 static int 259 rk_gpio_attach(device_t dev) 260 { 261 struct rk_gpio_softc *sc; 262 phandle_t node; 263 int err, i; 264 265 sc = device_get_softc(dev); 266 sc->sc_dev = dev; 267 sc->pinctrl = device_get_parent(dev); 268 269 node = ofw_bus_get_node(sc->sc_dev); 270 if (!OF_hasprop(node, "gpio-controller")) 271 return (ENXIO); 272 273 mtx_init(&sc->sc_mtx, "rk gpio", "gpio", MTX_SPIN); 274 275 if (bus_alloc_resources(dev, rk_gpio_spec, sc->sc_res)) { 276 device_printf(dev, "could not allocate resources\n"); 277 bus_release_resources(dev, rk_gpio_spec, sc->sc_res); 278 mtx_destroy(&sc->sc_mtx); 279 return (ENXIO); 280 } 281 282 sc->sc_bst = rman_get_bustag(sc->sc_res[0]); 283 sc->sc_bsh = rman_get_bushandle(sc->sc_res[0]); 284 285 if (clk_get_by_ofw_index(dev, 0, 0, &sc->clk) != 0) { 286 device_printf(dev, "Cannot get clock\n"); 287 rk_gpio_detach(dev); 288 return (ENXIO); 289 } 290 err = clk_enable(sc->clk); 291 if (err != 0) { 292 device_printf(dev, "Could not enable clock %s\n", 293 clk_get_name(sc->clk)); 294 rk_gpio_detach(dev); 295 return (ENXIO); 296 } 297 298 if ((err = bus_setup_intr(dev, sc->sc_res[1], 299 INTR_TYPE_MISC | INTR_MPSAFE, rk_gpio_intr, NULL, 300 sc, &sc->ihandle))) { 301 device_printf(dev, "Can not setup IRQ\n"); 302 rk_gpio_detach(dev); 303 return (ENXIO); 304 } 305 306 RK_GPIO_LOCK(sc); 307 sc->version = rk_gpio_read_4(sc, RK_GPIO_VERSION); 308 RK_GPIO_UNLOCK(sc); 309 310 switch (sc->version) { 311 case RK_GPIO_TYPE_V1: 312 sc->regs[RK_GPIO_SWPORTA_DR] = 0x00; 313 sc->regs[RK_GPIO_SWPORTA_DDR] = 0x04; 314 sc->regs[RK_GPIO_INTEN] = 0x30; 315 sc->regs[RK_GPIO_INTMASK] = 0x34; 316 sc->regs[RK_GPIO_INTTYPE_LEVEL] = 0x38; 317 sc->regs[RK_GPIO_INT_POLARITY] = 0x3c; 318 sc->regs[RK_GPIO_INT_STATUS] = 0x40; 319 sc->regs[RK_GPIO_INT_RAWSTATUS] = 0x44; 320 sc->regs[RK_GPIO_DEBOUNCE] = 0x48; 321 sc->regs[RK_GPIO_PORTA_EOI] = 0x4c; 322 sc->regs[RK_GPIO_EXT_PORTA] = 0x50; 323 break; 324 case RK_GPIO_TYPE_V2: 325 sc->regs[RK_GPIO_SWPORTA_DR] = 0x00; 326 sc->regs[RK_GPIO_SWPORTA_DDR] = 0x08; 327 sc->regs[RK_GPIO_INTEN] = 0x10; 328 sc->regs[RK_GPIO_INTMASK] = 0x18; 329 sc->regs[RK_GPIO_INTTYPE_LEVEL] = 0x20; 330 sc->regs[RK_GPIO_INTTYPE_BOTH] = 0x30; 331 sc->regs[RK_GPIO_INT_POLARITY] = 0x28; 332 sc->regs[RK_GPIO_INT_STATUS] = 0x50; 333 sc->regs[RK_GPIO_INT_RAWSTATUS] = 0x58; 334 sc->regs[RK_GPIO_DEBOUNCE] = 0x38; 335 sc->regs[RK_GPIO_PORTA_EOI] = 0x60; 336 sc->regs[RK_GPIO_EXT_PORTA] = 0x70; 337 break; 338 default: 339 device_printf(dev, "Unknown gpio version %08x\n", sc->version); 340 rk_gpio_detach(dev); 341 return (ENXIO); 342 } 343 344 for (i = 0; i < RK_GPIO_MAX_PINS; i++) { 345 sc->isrcs[i].irq = i; 346 sc->isrcs[i].mode = GPIO_INTR_CONFORM; 347 if ((err = intr_isrc_register(RK_GPIO_ISRC(sc, i), 348 dev, 0, "%s", device_get_nameunit(dev)))) { 349 device_printf(dev, "Can not register isrc %d\n", err); 350 rk_gpio_detach(dev); 351 return (ENXIO); 352 } 353 } 354 355 if (intr_pic_register(dev, OF_xref_from_node(node)) == NULL) { 356 device_printf(dev, "Can not register pic\n"); 357 rk_gpio_detach(dev); 358 return (ENXIO); 359 } 360 361 sc->sc_busdev = gpiobus_attach_bus(dev); 362 if (sc->sc_busdev == NULL) { 363 rk_gpio_detach(dev); 364 return (ENXIO); 365 } 366 367 /* Set the cached value to unknown */ 368 for (i = 0; i < RK_GPIO_MAX_PINS; i++) 369 sc->pin_cached[i].is_gpio = 2; 370 371 RK_GPIO_LOCK(sc); 372 sc->swporta = rk_gpio_read_4(sc, RK_GPIO_SWPORTA_DR); 373 sc->swporta_ddr = rk_gpio_read_4(sc, RK_GPIO_SWPORTA_DDR); 374 RK_GPIO_UNLOCK(sc); 375 376 return (0); 377 } 378 379 static int 380 rk_gpio_detach(device_t dev) 381 { 382 struct rk_gpio_softc *sc; 383 384 sc = device_get_softc(dev); 385 386 if (sc->sc_busdev) 387 gpiobus_detach_bus(dev); 388 bus_release_resources(dev, rk_gpio_spec, sc->sc_res); 389 mtx_destroy(&sc->sc_mtx); 390 clk_disable(sc->clk); 391 392 return(0); 393 } 394 395 static device_t 396 rk_gpio_get_bus(device_t dev) 397 { 398 struct rk_gpio_softc *sc; 399 400 sc = device_get_softc(dev); 401 402 return (sc->sc_busdev); 403 } 404 405 static int 406 rk_gpio_pin_max(device_t dev, int *maxpin) 407 { 408 409 /* Each bank have always 32 pins */ 410 /* XXX not true*/ 411 *maxpin = 31; 412 return (0); 413 } 414 415 static int 416 rk_gpio_pin_getname(device_t dev, uint32_t pin, char *name) 417 { 418 struct rk_gpio_softc *sc; 419 uint32_t bank; 420 421 sc = device_get_softc(dev); 422 423 if (pin >= 32) 424 return (EINVAL); 425 426 bank = pin / 8; 427 pin = pin - (bank * 8); 428 RK_GPIO_LOCK(sc); 429 snprintf(name, GPIOMAXNAME, "P%c%d", bank + 'A', pin); 430 RK_GPIO_UNLOCK(sc); 431 432 return (0); 433 } 434 435 static int 436 rk_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags) 437 { 438 struct rk_gpio_softc *sc; 439 int rv; 440 441 sc = device_get_softc(dev); 442 443 if (__predict_false(sc->pin_cached[pin].is_gpio != 1)) { 444 rv = FDT_PINCTRL_IS_GPIO(sc->pinctrl, dev, pin, (bool *)&sc->pin_cached[pin].is_gpio); 445 if (rv != 0) 446 return (rv); 447 if (sc->pin_cached[pin].is_gpio == 0) 448 return (EINVAL); 449 } 450 *flags = 0; 451 rv = FDT_PINCTRL_GET_FLAGS(sc->pinctrl, dev, pin, flags); 452 if (rv != 0) 453 return (rv); 454 sc->pin_cached[pin].flags = *flags; 455 456 if (sc->swporta_ddr & (1 << pin)) 457 *flags |= GPIO_PIN_OUTPUT; 458 else 459 *flags |= GPIO_PIN_INPUT; 460 461 return (0); 462 } 463 464 static int 465 rk_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps) 466 { 467 468 if (pin >= RK_GPIO_MAX_PINS) 469 return EINVAL; 470 471 *caps = RK_GPIO_DEFAULT_CAPS; 472 return (0); 473 } 474 475 static int 476 rk_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags) 477 { 478 struct rk_gpio_softc *sc; 479 int rv; 480 481 sc = device_get_softc(dev); 482 483 if (pin >= RK_GPIO_MAX_PINS) 484 return (EINVAL); 485 486 if (__predict_false(sc->pin_cached[pin].is_gpio != 1)) { 487 rv = FDT_PINCTRL_IS_GPIO(sc->pinctrl, dev, pin, (bool *)&sc->pin_cached[pin].is_gpio); 488 if (rv != 0) 489 return (rv); 490 if (sc->pin_cached[pin].is_gpio == 0) 491 return (EINVAL); 492 } 493 494 if (__predict_false((flags & GPIO_PIN_INPUT) && ((flags & GPIO_FLAGS_PINCTRL) != sc->pin_cached[pin].flags))) { 495 rv = FDT_PINCTRL_SET_FLAGS(sc->pinctrl, dev, pin, flags); 496 sc->pin_cached[pin].flags = flags & GPIO_FLAGS_PINCTRL; 497 if (rv != 0) 498 return (rv); 499 } 500 501 RK_GPIO_LOCK(sc); 502 if (flags & GPIO_PIN_INPUT) 503 sc->swporta_ddr &= ~(1 << pin); 504 else if (flags & GPIO_PIN_OUTPUT) 505 sc->swporta_ddr |= (1 << pin); 506 507 rk_gpio_write_4(sc, RK_GPIO_SWPORTA_DDR, sc->swporta_ddr); 508 RK_GPIO_UNLOCK(sc); 509 510 return (0); 511 } 512 513 static int 514 rk_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val) 515 { 516 struct rk_gpio_softc *sc; 517 518 sc = device_get_softc(dev); 519 520 if (pin >= RK_GPIO_MAX_PINS) 521 return (EINVAL); 522 523 RK_GPIO_LOCK(sc); 524 *val = rk_gpio_read_bit(sc, RK_GPIO_EXT_PORTA, pin); 525 RK_GPIO_UNLOCK(sc); 526 527 return (0); 528 } 529 530 static int 531 rk_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value) 532 { 533 struct rk_gpio_softc *sc; 534 535 sc = device_get_softc(dev); 536 537 if (pin >= RK_GPIO_MAX_PINS) 538 return (EINVAL); 539 540 RK_GPIO_LOCK(sc); 541 if (value) 542 sc->swporta |= (1 << pin); 543 else 544 sc->swporta &= ~(1 << pin); 545 rk_gpio_write_4(sc, RK_GPIO_SWPORTA_DR, sc->swporta); 546 RK_GPIO_UNLOCK(sc); 547 548 return (0); 549 } 550 551 static int 552 rk_gpio_pin_toggle(device_t dev, uint32_t pin) 553 { 554 struct rk_gpio_softc *sc; 555 556 sc = device_get_softc(dev); 557 558 if (pin >= RK_GPIO_MAX_PINS) 559 return (EINVAL); 560 561 RK_GPIO_LOCK(sc); 562 if (sc->swporta & (1 << pin)) 563 sc->swporta &= ~(1 << pin); 564 else 565 sc->swporta |= (1 << pin); 566 rk_gpio_write_4(sc, RK_GPIO_SWPORTA_DR, sc->swporta); 567 RK_GPIO_UNLOCK(sc); 568 569 return (0); 570 } 571 572 static int 573 rk_gpio_pin_access_32(device_t dev, uint32_t first_pin, uint32_t clear_pins, 574 uint32_t change_pins, uint32_t *orig_pins) 575 { 576 struct rk_gpio_softc *sc; 577 uint32_t reg; 578 579 sc = device_get_softc(dev); 580 581 RK_GPIO_LOCK(sc); 582 reg = rk_gpio_read_4(sc, RK_GPIO_SWPORTA_DR); 583 if (orig_pins) 584 *orig_pins = reg; 585 sc->swporta = reg; 586 587 if ((clear_pins | change_pins) != 0) { 588 reg = (reg & ~clear_pins) ^ change_pins; 589 rk_gpio_write_4(sc, RK_GPIO_SWPORTA_DR, reg); 590 } 591 RK_GPIO_UNLOCK(sc); 592 593 return (0); 594 } 595 596 static int 597 rk_gpio_pin_config_32(device_t dev, uint32_t first_pin, uint32_t num_pins, 598 uint32_t *pin_flags) 599 { 600 struct rk_gpio_softc *sc; 601 uint32_t reg, set, mask, flags; 602 int i; 603 604 sc = device_get_softc(dev); 605 606 if (first_pin != 0 || num_pins > 32) 607 return (EINVAL); 608 609 set = 0; 610 mask = 0; 611 for (i = 0; i < num_pins; i++) { 612 mask = (mask << 1) | 1; 613 flags = pin_flags[i]; 614 if (flags & GPIO_PIN_INPUT) { 615 set &= ~(1 << i); 616 } else if (flags & GPIO_PIN_OUTPUT) { 617 set |= (1 << i); 618 } 619 } 620 621 RK_GPIO_LOCK(sc); 622 reg = rk_gpio_read_4(sc, RK_GPIO_SWPORTA_DDR); 623 reg &= ~mask; 624 reg |= set; 625 rk_gpio_write_4(sc, RK_GPIO_SWPORTA_DDR, reg); 626 sc->swporta_ddr = reg; 627 RK_GPIO_UNLOCK(sc); 628 629 return (0); 630 } 631 632 static int 633 rk_gpio_map_gpios(device_t bus, phandle_t dev, phandle_t gparent, int gcells, 634 pcell_t *gpios, uint32_t *pin, uint32_t *flags) 635 { 636 637 /* The gpios are mapped as <pin flags> */ 638 *pin = gpios[0]; 639 *flags = gpios[1]; 640 return (0); 641 } 642 643 static phandle_t 644 rk_gpio_get_node(device_t bus, device_t dev) 645 { 646 647 /* We only have one child, the GPIO bus, which needs our own node. */ 648 return (ofw_bus_get_node(bus)); 649 } 650 651 static int 652 rk_pic_map_intr(device_t dev, struct intr_map_data *data, 653 struct intr_irqsrc **isrcp) 654 { 655 struct rk_gpio_softc *sc = device_get_softc(dev); 656 struct intr_map_data_gpio *gdata; 657 uint32_t irq; 658 659 if (data->type != INTR_MAP_DATA_GPIO) { 660 device_printf(dev, "Wrong type\n"); 661 return (ENOTSUP); 662 } 663 gdata = (struct intr_map_data_gpio *)data; 664 irq = gdata->gpio_pin_num; 665 if (irq >= RK_GPIO_MAX_PINS) { 666 device_printf(dev, "Invalid interrupt %u\n", irq); 667 return (EINVAL); 668 } 669 *isrcp = RK_GPIO_ISRC(sc, irq); 670 return (0); 671 } 672 673 static int 674 rk_pic_setup_intr(device_t dev, struct intr_irqsrc *isrc, 675 struct resource *res, struct intr_map_data *data) 676 { 677 struct rk_gpio_softc *sc = device_get_softc(dev); 678 struct rk_pin_irqsrc *rkisrc = (struct rk_pin_irqsrc *)isrc; 679 struct intr_map_data_gpio *gdata; 680 uint32_t mode; 681 uint8_t pin; 682 683 if (!data) { 684 device_printf(dev, "No map data\n"); 685 return (ENOTSUP); 686 } 687 gdata = (struct intr_map_data_gpio *)data; 688 mode = gdata->gpio_intr_mode; 689 pin = gdata->gpio_pin_num; 690 691 if (rkisrc->irq != gdata->gpio_pin_num) { 692 device_printf(dev, "Interrupts don't match\n"); 693 return (EINVAL); 694 } 695 696 if (isrc->isrc_handlers != 0) { 697 device_printf(dev, "Handler already attached\n"); 698 return (rkisrc->mode == mode ? 0 : EINVAL); 699 } 700 rkisrc->mode = mode; 701 702 RK_GPIO_LOCK(sc); 703 704 switch (mode & GPIO_INTR_MASK) { 705 case GPIO_INTR_EDGE_RISING: 706 rk_gpio_write_bit(sc, RK_GPIO_SWPORTA_DDR, pin, 0); 707 rk_gpio_write_bit(sc, RK_GPIO_INTTYPE_LEVEL, pin, 1); 708 rk_gpio_write_bit(sc, RK_GPIO_INT_POLARITY, pin, 1); 709 break; 710 case GPIO_INTR_EDGE_FALLING: 711 rk_gpio_write_bit(sc, RK_GPIO_SWPORTA_DDR, pin, 0); 712 rk_gpio_write_bit(sc, RK_GPIO_INTTYPE_LEVEL, pin, 1); 713 rk_gpio_write_bit(sc, RK_GPIO_INT_POLARITY, pin, 0); 714 break; 715 case GPIO_INTR_EDGE_BOTH: 716 rk_gpio_write_bit(sc, RK_GPIO_SWPORTA_DDR, pin, 0); 717 rk_gpio_write_bit(sc, RK_GPIO_INTTYPE_LEVEL, pin, 1); 718 if (sc->version == RK_GPIO_TYPE_V1) { 719 if (rk_gpio_read_bit(sc, RK_GPIO_EXT_PORTA, pin)) 720 rk_gpio_write_bit(sc, RK_GPIO_INT_POLARITY, 721 pin, 0); 722 else 723 rk_gpio_write_bit(sc, RK_GPIO_INT_POLARITY, 724 pin, 1); 725 } else 726 rk_gpio_write_bit(sc, RK_GPIO_INTTYPE_BOTH, pin, 1); 727 break; 728 case GPIO_INTR_LEVEL_HIGH: 729 rk_gpio_write_bit(sc, RK_GPIO_SWPORTA_DDR, pin, 0); 730 rk_gpio_write_bit(sc, RK_GPIO_INTTYPE_LEVEL, pin, 0); 731 rk_gpio_write_bit(sc, RK_GPIO_INT_POLARITY, pin, 1); 732 break; 733 case GPIO_INTR_LEVEL_LOW: 734 rk_gpio_write_bit(sc, RK_GPIO_SWPORTA_DDR, pin, 0); 735 rk_gpio_write_bit(sc, RK_GPIO_INTTYPE_LEVEL, pin, 0); 736 rk_gpio_write_bit(sc, RK_GPIO_INT_POLARITY, pin, 0); 737 break; 738 default: 739 rk_gpio_write_bit(sc, RK_GPIO_INTMASK, pin, 1); 740 rk_gpio_write_bit(sc, RK_GPIO_INTEN, pin, 0); 741 RK_GPIO_UNLOCK(sc); 742 return (EINVAL); 743 } 744 rk_gpio_write_bit(sc, RK_GPIO_DEBOUNCE, pin, 1); 745 rk_gpio_write_bit(sc, RK_GPIO_INTMASK, pin, 0); 746 rk_gpio_write_bit(sc, RK_GPIO_INTEN, pin, 1); 747 RK_GPIO_UNLOCK(sc); 748 749 return (0); 750 } 751 752 static int 753 rk_pic_teardown_intr(device_t dev, struct intr_irqsrc *isrc, 754 struct resource *res, struct intr_map_data *data) 755 { 756 struct rk_gpio_softc *sc = device_get_softc(dev); 757 struct rk_pin_irqsrc *irqsrc; 758 759 irqsrc = (struct rk_pin_irqsrc *)isrc; 760 761 if (isrc->isrc_handlers == 0) { 762 irqsrc->mode = GPIO_INTR_CONFORM; 763 RK_GPIO_LOCK(sc); 764 rk_gpio_write_bit(sc, RK_GPIO_INTEN, irqsrc->irq, 0); 765 rk_gpio_write_bit(sc, RK_GPIO_INTMASK, irqsrc->irq, 0); 766 rk_gpio_write_bit(sc, RK_GPIO_DEBOUNCE, irqsrc->irq, 0); 767 RK_GPIO_UNLOCK(sc); 768 } 769 return (0); 770 } 771 772 static device_method_t rk_gpio_methods[] = { 773 /* Device interface */ 774 DEVMETHOD(device_probe, rk_gpio_probe), 775 DEVMETHOD(device_attach, rk_gpio_attach), 776 DEVMETHOD(device_detach, rk_gpio_detach), 777 778 /* GPIO protocol */ 779 DEVMETHOD(gpio_get_bus, rk_gpio_get_bus), 780 DEVMETHOD(gpio_pin_max, rk_gpio_pin_max), 781 DEVMETHOD(gpio_pin_getname, rk_gpio_pin_getname), 782 DEVMETHOD(gpio_pin_getflags, rk_gpio_pin_getflags), 783 DEVMETHOD(gpio_pin_getcaps, rk_gpio_pin_getcaps), 784 DEVMETHOD(gpio_pin_setflags, rk_gpio_pin_setflags), 785 DEVMETHOD(gpio_pin_get, rk_gpio_pin_get), 786 DEVMETHOD(gpio_pin_set, rk_gpio_pin_set), 787 DEVMETHOD(gpio_pin_toggle, rk_gpio_pin_toggle), 788 DEVMETHOD(gpio_pin_access_32, rk_gpio_pin_access_32), 789 DEVMETHOD(gpio_pin_config_32, rk_gpio_pin_config_32), 790 DEVMETHOD(gpio_map_gpios, rk_gpio_map_gpios), 791 792 /* Interrupt controller interface */ 793 DEVMETHOD(pic_map_intr, rk_pic_map_intr), 794 DEVMETHOD(pic_setup_intr, rk_pic_setup_intr), 795 DEVMETHOD(pic_teardown_intr, rk_pic_teardown_intr), 796 797 /* ofw_bus interface */ 798 DEVMETHOD(ofw_bus_get_node, rk_gpio_get_node), 799 800 DEVMETHOD_END 801 }; 802 803 static driver_t rk_gpio_driver = { 804 "gpio", 805 rk_gpio_methods, 806 sizeof(struct rk_gpio_softc), 807 }; 808 809 /* 810 * GPIO driver is always a child of rk_pinctrl driver and should be probed 811 * and attached within rk_pinctrl_attach function. Due to this, bus pass order 812 * must be same as bus pass order of rk_pinctrl driver. 813 */ 814 EARLY_DRIVER_MODULE(rk_gpio, simplebus, rk_gpio_driver, 0, 0, 815 BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE); 816