1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2021, 2022 Soren Schmidt <sos@deepcore.dk> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 */ 28 29 #include <sys/param.h> 30 #include <sys/bus.h> 31 #include <sys/kernel.h> 32 #include <sys/module.h> 33 #include <sys/mutex.h> 34 #include <sys/rman.h> 35 #include <machine/bus.h> 36 37 #include <dev/ofw/openfirm.h> 38 #include <dev/ofw/ofw_bus.h> 39 #include <dev/ofw/ofw_bus_subr.h> 40 41 #include <dev/fdt/simple_mfd.h> 42 43 #include <dev/extres/clk/clk.h> 44 #include <dev/extres/hwreset/hwreset.h> 45 #include <dev/extres/regulator/regulator.h> 46 #include <dev/extres/syscon/syscon.h> 47 #include <dev/extres/phy/phy.h> 48 49 #include <contrib/device-tree/include/dt-bindings/phy/phy.h> 50 51 #include "syscon_if.h" 52 #include "phydev_if.h" 53 #include "phynode_if.h" 54 55 #define GRF_PCIE30PHY_CON1 0x04 56 #define GRF_PCIE30PHY_CON4 0x10 57 #define GRF_PCIE30PHY_CON5 0x14 58 #define GRF_PCIE30PHY_CON6 0x18 59 #define GRF_PCIE30PHY_WR_EN (0xf << 16) 60 #define GRF_PCIE30PHY_CON9 0x24 61 #define GRF_PCIE30PHY_DA_OCM ((1 << 15) | (1 << (15 + 16))) 62 #define GRF_PCIE30PHY_STATUS0 0x80 63 #define SRAM_INIT_DONE (1 << 14) 64 65 static struct ofw_compat_data compat_data[] = { 66 {"rockchip,rk3568-pcie3-phy", 1}, 67 {NULL, 0} 68 }; 69 70 struct rk3568_pciephy_softc { 71 device_t dev; 72 phandle_t node; 73 struct resource *mem; 74 struct phynode *phynode; 75 struct syscon *phy_grf; 76 clk_t refclk_m; 77 clk_t refclk_n; 78 clk_t pclk; 79 hwreset_t phy_reset; 80 }; 81 82 83 /* PHY class and methods */ 84 static int 85 rk3568_pciephy_enable(struct phynode *phynode, bool enable) 86 { 87 device_t dev = phynode_get_device(phynode); 88 struct rk3568_pciephy_softc *sc = device_get_softc(dev); 89 uint32_t data_lanes[2] = { 0, 0 }; 90 int count; 91 92 if (enable) { 93 /* Deassert PCIe PMA output clamp mode */ 94 SYSCON_WRITE_4(sc->phy_grf, GRF_PCIE30PHY_CON9, 95 GRF_PCIE30PHY_DA_OCM); 96 97 /* Set bifurcation according to DT entry */ 98 if (OF_hasprop(sc->node, "data-lanes")) { 99 OF_getencprop(sc->node, "data-lanes", data_lanes, 100 sizeof(data_lanes)); 101 if (data_lanes[0] > 0) { 102 SYSCON_WRITE_4(sc->phy_grf, GRF_PCIE30PHY_CON5, 103 GRF_PCIE30PHY_WR_EN | (data_lanes[0] - 1)); 104 device_printf(dev, "pcie3x1 1 lane\n"); 105 } 106 if (data_lanes[1] > 0) { 107 SYSCON_WRITE_4(sc->phy_grf, GRF_PCIE30PHY_CON6, 108 GRF_PCIE30PHY_WR_EN | (data_lanes[1] - 1)); 109 device_printf(dev, "pcie3x2 1 lane\n"); 110 } 111 if (data_lanes[0] > 1 || data_lanes[1] > 1) 112 SYSCON_WRITE_4(sc->phy_grf, GRF_PCIE30PHY_CON1, 113 GRF_PCIE30PHY_DA_OCM); 114 115 } else { 116 SYSCON_WRITE_4(sc->phy_grf, GRF_PCIE30PHY_CON5, 117 GRF_PCIE30PHY_WR_EN); 118 SYSCON_WRITE_4(sc->phy_grf, GRF_PCIE30PHY_CON6, 119 GRF_PCIE30PHY_WR_EN); 120 device_printf(dev, "pcie3 2 lanes\n"); 121 } 122 123 hwreset_deassert(sc->phy_reset); 124 125 /* Poll for SRAM loaded and ready */ 126 for (count = 100; count; count--) { 127 if (SYSCON_READ_4(sc->phy_grf, GRF_PCIE30PHY_STATUS0) & 128 SRAM_INIT_DONE) 129 break; 130 DELAY(10000); 131 if (count == 0) { 132 device_printf(dev, "SRAM init timeout!\n"); 133 return (ENXIO); 134 } 135 } 136 } 137 return (0); 138 } 139 140 static phynode_method_t rk3568_pciephy_phynode_methods[] = { 141 PHYNODEMETHOD(phynode_enable, rk3568_pciephy_enable), 142 143 PHYNODEMETHOD_END 144 }; 145 DEFINE_CLASS_1(rk3568_pciephy_phynode, rk3568_pciephy_phynode_class, 146 rk3568_pciephy_phynode_methods, 0, phynode_class); 147 148 149 /* Device class and methods */ 150 static int 151 rk3568_pciephy_probe(device_t dev) 152 { 153 154 if (!ofw_bus_status_okay(dev)) 155 return (ENXIO); 156 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 157 return (ENXIO); 158 device_set_desc(dev, "RockChip PCIe PHY"); 159 return (BUS_PROBE_DEFAULT); 160 } 161 162 static int 163 rk3568_pciephy_attach(device_t dev) 164 { 165 struct rk3568_pciephy_softc *sc = device_get_softc(dev); 166 struct phynode_init_def phy_init; 167 struct phynode *phynode; 168 int rid = 0; 169 170 sc->dev = dev; 171 sc->node = ofw_bus_get_node(dev); 172 173 /* Get memory resource */ 174 if (!(sc->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 175 RF_ACTIVE))) { 176 device_printf(dev, "Cannot allocate memory resources\n"); 177 return (ENXIO); 178 } 179 180 /* Get syncons handle */ 181 if (OF_hasprop(sc->node, "rockchip,phy-grf") && 182 syscon_get_by_ofw_property(dev, sc->node, "rockchip,phy-grf", 183 &sc->phy_grf)) 184 return (ENXIO); 185 186 /* Get & enable clocks */ 187 if (clk_get_by_ofw_name(dev, 0, "refclk_m", &sc->refclk_m)) { 188 device_printf(dev, "getting refclk_m failed\n"); 189 return (ENXIO); 190 } 191 if (clk_enable(sc->refclk_m)) 192 device_printf(dev, "enable refclk_m failed\n"); 193 if (clk_get_by_ofw_name(dev, 0, "refclk_n", &sc->refclk_n)) { 194 device_printf(dev, "getting refclk_n failed\n"); 195 return (ENXIO); 196 } 197 if (clk_enable(sc->refclk_n)) 198 device_printf(dev, "enable refclk_n failed\n"); 199 if (clk_get_by_ofw_name(dev, 0, "pclk", &sc->pclk)) { 200 device_printf(dev, "getting pclk failed\n"); 201 return (ENXIO); 202 } 203 if (clk_enable(sc->pclk)) 204 device_printf(dev, "enable pclk failed\n"); 205 206 /* Get & assert reset */ 207 if (hwreset_get_by_ofw_idx(dev, sc->node, 0, &sc->phy_reset)) { 208 device_printf(dev, "Cannot get reset\n"); 209 } 210 else 211 hwreset_assert(sc->phy_reset); 212 213 /* Set RC/EP mode not implemented yet (RC mode only) */ 214 215 bzero(&phy_init, sizeof(phy_init)); 216 phy_init.id = PHY_NONE; 217 phy_init.ofw_node = sc->node; 218 if (!(phynode = phynode_create(dev, &rk3568_pciephy_phynode_class, 219 &phy_init))) { 220 device_printf(dev, "failed to create pciephy PHY\n"); 221 return (ENXIO); 222 } 223 if (!phynode_register(phynode)) { 224 device_printf(dev, "failed to register pciephy PHY\n"); 225 return (ENXIO); 226 } 227 sc->phynode = phynode; 228 229 return (0); 230 } 231 232 static device_method_t rk3568_pciephy_methods[] = { 233 DEVMETHOD(device_probe, rk3568_pciephy_probe), 234 DEVMETHOD(device_attach, rk3568_pciephy_attach), 235 236 DEVMETHOD_END 237 }; 238 239 DEFINE_CLASS_1(rk3568_pciephy, rk3568_pciephy_driver, rk3568_pciephy_methods, 240 sizeof(struct simple_mfd_softc), simple_mfd_driver); 241 EARLY_DRIVER_MODULE(rk3568_pciephy, simplebus, rk3568_pciephy_driver, 242 0, 0, BUS_PASS_RESOURCE + BUS_PASS_ORDER_LATE); 243