1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2021, 2022 Soren Schmidt <sos@deepcore.dk> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer, 11 * without modification, immediately at the beginning of the file. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 * 27 */ 28 29 #include <sys/param.h> 30 #include <sys/systm.h> 31 #include <sys/endian.h> 32 #include <sys/kernel.h> 33 #include <sys/module.h> 34 #include <sys/bus.h> 35 #include <sys/proc.h> 36 #include <sys/rman.h> 37 #include <sys/intr.h> 38 #include <sys/mutex.h> 39 #include <sys/gpio.h> 40 41 #include <dev/gpio/gpiobusvar.h> 42 #include <dev/ofw/ofw_bus.h> 43 #include <dev/ofw/ofw_bus_subr.h> 44 #include <dev/ofw/ofw_pci.h> 45 #include <dev/ofw/ofwpci.h> 46 47 #include <dev/pci/pcivar.h> 48 #include <dev/pci/pcireg.h> 49 #include <dev/pci/pcib_private.h> 50 #include <dev/pci/pci_dw.h> 51 52 #include <dev/clk/clk.h> 53 #include <dev/phy/phy.h> 54 #include <dev/regulator/regulator.h> 55 #include <dev/hwreset/hwreset.h> 56 57 #include <machine/bus.h> 58 #include <machine/intr.h> 59 60 #include <vm/vm.h> 61 #include <vm/vm_extern.h> 62 #include <vm/vm_kern.h> 63 #include <vm/pmap.h> 64 65 #include "pcib_if.h" 66 67 /* APB Registers */ 68 #define PCIE_CLIENT_GENERAL_CON 0x0000 69 #define DEVICE_TYPE_MASK 0x00f0 70 #define DEVICE_TYPE_RC (1<<6) 71 #define LINK_REQ_RST_GRT (1<<3) 72 #define LTSSM_ENABLE (1<<2) 73 #define PCIE_CLIENT_INTR_MASK_MSG_RX 0x0018 74 #define PCIE_CLIENT_INTR_MASK_LEGACY 0x001c 75 #define PCIE_CLIENT_INTR_MASK_ERR 0x0020 76 #define PCIE_CLIENT_INTR_MASK_MISC 0x0024 77 #define PCIE_CLIENT_INTR_MASK_PMC 0x0028 78 #define PCIE_CLIENT_GENERAL_DEBUG_INFO 0x0104 79 #define PCIE_CLIENT_HOT_RESET_CTRL 0x0180 80 #define APP_LSSTM_ENABLE_ENHANCE (1<<4) 81 #define PCIE_CLIENT_LTSSM_STATUS 0x0300 82 #define RDLH_LINK_UP (1<<17) 83 #define SMLH_LINK_UP (1<<16) 84 #define SMLH_LTSSM_STATE_MASK 0x003f 85 #define SMLH_LTSSM_STATE_LINK_UP ((1<<4) | (1<<0)) 86 87 struct rk3568_pcie_softc { 88 struct pci_dw_softc dw_sc; /* Must be first */ 89 device_t dev; 90 int apb_rid; 91 struct resource *apb_res; 92 int dbi_rid; 93 struct resource *dbi_res; 94 int irq_rid; 95 struct resource *irq_res; 96 void *irq_handle; 97 phandle_t node; 98 struct gpiobus_pin *reset_gpio; 99 clk_t aclk_mst, aclk_slv, aclk_dbi, pclk, aux; 100 regulator_t regulator; 101 hwreset_t hwreset; 102 phy_t phy; 103 }; 104 105 static struct ofw_compat_data compat_data[] = { 106 {"rockchip,rk3568-pcie", 1}, 107 {NULL, 0} 108 }; 109 110 111 static void 112 rk3568_intr(void *data) 113 { 114 struct rk3568_pcie_softc *sc = data; 115 116 device_printf(sc->dev, "INTERRUPT!!\n"); 117 } 118 119 static int 120 rk3568_pcie_get_link(device_t dev, bool *status) 121 { 122 struct rk3568_pcie_softc *sc = device_get_softc(dev); 123 uint32_t val; 124 125 val = bus_read_4(sc->apb_res, PCIE_CLIENT_LTSSM_STATUS); 126 if (((val & (RDLH_LINK_UP | SMLH_LINK_UP)) == 127 (RDLH_LINK_UP | SMLH_LINK_UP)) && 128 ((val & SMLH_LTSSM_STATE_MASK) == SMLH_LTSSM_STATE_LINK_UP)) 129 *status = true; 130 else 131 *status = false; 132 return (0); 133 } 134 135 static int 136 rk3568_pcie_init_soc(device_t dev) 137 { 138 struct rk3568_pcie_softc *sc = device_get_softc(dev); 139 int err, count; 140 bool status; 141 142 /* Assert PCIe reset */ 143 if (sc->reset_gpio != NULL) { 144 if (gpio_pin_setflags(sc->reset_gpio, GPIO_PIN_OUTPUT)) { 145 device_printf(dev, "Could not setup PCIe reset\n"); 146 return (ENXIO); 147 } 148 if (gpio_pin_set_active(sc->reset_gpio, true)) { 149 device_printf(dev, "Could not set PCIe reset\n"); 150 return (ENXIO); 151 } 152 } 153 154 /* Assert reset */ 155 if (hwreset_assert(sc->hwreset)) { 156 device_printf(dev, "Could not assert reset\n"); 157 return (ENXIO); 158 } 159 160 /* Powerup PCIe */ 161 if (sc->regulator != NULL) { 162 if (regulator_enable(sc->regulator)) { 163 device_printf(dev, "Cannot enable regulator\n"); 164 return (ENXIO); 165 } 166 } 167 168 /* Enable PHY */ 169 if (phy_enable(sc->phy)) { 170 device_printf(dev, "Cannot enable phy\n"); 171 return (ENXIO); 172 } 173 174 /* Deassert reset */ 175 if (hwreset_deassert(sc->hwreset)) { 176 device_printf(dev, "Could not deassert reset\n"); 177 return (ENXIO); 178 } 179 180 /* Enable clocks */ 181 if ((err = clk_enable(sc->aclk_mst))) { 182 device_printf(dev, "Could not enable aclk_mst clk\n"); 183 return (ENXIO); 184 } 185 if ((err = clk_enable(sc->aclk_slv))) { 186 device_printf(dev, "Could not enable aclk_slv clk\n"); 187 return (ENXIO); 188 } 189 if ((err = clk_enable(sc->aclk_dbi))) { 190 device_printf(dev, "Could not enable aclk_dbi clk\n"); 191 return (ENXIO); 192 } 193 if ((err = clk_enable(sc->pclk))) { 194 device_printf(dev, "Could not enable pclk clk\n"); 195 return (ENXIO); 196 } 197 if ((err = clk_enable(sc->aux))) { 198 device_printf(dev, "Could not enable aux clk\n"); 199 return (ENXIO); 200 } 201 202 /* Set Root Complex (RC) mode */ 203 bus_write_4(sc->apb_res, PCIE_CLIENT_HOT_RESET_CTRL, 204 (APP_LSSTM_ENABLE_ENHANCE << 16) | APP_LSSTM_ENABLE_ENHANCE); 205 bus_write_4(sc->apb_res, PCIE_CLIENT_GENERAL_CON, 206 (DEVICE_TYPE_MASK << 16) | DEVICE_TYPE_RC); 207 208 /* Deassert PCIe reset */ 209 if ((err = gpio_pin_set_active(sc->reset_gpio, false))) 210 device_printf(dev, "reset_gpio set failed\n"); 211 212 /* Start Link Training and Status State Machine (LTSSM) */ 213 bus_write_4(sc->apb_res, PCIE_CLIENT_GENERAL_CON, 214 (LINK_REQ_RST_GRT | LTSSM_ENABLE) << 16 | 215 (LINK_REQ_RST_GRT | LTSSM_ENABLE)); 216 DELAY(100000); 217 218 /* Release PCIe reset */ 219 if (sc->reset_gpio != NULL) { 220 if (gpio_pin_set_active(sc->reset_gpio, true)) { 221 device_printf(dev, "Could not release PCIe reset"); 222 return (ENXIO); 223 } 224 } 225 226 /* Wait for link up/stable */ 227 for (count = 20; count; count--) { 228 rk3568_pcie_get_link(dev, &status); 229 if (status) 230 break; 231 DELAY(100000); 232 if (count == 0) { 233 device_printf(dev, "Link up timeout!\n"); 234 return (ENXIO); 235 } 236 } 237 238 if ((err = pci_dw_init(dev))) 239 return (ENXIO); 240 241 /* Delay to have things settle */ 242 DELAY(100000); 243 244 /* Enable all MSG interrupts */ 245 bus_write_4(sc->apb_res, PCIE_CLIENT_INTR_MASK_MSG_RX, 0x7fff0000); 246 247 /* Enable all Legacy interrupts */ 248 bus_write_4(sc->apb_res, PCIE_CLIENT_INTR_MASK_LEGACY, 0x00ff0000); 249 250 /* Enable all Error interrupts */ 251 bus_write_4(sc->apb_res, PCIE_CLIENT_INTR_MASK_ERR, 0x0fff0000); 252 253 return (0); 254 } 255 256 static int 257 rk3568_pcie_detach(device_t dev) 258 { 259 struct rk3568_pcie_softc *sc = device_get_softc(dev); 260 261 /* Release allocated resources */ 262 if (sc->irq_handle) 263 bus_teardown_intr(dev, sc->irq_res, sc->irq_handle); 264 if (sc->phy) 265 phy_release(sc->phy); 266 if (sc->aux) 267 clk_release(sc->aux); 268 if (sc->pclk) 269 clk_release(sc->pclk); 270 if (sc->aclk_dbi) 271 clk_release(sc->aclk_dbi); 272 if (sc->aclk_slv) 273 clk_release(sc->aclk_slv); 274 if (sc->aclk_mst) 275 clk_release(sc->aclk_mst); 276 if (sc->hwreset) 277 hwreset_release(sc->hwreset); 278 if (sc->regulator) 279 regulator_release(sc->regulator); 280 if (sc->irq_res) 281 bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid, 282 sc->irq_res); 283 if (sc->dbi_res) 284 bus_release_resource(dev, SYS_RES_MEMORY, sc->dbi_rid, 285 sc->dbi_res); 286 if (sc->apb_res) 287 bus_release_resource(dev, SYS_RES_MEMORY, sc->apb_rid, 288 sc->apb_res); 289 return (0); 290 } 291 292 static int 293 rk3568_pcie_attach(device_t dev) 294 { 295 struct rk3568_pcie_softc *sc = device_get_softc(dev); 296 int error; 297 298 sc->dev = dev; 299 sc->node = ofw_bus_get_node(dev); 300 301 /* Setup resources */ 302 if ((error = ofw_bus_find_string_index(sc->node, "reg-names", "apb", 303 &sc->apb_rid))) { 304 device_printf(dev, "Cannot get APB memory: %d\n", error); 305 goto fail; 306 } 307 if (!(sc->apb_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 308 &sc->apb_rid, RF_ACTIVE))) { 309 device_printf(dev, "Cannot allocate APB resource\n"); 310 goto fail; 311 } 312 if ((error = ofw_bus_find_string_index(sc->node, "reg-names", "dbi", 313 &sc->dbi_rid))) { 314 device_printf(dev, "Cannot get DBI memory: %d\n", error); 315 goto fail; 316 } 317 if (!(sc->dw_sc.dbi_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 318 &sc->dbi_rid, RF_ACTIVE))) { 319 device_printf(dev, "Cannot allocate DBI resource\n"); 320 goto fail; 321 } 322 323 if (!(sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 324 &sc->irq_rid, RF_ACTIVE | RF_SHAREABLE))) { 325 device_printf(dev, "Cannot allocate IRQ resource\n"); 326 goto fail; 327 } 328 329 /* Get regulator if present */ 330 error = regulator_get_by_ofw_property(dev, 0, "vpcie3v3-supply", 331 &sc->regulator); 332 if (error != 0 && error != ENOENT) { 333 device_printf(dev, "Cannot get regulator\n"); 334 goto fail; 335 } 336 337 /* Get reset */ 338 if (hwreset_get_by_ofw_name(dev, 0, "pipe", &sc->hwreset)) { 339 device_printf(dev, "Can not get reset\n"); 340 goto fail; 341 } 342 343 /* Get GPIO reset */ 344 error = gpio_pin_get_by_ofw_property(dev, sc->node, "reset-gpios", 345 &sc->reset_gpio); 346 if (error != 0 && error != ENOENT) { 347 device_printf(dev, "Cannot get reset-gpios\n"); 348 goto fail; 349 } 350 351 /* Get clocks */ 352 if (clk_get_by_ofw_name(dev, 0, "aclk_mst", &sc->aclk_mst)) { 353 device_printf(dev, "Can not get aclk_mst clk\n"); 354 goto fail; 355 } 356 if (clk_get_by_ofw_name(dev, 0, "aclk_slv", &sc->aclk_slv)) { 357 device_printf(dev, "Can not get aclk_slv clk\n"); 358 goto fail; 359 } 360 if (clk_get_by_ofw_name(dev, 0, "aclk_dbi", &sc->aclk_dbi)) { 361 device_printf(dev, "Can not get aclk_dbi clk\n"); 362 goto fail; 363 } 364 if (clk_get_by_ofw_name(dev, 0, "pclk", &sc->pclk)) { 365 device_printf(dev, "Can not get pclk clk\n"); 366 goto fail; 367 } 368 if (clk_get_by_ofw_name(dev, 0, "aux", &sc->aux)) { 369 device_printf(dev, "Can not get aux clk\n"); 370 goto fail; 371 } 372 373 /* Get PHY */ 374 if (phy_get_by_ofw_name(dev, 0, "pcie-phy", &sc->phy)) { 375 device_printf(dev, "Cannot get 'pcie-phy'\n"); 376 goto fail; 377 } 378 379 if ((error = rk3568_pcie_init_soc(dev))) 380 goto fail; 381 382 /* Enable interrupt */ 383 if ((bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 384 NULL, rk3568_intr, sc, &sc->irq_handle))) { 385 device_printf(dev, "unable to setup interrupt\n"); 386 goto fail; 387 } 388 389 bus_attach_children(dev); 390 return (0); 391 fail: 392 rk3568_pcie_detach(dev); 393 return (ENXIO); 394 } 395 396 static int 397 rk3568_pcie_probe(device_t dev) 398 { 399 400 if (!ofw_bus_status_okay(dev)) 401 return (ENXIO); 402 if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data) 403 return (ENXIO); 404 device_set_desc(dev, "RockChip RK3568 PCI-express controller"); 405 return (BUS_PROBE_DEFAULT); 406 } 407 408 static device_method_t rk3568_pcie_methods[] = { 409 /* Device interface */ 410 DEVMETHOD(device_probe, rk3568_pcie_probe), 411 DEVMETHOD(device_attach, rk3568_pcie_attach), 412 DEVMETHOD(device_detach, rk3568_pcie_detach), 413 414 /* PCI DW interface */ 415 DEVMETHOD(pci_dw_get_link, rk3568_pcie_get_link), 416 417 DEVMETHOD_END 418 }; 419 420 DEFINE_CLASS_1(pcib, rk3568_pcie_driver, rk3568_pcie_methods, 421 sizeof(struct rk3568_pcie_softc), pci_dw_driver); 422 DRIVER_MODULE(rk3568_pcie, simplebus, rk3568_pcie_driver, NULL, NULL); 423