xref: /freebsd/sys/arm64/rockchip/rk3568_combphy.c (revision 90737b632ee50f5275ea12498841883f7d739267)
1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause
3  *
4  * Copyright (c) 2021, 2022 Soren Schmidt <sos@deepcore.dk>
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions
8  * are met:
9  * 1. Redistributions of source code must retain the above copyright
10  *    notice, this list of conditions and the following disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  *
15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25  * SUCH DAMAGE.
26  *
27  */
28 
29 #include <sys/cdefs.h>
30 #include <sys/param.h>
31 #include <sys/bus.h>
32 #include <sys/kernel.h>
33 #include <sys/module.h>
34 #include <sys/mutex.h>
35 #include <sys/rman.h>
36 #include <machine/bus.h>
37 
38 #include <dev/ofw/openfirm.h>
39 #include <dev/ofw/ofw_bus.h>
40 #include <dev/ofw/ofw_bus_subr.h>
41 
42 #include <dev/fdt/simple_mfd.h>
43 
44 #include <dev/extres/clk/clk.h>
45 #include <dev/extres/hwreset/hwreset.h>
46 #include <dev/extres/regulator/regulator.h>
47 #include <dev/extres/syscon/syscon.h>
48 #include <dev/extres/phy/phy.h>
49 
50 #include <contrib/device-tree/include/dt-bindings/phy/phy.h>
51 
52 #include "syscon_if.h"
53 #include "phydev_if.h"
54 #include "phynode_if.h"
55 
56 
57 static struct ofw_compat_data compat_data[] = {
58 	{"rockchip,rk3568-naneng-combphy",	1},
59 	{NULL, 0}
60 };
61 
62 struct rk3568_combphy_softc {
63 	device_t	dev;
64 	phandle_t	node;
65 	struct resource	*mem;
66 	struct phynode	*phynode;
67 	struct syscon	*pipe_grf;
68 	struct syscon	*pipe_phy_grf;
69 	clk_t		ref_clk;
70 	clk_t		apb_clk;
71 	clk_t		pipe_clk;
72 	hwreset_t	phy_reset;
73 	int		mode;
74 };
75 
76 #define	PHYREG6				0x14
77 #define	 PHYREG6_PLL_DIV_MASK			0xc0
78 #define	 PHYREG6_PLL_DIV_2			(1 << 6)
79 #define	PHYREG7				0x18
80 #define	 PHYREG7_TX_RTERM_50OHM			(8 << 4)
81 #define	 PHYREG7_RX_RTERM_44OHM			(15 << 0)
82 #define	PHYREG8				0x1c
83 #define	 PHYREG8_SSC_EN			0x10
84 #define	PHYREG11			0x28
85 #define	 PHYREG11_SU_TRIM_0_7			0xf0
86 #define	PHYREG12			0x2c
87 #define	 PHYREG12_PLL_LPF_ADJ_VALUE		4
88 #define	PHYREG15			0x38
89 #define	 PHYREG15_CTLE_EN			0x01
90 #define	 PHYREG15_SSC_CNT_MASK			0xc0
91 #define	 PHYREG15_SSC_CNT_VALUE			(1 << 6)
92 #define	PHYREG16			0x3c
93 #define	 PHYREG16_SSC_CNT_VALUE			0x5f
94 #define	PHYREG18			0x44
95 #define	 PHYREG18_PLL_LOOP			0x32
96 #define	PHYREG32			0x7c
97 #define	 PHYREG32_SSC_MASK			0xf0
98 #define	 PHYREG32_SSC_UPWARD			(0 << 4)
99 #define	 PHYREG32_SSC_DOWNWARD			(1 << 4)
100 #define	 PHYREG32_SSC_OFFSET_500PPM		(1 << 6)
101 #define	PHYREG33			0x80
102 #define	 PHYREG33_PLL_KVCO_MASK			0x1c
103 #define	 PHYREG33_PLL_KVCO_VALUE		(2 << 2)
104 
105 #define	PIPE_MASK_ALL			(0xffff << 16)
106 #define	PIPE_PHY_GRF_PIPE_CON0		0x00
107 #define	 PIPE_DATABUSWIDTH_MASK			0x3
108 #define	 PIPE_DATABUSWIDTH_32BIT		0
109 #define	 PIPE_DATABUSWIDTH_16BIT		1
110 #define	 PIPE_PHYMODE_MASK			(3 << 2)
111 #define	 PIPE_PHYMODE_PCIE			(0 << 2)
112 #define	 PIPE_PHYMODE_USB3			(1 << 2)
113 #define	 PIPE_PHYMODE_SATA			(2 << 2)
114 #define	 PIPE_RATE_MASK				(3 << 4)
115 #define	 PIPE_RATE_PCIE_2_5GBPS			(0 << 4)
116 #define	 PIPE_RATE_PCIE_5GBPS			(1 << 4)
117 #define	 PIPE_RATE_USB3_5GBPS			(0 << 4)
118 #define	 PIPE_RATE_SATA_1GBPS5			(0 << 4)
119 #define	 PIPE_RATE_SATA_3GBPS			(1 << 4)
120 #define	 PIPE_RATE_SATA_6GBPS			(2 << 4)
121 #define	 PIPE_MAC_PCLKREQ_N			(1 << 8)
122 #define	 PIPE_L1SUB_ENTREQ			(1 << 9)
123 #define	 PIPE_RXTERM				(1 << 12)
124 #define	PIPE_PHY_GRF_PIPE_CON1		0x04
125 #define	 PHY_CLK_SEL_MASK			(3 << 13)
126 #define	 PHY_CLK_SEL_24M			(0 << 13)
127 #define	 PHY_CLK_SEL_25M			(1 << 13)
128 #define	 PHY_CLK_SEL_100M			(2 << 13)
129 #define	PIPE_PHY_GRF_PIPE_CON2		0x08
130 #define	 SEL_PIPE_TXCOMPLIANCE_I		(1 << 15)
131 #define	 SEL_PIPE_TXELECIDLE			(1 << 12)
132 #define	 SEL_PIPE_RXTERM			(1 << 8)
133 #define	 SEL_PIPE_BYPASS_CODEC			(1 << 7)
134 #define	 SEL_PIPE_PIPE_EBUF			(1 << 6)
135 #define	 SEL_PIPE_PIPE_PHYMODE			(1 << 1)
136 #define	 SEL_PIPE_DATABUSWIDTH			(1 << 0)
137 #define	PIPE_PHY_GRF_PIPE_CON3		0x0c
138 #define	 PIPE_SEL_MASK				(3 << 13)
139 #define	 PIPE_SEL_PCIE				(0 << 13)
140 #define	 PIPE_SEL_USB3				(1 << 13)
141 #define	 PIPE_SEL_SATA				(2 << 13)
142 #define	 PIPE_CLK_REF_SRC_I_MASK		(3 << 8)
143 #define	 PIPE_CLK_REF_SRC_I_PLL_CKREF_INNER	(2 << 8)
144 #define	 PIPE_RXELECIDLE			(1 << 10)
145 #define	 PIPE_FROM_PCIE_IO			(1 << 11)
146 
147 #define	PIPE_GRF_PIPE_CON0		0x00
148 #define	 SATA2_PHY_SPDMODE_1GBPS5		(0 << 12)
149 #define	 SATA2_PHY_SPDMODE_3GBPS		(1 << 12)
150 #define	 SATA2_PHY_SPDMODE_6GBPS		(2 << 12)
151 #define	 SATA1_PHY_SPDMODE_1GBPS5		(0 << 8)
152 #define	 SATA1_PHY_SPDMODE_3GBPS		(1 << 8)
153 #define	 SATA1_PHY_SPDMODE_6GBPS		(2 << 8)
154 #define	 SATA0_PHY_SPDMODE_1GBPS5		(0 << 4)
155 #define	 SATA0_PHY_SPDMODE_3GBPS		(1 << 4)
156 #define	 SATA0_PHY_SPDMODE_6GBPS		(2 << 4)
157 
158 #define	PIPE_GRF_SATA_CON0		0x10
159 #define	PIPE_GRF_SATA_CON1		0x14
160 #define	PIPE_GRF_SATA_CON2		0x18
161 #define	PIPE_GRF_XPCS_CON0		0x40
162 
163 
164 /* PHY class and methods */
165 static int
166 rk3568_combphy_enable(struct phynode *phynode, bool enable)
167 {
168 	device_t dev = phynode_get_device(phynode);
169 	struct rk3568_combphy_softc *sc = device_get_softc(dev);
170 	uint64_t rate;
171 
172 	if (enable == false)
173 		return (0);
174 
175 	switch (sc->mode) {
176 	case PHY_TYPE_SATA:
177 		device_printf(dev, "configuring for SATA");
178 
179 		/* tx_rterm 50 ohm & rx_rterm 44 ohm */
180 		bus_write_4(sc->mem, PHYREG7,
181 		    PHYREG7_TX_RTERM_50OHM | PHYREG7_RX_RTERM_44OHM);
182 
183 		/* Adaptive CTLE */
184 		bus_write_4(sc->mem, PHYREG15,
185 		    bus_read_4(sc->mem, PHYREG15) | PHYREG15_CTLE_EN);
186 
187 		/* config grf_pipe for PCIe */
188 		SYSCON_WRITE_4(sc->pipe_phy_grf, PIPE_PHY_GRF_PIPE_CON3,
189 		    PIPE_MASK_ALL | PIPE_SEL_SATA | PIPE_RXELECIDLE | 0x7);
190 
191 		SYSCON_WRITE_4(sc->pipe_phy_grf, PIPE_PHY_GRF_PIPE_CON2,
192 		    PIPE_MASK_ALL | SEL_PIPE_TXCOMPLIANCE_I |
193 		    SEL_PIPE_DATABUSWIDTH | 0xc3);
194 
195 		SYSCON_WRITE_4(sc->pipe_phy_grf, PIPE_PHY_GRF_PIPE_CON0,
196 		    PIPE_MASK_ALL | PIPE_RXTERM | PIPE_DATABUSWIDTH_16BIT |
197 		    PIPE_RATE_SATA_3GBPS | PIPE_PHYMODE_SATA);
198 
199 		SYSCON_WRITE_4(sc->pipe_grf, PIPE_GRF_PIPE_CON0,
200 		    PIPE_MASK_ALL | SATA0_PHY_SPDMODE_6GBPS |
201 		    SATA1_PHY_SPDMODE_6GBPS | SATA2_PHY_SPDMODE_6GBPS);
202 		break;
203 
204 	case PHY_TYPE_PCIE:
205 		device_printf(dev, "configuring for PCIe");
206 
207 		/* Set SSC downward spread spectrum */
208 		bus_write_4(sc->mem, PHYREG32,
209 		    (bus_read_4(sc->mem, PHYREG32) & PHYREG32_SSC_MASK) |
210 		    PHYREG32_SSC_DOWNWARD);
211 
212 		/* config grf_pipe for PCIe */
213 		SYSCON_WRITE_4(sc->pipe_phy_grf, PIPE_PHY_GRF_PIPE_CON3,
214 		    PIPE_MASK_ALL | PIPE_SEL_PCIE |
215 		    PIPE_CLK_REF_SRC_I_PLL_CKREF_INNER);
216 		SYSCON_WRITE_4(sc->pipe_phy_grf, PIPE_PHY_GRF_PIPE_CON2,
217 		    PIPE_MASK_ALL | SEL_PIPE_RXTERM | SEL_PIPE_DATABUSWIDTH);
218 		SYSCON_WRITE_4(sc->pipe_phy_grf, PIPE_PHY_GRF_PIPE_CON0,
219 		    PIPE_MASK_ALL | PIPE_RXTERM | PIPE_DATABUSWIDTH_32BIT |
220 		    PIPE_RATE_PCIE_2_5GBPS | PIPE_PHYMODE_PCIE);
221 		break;
222 
223 	case PHY_TYPE_USB3:
224 		device_printf(dev, "configuring for USB3");
225 
226 		/* Set SSC downward spread spectrum */
227 		bus_write_4(sc->mem, PHYREG32,
228 		    (bus_read_4(sc->mem, PHYREG32) & PHYREG32_SSC_MASK) |
229 		    PHYREG32_SSC_DOWNWARD);
230 
231 		/* Adaptive CTLE */
232 		bus_write_4(sc->mem, PHYREG15,
233 		    bus_read_4(sc->mem, PHYREG15) | PHYREG15_CTLE_EN);
234 
235 		/* Set PLL KVCO fine tuning signals */
236 		bus_write_4(sc->mem, PHYREG33,
237 		    (bus_read_4(sc->mem, PHYREG33) & PHYREG33_PLL_KVCO_MASK) |
238 		    PHYREG33_PLL_KVCO_VALUE);
239 
240 		/* Enable controlling random jitter. */
241 		bus_write_4(sc->mem, PHYREG12, PHYREG12_PLL_LPF_ADJ_VALUE);
242 
243 		/* Set PLL input clock divider 1/2 */
244 		bus_write_4(sc->mem, PHYREG6,
245 		    (bus_read_4(sc->mem, PHYREG6) & PHYREG6_PLL_DIV_MASK) |
246 		    PHYREG6_PLL_DIV_2);
247 
248 		/* Set PLL loop divider */
249 		bus_write_4(sc->mem, PHYREG18, PHYREG18_PLL_LOOP);
250 
251 		/* Set PLL LPF R1 to su_trim[0:7] */
252 		bus_write_4(sc->mem, PHYREG11, PHYREG11_SU_TRIM_0_7);
253 
254 		/* config grf_pipe for USB3 */
255 		SYSCON_WRITE_4(sc->pipe_phy_grf, PIPE_PHY_GRF_PIPE_CON3,
256 		    PIPE_MASK_ALL | PIPE_SEL_USB3);
257 		SYSCON_WRITE_4(sc->pipe_phy_grf, PIPE_PHY_GRF_PIPE_CON2,
258 		    PIPE_MASK_ALL);
259 		SYSCON_WRITE_4(sc->pipe_phy_grf, PIPE_PHY_GRF_PIPE_CON0,
260 		    PIPE_MASK_ALL | PIPE_DATABUSWIDTH_16BIT |
261 		    PIPE_PHYMODE_USB3 | PIPE_RATE_USB3_5GBPS);
262 		break;
263 
264 	default:
265 		printf("Unsupported mode=%d\n", sc->mode);
266 		return (-1);
267 	}
268 
269 	clk_get_freq(sc->ref_clk, &rate);
270 	printf(" ref_clk=%lu\n", rate);
271 
272 	switch (rate) {
273 	case 24000000:
274 		SYSCON_WRITE_4(sc->pipe_phy_grf, PIPE_PHY_GRF_PIPE_CON1,
275 		    (PHY_CLK_SEL_MASK << 16) | PHY_CLK_SEL_24M);
276 
277 		if (sc->mode == PHY_TYPE_USB3 || sc->mode == PHY_TYPE_SATA) {
278 			/* Adaptive CTLE */
279 			bus_write_4(sc->mem, PHYREG15,
280 			    (bus_read_4(sc->mem, PHYREG15) &
281 			    PHYREG15_SSC_CNT_MASK) | PHYREG15_SSC_CNT_VALUE);
282 
283 			/* SSC control period */
284 			bus_write_4(sc->mem, PHYREG16, PHYREG16_SSC_CNT_VALUE);
285 		}
286 		break;
287 
288 	case 25000000:
289 		SYSCON_WRITE_4(sc->pipe_phy_grf, PIPE_PHY_GRF_PIPE_CON1,
290 		    (PHY_CLK_SEL_MASK << 16) | PHY_CLK_SEL_25M);
291 		break;
292 
293 	case 100000000:
294 		SYSCON_WRITE_4(sc->pipe_phy_grf, PIPE_PHY_GRF_PIPE_CON1,
295 		    (PHY_CLK_SEL_MASK << 16) | PHY_CLK_SEL_100M);
296 
297 		if (sc->mode == PHY_TYPE_PCIE) {
298 			/* Set PLL KVCO fine tuning signals */
299 			bus_write_4(sc->mem, PHYREG33,
300 			    (bus_read_4(sc->mem, PHYREG33) &
301 			    PHYREG33_PLL_KVCO_MASK) | PHYREG33_PLL_KVCO_VALUE);
302 
303 			/* Enable controlling random jitter. */
304 			bus_write_4(sc->mem, PHYREG12,
305 			    PHYREG12_PLL_LPF_ADJ_VALUE);
306 
307 			/* Set PLL input clock divider 1/2 */
308 			bus_write_4(sc->mem, PHYREG6,
309 			    (bus_read_4(sc->mem, PHYREG6) &
310 			    PHYREG6_PLL_DIV_MASK) | PHYREG6_PLL_DIV_2);
311 
312 			/* Set PLL loop divider */
313 			bus_write_4(sc->mem, PHYREG18, PHYREG18_PLL_LOOP);
314 
315 			/* Set PLL LPF R1 to su_trim[0:7] */
316 			bus_write_4(sc->mem, PHYREG11, PHYREG11_SU_TRIM_0_7);
317 		}
318 		if (sc->mode == PHY_TYPE_SATA) {
319 			/* Set SSC downward spread spectrum */
320 			bus_write_4(sc->mem, PHYREG32,
321 			    (bus_read_4(sc->mem, PHYREG32) & ~0x000000f0) |
322 			    PHYREG32_SSC_DOWNWARD | PHYREG32_SSC_OFFSET_500PPM);
323 		}
324 		break;
325 
326 	default:
327 		device_printf(dev, "unknown ref rate=%lu\n", rate);
328 		break;
329 	}
330 
331 	if (OF_hasprop(sc->node, "rockchip,ext-refclk")) {
332 		device_printf(dev, "UNSUPPORTED rockchip,ext-refclk\n");
333 	}
334 	if (OF_hasprop(sc->node, "rockchip,enable-ssc")) {
335 		device_printf(dev, "setting rockchip,enable-ssc\n");
336 		bus_write_4(sc->mem, PHYREG8,
337 		    bus_read_4(sc->mem, PHYREG8) | PHYREG8_SSC_EN);
338 	}
339 
340 	if (hwreset_deassert(sc->phy_reset))
341 		device_printf(dev, "phy_reset failed to clear\n");
342 
343 	return (0);
344 }
345 
346 static phynode_method_t rk3568_combphy_phynode_methods[] = {
347 	PHYNODEMETHOD(phynode_enable,	rk3568_combphy_enable),
348 
349 	PHYNODEMETHOD_END
350 };
351 DEFINE_CLASS_1(rk3568_combphy_phynode, rk3568_combphy_phynode_class,
352     rk3568_combphy_phynode_methods, 0, phynode_class);
353 
354 
355 /* Device class and methods */
356 static int
357 rk3568_combphy_probe(device_t dev)
358 {
359 
360 	if (!ofw_bus_status_okay(dev))
361 		return (ENXIO);
362 	if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
363 		return (ENXIO);
364 	device_set_desc(dev, "RockChip combo PHY");
365 	return (BUS_PROBE_DEFAULT);
366 }
367 
368 static int
369 rk3568_combphy_attach(device_t dev)
370 {
371 	struct rk3568_combphy_softc *sc = device_get_softc(dev);
372 	struct phynode_init_def phy_init;
373 	struct phynode *phynode;
374 	int rid = 0;
375 
376 	sc->dev = dev;
377 	sc->node = ofw_bus_get_node(dev);
378 
379 	/* Get memory resource */
380 	if (!(sc->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
381 	    &rid, RF_ACTIVE))) {
382 		device_printf(dev, "Cannot allocate memory resources\n");
383 		return (ENXIO);
384 	}
385 
386 	/* Get syncons handles */
387 	if (OF_hasprop(sc->node, "rockchip,pipe-grf") &&
388 	    syscon_get_by_ofw_property(dev, sc->node, "rockchip,pipe-grf",
389 	    &sc->pipe_grf))
390 		return (ENXIO);
391 	if (OF_hasprop(sc->node, "rockchip,pipe-phy-grf") &&
392 	    syscon_get_by_ofw_property(dev, sc->node, "rockchip,pipe-phy-grf",
393 	    &sc->pipe_phy_grf))
394 		return (ENXIO);
395 
396 	/* Get & enable clocks */
397 	if (clk_get_by_ofw_name(dev, 0, "ref", &sc->ref_clk)) {
398 		device_printf(dev, "getting ref failed\n");
399 		return (ENXIO);
400 	}
401 	if (clk_enable(sc->ref_clk))
402 		device_printf(dev, "enable ref failed\n");
403 	if (clk_get_by_ofw_name(dev, 0, "apb", &sc->apb_clk)) {
404 		device_printf(dev, "getting apb failed\n");
405 		return (ENXIO);
406 	}
407 	if (clk_enable(sc->apb_clk))
408 		device_printf(dev, "enable apb failed\n");
409 	if (clk_get_by_ofw_name(dev, 0, "pipe", &sc->pipe_clk)) {
410 		device_printf(dev, "getting pipe failed\n");
411 		return (ENXIO);
412 	}
413 	if (clk_enable(sc->pipe_clk))
414 		device_printf(dev, "enable pipe failed\n");
415 
416 	/* get & assert reset */
417 	if (hwreset_get_by_ofw_idx(dev, sc->node, 0, &sc->phy_reset)) {
418 		device_printf(dev, "Cannot get reset\n");
419 		return (ENXIO);
420 	}
421 	hwreset_assert(sc->phy_reset);
422 
423 	bzero(&phy_init, sizeof(phy_init));
424 	phy_init.id = 0;
425 	phy_init.ofw_node = sc->node;
426 	if (!(phynode = phynode_create(dev, &rk3568_combphy_phynode_class,
427 	    &phy_init))) {
428 		device_printf(dev, "failed to create combphy PHY\n");
429 		return (ENXIO);
430 	}
431 	if (!phynode_register(phynode)) {
432 		device_printf(dev, "failed to register combphy PHY\n");
433 		return (ENXIO);
434 	}
435 	sc->phynode = phynode;
436 	sc->mode = 0;
437 
438 	return (0);
439 }
440 
441 static int
442 rk3568_combphy_map(device_t dev, phandle_t xref, int ncells, pcell_t *cells,
443     intptr_t *id)
444 {
445 	struct rk3568_combphy_softc *sc = device_get_softc(dev);
446 
447 	if (phydev_default_ofw_map(dev, xref, ncells, cells, id))
448 		return (ERANGE);
449 
450 	/* Store the phy mode that is handed to us in id */
451 	sc->mode = *id;
452 
453 	/* Set our id to 0 so the std phy_get_*() works as usual */
454 	*id = 0;
455 
456 	return (0);
457 }
458 
459 static device_method_t rk3568_combphy_methods[] = {
460 	DEVMETHOD(device_probe,		rk3568_combphy_probe),
461 	DEVMETHOD(device_attach,	rk3568_combphy_attach),
462 	DEVMETHOD(phydev_map,		rk3568_combphy_map),
463 
464 	DEVMETHOD_END
465 };
466 
467 DEFINE_CLASS_1(rk3568_combphy, rk3568_combphy_driver, rk3568_combphy_methods,
468     sizeof(struct simple_mfd_softc), simple_mfd_driver);
469 EARLY_DRIVER_MODULE(rk3568_combphy, simplebus, rk3568_combphy_driver,
470     0, 0, BUS_PASS_RESOURCE + BUS_PASS_ORDER_LATE);
471