1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright 2020 Michal Meloun <mmel@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 */ 28 29 /* Layerscape DesignWare PCIe driver */ 30 31 #include <sys/cdefs.h> 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/bus.h> 35 #include <sys/devmap.h> 36 #include <sys/proc.h> 37 #include <sys/kernel.h> 38 #include <sys/malloc.h> 39 #include <sys/module.h> 40 #include <sys/mutex.h> 41 #include <sys/rman.h> 42 #include <sys/sysctl.h> 43 44 #include <machine/bus.h> 45 #include <machine/intr.h> 46 #include <machine/resource.h> 47 48 #include <dev/ofw/ofw_bus.h> 49 #include <dev/ofw/ofw_bus_subr.h> 50 #include <dev/ofw/ofw_pci.h> 51 #include <dev/ofw/ofwpci.h> 52 #include <dev/pci/pcivar.h> 53 #include <dev/pci/pcireg.h> 54 #include <dev/pci/pcib_private.h> 55 #include <dev/pci/pci_dw.h> 56 57 #include "pcib_if.h" 58 #include "pci_dw_if.h" 59 60 #define PCIE_ABSERR 0x8D0 61 62 struct qoriq_dw_pci_cfg { 63 uint32_t pex_pf0_dgb; /* offset of PEX_PF0_DBG register */ 64 uint32_t ltssm_bit; /* LSB bit of of LTSSM state field */ 65 }; 66 67 struct qorif_dw_pci_softc { 68 struct pci_dw_softc dw_sc; 69 device_t dev; 70 phandle_t node; 71 struct resource *irq_res; 72 void *intr_cookie; 73 struct qoriq_dw_pci_cfg *soc_cfg; 74 75 }; 76 77 static struct qoriq_dw_pci_cfg ls1043_cfg = { 78 .pex_pf0_dgb = 0x10000 + 0x7FC, 79 .ltssm_bit = 24, 80 }; 81 82 static struct qoriq_dw_pci_cfg ls1012_cfg = { 83 .pex_pf0_dgb = 0x80000 + 0x407FC, 84 .ltssm_bit = 24, 85 }; 86 87 static struct qoriq_dw_pci_cfg ls2080_cfg = { 88 .pex_pf0_dgb = 0x80000 + 0x7FC, 89 .ltssm_bit = 0, 90 }; 91 92 static struct qoriq_dw_pci_cfg ls2028_cfg = { 93 .pex_pf0_dgb = 0x80000 + 0x407FC, 94 .ltssm_bit = 0, 95 }; 96 97 98 /* Compatible devices. */ 99 static struct ofw_compat_data compat_data[] = { 100 {"fsl,ls1012a-pcie", (uintptr_t)&ls1012_cfg}, 101 {"fsl,ls1028a-pcie", (uintptr_t)&ls2028_cfg}, 102 {"fsl,ls1043a-pcie", (uintptr_t)&ls1043_cfg}, 103 {"fsl,ls1046a-pcie", (uintptr_t)&ls1012_cfg}, 104 {"fsl,ls2080a-pcie", (uintptr_t)&ls2080_cfg}, 105 {"fsl,ls2085a-pcie", (uintptr_t)&ls2080_cfg}, 106 {"fsl,ls2088a-pcie", (uintptr_t)&ls2028_cfg}, 107 {"fsl,ls1088a-pcie", (uintptr_t)&ls2028_cfg}, 108 {NULL, 0}, 109 }; 110 111 static void 112 qorif_dw_pci_dbi_protect(struct qorif_dw_pci_softc *sc, bool protect) 113 { 114 uint32_t reg; 115 116 reg = pci_dw_dbi_rd4(sc->dev, DW_MISC_CONTROL_1); 117 if (protect) 118 reg &= ~DBI_RO_WR_EN; 119 else 120 reg |= DBI_RO_WR_EN; 121 pci_dw_dbi_wr4(sc->dev, DW_MISC_CONTROL_1, reg); 122 } 123 124 static int qorif_dw_pci_intr(void *arg) 125 { 126 #if 0 127 struct qorif_dw_pci_softc *sc = arg; 128 uint32_t cause1, cause2; 129 130 /* Ack all interrups */ 131 cause1 = pci_dw_dbi_rd4(sc->dev, MV_INT_CAUSE1); 132 cause2 = pci_dw_dbi_rd4(sc->dev, MV_INT_CAUSE2); 133 134 pci_dw_dbi_wr4(sc->dev, MV_INT_CAUSE1, cause1); 135 pci_dw_dbi_wr4(sc->dev, MV_INT_CAUSE2, cause2); 136 #endif 137 return (FILTER_HANDLED); 138 } 139 140 static int 141 qorif_dw_pci_get_link(device_t dev, bool *status) 142 { 143 struct qorif_dw_pci_softc *sc; 144 uint32_t reg; 145 146 sc = device_get_softc(dev); 147 reg = pci_dw_dbi_rd4(sc->dev, sc->soc_cfg->pex_pf0_dgb); 148 reg >>= sc->soc_cfg->ltssm_bit; 149 reg &= 0x3F; 150 *status = (reg == 0x11) ? true : false; 151 return (0); 152 } 153 154 static void 155 qorif_dw_pci_init(struct qorif_dw_pci_softc *sc) 156 { 157 158 // ls_pcie_disable_outbound_atus(pcie); 159 160 /* Forward error response */ 161 pci_dw_dbi_wr4(sc->dev, PCIE_ABSERR, 0x9401); 162 163 qorif_dw_pci_dbi_protect(sc, true); 164 pci_dw_dbi_wr1(sc->dev, PCIR_HDRTYPE, 1); 165 qorif_dw_pci_dbi_protect(sc, false); 166 167 // ls_pcie_drop_msg_tlp(pcie); 168 169 } 170 171 static int 172 qorif_dw_pci_probe(device_t dev) 173 { 174 175 if (!ofw_bus_status_okay(dev)) 176 return (ENXIO); 177 178 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 179 return (ENXIO); 180 181 device_set_desc(dev, "NPX Layaerscape PCI-E Controller"); 182 return (BUS_PROBE_DEFAULT); 183 } 184 185 static int 186 qorif_dw_pci_attach(device_t dev) 187 { 188 struct resource_map_request req; 189 struct resource_map map; 190 struct qorif_dw_pci_softc *sc; 191 phandle_t node; 192 int rv; 193 int rid; 194 195 sc = device_get_softc(dev); 196 node = ofw_bus_get_node(dev); 197 sc->dev = dev; 198 sc->node = node; 199 sc->soc_cfg = (struct qoriq_dw_pci_cfg *) 200 ofw_bus_search_compatible(dev, compat_data)->ocd_data; 201 202 rid = 0; 203 sc->dw_sc.dbi_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 204 RF_ACTIVE | RF_UNMAPPED); 205 if (sc->dw_sc.dbi_res == NULL) { 206 device_printf(dev, "Cannot allocate DBI memory\n"); 207 rv = ENXIO; 208 goto out; 209 } 210 211 resource_init_map_request(&req); 212 req.memattr = VM_MEMATTR_DEVICE_NP; 213 rv = bus_map_resource(dev, SYS_RES_MEMORY, sc->dw_sc.dbi_res, &req, 214 &map); 215 if (rv != 0) { 216 device_printf(dev, "could not map memory.\n"); 217 return (rv); 218 } 219 rman_set_mapping(sc->dw_sc.dbi_res, &map); 220 221 /* PCI interrupt */ 222 rid = 0; 223 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 224 RF_ACTIVE | RF_SHAREABLE); 225 if (sc->irq_res == NULL) { 226 device_printf(dev, "Cannot allocate IRQ resources\n"); 227 rv = ENXIO; 228 goto out; 229 } 230 231 rv = pci_dw_init(dev); 232 if (rv != 0) 233 goto out; 234 235 qorif_dw_pci_init(sc); 236 237 /* Setup interrupt */ 238 if (bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 239 qorif_dw_pci_intr, NULL, sc, &sc->intr_cookie)) { 240 device_printf(dev, "cannot setup interrupt handler\n"); 241 rv = ENXIO; 242 goto out; 243 } 244 245 return (bus_generic_attach(dev)); 246 out: 247 /* XXX Cleanup */ 248 return (rv); 249 } 250 251 static device_method_t qorif_dw_pci_methods[] = { 252 /* Device interface */ 253 DEVMETHOD(device_probe, qorif_dw_pci_probe), 254 DEVMETHOD(device_attach, qorif_dw_pci_attach), 255 256 DEVMETHOD(pci_dw_get_link, qorif_dw_pci_get_link), 257 258 DEVMETHOD_END 259 }; 260 261 DEFINE_CLASS_1(pcib, qorif_dw_pci_driver, qorif_dw_pci_methods, 262 sizeof(struct qorif_dw_pci_softc), pci_dw_driver); 263 DRIVER_MODULE( qorif_dw_pci, simplebus, qorif_dw_pci_driver, NULL, NULL); 264