1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright 2020 Michal Meloun <mmel@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 */ 28 29 /* Layerscape DesignWare PCIe driver */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/bus.h> 38 #include <sys/devmap.h> 39 #include <sys/proc.h> 40 #include <sys/kernel.h> 41 #include <sys/malloc.h> 42 #include <sys/module.h> 43 #include <sys/mutex.h> 44 #include <sys/rman.h> 45 #include <sys/sysctl.h> 46 47 #include <machine/bus.h> 48 #include <machine/intr.h> 49 #include <machine/resource.h> 50 51 #include <dev/ofw/ofw_bus.h> 52 #include <dev/ofw/ofw_bus_subr.h> 53 #include <dev/ofw/ofw_pci.h> 54 #include <dev/ofw/ofwpci.h> 55 #include <dev/pci/pcivar.h> 56 #include <dev/pci/pcireg.h> 57 #include <dev/pci/pcib_private.h> 58 #include <dev/pci/pci_dw.h> 59 60 #include "pcib_if.h" 61 #include "pci_dw_if.h" 62 63 #define PCIE_ABSERR 0x8D0 64 65 struct qoriq_dw_pci_cfg { 66 uint32_t pex_pf0_dgb; /* offset of PEX_PF0_DBG register */ 67 uint32_t ltssm_bit; /* LSB bit of of LTSSM state field */ 68 }; 69 70 struct qorif_dw_pci_softc { 71 struct pci_dw_softc dw_sc; 72 device_t dev; 73 phandle_t node; 74 struct resource *irq_res; 75 void *intr_cookie; 76 struct qoriq_dw_pci_cfg *soc_cfg; 77 78 }; 79 80 static struct qoriq_dw_pci_cfg ls1043_cfg = { 81 .pex_pf0_dgb = 0x10000 + 0x7FC, 82 .ltssm_bit = 24, 83 }; 84 85 static struct qoriq_dw_pci_cfg ls1012_cfg = { 86 .pex_pf0_dgb = 0x80000 + 0x407FC, 87 .ltssm_bit = 24, 88 }; 89 90 static struct qoriq_dw_pci_cfg ls2080_cfg = { 91 .pex_pf0_dgb = 0x80000 + 0x7FC, 92 .ltssm_bit = 0, 93 }; 94 95 static struct qoriq_dw_pci_cfg ls2028_cfg = { 96 .pex_pf0_dgb = 0x80000 + 0x407FC, 97 .ltssm_bit = 0, 98 }; 99 100 101 /* Compatible devices. */ 102 static struct ofw_compat_data compat_data[] = { 103 {"fsl,ls1012a-pcie", (uintptr_t)&ls1012_cfg}, 104 {"fsl,ls1028a-pcie", (uintptr_t)&ls2028_cfg}, 105 {"fsl,ls1043a-pcie", (uintptr_t)&ls1043_cfg}, 106 {"fsl,ls1046a-pcie", (uintptr_t)&ls1012_cfg}, 107 {"fsl,ls2080a-pcie", (uintptr_t)&ls2080_cfg}, 108 {"fsl,ls2085a-pcie", (uintptr_t)&ls2080_cfg}, 109 {"fsl,ls2088a-pcie", (uintptr_t)&ls2028_cfg}, 110 {"fsl,ls1088a-pcie", (uintptr_t)&ls2028_cfg}, 111 {NULL, 0}, 112 }; 113 114 static void 115 qorif_dw_pci_dbi_protect(struct qorif_dw_pci_softc *sc, bool protect) 116 { 117 uint32_t reg; 118 119 reg = pci_dw_dbi_rd4(sc->dev, DW_MISC_CONTROL_1); 120 if (protect) 121 reg &= ~DBI_RO_WR_EN; 122 else 123 reg |= DBI_RO_WR_EN; 124 pci_dw_dbi_wr4(sc->dev, DW_MISC_CONTROL_1, reg); 125 } 126 127 static int qorif_dw_pci_intr(void *arg) 128 { 129 #if 0 130 struct qorif_dw_pci_softc *sc = arg; 131 uint32_t cause1, cause2; 132 133 /* Ack all interrups */ 134 cause1 = pci_dw_dbi_rd4(sc->dev, MV_INT_CAUSE1); 135 cause2 = pci_dw_dbi_rd4(sc->dev, MV_INT_CAUSE2); 136 137 pci_dw_dbi_wr4(sc->dev, MV_INT_CAUSE1, cause1); 138 pci_dw_dbi_wr4(sc->dev, MV_INT_CAUSE2, cause2); 139 #endif 140 return (FILTER_HANDLED); 141 } 142 143 static int 144 qorif_dw_pci_get_link(device_t dev, bool *status) 145 { 146 struct qorif_dw_pci_softc *sc; 147 uint32_t reg; 148 149 sc = device_get_softc(dev); 150 reg = pci_dw_dbi_rd4(sc->dev, sc->soc_cfg->pex_pf0_dgb); 151 reg >>= sc->soc_cfg->ltssm_bit; 152 reg &= 0x3F; 153 *status = (reg == 0x11) ? true : false; 154 return (0); 155 } 156 157 static void 158 qorif_dw_pci_init(struct qorif_dw_pci_softc *sc) 159 { 160 161 // ls_pcie_disable_outbound_atus(pcie); 162 163 /* Forward error response */ 164 pci_dw_dbi_wr4(sc->dev, PCIE_ABSERR, 0x9401); 165 166 qorif_dw_pci_dbi_protect(sc, true); 167 pci_dw_dbi_wr1(sc->dev, PCIR_HDRTYPE, 1); 168 qorif_dw_pci_dbi_protect(sc, false); 169 170 // ls_pcie_drop_msg_tlp(pcie); 171 172 } 173 174 static int 175 qorif_dw_pci_probe(device_t dev) 176 { 177 178 if (!ofw_bus_status_okay(dev)) 179 return (ENXIO); 180 181 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 182 return (ENXIO); 183 184 device_set_desc(dev, "NPX Layaerscape PCI-E Controller"); 185 return (BUS_PROBE_DEFAULT); 186 } 187 188 static int 189 qorif_dw_pci_attach(device_t dev) 190 { 191 struct resource_map_request req; 192 struct resource_map map; 193 struct qorif_dw_pci_softc *sc; 194 phandle_t node; 195 int rv; 196 int rid; 197 198 sc = device_get_softc(dev); 199 node = ofw_bus_get_node(dev); 200 sc->dev = dev; 201 sc->node = node; 202 sc->soc_cfg = (struct qoriq_dw_pci_cfg *) 203 ofw_bus_search_compatible(dev, compat_data)->ocd_data; 204 205 rid = 0; 206 sc->dw_sc.dbi_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 207 RF_ACTIVE | RF_UNMAPPED); 208 if (sc->dw_sc.dbi_res == NULL) { 209 device_printf(dev, "Cannot allocate DBI memory\n"); 210 rv = ENXIO; 211 goto out; 212 } 213 214 resource_init_map_request(&req); 215 req.memattr = VM_MEMATTR_DEVICE_NP; 216 rv = bus_map_resource(dev, SYS_RES_MEMORY, sc->dw_sc.dbi_res, &req, 217 &map); 218 if (rv != 0) { 219 device_printf(dev, "could not map memory.\n"); 220 return (rv); 221 } 222 rman_set_mapping(sc->dw_sc.dbi_res, &map); 223 224 /* PCI interrupt */ 225 rid = 0; 226 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 227 RF_ACTIVE | RF_SHAREABLE); 228 if (sc->irq_res == NULL) { 229 device_printf(dev, "Cannot allocate IRQ resources\n"); 230 rv = ENXIO; 231 goto out; 232 } 233 234 rv = pci_dw_init(dev); 235 if (rv != 0) 236 goto out; 237 238 qorif_dw_pci_init(sc); 239 240 /* Setup interrupt */ 241 if (bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 242 qorif_dw_pci_intr, NULL, sc, &sc->intr_cookie)) { 243 device_printf(dev, "cannot setup interrupt handler\n"); 244 rv = ENXIO; 245 goto out; 246 } 247 248 return (bus_generic_attach(dev)); 249 out: 250 /* XXX Cleanup */ 251 return (rv); 252 } 253 254 static device_method_t qorif_dw_pci_methods[] = { 255 /* Device interface */ 256 DEVMETHOD(device_probe, qorif_dw_pci_probe), 257 DEVMETHOD(device_attach, qorif_dw_pci_attach), 258 259 DEVMETHOD(pci_dw_get_link, qorif_dw_pci_get_link), 260 261 DEVMETHOD_END 262 }; 263 264 DEFINE_CLASS_1(pcib, qorif_dw_pci_driver, qorif_dw_pci_methods, 265 sizeof(struct qorif_dw_pci_softc), pci_dw_driver); 266 DRIVER_MODULE( qorif_dw_pci, simplebus, qorif_dw_pci_driver, NULL, NULL); 267