1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2020 Alstom Group. 5 * Copyright (c) 2020 Semihalf. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/param.h> 30 #include <sys/systm.h> 31 #include <sys/bus.h> 32 #include <sys/endian.h> 33 #include <sys/rman.h> 34 #include <sys/kernel.h> 35 #include <sys/lock.h> 36 #include <sys/module.h> 37 #include <sys/mutex.h> 38 #include <machine/bus.h> 39 40 #include <dev/fdt/simplebus.h> 41 42 #include <dev/ofw/ofw_bus.h> 43 #include <dev/ofw/ofw_bus_subr.h> 44 45 #include <dev/clk/clk_fixed.h> 46 47 #include <arm64/qoriq/clk/qoriq_clkgen.h> 48 49 #include "clkdev_if.h" 50 51 MALLOC_DEFINE(M_QORIQ_CLKGEN, "qoriq_clkgen", "qoriq_clkgen"); 52 53 static struct resource_spec qoriq_clkgen_spec[] = { 54 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 55 { -1, 0 } 56 }; 57 58 static const char *qoriq_pll_parents_coreclk[] = { 59 QORIQ_CORECLK_NAME 60 }; 61 62 static const char *qoriq_pll_parents_sysclk[] = { 63 QORIQ_SYSCLK_NAME 64 }; 65 66 static int 67 qoriq_clkgen_ofw_mapper(struct clkdom *clkdom, uint32_t ncells, 68 phandle_t *cells, struct clknode **clk) 69 { 70 71 if (ncells != 2) 72 return (EINVAL); 73 74 if (cells[0] > 5) 75 return (EINVAL); 76 77 if (cells[0] == QORIQ_TYPE_SYSCLK || cells[0] == QORIQ_TYPE_CORECLK) 78 if (cells[1] != 0) 79 return (EINVAL); 80 81 *clk = clknode_find_by_id(clkdom, QORIQ_CLK_ID(cells[0], cells[1])); 82 83 if (*clk == NULL) 84 return (EINVAL); 85 86 return (0); 87 } 88 89 static int 90 qoriq_clkgen_write_4(device_t dev, bus_addr_t addr, uint32_t val) 91 { 92 struct qoriq_clkgen_softc *sc; 93 94 sc = device_get_softc(dev); 95 96 if (sc->flags & QORIQ_LITTLE_ENDIAN) 97 bus_write_4(sc->res, addr, htole32(val)); 98 else 99 bus_write_4(sc->res, addr, htobe32(val)); 100 return (0); 101 } 102 103 static int 104 qoriq_clkgen_read_4(device_t dev, bus_addr_t addr, uint32_t *val) 105 { 106 struct qoriq_clkgen_softc *sc; 107 108 sc = device_get_softc(dev); 109 110 if (sc->flags & QORIQ_LITTLE_ENDIAN) 111 *val = le32toh(bus_read_4(sc->res, addr)); 112 else 113 *val = be32toh(bus_read_4(sc->res, addr)); 114 return (0); 115 } 116 117 static int 118 qoriq_clkgen_modify_4(device_t dev, bus_addr_t addr, uint32_t clr, 119 uint32_t set) 120 { 121 struct qoriq_clkgen_softc *sc; 122 uint32_t reg; 123 124 sc = device_get_softc(dev); 125 126 if (sc->flags & QORIQ_LITTLE_ENDIAN) 127 reg = le32toh(bus_read_4(sc->res, addr)); 128 else 129 reg = be32toh(bus_read_4(sc->res, addr)); 130 131 reg &= ~clr; 132 reg |= set; 133 134 if (sc->flags & QORIQ_LITTLE_ENDIAN) 135 bus_write_4(sc->res, addr, htole32(reg)); 136 else 137 bus_write_4(sc->res, addr, htobe32(reg)); 138 139 return (0); 140 } 141 142 static void 143 qoriq_clkgen_device_lock(device_t dev) 144 { 145 struct qoriq_clkgen_softc *sc; 146 147 sc = device_get_softc(dev); 148 mtx_lock(&sc->mtx); 149 } 150 151 static void 152 qoriq_clkgen_device_unlock(device_t dev) 153 { 154 struct qoriq_clkgen_softc *sc; 155 156 sc = device_get_softc(dev); 157 mtx_unlock(&sc->mtx); 158 } 159 160 static device_method_t qoriq_clkgen_methods[] = { 161 DEVMETHOD(clkdev_write_4, qoriq_clkgen_write_4), 162 DEVMETHOD(clkdev_read_4, qoriq_clkgen_read_4), 163 DEVMETHOD(clkdev_modify_4, qoriq_clkgen_modify_4), 164 DEVMETHOD(clkdev_device_lock, qoriq_clkgen_device_lock), 165 DEVMETHOD(clkdev_device_unlock, qoriq_clkgen_device_unlock), 166 167 DEVMETHOD_END 168 }; 169 170 DEFINE_CLASS_0(qoriq_clkgen, qoriq_clkgen_driver, qoriq_clkgen_methods, 171 sizeof(struct qoriq_clkgen_softc)); 172 173 static int 174 qoriq_clkgen_create_sysclk(device_t dev) 175 { 176 struct qoriq_clkgen_softc *sc; 177 struct clk_fixed_def def; 178 const char *clkname; 179 phandle_t node; 180 uint32_t freq; 181 clk_t clock; 182 int rv; 183 184 sc = device_get_softc(dev); 185 node = ofw_bus_get_node(dev); 186 sc->has_coreclk = false; 187 188 memset(&def, 0, sizeof(def)); 189 190 rv = OF_getencprop(node, "clock-frequency", &freq, sizeof(freq)); 191 if (rv > 0) { 192 def.clkdef.name = QORIQ_SYSCLK_NAME; 193 def.clkdef.id = QORIQ_CLK_ID(QORIQ_TYPE_SYSCLK, 0); 194 def.freq = freq; 195 196 rv = clknode_fixed_register(sc->clkdom, &def); 197 return (rv); 198 } else { 199 /* 200 * As both sysclk and coreclk need to be accessible from 201 * device tree, create internal 1:1 divider nodes. 202 */ 203 def.clkdef.parent_cnt = 1; 204 def.freq = 0; 205 def.mult = 1; 206 def.div = 1; 207 208 rv = clk_get_by_ofw_name(dev, node, "coreclk", &clock); 209 if (rv == 0) { 210 def.clkdef.name = QORIQ_CORECLK_NAME; 211 clkname = clk_get_name(clock); 212 def.clkdef.parent_names = &clkname; 213 def.clkdef.id = QORIQ_CLK_ID(QORIQ_TYPE_CORECLK, 0); 214 215 rv = clknode_fixed_register(sc->clkdom, &def); 216 if (rv) 217 return (rv); 218 219 sc->has_coreclk = true; 220 } 221 222 rv = clk_get_by_ofw_name(dev, node, "sysclk", &clock); 223 if (rv != 0) { 224 rv = clk_get_by_ofw_index(dev, node, 0, &clock); 225 if (rv != 0) 226 return (rv); 227 } 228 229 clkname = clk_get_name(clock); 230 def.clkdef.name = QORIQ_SYSCLK_NAME; 231 def.clkdef.id = QORIQ_CLK_ID(QORIQ_TYPE_SYSCLK, 0); 232 def.clkdef.parent_names = &clkname; 233 234 rv = clknode_fixed_register(sc->clkdom, &def); 235 return (rv); 236 } 237 } 238 239 int 240 qoriq_clkgen_attach(device_t dev) 241 { 242 struct qoriq_clkgen_softc *sc; 243 int i, error; 244 245 sc = device_get_softc(dev); 246 sc->dev = dev; 247 248 if (bus_alloc_resources(dev, qoriq_clkgen_spec, &sc->res) != 0) { 249 device_printf(dev, "Cannot allocate resources.\n"); 250 return (ENXIO); 251 } 252 253 mtx_init(&sc->mtx, device_get_nameunit(dev), NULL, MTX_DEF); 254 255 sc->clkdom = clkdom_create(dev); 256 if (sc->clkdom == NULL) 257 panic("Cannot create clock domain.\n"); 258 259 error = qoriq_clkgen_create_sysclk(dev); 260 if (error != 0) { 261 device_printf(dev, "Cannot create sysclk.\n"); 262 return (error); 263 } 264 265 sc->pltfrm_pll_def->clkdef.parent_names = qoriq_pll_parents_sysclk; 266 sc->pltfrm_pll_def->clkdef.parent_cnt = 1; 267 error = qoriq_clk_pll_register(sc->clkdom, sc->pltfrm_pll_def); 268 if (error != 0) { 269 device_printf(dev, "Cannot create platform PLL.\n"); 270 return (error); 271 } 272 273 for (i = 0; i < sc->cga_pll_num; i++) { 274 if (sc->has_coreclk) 275 sc->cga_pll[i]->clkdef.parent_names = qoriq_pll_parents_coreclk; 276 else 277 sc->cga_pll[i]->clkdef.parent_names = qoriq_pll_parents_sysclk; 278 sc->cga_pll[i]->clkdef.parent_cnt = 1; 279 280 error = qoriq_clk_pll_register(sc->clkdom, sc->cga_pll[i]); 281 if (error != 0) { 282 device_printf(dev, "Cannot create CGA PLLs\n."); 283 return (error); 284 } 285 } 286 287 /* 288 * Both CMUX and HWACCEL multiplexer nodes can be represented 289 * by using built in clk_mux nodes. 290 */ 291 for (i = 0; i < sc->mux_num; i++) { 292 error = clknode_mux_register(sc->clkdom, sc->mux[i]); 293 if (error != 0) { 294 device_printf(dev, "Cannot create MUX nodes.\n"); 295 return (error); 296 } 297 } 298 299 if (sc->init_func != NULL) { 300 error = sc->init_func(dev); 301 if (error) { 302 device_printf(dev, "Clock init function failed.\n"); 303 return (error); 304 } 305 } 306 307 clkdom_set_ofw_mapper(sc->clkdom, qoriq_clkgen_ofw_mapper); 308 309 if (clkdom_finit(sc->clkdom) != 0) 310 panic("Cannot finalize clock domain initialization.\n"); 311 312 if (bootverbose) 313 clkdom_dump(sc->clkdom); 314 315 return (0); 316 } 317