1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2020 Alstom Group. 5 * Copyright (c) 2020 Semihalf. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/bus.h> 33 #include <sys/endian.h> 34 #include <sys/rman.h> 35 #include <sys/kernel.h> 36 #include <sys/lock.h> 37 #include <sys/module.h> 38 #include <sys/mutex.h> 39 #include <machine/bus.h> 40 41 #include <dev/fdt/simplebus.h> 42 43 #include <dev/ofw/ofw_bus.h> 44 #include <dev/ofw/ofw_bus_subr.h> 45 46 #include <dev/extres/clk/clk_fixed.h> 47 48 #include <arm64/qoriq/clk/qoriq_clkgen.h> 49 50 #include "clkdev_if.h" 51 52 MALLOC_DEFINE(M_QORIQ_CLKGEN, "qoriq_clkgen", "qoriq_clkgen"); 53 54 static struct resource_spec qoriq_clkgen_spec[] = { 55 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 56 { -1, 0 } 57 }; 58 59 static const char *qoriq_pll_parents_coreclk[] = { 60 QORIQ_CORECLK_NAME 61 }; 62 63 static const char *qoriq_pll_parents_sysclk[] = { 64 QORIQ_SYSCLK_NAME 65 }; 66 67 static int 68 qoriq_clkgen_ofw_mapper(struct clkdom *clkdom, uint32_t ncells, 69 phandle_t *cells, struct clknode **clk) 70 { 71 72 if (ncells != 2) 73 return (EINVAL); 74 75 if (cells[0] > 5) 76 return (EINVAL); 77 78 if (cells[0] == QORIQ_TYPE_SYSCLK || cells[0] == QORIQ_TYPE_CORECLK) 79 if (cells[1] != 0) 80 return (EINVAL); 81 82 *clk = clknode_find_by_id(clkdom, QORIQ_CLK_ID(cells[0], cells[1])); 83 84 if (*clk == NULL) 85 return (EINVAL); 86 87 return (0); 88 } 89 90 static int 91 qoriq_clkgen_write_4(device_t dev, bus_addr_t addr, uint32_t val) 92 { 93 struct qoriq_clkgen_softc *sc; 94 95 sc = device_get_softc(dev); 96 97 if (sc->flags & QORIQ_LITTLE_ENDIAN) 98 bus_write_4(sc->res, addr, htole32(val)); 99 else 100 bus_write_4(sc->res, addr, htobe32(val)); 101 return (0); 102 } 103 104 static int 105 qoriq_clkgen_read_4(device_t dev, bus_addr_t addr, uint32_t *val) 106 { 107 struct qoriq_clkgen_softc *sc; 108 109 sc = device_get_softc(dev); 110 111 if (sc->flags & QORIQ_LITTLE_ENDIAN) 112 *val = le32toh(bus_read_4(sc->res, addr)); 113 else 114 *val = be32toh(bus_read_4(sc->res, addr)); 115 return (0); 116 } 117 118 static int 119 qoriq_clkgen_modify_4(device_t dev, bus_addr_t addr, uint32_t clr, 120 uint32_t set) 121 { 122 struct qoriq_clkgen_softc *sc; 123 uint32_t reg; 124 125 sc = device_get_softc(dev); 126 127 if (sc->flags & QORIQ_LITTLE_ENDIAN) 128 reg = le32toh(bus_read_4(sc->res, addr)); 129 else 130 reg = be32toh(bus_read_4(sc->res, addr)); 131 132 reg &= ~clr; 133 reg |= set; 134 135 if (sc->flags & QORIQ_LITTLE_ENDIAN) 136 bus_write_4(sc->res, addr, htole32(reg)); 137 else 138 bus_write_4(sc->res, addr, htobe32(reg)); 139 140 return (0); 141 } 142 143 static void 144 qoriq_clkgen_device_lock(device_t dev) 145 { 146 struct qoriq_clkgen_softc *sc; 147 148 sc = device_get_softc(dev); 149 mtx_lock(&sc->mtx); 150 } 151 152 static void 153 qoriq_clkgen_device_unlock(device_t dev) 154 { 155 struct qoriq_clkgen_softc *sc; 156 157 sc = device_get_softc(dev); 158 mtx_unlock(&sc->mtx); 159 } 160 161 static device_method_t qoriq_clkgen_methods[] = { 162 DEVMETHOD(clkdev_write_4, qoriq_clkgen_write_4), 163 DEVMETHOD(clkdev_read_4, qoriq_clkgen_read_4), 164 DEVMETHOD(clkdev_modify_4, qoriq_clkgen_modify_4), 165 DEVMETHOD(clkdev_device_lock, qoriq_clkgen_device_lock), 166 DEVMETHOD(clkdev_device_unlock, qoriq_clkgen_device_unlock), 167 168 DEVMETHOD_END 169 }; 170 171 DEFINE_CLASS_0(qoriq_clkgen, qoriq_clkgen_driver, qoriq_clkgen_methods, 172 sizeof(struct qoriq_clkgen_softc)); 173 174 static int 175 qoriq_clkgen_create_sysclk(device_t dev) 176 { 177 struct qoriq_clkgen_softc *sc; 178 struct clk_fixed_def def; 179 const char *clkname; 180 phandle_t node; 181 uint32_t freq; 182 clk_t clock; 183 int rv; 184 185 sc = device_get_softc(dev); 186 node = ofw_bus_get_node(dev); 187 sc->has_coreclk = false; 188 189 memset(&def, 0, sizeof(def)); 190 191 rv = OF_getencprop(node, "clock-frequency", &freq, sizeof(freq)); 192 if (rv > 0) { 193 def.clkdef.name = QORIQ_SYSCLK_NAME; 194 def.clkdef.id = QORIQ_CLK_ID(QORIQ_TYPE_SYSCLK, 0); 195 def.freq = freq; 196 197 rv = clknode_fixed_register(sc->clkdom, &def); 198 return (rv); 199 } else { 200 /* 201 * As both sysclk and coreclk need to be accessible from 202 * device tree, create internal 1:1 divider nodes. 203 */ 204 def.clkdef.parent_cnt = 1; 205 def.freq = 0; 206 def.mult = 1; 207 def.div = 1; 208 209 rv = clk_get_by_ofw_name(dev, node, "coreclk", &clock); 210 if (rv == 0) { 211 def.clkdef.name = QORIQ_CORECLK_NAME; 212 clkname = clk_get_name(clock); 213 def.clkdef.parent_names = &clkname; 214 def.clkdef.id = QORIQ_CLK_ID(QORIQ_TYPE_CORECLK, 0); 215 216 rv = clknode_fixed_register(sc->clkdom, &def); 217 if (rv) 218 return (rv); 219 220 sc->has_coreclk = true; 221 } 222 223 rv = clk_get_by_ofw_name(dev, node, "sysclk", &clock); 224 if (rv != 0) { 225 rv = clk_get_by_ofw_index(dev, node, 0, &clock); 226 if (rv != 0) 227 return (rv); 228 } 229 230 clkname = clk_get_name(clock); 231 def.clkdef.name = QORIQ_SYSCLK_NAME; 232 def.clkdef.id = QORIQ_CLK_ID(QORIQ_TYPE_SYSCLK, 0); 233 def.clkdef.parent_names = &clkname; 234 235 rv = clknode_fixed_register(sc->clkdom, &def); 236 return (rv); 237 } 238 } 239 240 int 241 qoriq_clkgen_attach(device_t dev) 242 { 243 struct qoriq_clkgen_softc *sc; 244 int i, error; 245 246 sc = device_get_softc(dev); 247 sc->dev = dev; 248 249 if (bus_alloc_resources(dev, qoriq_clkgen_spec, &sc->res) != 0) { 250 device_printf(dev, "Cannot allocate resources.\n"); 251 return (ENXIO); 252 } 253 254 mtx_init(&sc->mtx, device_get_nameunit(dev), NULL, MTX_DEF); 255 256 sc->clkdom = clkdom_create(dev); 257 if (sc->clkdom == NULL) 258 panic("Cannot create clock domain.\n"); 259 260 error = qoriq_clkgen_create_sysclk(dev); 261 if (error != 0) { 262 device_printf(dev, "Cannot create sysclk.\n"); 263 return (error); 264 } 265 266 sc->pltfrm_pll_def->clkdef.parent_names = qoriq_pll_parents_sysclk; 267 sc->pltfrm_pll_def->clkdef.parent_cnt = 1; 268 error = qoriq_clk_pll_register(sc->clkdom, sc->pltfrm_pll_def); 269 if (error != 0) { 270 device_printf(dev, "Cannot create platform PLL.\n"); 271 return (error); 272 } 273 274 for (i = 0; i < sc->cga_pll_num; i++) { 275 if (sc->has_coreclk) 276 sc->cga_pll[i]->clkdef.parent_names = qoriq_pll_parents_coreclk; 277 else 278 sc->cga_pll[i]->clkdef.parent_names = qoriq_pll_parents_sysclk; 279 sc->cga_pll[i]->clkdef.parent_cnt = 1; 280 281 error = qoriq_clk_pll_register(sc->clkdom, sc->cga_pll[i]); 282 if (error != 0) { 283 device_printf(dev, "Cannot create CGA PLLs\n."); 284 return (error); 285 } 286 } 287 288 /* 289 * Both CMUX and HWACCEL multiplexer nodes can be represented 290 * by using built in clk_mux nodes. 291 */ 292 for (i = 0; i < sc->mux_num; i++) { 293 error = clknode_mux_register(sc->clkdom, sc->mux[i]); 294 if (error != 0) { 295 device_printf(dev, "Cannot create MUX nodes.\n"); 296 return (error); 297 } 298 } 299 300 if (sc->init_func != NULL) { 301 error = sc->init_func(dev); 302 if (error) { 303 device_printf(dev, "Clock init function failed.\n"); 304 return (error); 305 } 306 } 307 308 clkdom_set_ofw_mapper(sc->clkdom, qoriq_clkgen_ofw_mapper); 309 310 if (clkdom_finit(sc->clkdom) != 0) 311 panic("Cannot finalize clock domain initialization.\n"); 312 313 if (bootverbose) 314 clkdom_dump(sc->clkdom); 315 316 return (0); 317 } 318