xref: /freebsd/sys/arm64/qoriq/clk/lx2160a_clkgen.c (revision 9f23cbd6cae82fd77edfad7173432fa8dccd0a95)
1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause
3  *
4  * Copyright 2020 Michal Meloun <mmel@FreeBSD.org>
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions
8  * are met:
9  * 1. Redistributions of source code must retain the above copyright
10  *    notice, this list of conditions and the following disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  *
15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25  * SUCH DAMAGE.
26  */
27 
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
30 
31 /*
32  * Clock driver for LX2160A SoC.
33  */
34 #include <sys/param.h>
35 #include <sys/bus.h>
36 #include <sys/kernel.h>
37 #include <sys/module.h>
38 #include <sys/mutex.h>
39 #include <sys/rman.h>
40 #include <machine/bus.h>
41 
42 #include <dev/fdt/simplebus.h>
43 
44 #include <dev/ofw/ofw_bus.h>
45 #include <dev/ofw/ofw_bus_subr.h>
46 
47 #include <dev/extres/clk/clk_fixed.h>
48 
49 #include <arm64/qoriq/clk/qoriq_clkgen.h>
50 
51 #define	PLL(_id1, _id2, cname, o, d)					\
52 {									\
53 	.clkdef.id = QORIQ_CLK_ID(_id1, _id2),				\
54 	.clkdef.name = cname,						\
55 	.clkdef.flags = 0,						\
56 	.offset = o,							\
57 	.shift  = 1,							\
58 	.mask = 0xFE,							\
59 	.dividers = d,							\
60 	.flags = QORIQ_CLK_PLL_HAS_KILL_BIT,				\
61 }
62 
63 static const uint8_t plt_divs[] =
64     {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 0};
65 static const uint8_t cga_divs[] =  {2, 4, 0};
66 static const uint8_t cgb_divs[] =  {2, 3, 4, 0};
67 
68 static struct qoriq_clk_pll_def pltfrm_pll =
69     PLL(QORIQ_TYPE_PLATFORM_PLL, 0, "platform_pll", 0x60080, plt_divs);
70 static struct qoriq_clk_pll_def cga_pll1 =
71     PLL(QORIQ_TYPE_INTERNAL, 0, "cga_pll1", 0x80, cga_divs);
72 static struct qoriq_clk_pll_def cga_pll2 =
73     PLL(QORIQ_TYPE_INTERNAL, 0, "cga_pll2", 0xA0, cga_divs);
74 static struct qoriq_clk_pll_def cgb_pll1 =
75     PLL(QORIQ_TYPE_INTERNAL, 0, "cgb_pll1", 0x10080, cgb_divs);
76 static struct qoriq_clk_pll_def cgb_pll2 =
77     PLL(QORIQ_TYPE_INTERNAL, 0, "cgb_pll2", 0x100A0, cgb_divs);
78 
79 static struct qoriq_clk_pll_def *cg_plls[] = {
80 	&cga_pll1,
81 	&cga_pll2,
82 	&cgb_pll1,
83 	&cgb_pll2,
84 };
85 
86 #if 0
87 static struct qoriq_clk_pll_def *cg_plls[] = {
88 	&(struct qoriq_clk_pll_def)
89 	    {PLL(QORIQ_TYPE_INTERNAL, 0, "cga_pll1", 0x80, cg_divs)},
90 	&(struct qoriq_clk_pll_def)
91 	    {PLL(QORIQ_TYPE_INTERNAL, 0, "cga_pll2", 0xA0, cg_divs)},
92 	&(struct qoriq_clk_pll_def)
93 	    {PLL(QORIQ_TYPE_INTERNAL, 0, "cgb_pll1", 0x10080, cg_divs)},
94 	&(struct qoriq_clk_pll_def)
95 	    {PLL(QORIQ_TYPE_INTERNAL, 0, "cgb_pll2", 0x100A0, cg_divs)},
96 };
97 #endif
98 
99 static const char *cmuxa_plist[] = {
100 	"cga_pll1",
101 	"cga_pll1_div2",
102 	"cga_pll1_div4",
103 	NULL,
104 	"cga_pll2",
105 	"cga_pll2_div2",
106 	"cga_pll2_div4",
107 };
108 
109 static const char *cmuxb_plist[] = {
110 	"cgb_pll1",
111 	"cgb_pll1_div2",
112 	"cgb_pll1_div4",
113 	NULL,
114 	"cgb_pll2",
115 	"cgb_pll2_div2",
116 	"cgb_pll2_div4",
117 };
118 
119 #define	MUX(_id1, _id2, cname, plist, o)				\
120 {									\
121 	.clkdef.id = QORIQ_CLK_ID(_id1, _id2),				\
122 	.clkdef.name = cname,						\
123 	.clkdef.parent_names = plist,					\
124 	.clkdef.parent_cnt = nitems(plist),				\
125 	.clkdef.flags = 0,						\
126 	.offset = o,							\
127 	.width  = 4,							\
128 	.shift = 27,							\
129 	.mux_flags = 0,							\
130 }
131 static struct clk_mux_def cmux0 =
132    MUX(QORIQ_TYPE_CMUX, 0, "cg-cmux0", cmuxa_plist, 0x70000);
133 static struct clk_mux_def cmux1 =
134    MUX(QORIQ_TYPE_CMUX, 1, "cg-cmux1", cmuxa_plist, 0x70020);
135 static struct clk_mux_def cmux2 =
136    MUX(QORIQ_TYPE_CMUX, 2, "cg-cmux2", cmuxa_plist, 0x70040);
137 static struct clk_mux_def cmux3 =
138    MUX(QORIQ_TYPE_CMUX, 3, "cg-cmux3", cmuxa_plist, 0x70060);
139 static struct clk_mux_def cmux4 =
140    MUX(QORIQ_TYPE_CMUX, 4, "cg-cmux4", cmuxb_plist, 0x70080);
141 static struct clk_mux_def cmux5 =
142    MUX(QORIQ_TYPE_CMUX, 5, "cg-cmux5", cmuxb_plist, 0x700A0);
143 static struct clk_mux_def cmux6 =
144    MUX(QORIQ_TYPE_CMUX, 6, "cg-cmux6", cmuxb_plist,  0x700C0);
145 static struct clk_mux_def cmux7 =
146    MUX(QORIQ_TYPE_CMUX, 7, "cg-cmux7", cmuxb_plist,  0x700E0);
147 
148 static struct clk_mux_def *mux_nodes[] = {
149 	&cmux0,
150 	&cmux1,
151 	&cmux2,
152 	&cmux3,
153 	&cmux4,
154 	&cmux5,
155 	&cmux6,
156 	&cmux7,
157 };
158 
159 static int
160 lx2160a_clkgen_probe(device_t dev)
161 {
162 
163 	if (!ofw_bus_status_okay(dev))
164 		return (ENXIO);
165 
166 	if(!ofw_bus_is_compatible(dev, "fsl,lx2160a-clockgen"))
167 		return (ENXIO);
168 
169 	device_set_desc(dev, "LX2160A clockgen");
170 	return (BUS_PROBE_DEFAULT);
171 }
172 
173 static int
174 lx2160a_clkgen_attach(device_t dev)
175 {
176 	struct qoriq_clkgen_softc *sc;
177 	int rv;
178 
179 	sc = device_get_softc(dev);
180 
181 	sc->pltfrm_pll_def = &pltfrm_pll;
182 	sc->cga_pll = cg_plls;
183 	sc->cga_pll_num = nitems(cg_plls);
184 	sc->mux = mux_nodes;
185 	sc->mux_num = nitems(mux_nodes);
186 	sc->flags = QORIQ_LITTLE_ENDIAN;
187 
188 	rv = qoriq_clkgen_attach(dev);
189 
190 	printf(" %s: offset: 0x%08X, val: 0x%08X\n", __func__, 0x00080, bus_read_4(sc->res, 0x00080));
191 	printf(" %s: offset: 0x%08X, val: 0x%08X\n", __func__, 0x000A0, bus_read_4(sc->res, 0x000A0));
192 	printf(" %s: offset: 0x%08X, val: 0x%08X\n", __func__, 0x10080, bus_read_4(sc->res, 0x10080));
193 	printf(" %s: offset: 0x%08X, val: 0x%08X\n", __func__, 0x100A0, bus_read_4(sc->res, 0x100A0));
194 	printf(" %s: offset: 0x%08X, val: 0x%08X\n", __func__, 0x60080, bus_read_4(sc->res, 0x60080));
195 	printf(" %s: offset: 0x%08X, val: 0x%08X\n", __func__, 0x600A0, bus_read_4(sc->res, 0x600A0));
196 	return (rv);
197 }
198 
199 static device_method_t lx2160a_clkgen_methods[] = {
200 	DEVMETHOD(device_probe,		lx2160a_clkgen_probe),
201 	DEVMETHOD(device_attach,	lx2160a_clkgen_attach),
202 
203 	DEVMETHOD_END
204 };
205 
206 DEFINE_CLASS_1(lx2160a_clkgen, lx2160a_clkgen_driver, lx2160a_clkgen_methods,
207     sizeof(struct qoriq_clkgen_softc), qoriq_clkgen_driver);
208 EARLY_DRIVER_MODULE(lx2160a_clkgen, simplebus, lx2160a_clkgen_driver, 0, 0,
209     BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE);
210