xref: /freebsd/sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c (revision edf8578117e8844e02c0121147f45e4609b30680)
1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause
3  *
4  * Copyright 2020 Michal Meloun <mmel@FreeBSD.org>
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions
8  * are met:
9  * 1. Redistributions of source code must retain the above copyright
10  *    notice, this list of conditions and the following disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  *
15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25  * SUCH DAMAGE.
26  */
27 
28 #include <sys/cdefs.h>
29 #include <sys/param.h>
30 #include <sys/systm.h>
31 #include <sys/bus.h>
32 #include <sys/kernel.h>
33 #include <sys/module.h>
34 #include <sys/malloc.h>
35 #include <sys/rman.h>
36 
37 #include <machine/bus.h>
38 
39 #include <dev/extres/clk/clk.h>
40 #include <dev/extres/hwreset/hwreset.h>
41 #include <dev/extres/phy/phy.h>
42 #include <dev/extres/regulator/regulator.h>
43 #include <dev/fdt/fdt_common.h>
44 #include <dev/fdt/fdt_pinctrl.h>
45 #include <dev/ofw/openfirm.h>
46 #include <dev/ofw/ofw_bus.h>
47 #include <dev/ofw/ofw_bus_subr.h>
48 
49 #include <arm/nvidia/tegra_efuse.h>
50 
51 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
52 
53 #include "phynode_if.h"
54 
55 /* FUSE calibration data. */
56 #define	FUSE_SKU_CALIB_0			0x0F0
57 #define	  FUSE_SKU_CALIB_0_HS_CURR_LEVEL_123(x, i)	(((x) >> (11 + ((i) - 1) * 6)) & 0x3F);
58 #define	  FUSE_SKU_CALIB_0_HS_TERM_RANGE_ADJ(x)		(((x) >>  7) & 0x0F);
59 #define	  FUSE_SKU_CALIB_0_HS_CURR_LEVEL_0(x)		(((x) >>  0) & 0x3F);
60 
61 #define	FUSE_USB_CALIB_EXT_0			0x250
62 #define	  FUSE_USB_CALIB_EXT_0_RPD_CTRL(x)		(((x) >>  0) & 0x1F);
63 
64 
65 /* Registers. */
66 #define	XUSB_PADCTL_USB2_PAD_MUX		0x004
67 
68 #define	XUSB_PADCTL_USB2_PORT_CAP		0x008
69 #define	 USB2_PORT_CAP_PORT_REVERSE_ID(p)		(1 << (3 + (p) * 4))
70 #define	 USB2_PORT_CAP_PORT_INTERNAL(p)			(1 << (2 + (p) * 4))
71 #define	 USB2_PORT_CAP_PORT_CAP(p, x)			(((x) & 3) << ((p) * 4))
72 #define	  USB2_PORT_CAP_PORT_CAP_OTG			0x3
73 #define	  USB2_PORT_CAP_PORT_CAP_DEVICE			0x2
74 #define	  USB2_PORT_CAP_PORT_CAP_HOST			0x1
75 #define	  USB2_PORT_CAP_PORT_CAP_DISABLED		0x0
76 
77 #define	XUSB_PADCTL_SS_PORT_MAP			0x014
78 #define	 SS_PORT_MAP_PORT_INTERNAL(p)			(1 << (3 + (p) * 4))
79 #define	 SS_PORT_MAP_PORT_MAP(p, x)			(((x) & 7) << ((p) * 4))
80 
81 #define	XUSB_PADCTL_ELPG_PROGRAM1		0x024
82 #define	 ELPG_PROGRAM1_AUX_MUX_LP0_VCORE_DOWN		(1 << 31)
83 #define	 ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN_EARLY	(1 << 30)
84 #define	 ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN		(1 << 29)
85 #define	 ELPG_PROGRAM1_SSP_ELPG_VCORE_DOWN(x) 		(1 << (2 + (x) * 3))
86 #define	 ELPG_PROGRAM1_SSP_ELPG_CLAMP_EN_EARLY(x) 	(1 << (1 + (x) * 3))
87 #define	 ELPG_PROGRAM1_SSP_ELPG_CLAMP_EN(x)		(1 << (0 + (x) * 3))
88 
89 #define	XUSB_PADCTL_USB3_PAD_MUX		0x028
90 #define	 USB3_PAD_MUX_SATA_IDDQ_DISABLE(x) 		(1 << (8 + (x)))
91 #define	 USB3_PAD_MUX_PCIE_IDDQ_DISABLE(x) 		(1 << (1 + (x)))
92 
93 #define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1(x) (0x084 + (x) * 0x40)
94 #define	 USB2_BATTERY_CHRG_OTGPAD_CTL1_USBON_RPU_OVRD_VAL (1 << 23)
95 #define	 USB2_BATTERY_CHRG_OTGPAD_CTL1_USBON_RPU_OVRD	( 1 << 22)
96 #define	 USB2_BATTERY_CHRG_OTGPAD_CTL1_USBON_RPD_OVRD_VAL (1 << 21)
97 #define	 USB2_BATTERY_CHRG_OTGPAD_CTL1_USBON_RPD_OVRD	 (1 << 20)
98 #define	 USB2_BATTERY_CHRG_OTGPAD_CTL1_USBOP_RPU_OVRD_VAL (1 << 19)
99 #define	 USB2_BATTERY_CHRG_OTGPAD_CTL1_USBOP_RPU_OVRD	 (1 << 18)
100 #define	 USB2_BATTERY_CHRG_OTGPAD_CTL1_USBOP_RPD_OVRD_VAL (1 << 17)
101 #define	 USB2_BATTERY_CHRG_OTGPAD_CTL1_USBOP_RPD_OVRD	 (1 << 16)
102 #define	 USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_DYN_DLY(x)	 (((x) & 0x3) <<  9)
103 #define	 USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_LEV(x)	 (((x) & 0x3) <<  7)
104 #define	 USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_FIX18	 (1 <<  6)
105 #define	 USB2_BATTERY_CHRG_OTGPAD_CTL1_DIV_DET_EN	 (1 <<  4)
106 #define	 USB2_BATTERY_CHRG_OTGPAD_CTL1_VOP_DIV2P7_DET	 (1 <<  3)
107 #define	 USB2_BATTERY_CHRG_OTGPAD_CTL1_VOP_DIV2P0_DET	 (1 <<  2)
108 #define	 USB2_BATTERY_CHRG_OTGPAD_CTL1_VON_DIV2P7_DET	 (1 <<  1)
109 #define	 USB2_BATTERY_CHRG_OTGPAD_CTL1_VON_DIV2P0_DET	 (1 <<  0)
110 
111 #define	XUSB_PADCTL_USB2_OTG_PAD_CTL0(x) 	(0x088 + (x) * 0x40)
112 #define	 USB2_OTG_PAD_CTL0_PD_ZI			(1 << 29)
113 #define	 USB2_OTG_PAD_CTL0_PD2_OVRD_EN			(1 << 28)
114 #define	 USB2_OTG_PAD_CTL0_PD2				(1 << 27)
115 #define	 USB2_OTG_PAD_CTL0_PD				(1 << 26)
116 #define	 USB2_OTG_PAD_CTL0_TERM_EN			(1 << 25)
117 #define	 USB2_OTG_PAD_CTL0_LS_FSLEW(x)			(((x) & 0x0F) << 21)
118 #define	 USB2_OTG_PAD_CTL0_LS_RSLEW(x)			(((x) & 0x0F) << 17)
119 #define	 USB2_OTG_PAD_CTL0_FS_FSLEW(x)			(((x) & 0x0F) << 13)
120 #define	 USB2_OTG_PAD_CTL0_FS_RSLEW(x)			(((x) & 0x0F) <<  9)
121 #define	 USB2_OTG_PAD_CTL0_HS_SLEW(x)			(((x) & 0x3F) <<  6)
122 #define	 USB2_OTG_PAD_CTL0_HS_CURR_LEVEL(x)		(((x) & 0x3F) <<  0)
123 
124 #define XUSB_PADCTL_USB2_OTG_PAD_CTL1(x) 	(0x08C + (x) * 0x40)
125 #define	 USB2_OTG_PAD_CTL1_RPD_CTRL(x)			(((x) & 0x1F) <<  26)
126 #define	 USB2_OTG_PAD_CTL1_RPU_STATUS_HIGH		(1 <<  25)
127 #define	 USB2_OTG_PAD_CTL1_RPU_SWITCH_LOW		(1 <<  24)
128 #define	 USB2_OTG_PAD_CTL1_RPU_SWITCH_OVRD		(1 <<  23)
129 #define	 USB2_OTG_PAD_CTL1_HS_LOOPBACK_OVRD_VAL		(1 <<  22)
130 #define	 USB2_OTG_PAD_CTL1_HS_LOOPBACK_OVRD_EN		(1 <<  21)
131 #define	 USB2_OTG_PAD_CTL1_PTERM_RANGE_ADJ(x)		(((x) & 0x0F) << 17)
132 #define	 USB2_OTG_PAD_CTL1_PD_DISC_OVRD_VAL		(1 << 16)
133 #define	 USB2_OTG_PAD_CTL1_PD_CHRP_OVRD_VAL		(1 << 15)
134 #define	 USB2_OTG_PAD_CTL1_RPU_RANGE_ADJ(x)		(((x) & 0x03) << 13)
135 #define	 USB2_OTG_PAD_CTL1_HS_COUP_EN(x)		(((x) & 0x03) << 11)
136 #define	 USB2_OTG_PAD_CTL1_SPARE(x)			(((x) & 0x0F) <<  7)
137 #define	 USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ(x)		(((x) & 0x0F) <<  3)
138 #define	 USB2_OTG_PAD_CTL1_PD_DR			(1 <<  2)
139 #define	 USB2_OTG_PAD_CTL1_PD_DISC_OVRD			(1 <<  1)
140 #define	 USB2_OTG_PAD_CTL1_PD_CHRP_OVRD			(1 <<  0)
141 
142 #define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL0(x) (0x0C0 + (x) * 0x40)
143 #define	XUSB_PADCTL_USB2_BIAS_PAD_CTL0		0x0284
144 #define	 USB2_BIAS_PAD_CTL0_TRK_PWR_ENA			(1 << 29)
145 #define	 USB2_BIAS_PAD_CTL0_SPARE(x)			(((x) & 0xF) << 25)
146 #define	 USB2_BIAS_PAD_CTL0_CHG_DIV(x)			(((x) & 0xF) << 21)
147 #define	 USB2_BIAS_PAD_CTL0_TEMP_COEF(x)		(((x) & 0x7) << 18)
148 #define	 USB2_BIAS_PAD_CTL0_VREF_CTRL(x)		(((x) & 0x7) << 15)
149 #define	 USB2_BIAS_PAD_CTL0_ADJRPU(x)			(((x) & 0x7) << 12)
150 #define	 USB2_BIAS_PAD_CTL0_PD				(1 << 11)
151 #define	 USB2_BIAS_PAD_CTL0_TERM_OFFSETL(x)		(((x) & 0x7) <<  8)
152 #define	 USB2_BIAS_PAD_CTL0_HS_CHIRP_LEVEL(x)		(((x) & 0x3) <<  6)
153 #define	 USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL(x)		(((x) & 0x7) <<  3)
154 #define	 USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL(x)		(((x) & 0x7) <<  0)
155 
156 #define	XUSB_PADCTL_USB2_BIAS_PAD_CTL1		0x0288
157 #define	 USB2_BIAS_PAD_CTL1_FORCE_TRK_CLK_EN		(1 << 30)
158 #define	 USB2_BIAS_PAD_CTL1_TRK_SW_OVRD			(1 << 29)
159 #define	 USB2_BIAS_PAD_CTL1_TRK_DONE			(1 << 28)
160 #define	 USB2_BIAS_PAD_CTL1_TRK_START			(1 << 27)
161 #define	 USB2_BIAS_PAD_CTL1_PD_TRK			(1 << 26)
162 #define	 USB2_BIAS_PAD_CTL1_TRK_DONE_RESET_TIMER(x)	(((x) & 0x7F) << 19)
163 #define	 USB2_BIAS_PAD_CTL1_TRK_START_TIMER(x)		(((x) & 0x7F) << 12)
164 #define	 USB2_BIAS_PAD_CTL1_PCTRL(x)			(((x) & 0x3F) <<  6)
165 #define	 USB2_BIAS_PAD_CTL1_TCTRL(x)			(((x) & 0x3F) <<  0)
166 
167 #define	XUSB_PADCTL_HSIC_PAD_CTL0(x)		(0x300 + (x) * 0x20)
168 #define	 HSIC_PAD_CTL0_RPU_STROBE			(1 << 18)
169 #define	 HSIC_PAD_CTL0_RPU_DATA1			(1 << 17)
170 #define	 HSIC_PAD_CTL0_RPU_DATA0			(1 << 16)
171 #define	 HSIC_PAD_CTL0_RPD_STROBE			(1 << 15)
172 #define	 HSIC_PAD_CTL0_RPD_DATA1			(1 << 14)
173 #define	 HSIC_PAD_CTL0_RPD_DATA0			(1 << 13)
174 #define	 HSIC_PAD_CTL0_LPBK_STROBE			(1 << 12)
175 #define	 HSIC_PAD_CTL0_LPBK_DATA1			(1 << 11)
176 #define	 HSIC_PAD_CTL0_LPBK_DATA0			(1 << 10)
177 #define	 HSIC_PAD_CTL0_PD_ZI_STROBE			(1 <<  9)
178 #define	 HSIC_PAD_CTL0_PD_ZI_DATA1			(1 <<  8)
179 #define	 HSIC_PAD_CTL0_PD_ZI_DATA0			(1 <<  7)
180 #define	 HSIC_PAD_CTL0_PD_RX_STROBE			(1 <<  6)
181 #define	 HSIC_PAD_CTL0_PD_RX_DATA1			(1 <<  5)
182 #define	 HSIC_PAD_CTL0_PD_RX_DATA0			(1 <<  4)
183 #define	 HSIC_PAD_CTL0_PD_TX_STROBE			(1 <<  3)
184 #define	 HSIC_PAD_CTL0_PD_TX_DATA1			(1 <<  2)
185 #define	 HSIC_PAD_CTL0_PD_TX_DATA0			(1 <<  1)
186 #define	 HSIC_PAD_CTL0_IDDQ				(1 <<  0)
187 
188 #define	XUSB_PADCTL_HSIC_PAD_CTL1(x)		(0x304 + (x) * 0x20)
189 #define	 HSIC_PAD_CTL1_RTERM(x)				(((x) & 0xF) << 12)
190 #define	 HSIC_PAD_CTL1_HSIC_OPT(x)			(((x) & 0xF) <<  8)
191 #define	 HSIC_PAD_CTL1_TX_SLEW(x)			(((x) & 0xF) <<  4)
192 #define	 HSIC_PAD_CTL1_TX_RTUNEP(x)			(((x) & 0xF) <<  0)
193 
194 #define	XUSB_PADCTL_HSIC_PAD_CTL2(x)		(0x308 + (x) * 0x20)
195 #define	 HSIC_PAD_CTL2_RX_STROBE_TRIM(x)		(((x) & 0xF) <<  8)
196 #define	 HSIC_PAD_CTL2_RX_DATA1_TRIM(x)			(((x) & 0xF) <<  4)
197 #define	 HSIC_PAD_CTL2_RX_DATA0_TRIM(x)			(((x) & 0xF) <<  0)
198 
199 #define	XUSB_PADCTL_HSIC_PAD_TRK_CTL		0x340
200 #define	 HSIC_PAD_TRK_CTL_AUTO_RTERM_EN			(1 << 24)
201 #define	 HSIC_PAD_TRK_CTL_FORCE_TRK_CLK_EN		(1 << 23)
202 #define	 HSIC_PAD_TRK_CTL_TRK_SW_OVRD			(1 << 22)
203 #define	 HSIC_PAD_TRK_CTL_TRK_DONE			(1 << 21)
204 #define	 HSIC_PAD_TRK_CTL_TRK_START			(1 << 20)
205 #define	 HSIC_PAD_TRK_CTL_PD_TRK			(1 << 19)
206 #define	 HSIC_PAD_TRK_CTL_TRK_DONE_RESET_TIMER(x)	(((x) & 0x3F) << 12)
207 #define	 HSIC_PAD_TRK_CTL_TRK_START_TIMER(x)		(((x) & 0x7F) <<  5)
208 #define	 HSIC_PAD_TRK_CTL_RTERM_OUT(x)			(((x) & 0x1F) <<  0)
209 
210 #define XUSB_PADCTL_HSIC_STRB_TRIM_CONTROL	0x344
211 
212 #define XUSB_PADCTL_UPHY_PLL_P0_CTL1		0x360
213 #define  UPHY_PLL_P0_CTL1_PLL0_FREQ_PSDIV(x)		(((x) & 0x03) << 28)
214 #define  UPHY_PLL_P0_CTL1_PLL0_FREQ_NDIV(x)		(((x) & 0xFF) << 20)
215 #define  UPHY_PLL_P0_CTL1_PLL0_FREQ_MDIV(x)		(((x) & 0x03) << 16)
216 #define  UPHY_PLL_P0_CTL1_PLL0_LOCKDET_STATUS 		(1 << 15)
217 #define  UPHY_PLL_P0_CTL1_PLL0_MODE_GET(x)		(((x) >> 8) & 0x03)
218 #define  UPHY_PLL_P0_CTL1_PLL0_BYPASS_EN 		(1 <<  7)
219 #define  UPHY_PLL_P0_CTL1_PLL0_FREERUN_EN		(1 <<  6)
220 #define  UPHY_PLL_P0_CTL1_PLL0_PWR_OVRD			(1 <<  4)
221 #define  UPHY_PLL_P0_CTL1_PLL0_ENABLE 			(1 <<  3)
222 #define  UPHY_PLL_P0_CTL1_PLL0_SLEEP(x)			(((x) & 0x03) <<  1)
223 #define  UPHY_PLL_P0_CTL1_PLL0_IDDQ 			(1 << 0)
224 
225 #define XUSB_PADCTL_UPHY_PLL_P0_CTL2		0x364
226 #define  UPHY_PLL_P0_CTL2_PLL0_CAL_CTRL(x)		(((x) & 0xFFFFFF) << 4)
227 #define  UPHY_PLL_P0_CTL2_PLL0_CAL_RESET		(1 << 3)
228 #define  UPHY_PLL_P0_CTL2_PLL0_CAL_OVRD			(1 << 2)
229 #define  UPHY_PLL_P0_CTL2_PLL0_CAL_DONE			(1 << 1)
230 #define  UPHY_PLL_P0_CTL2_PLL0_CAL_EN			(1 << 0)
231 
232 #define XUSB_PADCTL_UPHY_PLL_P0_CTL4		0x36c
233 #define  UPHY_PLL_P0_CTL4_PLL0_TCLKOUT_EN		(1 << 28)
234 #define  UPHY_PLL_P0_CTL4_PLL0_CLKDIST_CTRL(x)		(((x) & 0xF) << 20)
235 #define  UPHY_PLL_P0_CTL4_PLL0_XDIGCLK_EN		(1 << 19)
236 #define  UPHY_PLL_P0_CTL4_PLL0_XDIGCLK_SEL(x)		(((x) & 0x7) << 16)
237 #define  UPHY_PLL_P0_CTL4_PLL0_TXCLKREF_EN		(1 << 15)
238 #define  UPHY_PLL_P0_CTL4_PLL0_TXCLKREF_SEL(x)		(((x) & 0x3) << 12)
239 #define  UPHY_PLL_P0_CTL4_PLL0_FBCLKBUF_EN		(1 <<  9)
240 #define  UPHY_PLL_P0_CTL4_PLL0_REFCLKBUF_EN		(1 <<  8)
241 #define  UPHY_PLL_P0_CTL4_PLL0_REFCLK_SEL(x)		(((x) & 0xF) <<  4)
242 #define  UPHY_PLL_P0_CTL4_PLL0_REFCLK_TERM100		(1 <<  0)
243 
244 #define XUSB_PADCTL_UPHY_PLL_P0_CTL5		0x370
245 #define  UPHY_PLL_P0_CTL5_PLL0_DCO_CTRL(x)		(((x) & 0xFF) << 16)
246 #define  UPHY_PLL_P0_CTL5_PLL0_LPF_CTRL(x)		(((x) & 0xFF) <<  8)
247 #define  UPHY_PLL_P0_CTL5_PLL0_CP_CTRL(x)		(((x) & 0x0F) <<  4)
248 #define  UPHY_PLL_P0_CTL5_PLL0_PFD_CTRL(x)		(((x) & 0x03) <<  0)
249 
250 #define XUSB_PADCTL_UPHY_PLL_P0_CTL8		0x37c
251 #define  UPHY_PLL_P0_CTL8_PLL0_RCAL_DONE		(1U << 31)
252 #define  UPHY_PLL_P0_CTL8_PLL0_RCAL_VAL(x)		(((x) & 0x1F) << 24)
253 #define  UPHY_PLL_P0_CTL8_PLL0_RCAL_BYP_EN		(1 << 23)
254 #define  UPHY_PLL_P0_CTL8_PLL0_RCAL_BYP_CODE(x)		(((x) & 0x1F) << 16)
255 #define  UPHY_PLL_P0_CTL8_PLL0_RCAL_OVRD		(1 << 15)
256 #define  UPHY_PLL_P0_CTL8_PLL0_RCAL_CLK_EN		(1 << 13)
257 #define  UPHY_PLL_P0_CTL8_PLL0_RCAL_EN			(1 << 12)
258 #define  UPHY_PLL_P0_CTL8_PLL0_BGAP_CTRL(x)		(((x) & 0xFFF) <<  0)
259 
260 #define XUSB_PADCTL_UPHY_MISC_PAD_P_CTL1(x)	(0x460 + (x) * 0x40)
261 #define XUSB_PADCTL_UPHY_PLL_S0_CTL1		0x860
262 #define  UPHY_PLL_S0_CTL1_PLL0_FREQ_PSDIV(x)		(((x) & 0x03) << 28)
263 #define  UPHY_PLL_S0_CTL1_PLL0_FREQ_NDIV(x)		(((x) & 0xFF) << 20)
264 #define  UPHY_PLL_S0_CTL1_PLL0_FREQ_MDIV(x)		(((x) & 0x03) << 16)
265 #define  UPHY_PLL_S0_CTL1_PLL0_LOCKDET_STATUS 		(1 << 15)
266 #define  UPHY_PLL_S0_CTL1_PLL0_MODE_GET(x)		(((x) >> 8) & 0x03)
267 #define  UPHY_PLL_S0_CTL1_PLL0_BYPASS_EN 		(1 <<  7)
268 #define  UPHY_PLL_S0_CTL1_PLL0_FREERUN_EN		(1 <<  6)
269 #define  UPHY_PLL_S0_CTL1_PLL0_PWR_OVRD			(1 <<  4)
270 #define  UPHY_PLL_S0_CTL1_PLL0_ENABLE 			(1 <<  3)
271 #define  UPHY_PLL_S0_CTL1_PLL0_SLEEP(x)			(((x) & 0x03) <<  1)
272 #define  UPHY_PLL_S0_CTL1_PLL0_IDDQ 			(1 << 0)
273 
274 #define XUSB_PADCTL_UPHY_PLL_S0_CTL2		0x864
275 #define  UPHY_PLL_S0_CTL2_PLL0_CAL_CTRL(x)		(((x) & 0xFFFFFF) << 4)
276 #define  UPHY_PLL_S0_CTL2_PLL0_CAL_RESET		(1 << 3)
277 #define  UPHY_PLL_S0_CTL2_PLL0_CAL_OVRD			(1 << 2)
278 #define  UPHY_PLL_S0_CTL2_PLL0_CAL_DONE			(1 << 1)
279 #define  UPHY_PLL_S0_CTL2_PLL0_CAL_EN			(1 << 0)
280 
281 #define XUSB_PADCTL_UPHY_PLL_S0_CTL4		0x86c
282 #define  UPHY_PLL_S0_CTL4_PLL0_TCLKOUT_EN		(1 << 28)
283 #define  UPHY_PLL_S0_CTL4_PLL0_CLKDIST_CTRL(x)		(((x) & 0xF) << 20)
284 #define  UPHY_PLL_S0_CTL4_PLL0_XDIGCLK_EN		(1 << 19)
285 #define  UPHY_PLL_S0_CTL4_PLL0_XDIGCLK_SEL(x)		(((x) & 0x7) << 16)
286 #define  UPHY_PLL_S0_CTL4_PLL0_TXCLKREF_EN		(1 << 15)
287 #define  UPHY_PLL_S0_CTL4_PLL0_TXCLKREF_SEL(x)		(((x) & 0x3) << 12)
288 #define  UPHY_PLL_S0_CTL4_PLL0_FBCLKBUF_EN		(1 <<  9)
289 #define  UPHY_PLL_S0_CTL4_PLL0_REFCLKBUF_EN		(1 <<  8)
290 #define  UPHY_PLL_S0_CTL4_PLL0_REFCLK_SEL(x)		(((x) & 0xF) <<  4)
291 #define  UPHY_PLL_S0_CTL4_PLL0_REFCLK_TERM100		(1 <<  0)
292 
293 #define XUSB_PADCTL_UPHY_PLL_S0_CTL5		0x870
294 #define  UPHY_PLL_S0_CTL5_PLL0_DCO_CTRL(x)		(((x) & 0xFF) << 16)
295 #define  UPHY_PLL_S0_CTL5_PLL0_LPF_CTRL(x)		(((x) & 0xFF) <<  8)
296 #define  UPHY_PLL_S0_CTL5_PLL0_CP_CTRL(x)		(((x) & 0x0F) <<  4)
297 #define  UPHY_PLL_S0_CTL5_PLL0_PFD_CTRL(x)		(((x) & 0x03) <<  0)
298 
299 #define XUSB_PADCTL_UPHY_PLL_S0_CTL8		0x87c
300 #define  UPHY_PLL_S0_CTL8_PLL0_RCAL_DONE		(1U << 31)
301 #define  UPHY_PLL_S0_CTL8_PLL0_RCAL_VAL(x)		(((x) & 0x1F) << 24)
302 #define  UPHY_PLL_S0_CTL8_PLL0_RCAL_BYP_EN		(1 << 23)
303 #define  UPHY_PLL_S0_CTL8_PLL0_RCAL_BYP_CODE(x)		(((x) & 0x1F) << 16)
304 #define  UPHY_PLL_S0_CTL8_PLL0_RCAL_OVRD		(1 << 15)
305 #define  UPHY_PLL_S0_CTL8_PLL0_RCAL_CLK_EN		(1 << 13)
306 #define  UPHY_PLL_S0_CTL8_PLL0_RCAL_EN			(1 << 12)
307 #define  UPHY_PLL_S0_CTL8_PLL0_BGAP_CTRL(x)		(((x) & 0xFFF) <<  0)
308 
309 #define XUSB_PADCTL_UPHY_MISC_PAD_S0_CTL1	0x960
310 #define XUSB_PADCTL_UPHY_USB3_PAD_ECTL1(x)	(0xa60 + (x) * 0x40)
311 #define	 UPHY_USB3_PAD_ECTL1_TX_TERM_CTRL(x)		(((x) & 0x3) << 16)
312 
313 #define XUSB_PADCTL_UPHY_USB3_PAD_ECTL2(x)	(0xa64 + (x) * 0x40)
314 #define	 UPHY_USB3_PAD_ECTL2_RX_IQ_CTRL(x)		(((x) & 0x000F) << 16)
315 #define	 UPHY_USB3_PAD_ECTL2_RX_CTLE(x)			(((x) & 0xFFFF) <<  0)
316 
317 #define XUSB_PADCTL_UPHY_USB3_PAD_ECTL3(x)	(0xa68 + (x) * 0x40)
318 #define XUSB_PADCTL_UPHY_USB3_PAD_ECTL4(x)	(0xa6c + (x) * 0x40)
319 #define	 UPHY_USB3_PAD_ECTL4_RX_CDR_CTRL(x)		(((x) & 0xFFFF) << 16)
320 #define	 UPHY_USB3_PAD_ECTL4_RX_PI_CTRL(x)		(((x) & 0x00FF) <<  0)
321 
322 #define XUSB_PADCTL_UPHY_USB3_PAD_ECTL6(x)	(0xa74 + (x) * 0x40)
323 
324 
325 #define	WR4(_sc, _r, _v)	bus_write_4((_sc)->mem_res, (_r), (_v))
326 #define	RD4(_sc, _r)		bus_read_4((_sc)->mem_res, (_r))
327 
328 
329 struct padctl_softc {
330 	device_t	dev;
331 	struct resource	*mem_res;
332 	hwreset_t	rst;
333 	int		phy_ena_cnt;
334 	int		pcie_ena_cnt;
335 	int		sata_ena_cnt;
336 
337 	/* Fuses calibration data */
338 	/* USB2 */
339 	uint32_t	hs_curr_level[4];
340 	uint32_t	hs_curr_level_offs;	/* Not inited yet, always 0 */
341 	uint32_t	hs_term_range_adj;
342 	uint32_t	rpd_ctrl;
343 
344 	/* HSIC */
345 	uint32_t	rx_strobe_trim;		/* Not inited yet, always 0 */
346 	uint32_t	rx_data0_trim;		/* Not inited yet, always 0 */
347 	uint32_t	rx_data1_trim;		/* Not inited yet, always 0 */
348 	uint32_t	tx_rtune_p;		/* Not inited yet, always 0 */
349 	uint32_t	strobe_trim;		/* Not inited yet, always 0 */
350 };
351 
352 static struct ofw_compat_data compat_data[] = {
353 	{"nvidia,tegra210-xusb-padctl",	1},
354 	{NULL,				0},
355 };
356 
357 /* Ports. */
358 enum padctl_port_type {
359 	PADCTL_PORT_USB2,
360 	PADCTL_PORT_HSIC,
361 	PADCTL_PORT_USB3,
362 };
363 
364 struct padctl_lane;
365 struct padctl_port {
366 	enum padctl_port_type	type;
367 	const char		*name;
368 	const char		*base_name;
369 	int			idx;
370 	int			(*init)(struct padctl_softc *sc,
371 				    struct padctl_port *port);
372 
373 	/* Runtime data. */
374 	phandle_t		xref;
375 	bool			enabled;
376 	bool			internal;
377 	uint32_t		companion;
378 	regulator_t		supply_vbus;
379 	struct padctl_lane	*lane;
380 };
381 
382 static int usb3_port_init(struct padctl_softc *sc, struct padctl_port *port);
383 
384 #define	PORT(t, n, p, i) {						\
385 	.type = t,							\
386 	.name = n "-" #p,						\
387 	.base_name = n,							\
388 	.idx = p,							\
389 	.init = i,							\
390 }
391 static struct padctl_port ports_tbl[] = {
392 	PORT(PADCTL_PORT_USB2, "usb2", 0, NULL),
393 	PORT(PADCTL_PORT_USB2, "usb2", 1, NULL),
394 	PORT(PADCTL_PORT_USB2, "usb2", 2, NULL),
395 	PORT(PADCTL_PORT_USB2, "usb2", 3, NULL),
396 	PORT(PADCTL_PORT_HSIC, "hsic", 0, NULL),
397 	PORT(PADCTL_PORT_HSIC, "hsic", 1, NULL),
398 	PORT(PADCTL_PORT_USB3, "usb3", 0, usb3_port_init),
399 	PORT(PADCTL_PORT_USB3, "usb3", 1, usb3_port_init),
400 };
401 
402 /* Pads - a group of lannes. */
403 enum padctl_pad_type {
404 	PADCTL_PAD_USB2,
405 	PADCTL_PAD_HSIC,
406 	PADCTL_PAD_PCIE,
407 	PADCTL_PAD_SATA,
408 };
409 
410 struct padctl_lane;
411 struct padctl_pad {
412 	const char		*name;
413 	enum padctl_pad_type	type;
414 	const char		*clock_name;
415 	char			*reset_name; 	/* XXX constify !!!!!! */
416 	int			(*enable)(struct padctl_softc *sc,
417 				    struct padctl_lane *lane);
418 	int			(*disable)(struct padctl_softc *sc,
419 				    struct padctl_lane *lane);
420 	/* Runtime data. */
421 	bool			enabled;
422 	clk_t			clk;
423 	hwreset_t		reset;
424 	int			nlanes;
425 	struct padctl_lane	*lanes[8]; 	/* Safe maximum value. */
426 };
427 
428 static int usb2_enable(struct padctl_softc *sc, struct padctl_lane *lane);
429 static int usb2_disable(struct padctl_softc *sc, struct padctl_lane *lane);
430 static int hsic_enable(struct padctl_softc *sc, struct padctl_lane *lane);
431 static int hsic_disable(struct padctl_softc *sc, struct padctl_lane *lane);
432 static int pcie_enable(struct padctl_softc *sc, struct padctl_lane *lane);
433 static int pcie_disable(struct padctl_softc *sc, struct padctl_lane *lane);
434 static int sata_enable(struct padctl_softc *sc, struct padctl_lane *lane);
435 static int sata_disable(struct padctl_softc *sc, struct padctl_lane *lane);
436 
437 #define	PAD(n, t, cn, rn, e, d) {						\
438 	.name = n,							\
439 	.type = t,							\
440 	.clock_name = cn,						\
441 	.reset_name = rn,						\
442 	.enable = e,							\
443 	.disable = d,							\
444 }
445 static struct padctl_pad pads_tbl[] = {
446 	PAD("usb2", PADCTL_PAD_USB2, "trk",  NULL, usb2_enable, usb2_disable),
447 	PAD("hsic", PADCTL_PAD_HSIC, "trk",  NULL, hsic_enable, hsic_disable),
448 	PAD("pcie", PADCTL_PAD_PCIE, "pll", "phy", pcie_enable, pcie_disable),
449 	PAD("sata", PADCTL_PAD_SATA, "pll", "phy", sata_enable, sata_disable),
450 };
451 
452 /* Lanes. */
453 static char *usb_mux[] = {"snps", "xusb", "uart", "rsvd"};
454 static char *hsic_mux[] = {"snps", "xusb"};
455 static char *pci_mux[] = {"pcie-x1", "usb3-ss", "sata", "pcie-x4"};
456 
457 struct padctl_lane {
458 	const char		*name;
459 	int			idx;
460 	bus_size_t		reg;
461 	uint32_t		shift;
462 	uint32_t		mask;
463 	char			**mux;
464 	int			nmux;
465 	/* Runtime data. */
466 	bool			enabled;
467 	phandle_t		xref;
468 	struct padctl_pad	*pad;
469 	struct padctl_port	*port;
470 	int			mux_idx;
471 
472 };
473 
474 #define	LANE(n, p, r, s, m, mx) {					\
475 	.name = n "-" #p,						\
476 	.idx = p,							\
477 	.reg = r,							\
478 	.shift = s,							\
479 	.mask = m,							\
480 	.mux = mx,							\
481 	.nmux = nitems(mx),						\
482 }
483 static struct padctl_lane lanes_tbl[] = {
484 	LANE("usb2", 0, XUSB_PADCTL_USB2_PAD_MUX,  0, 0x3, usb_mux),
485 	LANE("usb2", 1, XUSB_PADCTL_USB2_PAD_MUX,  2, 0x3, usb_mux),
486 	LANE("usb2", 2, XUSB_PADCTL_USB2_PAD_MUX,  4, 0x3, usb_mux),
487 	LANE("usb2", 3, XUSB_PADCTL_USB2_PAD_MUX,  6, 0x3, usb_mux),
488 	LANE("hsic", 0, XUSB_PADCTL_USB2_PAD_MUX, 14, 0x1, hsic_mux),
489 	LANE("hsic", 1, XUSB_PADCTL_USB2_PAD_MUX, 15, 0x1, hsic_mux),
490 	LANE("pcie", 0, XUSB_PADCTL_USB3_PAD_MUX, 12, 0x3, pci_mux),
491 	LANE("pcie", 1, XUSB_PADCTL_USB3_PAD_MUX, 14, 0x3, pci_mux),
492 	LANE("pcie", 2, XUSB_PADCTL_USB3_PAD_MUX, 16, 0x3, pci_mux),
493 	LANE("pcie", 3, XUSB_PADCTL_USB3_PAD_MUX, 18, 0x3, pci_mux),
494 	LANE("pcie", 4, XUSB_PADCTL_USB3_PAD_MUX, 20, 0x3, pci_mux),
495 	LANE("pcie", 5, XUSB_PADCTL_USB3_PAD_MUX, 22, 0x3, pci_mux),
496 	LANE("pcie", 6, XUSB_PADCTL_USB3_PAD_MUX, 24, 0x3, pci_mux),
497 	LANE("sata", 0, XUSB_PADCTL_USB3_PAD_MUX, 30, 0x3, pci_mux),
498 };
499 
500 /* Define all possible mappings for USB3 port lanes */
501 struct padctl_lane_map {
502 	int			port_idx;
503 	enum padctl_pad_type	pad_type;
504 	int			lane_idx;
505 };
506 
507 #define	LANE_MAP(pi, pt, li) {						\
508 	.port_idx = pi,							\
509 	.pad_type = pt,							\
510 	.lane_idx = li,							\
511 }
512 static struct padctl_lane_map lane_map_tbl[] = {
513 	LANE_MAP(0, PADCTL_PAD_PCIE, 6), 	/* port USB3-0 -> lane PCIE-0 */
514 	LANE_MAP(1, PADCTL_PAD_PCIE, 5), 	/* port USB3-1 -> lane PCIE-1 */
515 	LANE_MAP(2, PADCTL_PAD_PCIE, 0), 	/* port USB3-2 -> lane PCIE-0 */
516 	LANE_MAP(2, PADCTL_PAD_PCIE, 2), 	/* port USB3-2 -> lane PCIE-2 */
517 	LANE_MAP(3, PADCTL_PAD_PCIE, 4), 	/* port USB3-3 -> lane PCIE-4 */
518 };
519 
520 /* Phy class and methods. */
521 static int xusbpadctl_phy_enable(struct phynode *phy, bool enable);
522 static phynode_method_t xusbpadctl_phynode_methods[] = {
523 	PHYNODEMETHOD(phynode_enable,	xusbpadctl_phy_enable),
524 	PHYNODEMETHOD_END
525 
526 };
527 DEFINE_CLASS_1(xusbpadctl_phynode, xusbpadctl_phynode_class,
528     xusbpadctl_phynode_methods, 0, phynode_class);
529 
530 static struct padctl_port *search_lane_port(struct padctl_softc *sc,
531     struct padctl_lane *lane);
532 
533 
534 static void tegra210_xusb_pll_hw_control_enable(void) {}
535 static void tegra210_xusb_pll_hw_sequence_start(void) {}
536 static void tegra210_sata_pll_hw_control_enable(void) {}
537 static void tegra210_sata_pll_hw_sequence_start(void) {}
538 
539 /* -------------------------------------------------------------------------
540  *
541  *   PEX functions
542  */
543 static int
544 uphy_pex_enable(struct padctl_softc *sc, struct padctl_pad *pad)
545 {
546 	uint32_t reg;
547 	int rv, i;
548 
549 	if (sc->pcie_ena_cnt > 0) {
550 		sc->pcie_ena_cnt++;
551 		return (0);
552 	}
553 
554 	/* 22.8.4 UPHY PLLs, Step 4, page 1346 */
555 	/* 1. Deassert PLL/Lane resets. */
556 	rv = clk_enable(pad->clk);
557 	if (rv < 0) {
558 		device_printf(sc->dev, "Cannot enable clock for pad '%s': %d\n",
559 		    pad->name, rv);
560 		return (rv);
561 	}
562 
563 	rv = hwreset_deassert(pad->reset);
564 	if (rv < 0) {
565 		device_printf(sc->dev, "Cannot unreset pad '%s': %d\n",
566 		    pad->name, rv);
567 		clk_disable(pad->clk);
568 		return (rv);
569 	}
570 
571 	reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
572 	reg &= ~UPHY_PLL_P0_CTL2_PLL0_CAL_CTRL(~0);
573 	reg |= UPHY_PLL_P0_CTL2_PLL0_CAL_CTRL(0x136);
574 	WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2, reg);
575 
576 	reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL5);
577 	reg &= ~UPHY_PLL_P0_CTL5_PLL0_DCO_CTRL(~0);
578 	reg |= UPHY_PLL_P0_CTL5_PLL0_DCO_CTRL(0x2a);
579 	WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL5, reg);
580 
581 	reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
582 	reg |= UPHY_PLL_P0_CTL1_PLL0_PWR_OVRD;
583 	WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1, reg);
584 
585 	reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
586 	reg |= UPHY_PLL_P0_CTL2_PLL0_CAL_OVRD;
587 	WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2, reg);
588 
589 	reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
590 	reg |= UPHY_PLL_P0_CTL8_PLL0_RCAL_OVRD;
591 	WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL8, reg);
592 
593 	/*
594 	 * 2. For the following registers, default values
595 	 *    take care of the desired frequency.
596 	 */
597 	reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL4);
598 	reg &= ~UPHY_PLL_P0_CTL4_PLL0_TXCLKREF_SEL(~0);
599 	reg &= ~UPHY_PLL_P0_CTL4_PLL0_REFCLK_SEL(~0);
600 	reg |= UPHY_PLL_P0_CTL4_PLL0_TXCLKREF_SEL(0x2);
601 	reg |= UPHY_PLL_P0_CTL4_PLL0_TXCLKREF_EN;
602 	WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL4, reg);
603 
604 	reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
605 	reg &= ~UPHY_PLL_P0_CTL1_PLL0_FREQ_MDIV(~0);
606 	reg &= ~UPHY_PLL_P0_CTL1_PLL0_FREQ_NDIV(~0);
607 	reg |= UPHY_PLL_P0_CTL1_PLL0_FREQ_NDIV(0x19);
608 	WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1, reg);
609 
610 	reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
611 	reg &= ~UPHY_PLL_P0_CTL1_PLL0_IDDQ;
612 	WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1, reg);
613 
614 	reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
615 	reg &= ~UPHY_PLL_P0_CTL1_PLL0_SLEEP(~0);
616 	WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1, reg);
617 
618 	/* 3. Wait 100 ns. */
619 	DELAY(10);
620 
621 	/* XXX This in not in TRM */
622 	reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL4);
623 	reg |= UPHY_PLL_P0_CTL4_PLL0_REFCLKBUF_EN;
624 	WR4(sc,  XUSB_PADCTL_UPHY_PLL_P0_CTL4, reg);
625 
626 	/* 4. Calibration. */
627 	reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
628 	reg |= UPHY_PLL_P0_CTL2_PLL0_CAL_EN;
629 	WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2, reg);
630 	for (i = 30; i > 0; i--) {
631 		reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
632 		if (reg & UPHY_PLL_P0_CTL2_PLL0_CAL_DONE)
633 			break;
634 		DELAY(10);
635 	}
636 	if (i <= 0) {
637 		device_printf(sc->dev, "Timedout in calibration step 1 "
638 		    "for pad '%s' (0x%08X).\n", pad->name, reg);
639 		rv = ETIMEDOUT;
640 		goto err;
641 	}
642 
643 	reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
644 	reg &= ~UPHY_PLL_P0_CTL2_PLL0_CAL_EN;
645 	WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2, reg);
646 	for (i = 10; i > 0; i--) {
647 		reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
648 		if ((reg & UPHY_PLL_P0_CTL2_PLL0_CAL_DONE) == 0)
649 			break;
650 		DELAY(10);
651 	}
652 	if (i <= 0) {
653 		device_printf(sc->dev, "Timedout in calibration step 2 "
654 		    "for pad '%s'.\n", pad->name);
655 		rv = ETIMEDOUT;
656 		goto err;
657 	}
658 
659 	/* 5. Enable the PLL (20 �s Lock time) */
660 	reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
661 	reg |= UPHY_PLL_P0_CTL1_PLL0_ENABLE;
662 	WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1, reg);
663 	for (i = 10; i > 0; i--) {
664 		reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
665 		if (reg & UPHY_PLL_P0_CTL1_PLL0_LOCKDET_STATUS)
666 			break;
667 		DELAY(10);
668 	}
669 	if (i <= 0) {
670 		device_printf(sc->dev, "Timedout while enabling PLL "
671 		    "for pad '%s'.\n", pad->name);
672 		rv = ETIMEDOUT;
673 		goto err;
674 	}
675 
676 	/* 6. RCAL. */
677 	reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
678 	reg |= UPHY_PLL_P0_CTL8_PLL0_RCAL_EN;
679 	reg |= UPHY_PLL_P0_CTL8_PLL0_RCAL_CLK_EN;
680 	WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL8, reg);
681 
682 	for (i = 10; i > 0; i--) {
683 		reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
684 		if (reg & UPHY_PLL_P0_CTL8_PLL0_RCAL_DONE)
685 			break;
686 		DELAY(10);
687 	}
688 	if (i <= 0) {
689 		device_printf(sc->dev, "Timedout in RX calibration step 1 "
690 		    "for pad '%s'.\n", pad->name);
691 		rv = ETIMEDOUT;
692 		goto err;
693 	}
694 
695 	reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
696 	reg &= ~UPHY_PLL_P0_CTL8_PLL0_RCAL_EN;
697 	WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL8, reg);
698 
699 	for (i = 10; i > 0; i--) {
700 		reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
701 		if (!(reg & UPHY_PLL_P0_CTL8_PLL0_RCAL_DONE))
702 			break;
703 
704 		DELAY(10);
705 	}
706 	if (i <= 0) {
707 		device_printf(sc->dev, "Timedout in RX calibration step 2 "
708 		    "for pad '%s'.\n", pad->name);
709 		rv = ETIMEDOUT;
710 		goto err;
711 	}
712 
713 	reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
714 	reg &= ~UPHY_PLL_P0_CTL8_PLL0_RCAL_CLK_EN;
715 	WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL8, reg);
716 
717 	/* Enable Hardware Power Sequencer. */
718 	tegra210_xusb_pll_hw_control_enable();
719 
720 	reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
721 	reg &= ~UPHY_PLL_P0_CTL1_PLL0_PWR_OVRD;
722 	WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1, reg);
723 
724 	reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
725 	reg &= ~UPHY_PLL_P0_CTL2_PLL0_CAL_OVRD;
726 	WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2, reg);
727 
728 	reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
729 	reg &= ~UPHY_PLL_P0_CTL8_PLL0_RCAL_OVRD;
730 	WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL8, reg);
731 
732 	DELAY(50);
733 
734 	tegra210_xusb_pll_hw_sequence_start();
735 
736 	sc->pcie_ena_cnt++;
737 
738 	return (0);
739 
740 err:
741 	hwreset_deassert(pad->reset);
742 	clk_disable(pad->clk);
743 	return (rv);
744 }
745 
746 static void
747 uphy_pex_disable(struct padctl_softc *sc, struct padctl_pad *pad)
748 {
749 	int rv;
750 
751 	sc->pcie_ena_cnt--;
752 	if (sc->pcie_ena_cnt <= 0) {
753 		rv = hwreset_assert(pad->reset);
754 		if (rv != 0) {
755 			device_printf(sc->dev, "Cannot reset pad '%s': %d\n",
756 			    pad->name, rv);
757 		}
758 		rv = clk_disable(pad->clk);
759 		if (rv != 0) {
760 			device_printf(sc->dev,
761 			    "Cannot dicable clock for pad '%s': %d\n",
762 			    pad->name, rv);
763 		}
764 	}
765 }
766 
767 static int
768 uphy_sata_enable(struct padctl_softc *sc, struct padctl_pad *pad, bool usb)
769 {
770 	uint32_t reg;
771 	int rv, i;
772 
773 	/* 22.8.4 UPHY PLLs, Step 4, page 1346 */
774 	/* 1. Deassert PLL/Lane resets. */
775 	if (sc->sata_ena_cnt > 0) {
776 		sc->sata_ena_cnt++;
777 		return (0);
778 	}
779 
780 	rv = clk_enable(pad->clk);
781 	if (rv < 0) {
782 		device_printf(sc->dev, "Cannot enable clock for pad '%s': %d\n",
783 		    pad->name, rv);
784 		return (rv);
785 	}
786 
787 	rv = hwreset_deassert(pad->reset);
788 	if (rv < 0) {
789 		device_printf(sc->dev, "Cannot unreset pad '%s': %d\n",
790 		    pad->name, rv);
791 		clk_disable(pad->clk);
792 		return (rv);
793 	}
794 	reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
795 	reg &= ~UPHY_PLL_P0_CTL2_PLL0_CAL_CTRL(~0);
796 	reg |= UPHY_PLL_P0_CTL2_PLL0_CAL_CTRL(0x136);
797 	WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2, reg);
798 
799 	reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL5);
800 	reg &= ~UPHY_PLL_P0_CTL5_PLL0_DCO_CTRL(~0);
801 	reg |= UPHY_PLL_P0_CTL5_PLL0_DCO_CTRL(0x2a);
802 	WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL5, reg);
803 
804 	reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
805 	reg |= UPHY_PLL_S0_CTL1_PLL0_PWR_OVRD;
806 	WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL1, reg);
807 
808 	reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL2);
809 	reg |= UPHY_PLL_S0_CTL2_PLL0_CAL_OVRD;
810 	WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL2, reg);
811 
812 	reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL8);
813 	reg |= UPHY_PLL_S0_CTL8_PLL0_RCAL_OVRD;
814 	WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL8, reg);
815 
816 	/*
817 	 * 2. For the following registers, default values
818 	 *    take care of the desired frequency.
819 	 */
820 	 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL4);
821 	reg &= ~UPHY_PLL_S0_CTL4_PLL0_TXCLKREF_SEL(~0);
822 	reg &= ~UPHY_PLL_S0_CTL4_PLL0_REFCLK_SEL(~0);
823 	reg |= UPHY_PLL_S0_CTL4_PLL0_TXCLKREF_EN;
824 
825 	if (usb)
826 		reg |= UPHY_PLL_S0_CTL4_PLL0_TXCLKREF_SEL(0x2);
827 	else
828 		reg |= UPHY_PLL_S0_CTL4_PLL0_TXCLKREF_SEL(0x0);
829 
830 	/* XXX PLL0_XDIGCLK_EN */
831 	/*
832 	value &= ~(1 << 19);
833 	WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL4, reg);
834 	*/
835 
836 	reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
837 	reg &= ~UPHY_PLL_S0_CTL1_PLL0_FREQ_MDIV(~0);
838 	reg &= ~UPHY_PLL_S0_CTL1_PLL0_FREQ_NDIV(~0);
839 	if (usb)
840 		reg |= UPHY_PLL_S0_CTL1_PLL0_FREQ_NDIV(0x19);
841 	else
842 		reg |= UPHY_PLL_S0_CTL1_PLL0_FREQ_NDIV(0x1e);
843 	WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL1, reg);
844 
845 	reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
846 	reg &= ~UPHY_PLL_S0_CTL1_PLL0_IDDQ;
847 	WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL1, reg);
848 
849 	reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
850 	reg &= ~UPHY_PLL_S0_CTL1_PLL0_SLEEP(~0);
851 	WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL1, reg);
852 
853 	/* 3. Wait 100 ns. */
854 	DELAY(1);
855 
856 	/* XXX This in not in TRM */
857 	reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL4);
858 	reg |= UPHY_PLL_S0_CTL4_PLL0_REFCLKBUF_EN;
859 	WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL4, reg);
860 
861 	/* 4. Calibration. */
862 	reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL2);
863 	reg |= UPHY_PLL_S0_CTL2_PLL0_CAL_EN;
864 	WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL2, reg);
865 	for (i = 30; i > 0; i--) {
866 		reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL2);
867 		if (reg & UPHY_PLL_S0_CTL2_PLL0_CAL_DONE)
868 			break;
869 		DELAY(10);
870 	}
871 	if (i <= 0) {
872 		device_printf(sc->dev, "Timedout in calibration step 1 "
873 		    "for pad '%s'.\n", pad->name);
874 		rv = ETIMEDOUT;
875 		goto err;
876 	}
877 
878 	reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL2);
879 	reg &= ~UPHY_PLL_S0_CTL2_PLL0_CAL_EN;
880 	WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL2, reg);
881 	for (i = 10; i > 0; i--) {
882 		reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL2);
883 		if ((reg & UPHY_PLL_S0_CTL2_PLL0_CAL_DONE) == 0)
884 			break;
885 		DELAY(10);
886 	}
887 	if (i <= 0) {
888 		device_printf(sc->dev, "Timedout in calibration step 2 "
889 		    "for pad '%s'.\n", pad->name);
890 		rv = ETIMEDOUT;
891 		goto err;
892 	}
893 
894 	/* 5. Enable the PLL (20 �s Lock time) */
895 	reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
896 	reg |= UPHY_PLL_S0_CTL1_PLL0_ENABLE;
897 	WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL1, reg);
898 	for (i = 10; i > 0; i--) {
899 		reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
900 		if (reg & UPHY_PLL_S0_CTL1_PLL0_LOCKDET_STATUS)
901 			break;
902 		DELAY(10);
903 	}
904 	if (i <= 0) {
905 		device_printf(sc->dev, "Timedout while enabling PLL "
906 		    "for pad '%s'.\n", pad->name);
907 		rv = ETIMEDOUT;
908 		goto err;
909 	}
910 
911 	/* 6. RCAL. */
912 	reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL8);
913 	reg |= UPHY_PLL_S0_CTL8_PLL0_RCAL_EN;
914 	reg |= UPHY_PLL_S0_CTL8_PLL0_RCAL_CLK_EN;
915 	WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL8, reg);
916 	for (i = 10; i > 0; i--) {
917 		reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL8);
918 		if (reg & UPHY_PLL_S0_CTL8_PLL0_RCAL_DONE)
919 			break;
920 		DELAY(10);
921 	}
922 	if (i <= 0) {
923 		device_printf(sc->dev, "Timedout in RX calibration step 1 "
924 		    "for pad '%s'.\n", pad->name);
925 		rv = ETIMEDOUT;
926 		goto err;
927 	}
928 
929 	reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL8);
930 	reg &= ~UPHY_PLL_S0_CTL8_PLL0_RCAL_EN;
931 	WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL8, reg);
932 	for (i = 10; i > 0; i--) {
933 		reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL8);
934 		if (!(reg & UPHY_PLL_S0_CTL8_PLL0_RCAL_DONE))
935 			break;
936 		DELAY(10);
937 	}
938 	if (i <= 0) {
939 		device_printf(sc->dev, "Timedout in RX calibration step 2 "
940 		    "for pad '%s'.\n", pad->name);
941 		rv = ETIMEDOUT;
942 		goto err;
943 	}
944 
945 	reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL8);
946 	reg &= ~UPHY_PLL_S0_CTL8_PLL0_RCAL_CLK_EN;
947 	WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL8, reg);
948 
949 	/* Enable Hardware Power Sequencer. */
950 	tegra210_sata_pll_hw_control_enable();
951 
952 	reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
953 	reg &= ~UPHY_PLL_S0_CTL1_PLL0_PWR_OVRD;
954 	WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL1, reg);
955 
956 	reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL2);
957 	reg &= ~UPHY_PLL_S0_CTL2_PLL0_CAL_OVRD;
958 	WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL2, reg);
959 
960 	reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL8);
961 	reg &= ~UPHY_PLL_S0_CTL8_PLL0_RCAL_OVRD;
962 	WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL8, reg);
963 
964 	DELAY(50);
965 
966 	tegra210_sata_pll_hw_sequence_start();
967 
968 	sc->sata_ena_cnt++;
969 
970 	return (0);
971 
972 err:
973 	hwreset_deassert(pad->reset);
974 	clk_disable(pad->clk);
975 	return (rv);
976 }
977 
978 static void
979 uphy_sata_disable(struct padctl_softc *sc, struct padctl_pad *pad)
980 {
981 	int rv;
982 
983 	sc->sata_ena_cnt--;
984 	if (sc->sata_ena_cnt <= 0) {
985 		rv = hwreset_assert(pad->reset);
986 		if (rv != 0) {
987 			device_printf(sc->dev, "Cannot reset pad '%s': %d\n",
988 			    pad->name, rv);
989 		}
990 		rv = clk_disable(pad->clk);
991 		if (rv != 0) {
992 			device_printf(sc->dev,
993 			    "Cannot dicable clock for pad '%s': %d\n",
994 			    pad->name, rv);
995 		}
996 	}
997 }
998 
999 
1000 static int
1001 usb3_port_init(struct padctl_softc *sc, struct padctl_port *port)
1002 {
1003 	uint32_t reg;
1004 	struct padctl_pad *pad;
1005 	int rv;
1006 
1007 	pad = port->lane->pad;
1008 	reg = RD4(sc, XUSB_PADCTL_SS_PORT_MAP);
1009 	if (port->internal)
1010 		reg &= ~SS_PORT_MAP_PORT_INTERNAL(port->idx);
1011 	else
1012 		reg |= SS_PORT_MAP_PORT_INTERNAL(port->idx);
1013 	reg &= ~SS_PORT_MAP_PORT_MAP(port->idx, ~0);
1014 	reg |= SS_PORT_MAP_PORT_MAP(port->idx, port->companion);
1015 	WR4(sc, XUSB_PADCTL_SS_PORT_MAP, reg);
1016 
1017 	if (port->supply_vbus != NULL) {
1018 		rv = regulator_enable(port->supply_vbus);
1019 		if (rv != 0) {
1020 			device_printf(sc->dev,
1021 			    "Cannot enable vbus regulator\n");
1022 			return (rv);
1023 		}
1024 	}
1025 
1026 	reg = RD4(sc, XUSB_PADCTL_UPHY_USB3_PAD_ECTL1(port->idx));
1027 	reg &= ~UPHY_USB3_PAD_ECTL1_TX_TERM_CTRL(~0);
1028 	reg |= UPHY_USB3_PAD_ECTL1_TX_TERM_CTRL(2);
1029 	WR4(sc, XUSB_PADCTL_UPHY_USB3_PAD_ECTL1(port->idx), reg);
1030 
1031 	reg = RD4(sc, XUSB_PADCTL_UPHY_USB3_PAD_ECTL2(port->idx));
1032 	reg &= ~UPHY_USB3_PAD_ECTL2_RX_CTLE(~0);
1033 	reg |= UPHY_USB3_PAD_ECTL2_RX_CTLE(0x00fc);
1034 	WR4(sc, XUSB_PADCTL_UPHY_USB3_PAD_ECTL2(port->idx), reg);
1035 
1036 	WR4(sc, XUSB_PADCTL_UPHY_USB3_PAD_ECTL3(port->idx), 0xc0077f1f);
1037 
1038 	reg = RD4(sc,  XUSB_PADCTL_UPHY_USB3_PAD_ECTL4(port->idx));
1039 	reg &= ~UPHY_USB3_PAD_ECTL4_RX_CDR_CTRL(~0);
1040 	reg |= UPHY_USB3_PAD_ECTL4_RX_CDR_CTRL(0x01c7);
1041 	WR4(sc, XUSB_PADCTL_UPHY_USB3_PAD_ECTL4(port->idx), reg);
1042 
1043 	WR4(sc, XUSB_PADCTL_UPHY_USB3_PAD_ECTL6(port->idx), 0xfcf01368);
1044 
1045 	if (pad->type == PADCTL_PAD_SATA)
1046 		rv = uphy_sata_enable(sc, pad, true);
1047 	else
1048 		rv = uphy_pex_enable(sc, pad);
1049 	if (rv != 0)
1050 		return (rv);
1051 
1052 	reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM1);
1053 	reg &= ~ELPG_PROGRAM1_SSP_ELPG_VCORE_DOWN(port->idx);
1054 	WR4(sc, XUSB_PADCTL_ELPG_PROGRAM1, reg);
1055 	DELAY(100);
1056 
1057 	reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM1);
1058 	reg &= ~ELPG_PROGRAM1_SSP_ELPG_CLAMP_EN_EARLY(port->idx);
1059 	WR4(sc, XUSB_PADCTL_ELPG_PROGRAM1, reg);
1060 	DELAY(100);
1061 
1062 	reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM1);
1063 	reg &= ~ELPG_PROGRAM1_SSP_ELPG_CLAMP_EN(port->idx);
1064 	WR4(sc, XUSB_PADCTL_ELPG_PROGRAM1, reg);
1065 	DELAY(100);
1066 
1067 	return (0);
1068 }
1069 
1070 static int
1071 pcie_enable(struct padctl_softc *sc, struct padctl_lane *lane)
1072 {
1073 	uint32_t reg;
1074 	int rv;
1075 
1076 	rv = uphy_pex_enable(sc, lane->pad);
1077 	if (rv != 0)
1078 		return (rv);
1079 
1080 	reg = RD4(sc, XUSB_PADCTL_USB3_PAD_MUX);
1081 	reg |= USB3_PAD_MUX_PCIE_IDDQ_DISABLE(lane->idx);
1082 	WR4(sc, XUSB_PADCTL_USB3_PAD_MUX, reg);
1083 
1084 	return (0);
1085 }
1086 
1087 static int
1088 pcie_disable(struct padctl_softc *sc, struct padctl_lane *lane)
1089 {
1090 	uint32_t reg;
1091 
1092 	reg = RD4(sc, XUSB_PADCTL_USB3_PAD_MUX);
1093 	reg &= ~USB3_PAD_MUX_PCIE_IDDQ_DISABLE(lane->idx);
1094 	WR4(sc, XUSB_PADCTL_USB3_PAD_MUX, reg);
1095 
1096 	uphy_pex_disable(sc, lane->pad);
1097 
1098 	return (0);
1099 
1100 }
1101 
1102 static int
1103 sata_enable(struct padctl_softc *sc, struct padctl_lane *lane)
1104 {
1105 	uint32_t reg;
1106 	int rv;
1107 
1108 	rv = uphy_sata_enable(sc, lane->pad, false);
1109 	if (rv != 0)
1110 		return (rv);
1111 
1112 	reg = RD4(sc, XUSB_PADCTL_USB3_PAD_MUX);
1113 	reg |= USB3_PAD_MUX_SATA_IDDQ_DISABLE(lane->idx);
1114 	WR4(sc, XUSB_PADCTL_USB3_PAD_MUX, reg);
1115 
1116 	return (0);
1117 }
1118 
1119 static int
1120 sata_disable(struct padctl_softc *sc, struct padctl_lane *lane)
1121 {
1122 	uint32_t reg;
1123 
1124 	reg = RD4(sc, XUSB_PADCTL_USB3_PAD_MUX);
1125 	reg &= ~USB3_PAD_MUX_SATA_IDDQ_DISABLE(lane->idx);
1126 	WR4(sc, XUSB_PADCTL_USB3_PAD_MUX, reg);
1127 
1128 	uphy_sata_disable(sc, lane->pad);
1129 
1130 	return (0);
1131 }
1132 
1133 static int
1134 hsic_enable(struct padctl_softc *sc, struct padctl_lane *lane)
1135 {
1136 	uint32_t reg;
1137 	struct padctl_pad *pad;
1138 	struct padctl_port *port;
1139 	int rv;
1140 
1141 	port = search_lane_port(sc, lane);
1142 	if (port == NULL) {
1143 		device_printf(sc->dev, "Cannot find port for lane: %s\n",
1144 		    lane->name);
1145 	}
1146 	pad = lane->pad;
1147 
1148 	if (port->supply_vbus != NULL) {
1149 		rv = regulator_enable(port->supply_vbus);
1150 		if (rv != 0) {
1151 			device_printf(sc->dev,
1152 			    "Cannot enable vbus regulator\n");
1153 			return (rv);
1154 		}
1155 	}
1156 
1157 	WR4(sc, XUSB_PADCTL_HSIC_STRB_TRIM_CONTROL, sc->strobe_trim);
1158 
1159 	reg = RD4(sc, XUSB_PADCTL_HSIC_PAD_CTL1(lane->idx));
1160 	reg &= ~HSIC_PAD_CTL1_TX_RTUNEP(~0);
1161 	reg |= HSIC_PAD_CTL1_TX_RTUNEP(sc->tx_rtune_p);
1162 	WR4(sc, XUSB_PADCTL_HSIC_PAD_CTL1(lane->idx), reg);
1163 
1164 	reg = RD4(sc, XUSB_PADCTL_HSIC_PAD_CTL2(lane->idx));
1165 	reg &= ~HSIC_PAD_CTL2_RX_STROBE_TRIM(~0);
1166 	reg &= ~HSIC_PAD_CTL2_RX_DATA1_TRIM(~0);
1167 	reg &= ~HSIC_PAD_CTL2_RX_DATA0_TRIM(~0);
1168 	reg |= HSIC_PAD_CTL2_RX_STROBE_TRIM(sc->rx_strobe_trim);
1169 	reg |= HSIC_PAD_CTL2_RX_DATA1_TRIM(sc->rx_data1_trim);
1170 	reg |= HSIC_PAD_CTL2_RX_DATA0_TRIM(sc->rx_data0_trim);
1171 	WR4(sc, XUSB_PADCTL_HSIC_PAD_CTL2(lane->idx), reg);
1172 
1173 	reg = RD4(sc, XUSB_PADCTL_HSIC_PAD_CTL0(lane->idx));
1174 	reg &= ~HSIC_PAD_CTL0_RPU_DATA0;
1175 	reg &= ~HSIC_PAD_CTL0_RPU_DATA1;
1176 	reg &= ~HSIC_PAD_CTL0_RPU_STROBE;
1177 	reg &= ~HSIC_PAD_CTL0_PD_RX_DATA0;
1178 	reg &= ~HSIC_PAD_CTL0_PD_RX_DATA1;
1179 	reg &= ~HSIC_PAD_CTL0_PD_RX_STROBE;
1180 	reg &= ~HSIC_PAD_CTL0_PD_ZI_DATA0;
1181 	reg &= ~HSIC_PAD_CTL0_PD_ZI_DATA1;
1182 	reg &= ~HSIC_PAD_CTL0_PD_ZI_STROBE;
1183 	reg &= ~HSIC_PAD_CTL0_PD_TX_DATA0;
1184 	reg &= ~HSIC_PAD_CTL0_PD_TX_DATA1;
1185 	reg &= ~HSIC_PAD_CTL0_PD_TX_STROBE;
1186 	reg |= HSIC_PAD_CTL0_RPD_DATA0;
1187 	reg |= HSIC_PAD_CTL0_RPD_DATA1;
1188 	reg |= HSIC_PAD_CTL0_RPD_STROBE;
1189 	WR4(sc, XUSB_PADCTL_HSIC_PAD_CTL0(lane->idx), reg);
1190 
1191 	rv = clk_enable(pad->clk);
1192 	if (rv < 0) {
1193 		device_printf(sc->dev, "Cannot enable clock for pad '%s': %d\n",
1194 		    pad->name, rv);
1195 		if (port->supply_vbus != NULL)
1196 			regulator_disable(port->supply_vbus);
1197 		return (rv);
1198 	}
1199 
1200 	reg = RD4(sc, XUSB_PADCTL_HSIC_PAD_TRK_CTL);
1201 	reg &= ~HSIC_PAD_TRK_CTL_TRK_START_TIMER(~0);
1202 	reg &= ~HSIC_PAD_TRK_CTL_TRK_DONE_RESET_TIMER(~0);
1203 	reg |= HSIC_PAD_TRK_CTL_TRK_START_TIMER(0x1e);
1204 	reg |= HSIC_PAD_TRK_CTL_TRK_DONE_RESET_TIMER(0x0a);
1205 	WR4(sc, XUSB_PADCTL_HSIC_PAD_TRK_CTL, reg);
1206 
1207 	DELAY(10);
1208 
1209 	reg = RD4(sc, XUSB_PADCTL_HSIC_PAD_TRK_CTL);
1210 	reg &= ~HSIC_PAD_TRK_CTL_PD_TRK;
1211 	WR4(sc, XUSB_PADCTL_HSIC_PAD_TRK_CTL, reg);
1212 
1213 	DELAY(50);
1214 	clk_disable(pad->clk);
1215 	return (0);
1216 }
1217 
1218 static int
1219 hsic_disable(struct padctl_softc *sc, struct padctl_lane *lane)
1220 {
1221 	uint32_t reg;
1222 	struct padctl_port *port;
1223 	int rv;
1224 
1225 	port = search_lane_port(sc, lane);
1226 	if (port == NULL) {
1227 		device_printf(sc->dev, "Cannot find port for lane: %s\n",
1228 		    lane->name);
1229 	}
1230 
1231 	reg = RD4(sc, XUSB_PADCTL_HSIC_PAD_CTL0(lane->idx));
1232 	reg |= HSIC_PAD_CTL0_PD_RX_DATA0;
1233 	reg |= HSIC_PAD_CTL0_PD_RX_DATA1;
1234 	reg |= HSIC_PAD_CTL0_PD_RX_STROBE;
1235 	reg |= HSIC_PAD_CTL0_PD_ZI_DATA0;
1236 	reg |= HSIC_PAD_CTL0_PD_ZI_DATA1;
1237 	reg |= HSIC_PAD_CTL0_PD_ZI_STROBE;
1238 	reg |= HSIC_PAD_CTL0_PD_TX_DATA0;
1239 	reg |= HSIC_PAD_CTL0_PD_TX_DATA1;
1240 	reg |= HSIC_PAD_CTL0_PD_TX_STROBE;
1241 	WR4(sc, XUSB_PADCTL_HSIC_PAD_CTL1(lane->idx), reg);
1242 
1243 	if (port->supply_vbus != NULL) {
1244 		rv = regulator_disable(port->supply_vbus);
1245 		if (rv != 0) {
1246 			device_printf(sc->dev,
1247 			    "Cannot disable vbus regulator\n");
1248 			return (rv);
1249 		}
1250 	}
1251 
1252 	return (0);
1253 }
1254 
1255 static int
1256 usb2_enable(struct padctl_softc *sc, struct padctl_lane *lane)
1257 {
1258 	uint32_t reg;
1259 	struct padctl_pad *pad;
1260 	struct padctl_port *port;
1261 	int rv;
1262 
1263 	port = search_lane_port(sc, lane);
1264 	if (port == NULL) {
1265 		device_printf(sc->dev, "Cannot find port for lane: %s\n",
1266 		    lane->name);
1267 	}
1268 	pad = lane->pad;
1269 
1270 	reg = RD4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
1271 	reg &= ~USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL(~0);
1272 	reg &= ~USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL(~0);
1273 	reg |= USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL(0x7);
1274 	WR4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL0, reg);
1275 
1276 	reg = RD4(sc, XUSB_PADCTL_USB2_PORT_CAP);
1277 	reg &= ~USB2_PORT_CAP_PORT_CAP(lane->idx, ~0);
1278 	reg |= USB2_PORT_CAP_PORT_CAP(lane->idx, USB2_PORT_CAP_PORT_CAP_HOST);
1279 	WR4(sc, XUSB_PADCTL_USB2_PORT_CAP, reg);
1280 
1281 	reg = RD4(sc, XUSB_PADCTL_USB2_OTG_PAD_CTL0(lane->idx));
1282 	reg &= ~USB2_OTG_PAD_CTL0_HS_CURR_LEVEL(~0);
1283 	reg &= ~USB2_OTG_PAD_CTL0_HS_SLEW(~0);
1284 	reg &= ~USB2_OTG_PAD_CTL0_PD;
1285 	reg &= ~USB2_OTG_PAD_CTL0_PD2;
1286 	reg &= ~USB2_OTG_PAD_CTL0_PD_ZI;
1287 	reg |= USB2_OTG_PAD_CTL0_HS_SLEW(14);
1288 	reg |= USB2_OTG_PAD_CTL0_HS_CURR_LEVEL(sc->hs_curr_level[lane->idx] +
1289 	    sc->hs_curr_level_offs);
1290 	WR4(sc, XUSB_PADCTL_USB2_OTG_PAD_CTL0(lane->idx), reg);
1291 
1292 	reg = RD4(sc, XUSB_PADCTL_USB2_OTG_PAD_CTL1(lane->idx));
1293 	reg &= ~USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ(~0);
1294 	reg &= ~USB2_OTG_PAD_CTL1_RPD_CTRL(~0);
1295 	reg &= ~USB2_OTG_PAD_CTL1_PD_DR;
1296 	reg &= ~USB2_OTG_PAD_CTL1_PD_CHRP_OVRD;
1297 	reg &= ~USB2_OTG_PAD_CTL1_PD_DISC_OVRD;
1298 	reg |= USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ(sc->hs_term_range_adj);
1299 	reg |= USB2_OTG_PAD_CTL1_RPD_CTRL(sc->rpd_ctrl);
1300 	WR4(sc, XUSB_PADCTL_USB2_OTG_PAD_CTL1(lane->idx), reg);
1301 
1302 	reg = RD4(sc, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1(lane->idx));
1303 	reg &= ~USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_LEV(~0);
1304 	reg |= USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_FIX18;
1305 	WR4(sc, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1(lane->idx), reg);
1306 
1307 	if (port->supply_vbus != NULL) {
1308 		rv = regulator_enable(port->supply_vbus);
1309 		if (rv != 0) {
1310 			device_printf(sc->dev,
1311 			    "Cannot enable vbus regulator\n");
1312 			return (rv);
1313 		}
1314 	}
1315 	rv = clk_enable(pad->clk);
1316 	if (rv < 0) {
1317 		device_printf(sc->dev, "Cannot enable clock for pad '%s': %d\n",
1318 		    pad->name, rv);
1319 		if (port->supply_vbus != NULL)
1320 			regulator_disable(port->supply_vbus);
1321 		return (rv);
1322 	}
1323 	reg = RD4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
1324 	reg &= ~USB2_BIAS_PAD_CTL1_TRK_START_TIMER(~0);
1325 	reg &= ~USB2_BIAS_PAD_CTL1_TRK_DONE_RESET_TIMER(~0);
1326 	reg |= USB2_BIAS_PAD_CTL1_TRK_START_TIMER(0x1e);
1327 	reg |= USB2_BIAS_PAD_CTL1_TRK_DONE_RESET_TIMER(0x0a);
1328 	WR4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL1, reg);
1329 
1330 	reg = RD4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
1331 	reg &= ~USB2_BIAS_PAD_CTL0_PD;
1332 	WR4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL0, reg);
1333 	return (0);
1334 }
1335 
1336 static int
1337 usb2_disable(struct padctl_softc *sc, struct padctl_lane *lane)
1338 {
1339 	uint32_t reg;
1340 	struct padctl_pad *pad;
1341 	struct padctl_port *port;
1342 	int rv;
1343 
1344 	port = search_lane_port(sc, lane);
1345 	if (port == NULL) {
1346 		device_printf(sc->dev, "Cannot find port for lane: %s\n",
1347 		    lane->name);
1348 	}
1349 	pad = lane->pad;
1350 
1351 	reg = RD4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
1352 	reg |= USB2_BIAS_PAD_CTL0_PD;
1353 	WR4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL0, reg);
1354 
1355 	if (port->supply_vbus != NULL) {
1356 		rv = regulator_disable(port->supply_vbus);
1357 		if (rv != 0) {
1358 			device_printf(sc->dev,
1359 			    "Cannot disable vbus regulator\n");
1360 			return (rv);
1361 		}
1362 	}
1363 
1364 	rv = clk_disable(pad->clk);
1365 	if (rv < 0) {
1366 		device_printf(sc->dev, "Cannot disable clock for pad '%s': %d\n",
1367 		    pad->name, rv);
1368 		return (rv);
1369 	}
1370 
1371 	return (0);
1372 }
1373 
1374 
1375 static int
1376 pad_common_enable(struct padctl_softc *sc)
1377 {
1378 	uint32_t reg;
1379 
1380 	reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM1);
1381 	reg &= ~ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN;
1382 	WR4(sc, XUSB_PADCTL_ELPG_PROGRAM1, reg);
1383 	DELAY(100);
1384 
1385 	reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM1);
1386 	reg &= ~ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN_EARLY;
1387 	WR4(sc, XUSB_PADCTL_ELPG_PROGRAM1, reg);
1388 	DELAY(100);
1389 
1390 	reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM1);
1391 	reg &= ~ELPG_PROGRAM1_AUX_MUX_LP0_VCORE_DOWN;
1392 	WR4(sc, XUSB_PADCTL_ELPG_PROGRAM1, reg);
1393 	DELAY(100);
1394 
1395 	return (0);
1396 }
1397 
1398 static int
1399 pad_common_disable(struct padctl_softc *sc)
1400 {
1401 	uint32_t reg;
1402 
1403 	reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM1);
1404 	reg |= ELPG_PROGRAM1_AUX_MUX_LP0_VCORE_DOWN;
1405 	WR4(sc, XUSB_PADCTL_ELPG_PROGRAM1, reg);
1406 	DELAY(100);
1407 
1408 	reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM1);
1409 	reg |= ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN_EARLY;
1410 	WR4(sc, XUSB_PADCTL_ELPG_PROGRAM1, reg);
1411 	DELAY(100);
1412 
1413 	reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM1);
1414 	reg |= ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN;
1415 	WR4(sc, XUSB_PADCTL_ELPG_PROGRAM1, reg);
1416 	DELAY(100);
1417 
1418 	return (0);
1419 }
1420 
1421 static int
1422 xusbpadctl_phy_enable(struct phynode *phy, bool enable)
1423 {
1424 	device_t dev;
1425 	intptr_t id;
1426 	struct padctl_softc *sc;
1427 	struct padctl_lane *lane;
1428 	struct padctl_pad *pad;
1429 	int rv;
1430 
1431 	dev = phynode_get_device(phy);
1432 	id = phynode_get_id(phy);
1433 	sc = device_get_softc(dev);
1434 
1435 	if (id < 0 || id >= nitems(lanes_tbl)) {
1436 		device_printf(dev, "Unknown phy: %d\n", (int)id);
1437 		return (ENXIO);
1438 	}
1439 
1440 	lane = lanes_tbl + id;
1441 	if (!lane->enabled) {
1442 		device_printf(dev, "Lane is not enabled/configured: %s\n",
1443 		    lane->name);
1444 		return (ENXIO);
1445 	}
1446 
1447 	pad = lane->pad;
1448 	if (enable) {
1449 		if (sc->phy_ena_cnt == 0) {
1450 			rv = pad_common_enable(sc);
1451 			if (rv != 0)
1452 				return (rv);
1453 		}
1454 		sc->phy_ena_cnt++;
1455 	}
1456 
1457 	if (enable)
1458 		rv = pad->enable(sc, lane);
1459 	else
1460 		rv = pad->disable(sc, lane);
1461 	if (rv != 0)
1462 		return (rv);
1463 
1464 	if (!enable) {
1465 		 if (sc->phy_ena_cnt == 1) {
1466 			rv = pad_common_disable(sc);
1467 			if (rv != 0)
1468 				return (rv);
1469 		}
1470 		sc->phy_ena_cnt--;
1471 	}
1472 
1473 	return (0);
1474 }
1475 
1476 /* -------------------------------------------------------------------------
1477  *
1478  *   FDT processing
1479  */
1480 static struct padctl_port *
1481 search_port(struct padctl_softc *sc, char *port_name)
1482 {
1483 	int i;
1484 
1485 	for (i = 0; i < nitems(ports_tbl); i++) {
1486 		if (strcmp(port_name, ports_tbl[i].name) == 0)
1487 			return (&ports_tbl[i]);
1488 	}
1489 	return (NULL);
1490 }
1491 
1492 static struct padctl_port *
1493 search_lane_port(struct padctl_softc *sc, struct padctl_lane *lane)
1494 {
1495 	int i;
1496 
1497 	for (i = 0; i < nitems(ports_tbl); i++) {
1498 		if (!ports_tbl[i].enabled)
1499 			continue;
1500 		if (ports_tbl[i].lane == lane)
1501 			return (ports_tbl + i);
1502 	}
1503 	return (NULL);
1504 }
1505 
1506 static struct padctl_lane *
1507 search_lane(struct padctl_softc *sc, char *lane_name)
1508 {
1509 	int i;
1510 
1511 	for (i = 0; i < nitems(lanes_tbl); i++) {
1512 		if (strcmp(lane_name, lanes_tbl[i].name) == 0)
1513 			return 	(lanes_tbl + i);
1514 	}
1515 	return (NULL);
1516 }
1517 
1518 static struct padctl_lane *
1519 search_pad_lane(struct padctl_softc *sc, enum padctl_pad_type type, int idx)
1520 {
1521 	int i;
1522 
1523 	for (i = 0; i < nitems(lanes_tbl); i++) {
1524 		if (!lanes_tbl[i].enabled)
1525 			continue;
1526 		if (type == lanes_tbl[i].pad->type && idx == lanes_tbl[i].idx)
1527 			return 	(lanes_tbl + i);
1528 	}
1529 	return (NULL);
1530 }
1531 
1532 static struct padctl_lane *
1533 search_usb3_pad_lane(struct padctl_softc *sc, int idx)
1534 {
1535 	int i;
1536 	struct padctl_lane *lane, *tmp;
1537 
1538 	lane = NULL;
1539 	for (i = 0; i < nitems(lane_map_tbl); i++) {
1540 		if (idx != lane_map_tbl[i].port_idx)
1541 			continue;
1542 		tmp = search_pad_lane(sc, lane_map_tbl[i].pad_type,
1543 		    lane_map_tbl[i].lane_idx);
1544 		if (tmp == NULL)
1545 			continue;
1546 		if (strcmp(tmp->mux[tmp->mux_idx], "usb3-ss") != 0)
1547 			continue;
1548 		if (lane != NULL) {
1549 			device_printf(sc->dev, "Duplicated mappings found for"
1550 			 " lanes: %s and %s\n", lane->name, tmp->name);
1551 			return (NULL);
1552 		}
1553 		lane = tmp;
1554 	}
1555 	return (lane);
1556 }
1557 
1558 static struct padctl_pad *
1559 search_pad(struct padctl_softc *sc, char *pad_name)
1560 {
1561 	int i;
1562 
1563 	for (i = 0; i < nitems(pads_tbl); i++) {
1564 		if (strcmp(pad_name, pads_tbl[i].name) == 0)
1565 			return 	(pads_tbl + i);
1566 	}
1567 	return (NULL);
1568 }
1569 
1570 static int
1571 search_mux(struct padctl_softc *sc, struct padctl_lane *lane, char *fnc_name)
1572 {
1573 	int i;
1574 
1575 	for (i = 0; i < lane->nmux; i++) {
1576 		if (strcmp(fnc_name, lane->mux[i]) == 0)
1577 			return 	(i);
1578 	}
1579 	return (-1);
1580 }
1581 
1582 static int
1583 config_lane(struct padctl_softc *sc, struct padctl_lane *lane)
1584 {
1585 	uint32_t reg;
1586 
1587 	reg = RD4(sc, lane->reg);
1588 	reg &= ~(lane->mask << lane->shift);
1589 	reg |=  (lane->mux_idx & lane->mask) << lane->shift;
1590 	WR4(sc, lane->reg, reg);
1591 	return (0);
1592 }
1593 
1594 static int
1595 process_lane(struct padctl_softc *sc, phandle_t node, struct padctl_pad *pad)
1596 {
1597 	struct padctl_lane *lane;
1598 	struct phynode *phynode;
1599 	struct phynode_init_def phy_init;
1600 	char *name;
1601 	char *function;
1602 	int rv;
1603 
1604 	name = NULL;
1605 	function = NULL;
1606 	rv = OF_getprop_alloc(node, "name", (void **)&name);
1607 	if (rv <= 0) {
1608 		device_printf(sc->dev, "Cannot read lane name.\n");
1609 		return (ENXIO);
1610 	}
1611 
1612 	lane = search_lane(sc, name);
1613 	if (lane == NULL) {
1614 		device_printf(sc->dev, "Unknown lane: %s\n", name);
1615 		rv = ENXIO;
1616 		goto end;
1617 	}
1618 
1619 	/* Read function (mux) settings. */
1620 	rv = OF_getprop_alloc(node, "nvidia,function", (void **)&function);
1621 	if (rv <= 0) {
1622 		device_printf(sc->dev, "Cannot read lane function.\n");
1623 		rv = ENXIO;
1624 		goto end;
1625 	}
1626 
1627 	lane->mux_idx = search_mux(sc, lane, function);
1628 	if (lane->mux_idx == ~0) {
1629 		device_printf(sc->dev, "Unknown function %s for lane %s\n",
1630 		    function, name);
1631 		rv = ENXIO;
1632 		goto end;
1633 	}
1634 
1635 	rv = config_lane(sc, lane);
1636 	if (rv != 0) {
1637 		device_printf(sc->dev, "Cannot configure lane: %s: %d\n",
1638 		    name, rv);
1639 		rv = ENXIO;
1640 		goto end;
1641 	}
1642 	lane->xref = OF_xref_from_node(node);
1643 	lane->pad = pad;
1644 	lane->enabled = true;
1645 	pad->lanes[pad->nlanes++] = lane;
1646 
1647 	/* Create and register phy. */
1648 	bzero(&phy_init, sizeof(phy_init));
1649 	phy_init.id = lane - lanes_tbl;
1650 	phy_init.ofw_node = node;
1651 	phynode = phynode_create(sc->dev, &xusbpadctl_phynode_class, &phy_init);
1652 	if (phynode == NULL) {
1653 		device_printf(sc->dev, "Cannot create phy\n");
1654 		rv = ENXIO;
1655 		goto end;
1656 	}
1657 	if (phynode_register(phynode) == NULL) {
1658 		device_printf(sc->dev, "Cannot create phy\n");
1659 		return (ENXIO);
1660 	}
1661 
1662 	rv = 0;
1663 
1664 end:
1665 	if (name != NULL)
1666 		OF_prop_free(name);
1667 	if (function != NULL)
1668 		OF_prop_free(function);
1669 	return (rv);
1670 }
1671 
1672 static int
1673 process_pad(struct padctl_softc *sc, phandle_t node)
1674 {
1675 	phandle_t  xref;
1676 	struct padctl_pad *pad;
1677 	char *name;
1678 	int rv;
1679 
1680 	name = NULL;
1681 	rv = OF_getprop_alloc(node, "name", (void **)&name);
1682 	if (rv <= 0) {
1683 		device_printf(sc->dev, "Cannot read pad name.\n");
1684 		return (ENXIO);
1685 	}
1686 
1687 	pad = search_pad(sc, name);
1688 	if (pad == NULL) {
1689 		device_printf(sc->dev, "Unknown pad: %s\n", name);
1690 		rv = ENXIO;
1691 		goto end;
1692 	}
1693 
1694 	if (pad->clock_name != NULL) {
1695 		rv = clk_get_by_ofw_name(sc->dev, node, pad->clock_name,
1696 		    &pad->clk);
1697 		if (rv != 0) {
1698 			device_printf(sc->dev, "Cannot get '%s' clock\n",
1699 			    pad->clock_name);
1700 			return (ENXIO);
1701 		}
1702 	}
1703 
1704 	if (pad->reset_name != NULL) {
1705 		rv = hwreset_get_by_ofw_name(sc->dev, node, pad->reset_name,
1706 		    &pad->reset);
1707 		if (rv != 0) {
1708 			device_printf(sc->dev, "Cannot get '%s' reset\n",
1709 			    pad->reset_name);
1710 			return (ENXIO);
1711 		}
1712 	}
1713 
1714 	/* Read and process associated lanes. */
1715 	node = ofw_bus_find_child(node, "lanes");
1716 	if (node <= 0) {
1717 		device_printf(sc->dev, "Cannot find 'lanes' subnode\n");
1718 		rv = ENXIO;
1719 		goto end;
1720 	}
1721 
1722 	for (node = OF_child(node); node != 0; node = OF_peer(node)) {
1723 		if (!ofw_bus_node_status_okay(node))
1724 			continue;
1725 
1726 		rv = process_lane(sc, node, pad);
1727 		if (rv != 0)
1728 			goto end;
1729 
1730 		xref = OF_xref_from_node(node);
1731 		OF_device_register_xref(xref, sc->dev);
1732 	}
1733 	pad->enabled = true;
1734 	rv = 0;
1735 end:
1736 	if (name != NULL)
1737 		OF_prop_free(name);
1738 	return (rv);
1739 }
1740 
1741 static int
1742 process_port(struct padctl_softc *sc, phandle_t node)
1743 {
1744 
1745 	struct padctl_port *port;
1746 	char *name;
1747 	int rv;
1748 
1749 	name = NULL;
1750 	rv = OF_getprop_alloc(node, "name", (void **)&name);
1751 	if (rv <= 0) {
1752 		device_printf(sc->dev, "Cannot read port name.\n");
1753 		return (ENXIO);
1754 	}
1755 
1756 	port = search_port(sc, name);
1757 	if (port == NULL) {
1758 		device_printf(sc->dev, "Unknown port: %s\n", name);
1759 		rv = ENXIO;
1760 		goto end;
1761 	}
1762 
1763 	regulator_get_by_ofw_property(sc->dev, node,
1764 	    "vbus-supply", &port->supply_vbus);
1765 
1766 	if (OF_hasprop(node, "nvidia,internal"))
1767 		port->internal = true;
1768 
1769 	/* Find assigned lane */
1770 	if (port->lane == NULL) {
1771 		switch(port->type) {
1772 		/* Routing is fixed for USB2 AND HSIC. */
1773 		case PADCTL_PORT_USB2:
1774 			port->lane = search_pad_lane(sc, PADCTL_PAD_USB2,
1775 			    port->idx);
1776 			break;
1777 		case PADCTL_PORT_HSIC:
1778 			port->lane = search_pad_lane(sc, PADCTL_PAD_HSIC,
1779 			    port->idx);
1780 			break;
1781 		case PADCTL_PORT_USB3:
1782 			port->lane = search_usb3_pad_lane(sc, port->idx);
1783 			break;
1784 		}
1785 	}
1786 	if (port->lane == NULL) {
1787 		device_printf(sc->dev, "Cannot find lane for port: %s\n", name);
1788 		rv = ENXIO;
1789 		goto end;
1790 	}
1791 
1792 	if (port->type == PADCTL_PORT_USB3) {
1793 		rv = OF_getencprop(node,  "nvidia,usb2-companion",
1794 		   &(port->companion), sizeof(port->companion));
1795 		if (rv <= 0) {
1796 			device_printf(sc->dev,
1797 			    "Missing 'nvidia,usb2-companion' property "
1798 			    "for port: %s\n", name);
1799 			rv = ENXIO;
1800 			goto end;
1801 		}
1802 	}
1803 
1804 	port->enabled = true;
1805 	rv = 0;
1806 end:
1807 	if (name != NULL)
1808 		OF_prop_free(name);
1809 	return (rv);
1810 }
1811 
1812 static int
1813 parse_fdt(struct padctl_softc *sc, phandle_t base_node)
1814 {
1815 	phandle_t node;
1816 	int rv;
1817 
1818 	rv = 0;
1819 	node = ofw_bus_find_child(base_node, "pads");
1820 
1821 	if (node <= 0) {
1822 		device_printf(sc->dev, "Cannot find pads subnode.\n");
1823 		return (ENXIO);
1824 	}
1825 	for (node = OF_child(node); node != 0; node = OF_peer(node)) {
1826 		if (!ofw_bus_node_status_okay(node))
1827 			continue;
1828 		rv = process_pad(sc, node);
1829 		if (rv != 0)
1830 			return (rv);
1831 	}
1832 
1833 	node = ofw_bus_find_child(base_node, "ports");
1834 	if (node <= 0) {
1835 		device_printf(sc->dev, "Cannot find ports subnode.\n");
1836 		return (ENXIO);
1837 	}
1838 	for (node = OF_child(node); node != 0; node = OF_peer(node)) {
1839 		if (!ofw_bus_node_status_okay(node))
1840 			continue;
1841 		rv = process_port(sc, node);
1842 		if (rv != 0)
1843 			return (rv);
1844 	}
1845 
1846 	return (0);
1847 }
1848 
1849 static void
1850 load_calibration(struct padctl_softc *sc)
1851 {
1852 	uint32_t reg;
1853 	int i;
1854 
1855 	reg = tegra_fuse_read_4(FUSE_SKU_CALIB_0);
1856 	sc->hs_curr_level[0] = FUSE_SKU_CALIB_0_HS_CURR_LEVEL_0(reg);
1857 	for (i = 1; i < nitems(sc->hs_curr_level); i++) {
1858 		sc->hs_curr_level[i] =
1859 		    FUSE_SKU_CALIB_0_HS_CURR_LEVEL_123(reg, i);
1860 	}
1861 	sc->hs_term_range_adj = FUSE_SKU_CALIB_0_HS_TERM_RANGE_ADJ(reg);
1862 
1863 	tegra_fuse_read_4(FUSE_USB_CALIB_EXT_0);
1864 	sc->rpd_ctrl = FUSE_USB_CALIB_EXT_0_RPD_CTRL(reg);
1865 }
1866 
1867 /* -------------------------------------------------------------------------
1868  *
1869  *   BUS functions
1870  */
1871 static int
1872 xusbpadctl_probe(device_t dev)
1873 {
1874 
1875 	if (!ofw_bus_status_okay(dev))
1876 		return (ENXIO);
1877 
1878 	if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data)
1879 		return (ENXIO);
1880 
1881 	device_set_desc(dev, "Tegra XUSB phy");
1882 	return (BUS_PROBE_DEFAULT);
1883 }
1884 
1885 static int
1886 xusbpadctl_detach(device_t dev)
1887 {
1888 
1889 	/* This device is always present. */
1890 	return (EBUSY);
1891 }
1892 
1893 static int
1894 xusbpadctl_attach(device_t dev)
1895 {
1896 	struct padctl_softc * sc;
1897 	int i, rid, rv;
1898 	struct padctl_port *port;
1899 	phandle_t node;
1900 
1901 	sc = device_get_softc(dev);
1902 	sc->dev = dev;
1903 	node = ofw_bus_get_node(dev);
1904 	rid = 0;
1905 	sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1906 	    RF_ACTIVE);
1907 	if (sc->mem_res == NULL) {
1908 		device_printf(dev, "Cannot allocate memory resources\n");
1909 		return (ENXIO);
1910 	}
1911 
1912 	rv = hwreset_get_by_ofw_name(dev, 0, "padctl", &sc->rst);
1913 	if (rv != 0) {
1914 		device_printf(dev, "Cannot get 'padctl' reset: %d\n", rv);
1915 		return (rv);
1916 	}
1917 	rv = hwreset_deassert(sc->rst);
1918 	if (rv != 0) {
1919 		device_printf(dev, "Cannot unreset 'padctl' reset: %d\n", rv);
1920 		return (rv);
1921 	}
1922 
1923 	load_calibration(sc);
1924 
1925 	rv = parse_fdt(sc, node);
1926 	if (rv != 0) {
1927 		device_printf(dev, "Cannot parse fdt configuration: %d\n", rv);
1928 		return (rv);
1929 	}
1930 	for (i = 0; i < nitems(ports_tbl); i++) {
1931 		port = ports_tbl + i;
1932 		if (!port->enabled)
1933 			continue;
1934 		if (port->init == NULL)
1935 			continue;
1936 		rv = port->init(sc, port);
1937 		if (rv != 0) {
1938 			device_printf(dev, "Cannot init port '%s'\n",
1939 			    port->name);
1940 			return (rv);
1941 		}
1942 	}
1943 	return (0);
1944 }
1945 
1946 static device_method_t tegra_xusbpadctl_methods[] = {
1947 	/* Device interface */
1948 	DEVMETHOD(device_probe,         xusbpadctl_probe),
1949 	DEVMETHOD(device_attach,        xusbpadctl_attach),
1950 	DEVMETHOD(device_detach,        xusbpadctl_detach),
1951 
1952 	DEVMETHOD_END
1953 };
1954 
1955 static DEFINE_CLASS_0(xusbpadctl, tegra_xusbpadctl_driver,
1956     tegra_xusbpadctl_methods, sizeof(struct padctl_softc));
1957 EARLY_DRIVER_MODULE(tegra_xusbpadctl, simplebus, tegra_xusbpadctl_driver,
1958     NULL, NULL, 73);
1959