1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright 2020 Michal Meloun <mmel@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/param.h> 29 #include <sys/systm.h> 30 #include <sys/bus.h> 31 #include <sys/lock.h> 32 #include <sys/mutex.h> 33 #include <sys/rman.h> 34 35 #include <machine/bus.h> 36 37 #include <dev/extres/clk/clk_div.h> 38 #include <dev/extres/clk/clk_fixed.h> 39 #include <dev/extres/clk/clk_gate.h> 40 #include <dev/extres/clk/clk_mux.h> 41 42 #include <dt-bindings/clock/tegra210-car.h> 43 #include "tegra210_car.h" 44 45 #if 0 46 #define dprintf(...) printf(__VA_ARGS__) 47 #else 48 #define dprintf(...) 49 #endif 50 51 /* All PLLs. */ 52 enum pll_type { 53 PLL_M, 54 PLL_MB, 55 PLL_X, 56 PLL_C, 57 PLL_C2, 58 PLL_C3, 59 PLL_C4, 60 PLL_P, 61 PLL_A, 62 PLL_A1, 63 PLL_U, 64 PLL_D, 65 PLL_D2, 66 PLL_DP, 67 PLL_E, 68 PLL_REFE}; 69 /* Flags for PLLs */ 70 71 #define PLL_FLAG_PDIV_POWER2 0x01 /* P Divider is 2^n */ 72 #define PLL_FLAG_VCO_OUT 0x02 /* Output VCO directly */ 73 #define PLL_FLAG_HAVE_SDM 0x04 /* Have SDM implemented */ 74 #define PLL_FLAG_HAVE_SDA 0x04 /* Have SDA implemented */ 75 76 /* Common base register bits. */ 77 #define PLL_BASE_BYPASS (1U << 31) 78 #define PLL_BASE_ENABLE (1 << 30) 79 #define PLL_BASE_REFDISABLE (1 << 29) 80 #define PLL_BASE_LOCK (1 << 27) 81 82 #define PLLREFE_MISC_LOCK (1 << 27) 83 84 #define PLL_MISC_LOCK_ENABLE (1 << 18) 85 #define PLLM_LOCK_ENABLE (1 << 4) 86 #define PLLMB_LOCK_ENABLE (1 << 16) 87 #define PLLC_LOCK_ENABLE (1 << 24) 88 #define PLLC4_LOCK_ENABLE (1 << 30) 89 #define PLLA_LOCK_ENABLE (1 << 28) 90 #define PLLD2_LOCK_ENABLE (1 << 30) 91 #define PLLU_LOCK_ENABLE (1 << 29) 92 #define PLLREFE_LOCK_ENABLE (1 << 30) 93 #define PLLPD_LOCK_ENABLE (1 << 30) 94 #define PLLE_LOCK_ENABLE (1 << 9) 95 96 #define PLLM_IDDQ_BIT 5 97 #define PLLMB_IDDQ_BIT 17 98 #define PLLC_IDDQ_BIT 27 99 #define PLLC4_IDDQ_BIT 18 100 #define PLLP_IDDQ_BIT 3 101 #define PLLA_IDDQ_BIT 25 102 #define PLLA1_IDDQ_BIT 27 103 #define PLLU_IDDQ_BIT 31 104 #define PLLD_IDDQ_BIT 20 105 #define PLLD2_IDDQ_BIT 18 106 #define PLLX_IDDQ_BIT 3 107 #define PLLREFE_IDDQ_BIT 24 108 #define PLLDP_IDDQ_BIT 18 109 110 111 #define PLL_LOCK_TIMEOUT 5000 112 113 /* Post divider <-> register value mapping. */ 114 struct pdiv_table { 115 uint32_t divider; /* real divider */ 116 uint32_t value; /* register value */ 117 }; 118 119 /* Bits definition of M, N and P fields. */ 120 struct mnp_bits { 121 uint32_t m_width; 122 uint32_t n_width; 123 uint32_t p_width; 124 uint32_t m_shift; 125 uint32_t n_shift; 126 uint32_t p_shift; 127 }; 128 129 struct clk_pll_def { 130 struct clknode_init_def clkdef; 131 enum pll_type type; 132 uint32_t base_reg; 133 uint32_t misc_reg; 134 uint32_t lock_enable; 135 uint32_t iddq_reg; 136 uint32_t iddq_mask; 137 uint32_t flags; 138 struct pdiv_table *pdiv_table; 139 struct mnp_bits mnp_bits; 140 }; 141 142 #define PLIST(x) static const char *x[] 143 144 #define PLL(_id, cname, pname) \ 145 .clkdef.id = _id, \ 146 .clkdef.name = cname, \ 147 .clkdef.parent_names = (const char *[]){pname}, \ 148 .clkdef.parent_cnt = 1, \ 149 .clkdef.flags = CLK_NODE_STATIC_STRINGS 150 151 /* multiplexer for pll sources. */ 152 #define MUX(_id, cname, plists, o, s, w) \ 153 { \ 154 .clkdef.id = _id, \ 155 .clkdef.name = cname, \ 156 .clkdef.parent_names = plists, \ 157 .clkdef.parent_cnt = nitems(plists), \ 158 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ 159 .offset = o, \ 160 .shift = s, \ 161 .width = w, \ 162 } 163 164 /* Fractional divider (7.1) for PLL branch. */ 165 #define DIV7_1(_id, cname, plist, o, s) \ 166 { \ 167 .clkdef.id = _id, \ 168 .clkdef.name = cname, \ 169 .clkdef.parent_names = (const char *[]){plist}, \ 170 .clkdef.parent_cnt = 1, \ 171 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ 172 .offset = o, \ 173 .i_shift = (s) + 1, \ 174 .i_width = 7, \ 175 .f_shift = s, \ 176 .f_width = 1, \ 177 } 178 179 /* P divider (2^n). for PLL branch. */ 180 #define DIV5_E(_id, cname, plist, o, s) \ 181 { \ 182 .clkdef.id = _id, \ 183 .clkdef.name = cname, \ 184 .clkdef.parent_names = (const char *[]){plist}, \ 185 .clkdef.parent_cnt = 1, \ 186 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ 187 .offset = o, \ 188 .i_shift = s, \ 189 .i_width = 5, \ 190 } 191 192 /* P divider (2^n). for PLL branch. */ 193 #define DIV_TB(_id, cname, plist, o, s, n, table) \ 194 { \ 195 .clkdef.id = _id, \ 196 .clkdef.name = cname, \ 197 .clkdef.parent_names = (const char *[]){plist}, \ 198 .clkdef.parent_cnt = 1, \ 199 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ 200 .div_flags = CLK_DIV_WITH_TABLE | CLK_DIV_ZERO_BASED, \ 201 .offset = o, \ 202 .i_shift = s, \ 203 .i_width = n, \ 204 .div_table = table, \ 205 } 206 207 /* Standard gate. */ 208 #define GATE(_id, cname, plist, o, s) \ 209 { \ 210 .clkdef.id = _id, \ 211 .clkdef.name = cname, \ 212 .clkdef.parent_names = (const char *[]){plist}, \ 213 .clkdef.parent_cnt = 1, \ 214 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ 215 .offset = o, \ 216 .shift = s, \ 217 .mask = 1, \ 218 .on_value = 1, \ 219 .off_value = 0, \ 220 } 221 /* Gate for PLL branch. */ 222 #define GATE_PLL(_id, cname, plist, o, s) \ 223 { \ 224 .clkdef.id = _id, \ 225 .clkdef.name = cname, \ 226 .clkdef.parent_names = (const char *[]){plist}, \ 227 .clkdef.parent_cnt = 1, \ 228 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ 229 .offset = o, \ 230 .shift = s, \ 231 .mask = 3, \ 232 .on_value = 3, \ 233 .off_value = 0, \ 234 } 235 236 /* Fixed rate multipier/divider. */ 237 #define FACT(_id, cname, pname, _mult, _div) \ 238 { \ 239 .clkdef.id = _id, \ 240 .clkdef.name = cname, \ 241 .clkdef.parent_names = (const char *[]){pname}, \ 242 .clkdef.parent_cnt = 1, \ 243 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ 244 .mult = _mult, \ 245 .div = _div, \ 246 } 247 248 static struct pdiv_table qlin_map[] = { 249 { 1, 0}, 250 { 2, 1}, 251 { 3, 2}, 252 { 4, 3}, 253 { 5, 4}, 254 { 6, 5}, 255 { 8, 6}, 256 { 9, 7}, 257 {10, 8}, 258 {12, 9}, 259 {15, 10}, 260 {16, 11}, 261 {18, 12}, 262 {20, 13}, 263 {24, 14}, 264 {30, 15}, 265 {32, 16}, 266 { 0, 0}, 267 }; 268 269 static struct clk_pll_def pll_clks[] = { 270 /* PLLM: 880 MHz Clock source for EMC 2x clock */ 271 { 272 PLL(TEGRA210_CLK_PLL_M, "pllM_out0", "osc"), 273 .type = PLL_M, 274 .base_reg = PLLM_BASE, 275 .misc_reg = PLLM_MISC2, 276 .lock_enable = PLLM_LOCK_ENABLE, 277 .iddq_reg = PLLM_MISC2, 278 .iddq_mask = 1 << PLLM_IDDQ_BIT, 279 .pdiv_table = qlin_map, 280 .mnp_bits = {8, 8, 5, 0, 8, 20}, 281 }, 282 /* PLLMB: 880 MHz Clock source for EMC 2x clock */ 283 { 284 PLL(TEGRA210_CLK_PLL_M, "pllMB_out0", "osc"), 285 .type = PLL_MB, 286 .base_reg = PLLMB_BASE, 287 .misc_reg = PLLMB_MISC1, 288 .lock_enable = PLLMB_LOCK_ENABLE, 289 .iddq_reg = PLLMB_MISC1, 290 .iddq_mask = 1 << PLLMB_IDDQ_BIT, 291 .pdiv_table = qlin_map, 292 .mnp_bits = {8, 8, 5, 0, 8, 20}, 293 }, 294 /* PLLX: 1GHz Clock source for the fast CPU cluster and the shadow CPU */ 295 { 296 PLL(TEGRA210_CLK_PLL_X, "pllX_out0", "osc_div_clk"), 297 .type = PLL_X, 298 .base_reg = PLLX_BASE, 299 .misc_reg = PLLX_MISC, 300 .lock_enable = PLL_MISC_LOCK_ENABLE, 301 .iddq_reg = PLLX_MISC_3, 302 .iddq_mask = 1 << PLLX_IDDQ_BIT, 303 .pdiv_table = qlin_map, 304 .mnp_bits = {8, 8, 5, 0, 8, 20}, 305 }, 306 /* PLLC: 510 MHz Clock source for camera use */ 307 { 308 PLL(TEGRA210_CLK_PLL_C, "pllC_out0", "osc_div_clk"), 309 .type = PLL_C, 310 .base_reg = PLLC_BASE, 311 .misc_reg = PLLC_MISC_0, 312 .iddq_reg = PLLC_MISC_1, 313 .iddq_mask = 1 << PLLC_IDDQ_BIT, 314 .pdiv_table = qlin_map, 315 .mnp_bits = {8, 8, 5, 0, 10, 20}, 316 }, 317 /* PLLC2: 510 MHz Clock source for SE, VIC, TSECB, NVJPG scaling */ 318 { 319 PLL(TEGRA210_CLK_PLL_C2, "pllC2_out0", "osc_div_clk"), 320 .type = PLL_C2, 321 .base_reg = PLLC2_BASE, 322 .misc_reg = PLLC2_MISC_0, 323 .iddq_reg = PLLC2_MISC_1, 324 .iddq_mask = 1 << PLLC_IDDQ_BIT, 325 .pdiv_table = qlin_map, 326 .mnp_bits = {8, 8, 5, 0, 10, 20}, 327 }, 328 /* PLLC3: 510 MHz Clock source for NVENC, NVDEC scaling */ 329 { 330 PLL(TEGRA210_CLK_PLL_C3, "pllC3_out0", "osc_div_clk"), 331 .type = PLL_C3, 332 .base_reg = PLLC3_BASE, 333 .misc_reg = PLLC3_MISC_0, 334 .lock_enable = PLL_MISC_LOCK_ENABLE, 335 .iddq_reg = PLLC3_MISC_1, 336 .iddq_mask = 1 << PLLC_IDDQ_BIT, 337 .mnp_bits = {8, 8, 5, 0, 10, 20}, 338 }, 339 /* PLLC4: 600 MHz Clock source for SD/eMMC ans system busses */ 340 { 341 PLL(TEGRA210_CLK_PLL_C4, "pllC4", "pllC4_src"), 342 .type = PLL_C4, 343 .flags = PLL_FLAG_VCO_OUT, 344 .base_reg = PLLC4_BASE, 345 .misc_reg = PLLC4_MISC, 346 .lock_enable = PLLC4_LOCK_ENABLE, 347 .iddq_reg = PLLC4_BASE, 348 .iddq_mask = 1 << PLLC4_IDDQ_BIT, 349 .pdiv_table = qlin_map, 350 .mnp_bits = {8, 8, 5, 0, 8, 19}, 351 }, 352 /* PLLP: 408 MHz Clock source for most peripherals */ 353 { 354 /* 355 * VCO is directly exposed as pllP_out0, P div is used for 356 * pllP_out2 357 */ 358 PLL(TEGRA210_CLK_PLL_P, "pllP_out0", "osc_div_clk"), 359 .type = PLL_P, 360 .flags = PLL_FLAG_VCO_OUT, 361 .base_reg = PLLP_BASE, 362 .misc_reg = PLLP_MISC, 363 .lock_enable = PLL_MISC_LOCK_ENABLE, 364 .iddq_reg = PLLP_MISC, 365 .iddq_mask = 1 << PLLA_IDDQ_BIT, 366 .mnp_bits = {8, 8, 5, 0, 10, 20}, 367 }, 368 /* PLLA: Audio clock for precise codec sampling */ 369 { 370 PLL(TEGRA210_CLK_PLL_A, "pllA", "osc_div_clk"), 371 .type = PLL_A, 372 .base_reg = PLLA_BASE, 373 .misc_reg = PLLA_MISC, 374 .lock_enable = PLLA_LOCK_ENABLE, 375 .iddq_reg = PLLA_BASE, 376 .iddq_mask = 1 << PLLA_IDDQ_BIT, 377 .pdiv_table = qlin_map, 378 .mnp_bits = {8, 8, 5, 0, 8, 20}, 379 }, 380 /* PLLA1: Audio clock for ADSP */ 381 { 382 PLL(TEGRA210_CLK_PLL_A1, "pllA1_out0", "osc_div_clk"), 383 .type = PLL_A1, 384 .base_reg = PLLA1_BASE, 385 .misc_reg = PLLA1_MISC_1, 386 .iddq_reg = PLLA1_MISC_1, 387 .iddq_mask = 1 << PLLA_IDDQ_BIT, 388 .pdiv_table = qlin_map, 389 .mnp_bits = {8, 8, 5, 0, 8, 20}, 390 }, 391 /* PLLU: 480 MHz Clock source for USB PHY, provides 12/60/480 MHz */ 392 { 393 PLL(TEGRA210_CLK_PLL_U, "pllU", "osc_div_clk"), 394 .type = PLL_U, 395 .flags = PLL_FLAG_VCO_OUT | PLL_FLAG_HAVE_SDA, 396 .base_reg = PLLU_BASE, 397 .misc_reg = PLLU_MISC, 398 .lock_enable = PLLU_LOCK_ENABLE, 399 .iddq_reg = PLLU_MISC, 400 .iddq_mask = 1 << PLLU_IDDQ_BIT, 401 .pdiv_table = qlin_map, 402 .mnp_bits = {8, 8, 5, 0, 8, 16}, 403 }, 404 /* PLLD: 594 MHz Clock sources for the DSI and display subsystem */ 405 { 406 PLL(TEGRA210_CLK_PLL_D, "pllD_out", "osc_div_clk"), 407 .type = PLL_D, 408 .flags = PLL_FLAG_PDIV_POWER2, 409 .base_reg = PLLD_BASE, 410 .misc_reg = PLLD_MISC, 411 .lock_enable = PLL_MISC_LOCK_ENABLE, 412 .iddq_reg = PLLA1_MISC_1, 413 .iddq_mask = 1 << PLLA_IDDQ_BIT, 414 .mnp_bits = {8, 8, 3, 0, 11, 20}, 415 }, 416 /* PLLD2: 594 MHz Clock sources for the DSI and display subsystem */ 417 { 418 PLL(TEGRA210_CLK_PLL_D2, "pllD2_out", "pllD2_src"), 419 .type = PLL_D2, 420 .flags = PLL_FLAG_HAVE_SDM, 421 .base_reg = PLLD2_BASE, 422 .misc_reg = PLLD2_MISC, 423 .lock_enable = PLLD2_LOCK_ENABLE, 424 .iddq_reg = PLLD2_BASE, 425 .iddq_mask = 1 << PLLD_IDDQ_BIT, 426 .pdiv_table = qlin_map, 427 .mnp_bits = {8, 8, 5, 0, 8, 19}, 428 }, 429 /* PLLREFE: 624 Mhz*/ 430 { 431 PLL(0, "pllREFE", "osc_div_clk"), 432 .type = PLL_REFE, 433 .flags = PLL_FLAG_VCO_OUT, 434 .base_reg = PLLREFE_BASE, 435 .misc_reg = PLLREFE_MISC, 436 .lock_enable = PLLREFE_LOCK_ENABLE, 437 .iddq_reg = PLLREFE_MISC, 438 .iddq_mask = 1 << PLLREFE_IDDQ_BIT, 439 .pdiv_table = qlin_map, 440 .mnp_bits = {8, 8, 5, 0, 8, 16}, 441 }, 442 /* PLLE: 100 MHz reference clock for PCIe/SATA/USB 3.0 (spread spectrum) */ 443 { 444 PLL(TEGRA210_CLK_PLL_E, "pllE_out0", "pllE_src"), 445 .type = PLL_E, 446 .base_reg = PLLE_BASE, 447 .misc_reg = PLLE_MISC, 448 .lock_enable = PLLE_LOCK_ENABLE, 449 .pdiv_table = qlin_map, 450 .mnp_bits = {8, 8, 5, 0, 8, 24}, 451 }, 452 /* PLLDP: 270 MHz Clock source fordisplay SOR (spread spectrum) */ 453 { 454 PLL(0, "pllDP_out0", "pllDP_src"), 455 .type = PLL_DP, 456 .flags = PLL_FLAG_HAVE_SDM, 457 .base_reg = PLLDP_BASE, 458 .misc_reg = PLLDP_MISC, 459 .lock_enable = PLLPD_LOCK_ENABLE, 460 .iddq_reg = PLLDP_BASE, 461 .iddq_mask = 1 << PLLDP_IDDQ_BIT, 462 .pdiv_table = qlin_map, 463 .mnp_bits = {8, 8, 5, 0, 8, 19}, 464 }, 465 }; 466 467 /* Fixed rate dividers. */ 468 static struct clk_fixed_def tegra210_pll_fdivs[] = { 469 FACT(0, "pllP_UD", "pllP_out0", 1, 1), 470 FACT(0, "pllC_UD", "pllC_out0", 1, 1), 471 FACT(0, "pllD_UD", "pllD_out0", 1, 1), 472 FACT(0, "pllM_UD", "pllM_out0", 1, 1), 473 FACT(0, "pllMB_UD", "pllMB_out0", 1, 1), 474 FACT(TEGRA210_CLK_PLL_D_OUT0, "pllD_out0", "pllD_out", 1, 2), 475 476 FACT(0, "pllC4_out1", "pllC4", 1, 3), 477 FACT(0, "pllC4_out2", "pllC4", 1, 5), 478 FACT(0, "pllD2_out0", "pllD2_out", 1, 2), 479 480 /* Aliases used in super mux. */ 481 FACT(0, "pllX_out0_alias", "pllX_out0", 1, 1), 482 FACT(0, "dfllCPU_out_alias", "dfllCPU_out", 1, 1), 483 }; 484 485 /* MUXes for PLL sources. */ 486 PLIST(mux_pll_srcs) = {"osc_div_clk", NULL, "pllP_out0", NULL}; /* FIXME */ 487 PLIST(mux_plle_src1) = {"osc_div_clk", "pllP_out0"}; 488 PLIST(mux_plle_src) = {"pllE_src1", "pllREFE_out0"}; 489 static struct clk_mux_def tegra210_pll_sources[] = { 490 /* Core clocks. */ 491 MUX(0, "pllD2_src", mux_pll_srcs, PLLD2_BASE, 25, 2), 492 MUX(0, "pllDP_src", mux_pll_srcs, PLLDP_BASE, 25, 2), 493 MUX(0, "pllC4_src", mux_pll_srcs, PLLC4_BASE, 25, 2), 494 MUX(0, "pllE_src1", mux_plle_src1, PLLE_AUX, 2, 1), 495 MUX(0, "pllE_src", mux_plle_src, PLLE_AUX, 28, 1), 496 }; 497 498 /* Gates for PLL branches. */ 499 static struct clk_gate_def tegra210_pll_gates[] = { 500 /* Core clocks. */ 501 GATE_PLL(0, "pllC_out1", "pllC_out1_div", PLLC_OUT, 0), 502 503 GATE_PLL(0, "pllP_out1", "pllP_out1_div", PLLP_OUTA, 0), 504 GATE_PLL(0, "pllP_out3", "pllP_out3_div", PLLP_OUTB, 0), 505 GATE_PLL(TEGRA210_CLK_PLL_P_OUT4, "pllP_out4", "pllP_out4_div", PLLP_OUTB, 16), 506 GATE_PLL(0, "pllP_out5", "pllP_out5_div", PLLP_OUTC, 16), 507 508 GATE_PLL(0, "pllU_out1", "pllU_out1_div", PLLU_OUTA, 0), 509 GATE_PLL(0, "pllU_out2", "pllU_out2_div", PLLU_OUTA, 16), 510 GATE(0, "pllU_480", "pllU", PLLU_BASE, 22), 511 GATE(0, "pllU_60", "pllU_out2", PLLU_BASE, 23), 512 GATE(0, "pllU_48", "pllU_out1", PLLU_BASE, 25), 513 514 GATE_PLL(0, "pllREFE_out1", "pllREFE_out1_div", PLLREFE_OUT, 0), 515 GATE_PLL(0, "pllC4_out3", "pllC4_out3_div", PLLC4_OUT, 0), 516 517 GATE_PLL(0, "pllA_out0", "pllA_out0_div", PLLA_OUT, 0), 518 }; 519 520 struct clk_div_table tegra210_pll_pdiv_tbl[] = { 521 /* value , divider */ 522 { 0, 1 }, 523 { 1, 2 }, 524 { 2, 3 }, 525 { 3, 4 }, 526 { 4, 5 }, 527 { 5, 6 }, 528 { 6, 8 }, 529 { 7, 10 }, 530 { 8, 12 }, 531 { 9, 16 }, 532 {10, 12 }, 533 {11, 16 }, 534 {12, 20 }, 535 {13, 24 }, 536 {14, 32 }, 537 { 0, 0 }, 538 }; 539 540 /* Dividers for PLL branches. */ 541 static struct clk_div_def tegra210_pll_divs[] = { 542 /* Core clocks. */ 543 DIV7_1(0, "pllC_out1_div", "pllC_out0", PLLC_OUT, 8), 544 545 DIV7_1(0, "pllP_out1_div", "pllP_out0", PLLP_OUTA, 8), 546 DIV_TB(0, "pllP_out2", "pllP_out0", PLLP_BASE, 20, 5, tegra210_pll_pdiv_tbl), 547 DIV7_1(0, "pllP_out3_div", "pllP_out0", PLLP_OUTB, 8), 548 DIV7_1(0, "pllP_out4_div", "pllP_out0", PLLP_OUTB, 24), 549 DIV7_1(0, "pllP_out5_div", "pllP_out0", PLLP_OUTC, 24), 550 551 DIV_TB(0, "pllU_out0", "pllU", PLLU_BASE, 16, 5, tegra210_pll_pdiv_tbl), 552 DIV7_1(0, "pllU_out1_div", "pllU_out0", PLLU_OUTA, 8), 553 DIV7_1(0, "pllU_out2_div", "pllU_out0", PLLU_OUTA, 24), 554 555 DIV_TB(0, "pllREFE_out0", "pllREFE", PLLREFE_BASE, 16, 5, tegra210_pll_pdiv_tbl), 556 DIV7_1(0, "pllREFE_out1_div", "pllREFE", PLLREFE_OUT, 8), 557 558 DIV_TB(TEGRA210_CLK_PLL_C4_OUT0, 559 "pllC4_out0", "pllC4", PLLC4_BASE, 19, 5, tegra210_pll_pdiv_tbl), 560 DIV7_1(0, "pllC4_out3_div", "pllC4_out0", PLLC4_OUT, 8), 561 562 DIV7_1(0, "pllA_out0_div", "pllA", PLLA_OUT, 8), 563 564 }; 565 566 static int tegra210_pll_init(struct clknode *clk, device_t dev); 567 static int tegra210_pll_set_gate(struct clknode *clk, bool enable); 568 static int tegra210_pll_get_gate(struct clknode *clk, bool *enabled); 569 static int tegra210_pll_recalc(struct clknode *clk, uint64_t *freq); 570 static int tegra210_pll_set_freq(struct clknode *clknode, uint64_t fin, 571 uint64_t *fout, int flags, int *stop); 572 struct pll_sc { 573 device_t clkdev; 574 enum pll_type type; 575 uint32_t base_reg; 576 uint32_t misc_reg; 577 uint32_t lock_enable; 578 uint32_t iddq_reg; 579 uint32_t iddq_mask; 580 uint32_t flags; 581 struct pdiv_table *pdiv_table; 582 struct mnp_bits mnp_bits; 583 }; 584 585 static clknode_method_t tegra210_pll_methods[] = { 586 /* Device interface */ 587 CLKNODEMETHOD(clknode_init, tegra210_pll_init), 588 CLKNODEMETHOD(clknode_set_gate, tegra210_pll_set_gate), 589 CLKNODEMETHOD(clknode_get_gate, tegra210_pll_get_gate), 590 CLKNODEMETHOD(clknode_recalc_freq, tegra210_pll_recalc), 591 CLKNODEMETHOD(clknode_set_freq, tegra210_pll_set_freq), 592 CLKNODEMETHOD_END 593 }; 594 DEFINE_CLASS_1(tegra210_pll, tegra210_pll_class, tegra210_pll_methods, 595 sizeof(struct pll_sc), clknode_class); 596 597 static int 598 pll_enable(struct pll_sc *sc) 599 { 600 uint32_t reg; 601 602 603 RD4(sc, sc->base_reg, ®); 604 if (sc->type != PLL_E) 605 reg &= ~PLL_BASE_BYPASS; 606 reg |= PLL_BASE_ENABLE; 607 WR4(sc, sc->base_reg, reg); 608 return (0); 609 } 610 611 static int 612 pll_disable(struct pll_sc *sc) 613 { 614 uint32_t reg; 615 616 RD4(sc, sc->base_reg, ®); 617 if (sc->type != PLL_E) 618 reg |= PLL_BASE_BYPASS; 619 reg &= ~PLL_BASE_ENABLE; 620 WR4(sc, sc->base_reg, reg); 621 return (0); 622 } 623 624 static uint32_t 625 pdiv_to_reg(struct pll_sc *sc, uint32_t p_div) 626 { 627 struct pdiv_table *tbl; 628 629 tbl = sc->pdiv_table; 630 if (tbl == NULL) { 631 if (sc->flags & PLL_FLAG_PDIV_POWER2) 632 return (ffs(p_div) - 1); 633 else 634 return (p_div); 635 } 636 637 while (tbl->divider != 0) { 638 if (p_div <= tbl->divider) 639 return (tbl->value); 640 tbl++; 641 } 642 return (0xFFFFFFFF); 643 } 644 645 static uint32_t 646 reg_to_pdiv(struct pll_sc *sc, uint32_t reg) 647 { 648 struct pdiv_table *tbl; 649 650 tbl = sc->pdiv_table; 651 if (tbl == NULL) { 652 if (sc->flags & PLL_FLAG_PDIV_POWER2) 653 return (1 << reg); 654 else 655 return (reg == 0 ? 1: reg); 656 } 657 while (tbl->divider) { 658 if (reg == tbl->value) 659 return (tbl->divider); 660 tbl++; 661 } 662 return (0); 663 } 664 665 static uint32_t 666 get_masked(uint32_t val, uint32_t shift, uint32_t width) 667 { 668 669 return ((val >> shift) & ((1 << width) - 1)); 670 } 671 672 static uint32_t 673 set_masked(uint32_t val, uint32_t v, uint32_t shift, uint32_t width) 674 { 675 676 val &= ~(((1 << width) - 1) << shift); 677 val |= (v & ((1 << width) - 1)) << shift; 678 return (val); 679 } 680 681 static void 682 get_divisors(struct pll_sc *sc, uint32_t *m, uint32_t *n, uint32_t *p) 683 { 684 uint32_t val; 685 struct mnp_bits *mnp_bits; 686 687 mnp_bits = &sc->mnp_bits; 688 RD4(sc, sc->base_reg, &val); 689 *m = get_masked(val, mnp_bits->m_shift, mnp_bits->m_width); 690 *n = get_masked(val, mnp_bits->n_shift, mnp_bits->n_width); 691 *p = get_masked(val, mnp_bits->p_shift, mnp_bits->p_width); 692 } 693 694 static uint32_t 695 set_divisors(struct pll_sc *sc, uint32_t val, uint32_t m, uint32_t n, 696 uint32_t p) 697 { 698 struct mnp_bits *mnp_bits; 699 700 mnp_bits = &sc->mnp_bits; 701 val = set_masked(val, m, mnp_bits->m_shift, mnp_bits->m_width); 702 val = set_masked(val, n, mnp_bits->n_shift, mnp_bits->n_width); 703 val = set_masked(val, p, mnp_bits->p_shift, mnp_bits->p_width); 704 return (val); 705 } 706 707 static bool 708 is_locked(struct pll_sc *sc) 709 { 710 uint32_t reg; 711 712 switch (sc->type) { 713 case PLL_REFE: 714 RD4(sc, sc->misc_reg, ®); 715 reg &= PLLREFE_MISC_LOCK; 716 break; 717 718 case PLL_E: 719 RD4(sc, sc->misc_reg, ®); 720 reg &= PLLE_MISC_LOCK; 721 break; 722 723 default: 724 RD4(sc, sc->base_reg, ®); 725 reg &= PLL_BASE_LOCK; 726 break; 727 } 728 return (reg != 0); 729 } 730 731 static int 732 wait_for_lock(struct pll_sc *sc) 733 { 734 int i; 735 736 for (i = PLL_LOCK_TIMEOUT / 10; i > 0; i--) { 737 if (is_locked(sc)) 738 break; 739 DELAY(10); 740 } 741 if (i <= 0) { 742 printf("PLL lock timeout\n"); 743 return (ETIMEDOUT); 744 } 745 return (0); 746 } 747 748 static int 749 plle_enable(struct pll_sc *sc) 750 { 751 uint32_t reg; 752 int rv; 753 uint32_t pll_m = 2; 754 uint32_t pll_n = 125; 755 uint32_t pll_cml = 14; 756 757 /* Disable lock override. */ 758 RD4(sc, sc->base_reg, ®); 759 reg &= ~PLLE_BASE_LOCK_OVERRIDE; 760 WR4(sc, sc->base_reg, reg); 761 762 /* Enable SW control */ 763 RD4(sc, PLLE_AUX, ®); 764 reg |= PLLE_AUX_ENABLE_SWCTL; 765 reg &= ~PLLE_AUX_SEQ_ENABLE; 766 WR4(sc, PLLE_AUX, reg); 767 DELAY(10); 768 769 RD4(sc, sc->misc_reg, ®); 770 reg |= PLLE_MISC_LOCK_ENABLE; 771 reg |= PLLE_MISC_IDDQ_SWCTL; 772 reg &= ~PLLE_MISC_IDDQ_OVERRIDE_VALUE; 773 reg |= PLLE_MISC_PTS; 774 reg &= ~PLLE_MISC_VREG_BG_CTRL(~0); 775 reg &= ~PLLE_MISC_VREG_CTRL(~0); 776 WR4(sc, sc->misc_reg, reg); 777 DELAY(10); 778 779 RD4(sc, PLLE_SS_CNTL, ®); 780 reg |= PLLE_SS_CNTL_DISABLE; 781 WR4(sc, PLLE_SS_CNTL, reg); 782 783 RD4(sc, sc->base_reg, ®); 784 reg = set_divisors(sc, reg, pll_m, pll_n, pll_cml); 785 WR4(sc, sc->base_reg, reg); 786 DELAY(10); 787 788 pll_enable(sc); 789 rv = wait_for_lock(sc); 790 if (rv != 0) 791 return (rv); 792 793 RD4(sc, PLLE_SS_CNTL, ®); 794 reg &= ~PLLE_SS_CNTL_SSCINCINTRV(~0); 795 reg &= ~PLLE_SS_CNTL_SSCINC(~0); 796 reg &= ~PLLE_SS_CNTL_SSCINVERT; 797 reg &= ~PLLE_SS_CNTL_SSCCENTER; 798 reg &= ~PLLE_SS_CNTL_SSCMAX(~0); 799 reg |= PLLE_SS_CNTL_SSCINCINTRV(0x23); 800 reg |= PLLE_SS_CNTL_SSCINC(0x1); 801 reg |= PLLE_SS_CNTL_SSCMAX(0x21); 802 WR4(sc, PLLE_SS_CNTL, reg); 803 reg &= ~PLLE_SS_CNTL_SSCBYP; 804 reg &= ~PLLE_SS_CNTL_BYPASS_SS; 805 WR4(sc, PLLE_SS_CNTL, reg); 806 DELAY(10); 807 808 reg &= ~PLLE_SS_CNTL_INTERP_RESET; 809 WR4(sc, PLLE_SS_CNTL, reg); 810 DELAY(10); 811 812 /* HW control of brick pll. */ 813 RD4(sc, sc->misc_reg, ®); 814 reg &= ~PLLE_MISC_IDDQ_SWCTL; 815 WR4(sc, sc->misc_reg, reg); 816 817 RD4(sc, PLLE_AUX, ®); 818 reg |= PLLE_AUX_USE_LOCKDET; 819 reg |= PLLE_AUX_SS_SEQ_INCLUDE; 820 reg &= ~PLLE_AUX_ENABLE_SWCTL; 821 reg &= ~PLLE_AUX_SS_SWCTL; 822 WR4(sc, PLLE_AUX, reg); 823 reg |= PLLE_AUX_SEQ_START_STATE; 824 DELAY(10); 825 reg |= PLLE_AUX_SEQ_ENABLE; 826 WR4(sc, PLLE_AUX, reg); 827 828 /* Enable and start XUSBIO PLL HW control*/ 829 RD4(sc, XUSBIO_PLL_CFG0, ®); 830 reg &= ~XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL; 831 reg &= ~XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL; 832 reg |= XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET; 833 reg |= XUSBIO_PLL_CFG0_PADPLL_SLEEP_IDDQ; 834 reg &= ~XUSBIO_PLL_CFG0_SEQ_ENABLE; 835 WR4(sc, XUSBIO_PLL_CFG0, reg); 836 DELAY(10); 837 838 reg |= XUSBIO_PLL_CFG0_SEQ_ENABLE; 839 WR4(sc, XUSBIO_PLL_CFG0, reg); 840 841 842 /* Enable and start SATA PLL HW control */ 843 RD4(sc, SATA_PLL_CFG0, ®); 844 reg &= ~SATA_PLL_CFG0_PADPLL_RESET_SWCTL; 845 reg &= ~SATA_PLL_CFG0_PADPLL_RESET_OVERRIDE_VALUE; 846 reg |= SATA_PLL_CFG0_PADPLL_USE_LOCKDET; 847 reg |= SATA_PLL_CFG0_PADPLL_SLEEP_IDDQ; 848 reg &= ~SATA_PLL_CFG0_SEQ_IN_SWCTL; 849 reg &= ~SATA_PLL_CFG0_SEQ_RESET_INPUT_VALUE; 850 reg &= ~SATA_PLL_CFG0_SEQ_LANE_PD_INPUT_VALUE; 851 reg &= ~SATA_PLL_CFG0_SEQ_PADPLL_PD_INPUT_VALUE; 852 reg &= ~SATA_PLL_CFG0_SEQ_ENABLE; 853 WR4(sc, SATA_PLL_CFG0, reg); 854 DELAY(10); 855 reg |= SATA_PLL_CFG0_SEQ_ENABLE; 856 WR4(sc, SATA_PLL_CFG0, reg); 857 858 /* Enable HW control of PCIe PLL. */ 859 RD4(sc, PCIE_PLL_CFG, ®); 860 reg |= PCIE_PLL_CFG_SEQ_ENABLE; 861 WR4(sc, PCIE_PLL_CFG, reg); 862 863 return (0); 864 } 865 866 static int 867 tegra210_pll_set_gate(struct clknode *clknode, bool enable) 868 { 869 int rv; 870 struct pll_sc *sc; 871 872 sc = clknode_get_softc(clknode); 873 if (enable == 0) { 874 rv = pll_disable(sc); 875 return(rv); 876 } 877 878 if (sc->type == PLL_E) 879 rv = plle_enable(sc); 880 else 881 rv = pll_enable(sc); 882 return (rv); 883 } 884 885 static int 886 tegra210_pll_get_gate(struct clknode *clknode, bool *enabled) 887 { 888 uint32_t reg; 889 struct pll_sc *sc; 890 891 sc = clknode_get_softc(clknode); 892 RD4(sc, sc->base_reg, ®); 893 *enabled = reg & PLL_BASE_ENABLE ? true: false; 894 WR4(sc, sc->base_reg, reg); 895 return (0); 896 } 897 898 static int 899 pll_set_std(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags, 900 uint32_t m, uint32_t n, uint32_t p) 901 { 902 uint32_t reg; 903 struct mnp_bits *mnp_bits; 904 int rv; 905 906 mnp_bits = &sc->mnp_bits; 907 if (m >= (1 << mnp_bits->m_width)) 908 return (ERANGE); 909 if (n >= (1 << mnp_bits->n_width)) 910 return (ERANGE); 911 if (pdiv_to_reg(sc, p) >= (1 << mnp_bits->p_width)) 912 return (ERANGE); 913 914 if (flags & CLK_SET_DRYRUN) { 915 if (((flags & (CLK_SET_ROUND_UP | CLK_SET_ROUND_DOWN)) == 0) && 916 (*fout != (((fin / m) * n) /p))) 917 return (ERANGE); 918 919 *fout = ((fin / m) * n) /p; 920 921 return (0); 922 } 923 924 pll_disable(sc); 925 926 /* take pll out of IDDQ */ 927 if (sc->iddq_reg != 0) 928 MD4(sc, sc->iddq_reg, sc->iddq_mask, 0); 929 930 RD4(sc, sc->base_reg, ®); 931 reg = set_masked(reg, m, mnp_bits->m_shift, mnp_bits->m_width); 932 reg = set_masked(reg, n, mnp_bits->n_shift, mnp_bits->n_width); 933 reg = set_masked(reg, pdiv_to_reg(sc, p), mnp_bits->p_shift, 934 mnp_bits->p_width); 935 WR4(sc, sc->base_reg, reg); 936 937 /* Enable PLL. */ 938 RD4(sc, sc->base_reg, ®); 939 reg |= PLL_BASE_ENABLE; 940 WR4(sc, sc->base_reg, reg); 941 942 /* Enable lock detection. */ 943 RD4(sc, sc->misc_reg, ®); 944 reg |= sc->lock_enable; 945 WR4(sc, sc->misc_reg, reg); 946 947 rv = wait_for_lock(sc); 948 if (rv != 0) { 949 /* Disable PLL */ 950 RD4(sc, sc->base_reg, ®); 951 reg &= ~PLL_BASE_ENABLE; 952 WR4(sc, sc->base_reg, reg); 953 return (rv); 954 } 955 RD4(sc, sc->misc_reg, ®); 956 957 pll_enable(sc); 958 *fout = ((fin / m) * n) / p; 959 return 0; 960 } 961 962 static int 963 plla_set_freq(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags) 964 { 965 uint32_t m, n, p; 966 967 p = 1; 968 m = 3; 969 n = (*fout * p * m + fin / 2)/ fin; 970 dprintf("%s: m: %d, n: %d, p: %d\n", __func__, m, n, p); 971 return (pll_set_std(sc, fin, fout, flags, m, n, p)); 972 } 973 974 static int 975 pllc_set_freq(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags) 976 { 977 uint32_t m, n, p; 978 979 p = 2; 980 m = 3; 981 n = (*fout * p * m + fin / 2)/ fin; 982 dprintf("%s: m: %d, n: %d, p: %d\n", __func__, m, n, p); 983 return (pll_set_std( sc, fin, fout, flags, m, n, p)); 984 } 985 986 static int 987 pllc4_set_freq(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags) 988 { 989 uint32_t m, n, p; 990 991 p = 1; 992 m = 4; 993 n = (*fout * p * m + fin / 2)/ fin; 994 dprintf("%s: m: %d, n: %d, p: %d\n", __func__, m, n, p); 995 return (pll_set_std( sc, fin, fout, flags, m, n, p)); 996 } 997 998 static int 999 plldp_set_freq(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags) 1000 { 1001 uint32_t m, n, p; 1002 1003 p = 1; 1004 m = 4; 1005 n = (*fout * p * m + fin / 2)/ fin; 1006 dprintf("%s: m: %d, n: %d, p: %d\n", __func__, m, n, p); 1007 return (pll_set_std( sc, fin, fout, flags, m, n, p)); 1008 } 1009 1010 1011 /* 1012 * PLLD2 is used as source for pixel clock for HDMI. 1013 * We must be able to set it frequency very flexibly and 1014 * precisely (within 5% tolerance limit allowed by HDMI specs). 1015 * 1016 * For this reason, it is necessary to search the full state space. 1017 * Fortunately, thanks to early cycle terminations, performance 1018 * is within acceptable limits. 1019 */ 1020 #define PLLD2_PFD_MIN 12000000 /* 12 MHz */ 1021 #define PLLD2_PFD_MAX 38400000 /* 38.4 MHz */ 1022 #define PLLD2_VCO_MIN 750000000 /* 750 MHz */ 1023 #define PLLD2_VCO_MAX 1500000000 /* 1.5 GHz */ 1024 1025 static int 1026 plld2_set_freq(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags) 1027 { 1028 uint32_t m, n, p; 1029 uint32_t best_m, best_n, best_p; 1030 uint64_t vco, pfd; 1031 int64_t err, best_err; 1032 struct mnp_bits *mnp_bits; 1033 struct pdiv_table *tbl; 1034 int p_idx, rv; 1035 1036 mnp_bits = &sc->mnp_bits; 1037 tbl = sc->pdiv_table; 1038 best_err = INT64_MAX; 1039 1040 for (p_idx = 0; tbl[p_idx].divider != 0; p_idx++) { 1041 p = tbl[p_idx].divider; 1042 1043 /* Check constraints */ 1044 vco = *fout * p; 1045 if (vco < PLLD2_VCO_MIN) 1046 continue; 1047 if (vco > PLLD2_VCO_MAX) 1048 break; 1049 1050 for (m = 1; m < (1 << mnp_bits->m_width); m++) { 1051 n = (*fout * p * m + fin / 2) / fin; 1052 1053 /* Check constraints */ 1054 if (n == 0) 1055 continue; 1056 if (n >= (1 << mnp_bits->n_width)) 1057 break; 1058 vco = (fin * n) / m; 1059 if (vco > PLLD2_VCO_MAX || vco < PLLD2_VCO_MIN) 1060 continue; 1061 pfd = fin / m; 1062 if (pfd > PLLD2_PFD_MAX || vco < PLLD2_PFD_MIN) 1063 continue; 1064 1065 /* Constraints passed, save best result */ 1066 err = *fout - vco / p; 1067 if (err < 0) 1068 err = -err; 1069 if (err < best_err) { 1070 best_err = err; 1071 best_p = p; 1072 best_m = m; 1073 best_n = n; 1074 } 1075 if (err == 0) 1076 goto done; 1077 } 1078 } 1079 done: 1080 /* 1081 * HDMI specification allows 5% pixel clock tolerance, 1082 * we will by a slightly stricter 1083 */ 1084 if (best_err > ((*fout * 100) / 4)) 1085 return (ERANGE); 1086 1087 if (flags & CLK_SET_DRYRUN) 1088 return (0); 1089 rv = pll_set_std(sc, fin, fout, flags, best_m, best_n, best_p); 1090 /* XXXX Panic for rv == ERANGE ? */ 1091 return (rv); 1092 } 1093 1094 static int 1095 pllrefe_set_freq(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags) 1096 { 1097 uint32_t m, n, p; 1098 1099 m = 1; 1100 p = 1; 1101 n = *fout * p * m / fin; 1102 dprintf("%s: m: %d, n: %d, p: %d\n", __func__, m, n, p); 1103 return (pll_set_std(sc, fin, fout, flags, m, n, p)); 1104 } 1105 1106 #define PLLX_PFD_MIN 12000000LL /* 12 MHz */ 1107 #define PLLX_PFD_MAX 38400000LL /* 38.4 MHz */ 1108 #define PLLX_VCO_MIN 900000000LL /* 0.9 GHz */ 1109 #define PLLX_VCO_MAX 3000000000LL /* 3 GHz */ 1110 1111 static int 1112 pllx_set_freq(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags) 1113 { 1114 struct mnp_bits *mnp_bits; 1115 uint32_t m, n, p; 1116 uint32_t old_m, old_n, old_p; 1117 uint32_t reg; 1118 int i, rv; 1119 1120 mnp_bits = &sc->mnp_bits; 1121 1122 get_divisors(sc, &old_m, &old_n, &old_p); 1123 old_p = reg_to_pdiv(sc, old_p); 1124 1125 /* Pre-divider is fixed, Compute post-divider */ 1126 m = old_m; 1127 p = 1; 1128 while ((*fout * p) < PLLX_VCO_MIN) 1129 p++; 1130 if ((*fout * p) > PLLX_VCO_MAX) 1131 return (ERANGE); 1132 1133 n = (*fout * p * m + fin / 2) / fin; 1134 dprintf("%s: m: %d, n: %d, p: %d\n", __func__, m, n, p); 1135 1136 if (m >= (1 << mnp_bits->m_width)) 1137 return (ERANGE); 1138 if (n >= (1 << mnp_bits->n_width)) 1139 return (ERANGE); 1140 if (pdiv_to_reg(sc, p) >= (1 << mnp_bits->p_width)) 1141 return (ERANGE); 1142 1143 if (flags & CLK_SET_DRYRUN) { 1144 if (((flags & (CLK_SET_ROUND_UP | CLK_SET_ROUND_DOWN)) == 0) && 1145 (*fout != (((fin / m) * n) /p))) 1146 return (ERANGE); 1147 *fout = ((fin / m) * n) /p; 1148 return (0); 1149 } 1150 1151 /* If new post-divider is bigger that original, set it now. */ 1152 if (p < old_p) { 1153 RD4(sc, sc->base_reg, ®); 1154 reg = set_masked(reg, pdiv_to_reg(sc, p), mnp_bits->p_shift, 1155 mnp_bits->p_width); 1156 WR4(sc, sc->base_reg, reg); 1157 } 1158 DELAY(100); 1159 1160 /* vvv Program dynamic VCO ramp. vvv */ 1161 /* 1 - disable dynamic ramp mode. */ 1162 RD4(sc, PLLX_MISC_2, ®); 1163 reg &= ~PLLX_MISC_2_EN_DYNRAMP; 1164 WR4(sc, PLLX_MISC_2, reg); 1165 1166 /* 2 - Setup new ndiv. */ 1167 RD4(sc, PLLX_MISC_2, ®); 1168 reg &= ~PLLX_MISC_2_NDIV_NEW(~0); 1169 reg |= PLLX_MISC_2_NDIV_NEW(n); 1170 WR4(sc, PLLX_MISC_2, reg); 1171 1172 /* 3 - enable dynamic ramp. */ 1173 RD4(sc, PLLX_MISC_2, ®); 1174 reg |= PLLX_MISC_2_EN_DYNRAMP; 1175 WR4(sc, PLLX_MISC_2, reg); 1176 1177 /* 4 - wait for done. */ 1178 for (i = PLL_LOCK_TIMEOUT / 10; i > 0; i--) { 1179 RD4(sc, PLLX_MISC_2, ®); 1180 if (reg & PLLX_MISC_2_DYNRAMP_DONE) 1181 break; 1182 DELAY(10); 1183 } 1184 if (i <= 0) { 1185 printf("PLL X dynamic ramp timedout\n"); 1186 return (ETIMEDOUT); 1187 } 1188 1189 /* 5 - copy new ndiv to base register. */ 1190 RD4(sc, sc->base_reg, ®); 1191 reg = set_masked(reg, n, mnp_bits->n_shift, 1192 mnp_bits->n_width); 1193 WR4(sc, sc->base_reg, reg); 1194 1195 /* 6 - disable dynamic ramp mode. */ 1196 RD4(sc, PLLX_MISC_2, ®); 1197 reg &= ~PLLX_MISC_2_EN_DYNRAMP; 1198 WR4(sc, PLLX_MISC_2, reg); 1199 1200 rv = wait_for_lock(sc); 1201 if (rv != 0) { 1202 printf("PLL X is not locked !!\n"); 1203 } 1204 /* ^^^ Dynamic ramp done. ^^^ */ 1205 1206 /* If new post-divider is smaller that original, set it. */ 1207 if (p > old_p) { 1208 RD4(sc, sc->base_reg, ®); 1209 reg = set_masked(reg, pdiv_to_reg(sc, p), mnp_bits->p_shift, 1210 mnp_bits->p_width); 1211 WR4(sc, sc->base_reg, reg); 1212 } 1213 1214 *fout = ((fin / m) * n) / p; 1215 return (0); 1216 } 1217 1218 /* Simplified setup for 38.4 MHz clock. */ 1219 #define PLLX_STEP_A 0x04 1220 #define PLLX_STEP_B 0x05 1221 static int 1222 pllx_init(struct pll_sc *sc) 1223 { 1224 uint32_t reg; 1225 1226 RD4(sc, PLLX_MISC, ®); 1227 reg = PLLX_MISC_LOCK_ENABLE; 1228 WR4(sc, PLLX_MISC, reg); 1229 1230 /* Setup dynamic ramp. */ 1231 reg = 0; 1232 reg |= PLLX_MISC_2_DYNRAMP_STEPA(PLLX_STEP_A); 1233 reg |= PLLX_MISC_2_DYNRAMP_STEPB(PLLX_STEP_B); 1234 WR4(sc, PLLX_MISC_2, reg); 1235 1236 /* Disable SDM. */ 1237 reg = 0; 1238 WR4(sc, PLLX_MISC_4, reg); 1239 WR4(sc, PLLX_MISC_5, reg); 1240 1241 return (0); 1242 } 1243 1244 static int 1245 tegra210_pll_set_freq(struct clknode *clknode, uint64_t fin, uint64_t *fout, 1246 int flags, int *stop) 1247 { 1248 *stop = 1; 1249 int rv; 1250 struct pll_sc *sc; 1251 1252 sc = clknode_get_softc(clknode); 1253 dprintf("%s: %s requested freq: %lu, input freq: %lu\n", __func__, 1254 clknode_get_name(clknode), *fout, fin); 1255 switch (sc->type) { 1256 case PLL_A: 1257 rv = plla_set_freq(sc, fin, fout, flags); 1258 break; 1259 1260 case PLL_C: 1261 case PLL_C2: 1262 case PLL_C3: 1263 rv = pllc_set_freq(sc, fin, fout, flags); 1264 break; 1265 1266 case PLL_C4: 1267 rv = pllc4_set_freq(sc, fin, fout, flags); 1268 break; 1269 1270 case PLL_D2: 1271 rv = plld2_set_freq(sc, fin, fout, flags); 1272 break; 1273 1274 case PLL_DP: 1275 rv = plldp_set_freq(sc, fin, fout, flags); 1276 break; 1277 1278 case PLL_REFE: 1279 rv = pllrefe_set_freq(sc, fin, fout, flags); 1280 break; 1281 1282 case PLL_X: 1283 rv = pllx_set_freq(sc, fin, fout, flags); 1284 break; 1285 1286 case PLL_U: 1287 if (*fout == 480000000) /* PLLU is fixed to 480 MHz */ 1288 rv = 0; 1289 else 1290 rv = ERANGE; 1291 break; 1292 default: 1293 rv = ENXIO; 1294 break; 1295 } 1296 1297 return (rv); 1298 } 1299 1300 1301 static int 1302 tegra210_pll_init(struct clknode *clk, device_t dev) 1303 { 1304 struct pll_sc *sc; 1305 uint32_t reg, rv; 1306 1307 sc = clknode_get_softc(clk); 1308 1309 if (sc->type == PLL_X) { 1310 rv = pllx_init(sc); 1311 if (rv != 0) 1312 return (rv); 1313 } 1314 1315 /* If PLL is enabled, enable lock detect too. */ 1316 RD4(sc, sc->base_reg, ®); 1317 if (reg & PLL_BASE_ENABLE) { 1318 RD4(sc, sc->misc_reg, ®); 1319 reg |= sc->lock_enable; 1320 WR4(sc, sc->misc_reg, reg); 1321 } 1322 if (sc->type == PLL_REFE) { 1323 RD4(sc, sc->misc_reg, ®); 1324 reg &= ~(1 << 29); /* Disable lock override */ 1325 WR4(sc, sc->misc_reg, reg); 1326 } 1327 clknode_init_parent_idx(clk, 0); 1328 return(0); 1329 } 1330 1331 static int 1332 tegra210_pll_recalc(struct clknode *clk, uint64_t *freq) 1333 { 1334 struct pll_sc *sc; 1335 uint32_t m, n, p, pr; 1336 uint32_t reg, misc_reg; 1337 int locked; 1338 1339 sc = clknode_get_softc(clk); 1340 1341 RD4(sc, sc->base_reg, ®); 1342 RD4(sc, sc->misc_reg, &misc_reg); 1343 1344 get_divisors(sc, &m, &n, &pr); 1345 1346 /* If VCO is directlu exposed, P divider is handled by external node */ 1347 if (sc->flags & PLL_FLAG_VCO_OUT) 1348 p = 1; 1349 else 1350 p = reg_to_pdiv(sc, pr); 1351 1352 locked = is_locked(sc); 1353 1354 dprintf("%s: %s (0x%08x, 0x%08x) - m: %d, n: %d, p: %d (%d): " 1355 "e: %d, r: %d, o: %d - %s\n", __func__, 1356 clknode_get_name(clk), reg, misc_reg, m, n, p, pr, 1357 (reg >> 30) & 1, (reg >> 29) & 1, (reg >> 28) & 1, 1358 locked ? "locked" : "unlocked"); 1359 1360 if ((m == 0) || (n == 0) || (p == 0)) { 1361 *freq = 0; 1362 return (EINVAL); 1363 } 1364 if (!locked) { 1365 *freq = 0; 1366 return (0); 1367 } 1368 *freq = ((*freq / m) * n) / p; 1369 return (0); 1370 } 1371 1372 static int 1373 pll_register(struct clkdom *clkdom, struct clk_pll_def *clkdef) 1374 { 1375 struct clknode *clk; 1376 struct pll_sc *sc; 1377 1378 clk = clknode_create(clkdom, &tegra210_pll_class, &clkdef->clkdef); 1379 if (clk == NULL) 1380 return (ENXIO); 1381 1382 sc = clknode_get_softc(clk); 1383 sc->clkdev = clknode_get_device(clk); 1384 sc->type = clkdef->type; 1385 sc->base_reg = clkdef->base_reg; 1386 sc->misc_reg = clkdef->misc_reg; 1387 sc->lock_enable = clkdef->lock_enable; 1388 sc->iddq_reg = clkdef->iddq_reg; 1389 sc->iddq_mask = clkdef->iddq_mask; 1390 sc->flags = clkdef->flags; 1391 sc->pdiv_table = clkdef->pdiv_table; 1392 sc->mnp_bits = clkdef->mnp_bits; 1393 clknode_register(clkdom, clk); 1394 return (0); 1395 } 1396 1397 static void config_utmi_pll(struct tegra210_car_softc *sc) 1398 { 1399 uint32_t reg; 1400 /* 1401 * XXX Simplified UTMIP settings for 38.4MHz base clock. 1402 */ 1403 #define ENABLE_DELAY_COUNT 0x00 1404 #define STABLE_COUNT 0x00 1405 #define ACTIVE_DELAY_COUNT 0x06 1406 #define XTAL_FREQ_COUNT 0x80 1407 1408 CLKDEV_READ_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, ®); 1409 reg &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE; 1410 CLKDEV_WRITE_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, reg); 1411 1412 CLKDEV_READ_4(sc->dev, UTMIP_PLL_CFG2, ®); 1413 reg &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0); 1414 reg |= UTMIP_PLL_CFG2_STABLE_COUNT(STABLE_COUNT); 1415 reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0); 1416 reg |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(ACTIVE_DELAY_COUNT); 1417 CLKDEV_WRITE_4(sc->dev, UTMIP_PLL_CFG2, reg); 1418 1419 CLKDEV_READ_4(sc->dev, UTMIP_PLL_CFG1, ®); 1420 reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0); 1421 reg |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(ENABLE_DELAY_COUNT); 1422 reg &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0); 1423 reg |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(XTAL_FREQ_COUNT); 1424 reg |= UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP; 1425 CLKDEV_WRITE_4(sc->dev, UTMIP_PLL_CFG1, reg); 1426 1427 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN; 1428 reg |= UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP; 1429 CLKDEV_WRITE_4(sc->dev, UTMIP_PLL_CFG1, reg); 1430 DELAY(20); 1431 1432 /* Setup samplers. */ 1433 CLKDEV_READ_4(sc->dev, UTMIP_PLL_CFG2, ®); 1434 reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERUP; 1435 reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERUP; 1436 reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERUP; 1437 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN; 1438 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN; 1439 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERDOWN; 1440 CLKDEV_WRITE_4(sc->dev, UTMIP_PLL_CFG2, reg); 1441 1442 /* Powerup UTMIP. */ 1443 CLKDEV_READ_4(sc->dev, UTMIP_PLL_CFG1, ®); 1444 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP; 1445 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN; 1446 CLKDEV_WRITE_4(sc->dev, UTMIP_PLL_CFG1, reg); 1447 DELAY(10); 1448 1449 /* Prepare UTMIP sequencer. */ 1450 CLKDEV_READ_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, ®); 1451 reg |= UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET; 1452 reg &= ~UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL; 1453 CLKDEV_WRITE_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, reg); 1454 DELAY(10); 1455 1456 CLKDEV_READ_4(sc->dev, XUSB_PLL_CFG0, ®); 1457 reg &= ~XUSB_PLL_CFG0_UTMIPLL_LOCK_DLY; 1458 CLKDEV_WRITE_4(sc->dev, XUSB_PLL_CFG0, reg); 1459 DELAY(10); 1460 1461 /* HW control of UTMIPLL. */ 1462 CLKDEV_READ_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, ®); 1463 reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE; 1464 CLKDEV_WRITE_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, reg); 1465 } 1466 1467 void 1468 tegra210_init_plls(struct tegra210_car_softc *sc) 1469 { 1470 int i, rv; 1471 1472 for (i = 0; i < nitems(tegra210_pll_sources); i++) { 1473 rv = clknode_mux_register(sc->clkdom, tegra210_pll_sources + i); 1474 if (rv != 0) 1475 panic("clk_mux_register failed"); 1476 } 1477 1478 for (i = 0; i < nitems(pll_clks); i++) { 1479 rv = pll_register(sc->clkdom, pll_clks + i); 1480 if (rv != 0) 1481 panic("pll_register failed"); 1482 } 1483 1484 config_utmi_pll(sc); 1485 1486 for (i = 0; i < nitems(tegra210_pll_fdivs); i++) { 1487 rv = clknode_fixed_register(sc->clkdom, tegra210_pll_fdivs + i); 1488 if (rv != 0) 1489 panic("clk_fixed_register failed"); 1490 } 1491 1492 for (i = 0; i < nitems(tegra210_pll_gates); i++) { 1493 rv = clknode_gate_register(sc->clkdom, tegra210_pll_gates + i); 1494 if (rv != 0) 1495 panic("clk_gate_register failed"); 1496 } 1497 1498 for (i = 0; i < nitems(tegra210_pll_divs); i++) { 1499 rv = clknode_div_register(sc->clkdom, tegra210_pll_divs + i); 1500 if (rv != 0) 1501 panic("clk_div_register failed"); 1502 } 1503 } 1504