1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright 2020 Michal Meloun <mmel@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 #include <sys/param.h> 30 #include <sys/systm.h> 31 #include <sys/bus.h> 32 #include <sys/lock.h> 33 #include <sys/mutex.h> 34 #include <sys/rman.h> 35 36 #include <machine/bus.h> 37 38 #include <dev/extres/clk/clk_div.h> 39 #include <dev/extres/clk/clk_fixed.h> 40 #include <dev/extres/clk/clk_gate.h> 41 #include <dev/extres/clk/clk_mux.h> 42 43 #include <dt-bindings/clock/tegra210-car.h> 44 #include "tegra210_car.h" 45 46 #if 0 47 #define dprintf(...) printf(__VA_ARGS__) 48 #else 49 #define dprintf(...) 50 #endif 51 52 /* All PLLs. */ 53 enum pll_type { 54 PLL_M, 55 PLL_MB, 56 PLL_X, 57 PLL_C, 58 PLL_C2, 59 PLL_C3, 60 PLL_C4, 61 PLL_P, 62 PLL_A, 63 PLL_A1, 64 PLL_U, 65 PLL_D, 66 PLL_D2, 67 PLL_DP, 68 PLL_E, 69 PLL_REFE}; 70 /* Flags for PLLs */ 71 72 #define PLL_FLAG_PDIV_POWER2 0x01 /* P Divider is 2^n */ 73 #define PLL_FLAG_VCO_OUT 0x02 /* Output VCO directly */ 74 #define PLL_FLAG_HAVE_SDM 0x04 /* Have SDM implemented */ 75 #define PLL_FLAG_HAVE_SDA 0x04 /* Have SDA implemented */ 76 77 /* Common base register bits. */ 78 #define PLL_BASE_BYPASS (1U << 31) 79 #define PLL_BASE_ENABLE (1 << 30) 80 #define PLL_BASE_REFDISABLE (1 << 29) 81 #define PLL_BASE_LOCK (1 << 27) 82 83 #define PLLREFE_MISC_LOCK (1 << 27) 84 85 #define PLL_MISC_LOCK_ENABLE (1 << 18) 86 #define PLLM_LOCK_ENABLE (1 << 4) 87 #define PLLMB_LOCK_ENABLE (1 << 16) 88 #define PLLC_LOCK_ENABLE (1 << 24) 89 #define PLLC4_LOCK_ENABLE (1 << 30) 90 #define PLLA_LOCK_ENABLE (1 << 28) 91 #define PLLD2_LOCK_ENABLE (1 << 30) 92 #define PLLU_LOCK_ENABLE (1 << 29) 93 #define PLLREFE_LOCK_ENABLE (1 << 30) 94 #define PLLPD_LOCK_ENABLE (1 << 30) 95 #define PLLE_LOCK_ENABLE (1 << 9) 96 97 #define PLLM_IDDQ_BIT 5 98 #define PLLMB_IDDQ_BIT 17 99 #define PLLC_IDDQ_BIT 27 100 #define PLLC4_IDDQ_BIT 18 101 #define PLLP_IDDQ_BIT 3 102 #define PLLA_IDDQ_BIT 25 103 #define PLLA1_IDDQ_BIT 27 104 #define PLLU_IDDQ_BIT 31 105 #define PLLD_IDDQ_BIT 20 106 #define PLLD2_IDDQ_BIT 18 107 #define PLLX_IDDQ_BIT 3 108 #define PLLREFE_IDDQ_BIT 24 109 #define PLLDP_IDDQ_BIT 18 110 111 112 #define PLL_LOCK_TIMEOUT 5000 113 114 /* Post divider <-> register value mapping. */ 115 struct pdiv_table { 116 uint32_t divider; /* real divider */ 117 uint32_t value; /* register value */ 118 }; 119 120 /* Bits definition of M, N and P fields. */ 121 struct mnp_bits { 122 uint32_t m_width; 123 uint32_t n_width; 124 uint32_t p_width; 125 uint32_t m_shift; 126 uint32_t n_shift; 127 uint32_t p_shift; 128 }; 129 130 struct clk_pll_def { 131 struct clknode_init_def clkdef; 132 enum pll_type type; 133 uint32_t base_reg; 134 uint32_t misc_reg; 135 uint32_t lock_enable; 136 uint32_t iddq_reg; 137 uint32_t iddq_mask; 138 uint32_t flags; 139 struct pdiv_table *pdiv_table; 140 struct mnp_bits mnp_bits; 141 }; 142 143 #define PLIST(x) static const char *x[] 144 145 #define PLL(_id, cname, pname) \ 146 .clkdef.id = _id, \ 147 .clkdef.name = cname, \ 148 .clkdef.parent_names = (const char *[]){pname}, \ 149 .clkdef.parent_cnt = 1, \ 150 .clkdef.flags = CLK_NODE_STATIC_STRINGS 151 152 /* multiplexer for pll sources. */ 153 #define MUX(_id, cname, plists, o, s, w) \ 154 { \ 155 .clkdef.id = _id, \ 156 .clkdef.name = cname, \ 157 .clkdef.parent_names = plists, \ 158 .clkdef.parent_cnt = nitems(plists), \ 159 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ 160 .offset = o, \ 161 .shift = s, \ 162 .width = w, \ 163 } 164 165 /* Fractional divider (7.1) for PLL branch. */ 166 #define DIV7_1(_id, cname, plist, o, s) \ 167 { \ 168 .clkdef.id = _id, \ 169 .clkdef.name = cname, \ 170 .clkdef.parent_names = (const char *[]){plist}, \ 171 .clkdef.parent_cnt = 1, \ 172 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ 173 .offset = o, \ 174 .i_shift = (s) + 1, \ 175 .i_width = 7, \ 176 .f_shift = s, \ 177 .f_width = 1, \ 178 } 179 180 /* P divider (2^n). for PLL branch. */ 181 #define DIV5_E(_id, cname, plist, o, s) \ 182 { \ 183 .clkdef.id = _id, \ 184 .clkdef.name = cname, \ 185 .clkdef.parent_names = (const char *[]){plist}, \ 186 .clkdef.parent_cnt = 1, \ 187 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ 188 .offset = o, \ 189 .i_shift = s, \ 190 .i_width = 5, \ 191 } 192 193 /* P divider (2^n). for PLL branch. */ 194 #define DIV_TB(_id, cname, plist, o, s, n, table) \ 195 { \ 196 .clkdef.id = _id, \ 197 .clkdef.name = cname, \ 198 .clkdef.parent_names = (const char *[]){plist}, \ 199 .clkdef.parent_cnt = 1, \ 200 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ 201 .div_flags = CLK_DIV_WITH_TABLE | CLK_DIV_ZERO_BASED, \ 202 .offset = o, \ 203 .i_shift = s, \ 204 .i_width = n, \ 205 .div_table = table, \ 206 } 207 208 /* Standard gate. */ 209 #define GATE(_id, cname, plist, o, s) \ 210 { \ 211 .clkdef.id = _id, \ 212 .clkdef.name = cname, \ 213 .clkdef.parent_names = (const char *[]){plist}, \ 214 .clkdef.parent_cnt = 1, \ 215 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ 216 .offset = o, \ 217 .shift = s, \ 218 .mask = 1, \ 219 .on_value = 1, \ 220 .off_value = 0, \ 221 } 222 /* Gate for PLL branch. */ 223 #define GATE_PLL(_id, cname, plist, o, s) \ 224 { \ 225 .clkdef.id = _id, \ 226 .clkdef.name = cname, \ 227 .clkdef.parent_names = (const char *[]){plist}, \ 228 .clkdef.parent_cnt = 1, \ 229 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ 230 .offset = o, \ 231 .shift = s, \ 232 .mask = 3, \ 233 .on_value = 3, \ 234 .off_value = 0, \ 235 } 236 237 /* Fixed rate multipier/divider. */ 238 #define FACT(_id, cname, pname, _mult, _div) \ 239 { \ 240 .clkdef.id = _id, \ 241 .clkdef.name = cname, \ 242 .clkdef.parent_names = (const char *[]){pname}, \ 243 .clkdef.parent_cnt = 1, \ 244 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ 245 .mult = _mult, \ 246 .div = _div, \ 247 } 248 249 static struct pdiv_table qlin_map[] = { 250 { 1, 0}, 251 { 2, 1}, 252 { 3, 2}, 253 { 4, 3}, 254 { 5, 4}, 255 { 6, 5}, 256 { 8, 6}, 257 { 9, 7}, 258 {10, 8}, 259 {12, 9}, 260 {15, 10}, 261 {16, 11}, 262 {18, 12}, 263 {20, 13}, 264 {24, 14}, 265 {30, 15}, 266 {32, 16}, 267 { 0, 0}, 268 }; 269 270 static struct clk_pll_def pll_clks[] = { 271 /* PLLM: 880 MHz Clock source for EMC 2x clock */ 272 { 273 PLL(TEGRA210_CLK_PLL_M, "pllM_out0", "osc"), 274 .type = PLL_M, 275 .base_reg = PLLM_BASE, 276 .misc_reg = PLLM_MISC2, 277 .lock_enable = PLLM_LOCK_ENABLE, 278 .iddq_reg = PLLM_MISC2, 279 .iddq_mask = 1 << PLLM_IDDQ_BIT, 280 .pdiv_table = qlin_map, 281 .mnp_bits = {8, 8, 5, 0, 8, 20}, 282 }, 283 /* PLLMB: 880 MHz Clock source for EMC 2x clock */ 284 { 285 PLL(TEGRA210_CLK_PLL_M, "pllMB_out0", "osc"), 286 .type = PLL_MB, 287 .base_reg = PLLMB_BASE, 288 .misc_reg = PLLMB_MISC1, 289 .lock_enable = PLLMB_LOCK_ENABLE, 290 .iddq_reg = PLLMB_MISC1, 291 .iddq_mask = 1 << PLLMB_IDDQ_BIT, 292 .pdiv_table = qlin_map, 293 .mnp_bits = {8, 8, 5, 0, 8, 20}, 294 }, 295 /* PLLX: 1GHz Clock source for the fast CPU cluster and the shadow CPU */ 296 { 297 PLL(TEGRA210_CLK_PLL_X, "pllX_out0", "osc_div_clk"), 298 .type = PLL_X, 299 .base_reg = PLLX_BASE, 300 .misc_reg = PLLX_MISC, 301 .lock_enable = PLL_MISC_LOCK_ENABLE, 302 .iddq_reg = PLLX_MISC_3, 303 .iddq_mask = 1 << PLLX_IDDQ_BIT, 304 .pdiv_table = qlin_map, 305 .mnp_bits = {8, 8, 5, 0, 8, 20}, 306 }, 307 /* PLLC: 510 MHz Clock source for camera use */ 308 { 309 PLL(TEGRA210_CLK_PLL_C, "pllC_out0", "osc_div_clk"), 310 .type = PLL_C, 311 .base_reg = PLLC_BASE, 312 .misc_reg = PLLC_MISC_0, 313 .iddq_reg = PLLC_MISC_1, 314 .iddq_mask = 1 << PLLC_IDDQ_BIT, 315 .pdiv_table = qlin_map, 316 .mnp_bits = {8, 8, 5, 0, 10, 20}, 317 }, 318 /* PLLC2: 510 MHz Clock source for SE, VIC, TSECB, NVJPG scaling */ 319 { 320 PLL(TEGRA210_CLK_PLL_C2, "pllC2_out0", "osc_div_clk"), 321 .type = PLL_C2, 322 .base_reg = PLLC2_BASE, 323 .misc_reg = PLLC2_MISC_0, 324 .iddq_reg = PLLC2_MISC_1, 325 .iddq_mask = 1 << PLLC_IDDQ_BIT, 326 .pdiv_table = qlin_map, 327 .mnp_bits = {8, 8, 5, 0, 10, 20}, 328 }, 329 /* PLLC3: 510 MHz Clock source for NVENC, NVDEC scaling */ 330 { 331 PLL(TEGRA210_CLK_PLL_C3, "pllC3_out0", "osc_div_clk"), 332 .type = PLL_C3, 333 .base_reg = PLLC3_BASE, 334 .misc_reg = PLLC3_MISC_0, 335 .lock_enable = PLL_MISC_LOCK_ENABLE, 336 .iddq_reg = PLLC3_MISC_1, 337 .iddq_mask = 1 << PLLC_IDDQ_BIT, 338 .mnp_bits = {8, 8, 5, 0, 10, 20}, 339 }, 340 /* PLLC4: 600 MHz Clock source for SD/eMMC ans system busses */ 341 { 342 PLL(TEGRA210_CLK_PLL_C4, "pllC4", "pllC4_src"), 343 .type = PLL_C4, 344 .flags = PLL_FLAG_VCO_OUT, 345 .base_reg = PLLC4_BASE, 346 .misc_reg = PLLC4_MISC, 347 .lock_enable = PLLC4_LOCK_ENABLE, 348 .iddq_reg = PLLC4_BASE, 349 .iddq_mask = 1 << PLLC4_IDDQ_BIT, 350 .pdiv_table = qlin_map, 351 .mnp_bits = {8, 8, 5, 0, 8, 19}, 352 }, 353 /* PLLP: 408 MHz Clock source for most peripherals */ 354 { 355 /* 356 * VCO is directly exposed as pllP_out0, P div is used for 357 * pllP_out2 358 */ 359 PLL(TEGRA210_CLK_PLL_P, "pllP_out0", "osc_div_clk"), 360 .type = PLL_P, 361 .flags = PLL_FLAG_VCO_OUT, 362 .base_reg = PLLP_BASE, 363 .misc_reg = PLLP_MISC, 364 .lock_enable = PLL_MISC_LOCK_ENABLE, 365 .iddq_reg = PLLP_MISC, 366 .iddq_mask = 1 << PLLA_IDDQ_BIT, 367 .mnp_bits = {8, 8, 5, 0, 10, 20}, 368 }, 369 /* PLLA: Audio clock for precise codec sampling */ 370 { 371 PLL(TEGRA210_CLK_PLL_A, "pllA", "osc_div_clk"), 372 .type = PLL_A, 373 .base_reg = PLLA_BASE, 374 .misc_reg = PLLA_MISC, 375 .lock_enable = PLLA_LOCK_ENABLE, 376 .iddq_reg = PLLA_BASE, 377 .iddq_mask = 1 << PLLA_IDDQ_BIT, 378 .pdiv_table = qlin_map, 379 .mnp_bits = {8, 8, 5, 0, 8, 20}, 380 }, 381 /* PLLA1: Audio clock for ADSP */ 382 { 383 PLL(TEGRA210_CLK_PLL_A1, "pllA1_out0", "osc_div_clk"), 384 .type = PLL_A1, 385 .base_reg = PLLA1_BASE, 386 .misc_reg = PLLA1_MISC_1, 387 .iddq_reg = PLLA1_MISC_1, 388 .iddq_mask = 1 << PLLA_IDDQ_BIT, 389 .pdiv_table = qlin_map, 390 .mnp_bits = {8, 8, 5, 0, 8, 20}, 391 }, 392 /* PLLU: 480 MHz Clock source for USB PHY, provides 12/60/480 MHz */ 393 { 394 PLL(TEGRA210_CLK_PLL_U, "pllU", "osc_div_clk"), 395 .type = PLL_U, 396 .flags = PLL_FLAG_VCO_OUT | PLL_FLAG_HAVE_SDA, 397 .base_reg = PLLU_BASE, 398 .misc_reg = PLLU_MISC, 399 .lock_enable = PLLU_LOCK_ENABLE, 400 .iddq_reg = PLLU_MISC, 401 .iddq_mask = 1 << PLLU_IDDQ_BIT, 402 .pdiv_table = qlin_map, 403 .mnp_bits = {8, 8, 5, 0, 8, 16}, 404 }, 405 /* PLLD: 594 MHz Clock sources for the DSI and display subsystem */ 406 { 407 PLL(TEGRA210_CLK_PLL_D, "pllD_out", "osc_div_clk"), 408 .type = PLL_D, 409 .flags = PLL_FLAG_PDIV_POWER2, 410 .base_reg = PLLD_BASE, 411 .misc_reg = PLLD_MISC, 412 .lock_enable = PLL_MISC_LOCK_ENABLE, 413 .iddq_reg = PLLA1_MISC_1, 414 .iddq_mask = 1 << PLLA_IDDQ_BIT, 415 .mnp_bits = {8, 8, 3, 0, 11, 20}, 416 }, 417 /* PLLD2: 594 MHz Clock sources for the DSI and display subsystem */ 418 { 419 PLL(TEGRA210_CLK_PLL_D2, "pllD2_out", "pllD2_src"), 420 .type = PLL_D2, 421 .flags = PLL_FLAG_HAVE_SDM, 422 .base_reg = PLLD2_BASE, 423 .misc_reg = PLLD2_MISC, 424 .lock_enable = PLLD2_LOCK_ENABLE, 425 .iddq_reg = PLLD2_BASE, 426 .iddq_mask = 1 << PLLD_IDDQ_BIT, 427 .pdiv_table = qlin_map, 428 .mnp_bits = {8, 8, 5, 0, 8, 19}, 429 }, 430 /* PLLREFE: 624 Mhz*/ 431 { 432 PLL(0, "pllREFE", "osc_div_clk"), 433 .type = PLL_REFE, 434 .flags = PLL_FLAG_VCO_OUT, 435 .base_reg = PLLREFE_BASE, 436 .misc_reg = PLLREFE_MISC, 437 .lock_enable = PLLREFE_LOCK_ENABLE, 438 .iddq_reg = PLLREFE_MISC, 439 .iddq_mask = 1 << PLLREFE_IDDQ_BIT, 440 .pdiv_table = qlin_map, 441 .mnp_bits = {8, 8, 5, 0, 8, 16}, 442 }, 443 /* PLLE: 100 MHz reference clock for PCIe/SATA/USB 3.0 (spread spectrum) */ 444 { 445 PLL(TEGRA210_CLK_PLL_E, "pllE_out0", "pllE_src"), 446 .type = PLL_E, 447 .base_reg = PLLE_BASE, 448 .misc_reg = PLLE_MISC, 449 .lock_enable = PLLE_LOCK_ENABLE, 450 .pdiv_table = qlin_map, 451 .mnp_bits = {8, 8, 5, 0, 8, 24}, 452 }, 453 /* PLLDP: 270 MHz Clock source fordisplay SOR (spread spectrum) */ 454 { 455 PLL(0, "pllDP_out0", "pllDP_src"), 456 .type = PLL_DP, 457 .flags = PLL_FLAG_HAVE_SDM, 458 .base_reg = PLLDP_BASE, 459 .misc_reg = PLLDP_MISC, 460 .lock_enable = PLLPD_LOCK_ENABLE, 461 .iddq_reg = PLLDP_BASE, 462 .iddq_mask = 1 << PLLDP_IDDQ_BIT, 463 .pdiv_table = qlin_map, 464 .mnp_bits = {8, 8, 5, 0, 8, 19}, 465 }, 466 }; 467 468 /* Fixed rate dividers. */ 469 static struct clk_fixed_def tegra210_pll_fdivs[] = { 470 FACT(0, "pllP_UD", "pllP_out0", 1, 1), 471 FACT(0, "pllC_UD", "pllC_out0", 1, 1), 472 FACT(0, "pllD_UD", "pllD_out0", 1, 1), 473 FACT(0, "pllM_UD", "pllM_out0", 1, 1), 474 FACT(0, "pllMB_UD", "pllMB_out0", 1, 1), 475 FACT(TEGRA210_CLK_PLL_D_OUT0, "pllD_out0", "pllD_out", 1, 2), 476 477 FACT(0, "pllC4_out1", "pllC4", 1, 3), 478 FACT(0, "pllC4_out2", "pllC4", 1, 5), 479 FACT(0, "pllD2_out0", "pllD2_out", 1, 2), 480 481 /* Aliases used in super mux. */ 482 FACT(0, "pllX_out0_alias", "pllX_out0", 1, 1), 483 FACT(0, "dfllCPU_out_alias", "dfllCPU_out", 1, 1), 484 }; 485 486 /* MUXes for PLL sources. */ 487 PLIST(mux_pll_srcs) = {"osc_div_clk", NULL, "pllP_out0", NULL}; /* FIXME */ 488 PLIST(mux_plle_src1) = {"osc_div_clk", "pllP_out0"}; 489 PLIST(mux_plle_src) = {"pllE_src1", "pllREFE_out0"}; 490 static struct clk_mux_def tegra210_pll_sources[] = { 491 /* Core clocks. */ 492 MUX(0, "pllD2_src", mux_pll_srcs, PLLD2_BASE, 25, 2), 493 MUX(0, "pllDP_src", mux_pll_srcs, PLLDP_BASE, 25, 2), 494 MUX(0, "pllC4_src", mux_pll_srcs, PLLC4_BASE, 25, 2), 495 MUX(0, "pllE_src1", mux_plle_src1, PLLE_AUX, 2, 1), 496 MUX(0, "pllE_src", mux_plle_src, PLLE_AUX, 28, 1), 497 }; 498 499 /* Gates for PLL branches. */ 500 static struct clk_gate_def tegra210_pll_gates[] = { 501 /* Core clocks. */ 502 GATE_PLL(0, "pllC_out1", "pllC_out1_div", PLLC_OUT, 0), 503 504 GATE_PLL(0, "pllP_out1", "pllP_out1_div", PLLP_OUTA, 0), 505 GATE_PLL(0, "pllP_out3", "pllP_out3_div", PLLP_OUTB, 0), 506 GATE_PLL(TEGRA210_CLK_PLL_P_OUT4, "pllP_out4", "pllP_out4_div", PLLP_OUTB, 16), 507 GATE_PLL(0, "pllP_out5", "pllP_out5_div", PLLP_OUTC, 16), 508 509 GATE_PLL(0, "pllU_out1", "pllU_out1_div", PLLU_OUTA, 0), 510 GATE_PLL(0, "pllU_out2", "pllU_out2_div", PLLU_OUTA, 16), 511 GATE(0, "pllU_480", "pllU", PLLU_BASE, 22), 512 GATE(0, "pllU_60", "pllU_out2", PLLU_BASE, 23), 513 GATE(0, "pllU_48", "pllU_out1", PLLU_BASE, 25), 514 515 GATE_PLL(0, "pllREFE_out1", "pllREFE_out1_div", PLLREFE_OUT, 0), 516 GATE_PLL(0, "pllC4_out3", "pllC4_out3_div", PLLC4_OUT, 0), 517 518 GATE_PLL(0, "pllA_out0", "pllA_out0_div", PLLA_OUT, 0), 519 }; 520 521 struct clk_div_table tegra210_pll_pdiv_tbl[] = { 522 /* value , divider */ 523 { 0, 1 }, 524 { 1, 2 }, 525 { 2, 3 }, 526 { 3, 4 }, 527 { 4, 5 }, 528 { 5, 6 }, 529 { 6, 8 }, 530 { 7, 10 }, 531 { 8, 12 }, 532 { 9, 16 }, 533 {10, 12 }, 534 {11, 16 }, 535 {12, 20 }, 536 {13, 24 }, 537 {14, 32 }, 538 { 0, 0 }, 539 }; 540 541 /* Dividers for PLL branches. */ 542 static struct clk_div_def tegra210_pll_divs[] = { 543 /* Core clocks. */ 544 DIV7_1(0, "pllC_out1_div", "pllC_out0", PLLC_OUT, 8), 545 546 DIV7_1(0, "pllP_out1_div", "pllP_out0", PLLP_OUTA, 8), 547 DIV_TB(0, "pllP_out2", "pllP_out0", PLLP_BASE, 20, 5, tegra210_pll_pdiv_tbl), 548 DIV7_1(0, "pllP_out3_div", "pllP_out0", PLLP_OUTB, 8), 549 DIV7_1(0, "pllP_out4_div", "pllP_out0", PLLP_OUTB, 24), 550 DIV7_1(0, "pllP_out5_div", "pllP_out0", PLLP_OUTC, 24), 551 552 DIV_TB(0, "pllU_out0", "pllU", PLLU_BASE, 16, 5, tegra210_pll_pdiv_tbl), 553 DIV7_1(0, "pllU_out1_div", "pllU_out0", PLLU_OUTA, 8), 554 DIV7_1(0, "pllU_out2_div", "pllU_out0", PLLU_OUTA, 24), 555 556 DIV_TB(0, "pllREFE_out0", "pllREFE", PLLREFE_BASE, 16, 5, tegra210_pll_pdiv_tbl), 557 DIV7_1(0, "pllREFE_out1_div", "pllREFE", PLLREFE_OUT, 8), 558 559 DIV_TB(TEGRA210_CLK_PLL_C4_OUT0, 560 "pllC4_out0", "pllC4", PLLC4_BASE, 19, 5, tegra210_pll_pdiv_tbl), 561 DIV7_1(0, "pllC4_out3_div", "pllC4_out0", PLLC4_OUT, 8), 562 563 DIV7_1(0, "pllA_out0_div", "pllA", PLLA_OUT, 8), 564 565 }; 566 567 static int tegra210_pll_init(struct clknode *clk, device_t dev); 568 static int tegra210_pll_set_gate(struct clknode *clk, bool enable); 569 static int tegra210_pll_get_gate(struct clknode *clk, bool *enabled); 570 static int tegra210_pll_recalc(struct clknode *clk, uint64_t *freq); 571 static int tegra210_pll_set_freq(struct clknode *clknode, uint64_t fin, 572 uint64_t *fout, int flags, int *stop); 573 struct pll_sc { 574 device_t clkdev; 575 enum pll_type type; 576 uint32_t base_reg; 577 uint32_t misc_reg; 578 uint32_t lock_enable; 579 uint32_t iddq_reg; 580 uint32_t iddq_mask; 581 uint32_t flags; 582 struct pdiv_table *pdiv_table; 583 struct mnp_bits mnp_bits; 584 }; 585 586 static clknode_method_t tegra210_pll_methods[] = { 587 /* Device interface */ 588 CLKNODEMETHOD(clknode_init, tegra210_pll_init), 589 CLKNODEMETHOD(clknode_set_gate, tegra210_pll_set_gate), 590 CLKNODEMETHOD(clknode_get_gate, tegra210_pll_get_gate), 591 CLKNODEMETHOD(clknode_recalc_freq, tegra210_pll_recalc), 592 CLKNODEMETHOD(clknode_set_freq, tegra210_pll_set_freq), 593 CLKNODEMETHOD_END 594 }; 595 DEFINE_CLASS_1(tegra210_pll, tegra210_pll_class, tegra210_pll_methods, 596 sizeof(struct pll_sc), clknode_class); 597 598 static int 599 pll_enable(struct pll_sc *sc) 600 { 601 uint32_t reg; 602 603 604 RD4(sc, sc->base_reg, ®); 605 if (sc->type != PLL_E) 606 reg &= ~PLL_BASE_BYPASS; 607 reg |= PLL_BASE_ENABLE; 608 WR4(sc, sc->base_reg, reg); 609 return (0); 610 } 611 612 static int 613 pll_disable(struct pll_sc *sc) 614 { 615 uint32_t reg; 616 617 RD4(sc, sc->base_reg, ®); 618 if (sc->type != PLL_E) 619 reg |= PLL_BASE_BYPASS; 620 reg &= ~PLL_BASE_ENABLE; 621 WR4(sc, sc->base_reg, reg); 622 return (0); 623 } 624 625 static uint32_t 626 pdiv_to_reg(struct pll_sc *sc, uint32_t p_div) 627 { 628 struct pdiv_table *tbl; 629 630 tbl = sc->pdiv_table; 631 if (tbl == NULL) { 632 if (sc->flags & PLL_FLAG_PDIV_POWER2) 633 return (ffs(p_div) - 1); 634 else 635 return (p_div); 636 } 637 638 while (tbl->divider != 0) { 639 if (p_div <= tbl->divider) 640 return (tbl->value); 641 tbl++; 642 } 643 return (0xFFFFFFFF); 644 } 645 646 static uint32_t 647 reg_to_pdiv(struct pll_sc *sc, uint32_t reg) 648 { 649 struct pdiv_table *tbl; 650 651 tbl = sc->pdiv_table; 652 if (tbl == NULL) { 653 if (sc->flags & PLL_FLAG_PDIV_POWER2) 654 return (1 << reg); 655 else 656 return (reg == 0 ? 1: reg); 657 } 658 while (tbl->divider) { 659 if (reg == tbl->value) 660 return (tbl->divider); 661 tbl++; 662 } 663 return (0); 664 } 665 666 static uint32_t 667 get_masked(uint32_t val, uint32_t shift, uint32_t width) 668 { 669 670 return ((val >> shift) & ((1 << width) - 1)); 671 } 672 673 static uint32_t 674 set_masked(uint32_t val, uint32_t v, uint32_t shift, uint32_t width) 675 { 676 677 val &= ~(((1 << width) - 1) << shift); 678 val |= (v & ((1 << width) - 1)) << shift; 679 return (val); 680 } 681 682 static void 683 get_divisors(struct pll_sc *sc, uint32_t *m, uint32_t *n, uint32_t *p) 684 { 685 uint32_t val; 686 struct mnp_bits *mnp_bits; 687 688 mnp_bits = &sc->mnp_bits; 689 RD4(sc, sc->base_reg, &val); 690 *m = get_masked(val, mnp_bits->m_shift, mnp_bits->m_width); 691 *n = get_masked(val, mnp_bits->n_shift, mnp_bits->n_width); 692 *p = get_masked(val, mnp_bits->p_shift, mnp_bits->p_width); 693 } 694 695 static uint32_t 696 set_divisors(struct pll_sc *sc, uint32_t val, uint32_t m, uint32_t n, 697 uint32_t p) 698 { 699 struct mnp_bits *mnp_bits; 700 701 mnp_bits = &sc->mnp_bits; 702 val = set_masked(val, m, mnp_bits->m_shift, mnp_bits->m_width); 703 val = set_masked(val, n, mnp_bits->n_shift, mnp_bits->n_width); 704 val = set_masked(val, p, mnp_bits->p_shift, mnp_bits->p_width); 705 return (val); 706 } 707 708 static bool 709 is_locked(struct pll_sc *sc) 710 { 711 uint32_t reg; 712 713 switch (sc->type) { 714 case PLL_REFE: 715 RD4(sc, sc->misc_reg, ®); 716 reg &= PLLREFE_MISC_LOCK; 717 break; 718 719 case PLL_E: 720 RD4(sc, sc->misc_reg, ®); 721 reg &= PLLE_MISC_LOCK; 722 break; 723 724 default: 725 RD4(sc, sc->base_reg, ®); 726 reg &= PLL_BASE_LOCK; 727 break; 728 } 729 return (reg != 0); 730 } 731 732 static int 733 wait_for_lock(struct pll_sc *sc) 734 { 735 int i; 736 737 for (i = PLL_LOCK_TIMEOUT / 10; i > 0; i--) { 738 if (is_locked(sc)) 739 break; 740 DELAY(10); 741 } 742 if (i <= 0) { 743 printf("PLL lock timeout\n"); 744 return (ETIMEDOUT); 745 } 746 return (0); 747 } 748 749 static int 750 plle_enable(struct pll_sc *sc) 751 { 752 uint32_t reg; 753 int rv; 754 uint32_t pll_m = 2; 755 uint32_t pll_n = 125; 756 uint32_t pll_cml = 14; 757 758 /* Disable lock override. */ 759 RD4(sc, sc->base_reg, ®); 760 reg &= ~PLLE_BASE_LOCK_OVERRIDE; 761 WR4(sc, sc->base_reg, reg); 762 763 /* Enable SW control */ 764 RD4(sc, PLLE_AUX, ®); 765 reg |= PLLE_AUX_ENABLE_SWCTL; 766 reg &= ~PLLE_AUX_SEQ_ENABLE; 767 WR4(sc, PLLE_AUX, reg); 768 DELAY(10); 769 770 RD4(sc, sc->misc_reg, ®); 771 reg |= PLLE_MISC_LOCK_ENABLE; 772 reg |= PLLE_MISC_IDDQ_SWCTL; 773 reg &= ~PLLE_MISC_IDDQ_OVERRIDE_VALUE; 774 reg |= PLLE_MISC_PTS; 775 reg &= ~PLLE_MISC_VREG_BG_CTRL(~0); 776 reg &= ~PLLE_MISC_VREG_CTRL(~0); 777 WR4(sc, sc->misc_reg, reg); 778 DELAY(10); 779 780 RD4(sc, PLLE_SS_CNTL, ®); 781 reg |= PLLE_SS_CNTL_DISABLE; 782 WR4(sc, PLLE_SS_CNTL, reg); 783 784 RD4(sc, sc->base_reg, ®); 785 reg = set_divisors(sc, reg, pll_m, pll_n, pll_cml); 786 WR4(sc, sc->base_reg, reg); 787 DELAY(10); 788 789 pll_enable(sc); 790 rv = wait_for_lock(sc); 791 if (rv != 0) 792 return (rv); 793 794 RD4(sc, PLLE_SS_CNTL, ®); 795 reg &= ~PLLE_SS_CNTL_SSCINCINTRV(~0); 796 reg &= ~PLLE_SS_CNTL_SSCINC(~0); 797 reg &= ~PLLE_SS_CNTL_SSCINVERT; 798 reg &= ~PLLE_SS_CNTL_SSCCENTER; 799 reg &= ~PLLE_SS_CNTL_SSCMAX(~0); 800 reg |= PLLE_SS_CNTL_SSCINCINTRV(0x23); 801 reg |= PLLE_SS_CNTL_SSCINC(0x1); 802 reg |= PLLE_SS_CNTL_SSCMAX(0x21); 803 WR4(sc, PLLE_SS_CNTL, reg); 804 reg &= ~PLLE_SS_CNTL_SSCBYP; 805 reg &= ~PLLE_SS_CNTL_BYPASS_SS; 806 WR4(sc, PLLE_SS_CNTL, reg); 807 DELAY(10); 808 809 reg &= ~PLLE_SS_CNTL_INTERP_RESET; 810 WR4(sc, PLLE_SS_CNTL, reg); 811 DELAY(10); 812 813 /* HW control of brick pll. */ 814 RD4(sc, sc->misc_reg, ®); 815 reg &= ~PLLE_MISC_IDDQ_SWCTL; 816 WR4(sc, sc->misc_reg, reg); 817 818 RD4(sc, PLLE_AUX, ®); 819 reg |= PLLE_AUX_USE_LOCKDET; 820 reg |= PLLE_AUX_SS_SEQ_INCLUDE; 821 reg &= ~PLLE_AUX_ENABLE_SWCTL; 822 reg &= ~PLLE_AUX_SS_SWCTL; 823 WR4(sc, PLLE_AUX, reg); 824 reg |= PLLE_AUX_SEQ_START_STATE; 825 DELAY(10); 826 reg |= PLLE_AUX_SEQ_ENABLE; 827 WR4(sc, PLLE_AUX, reg); 828 829 /* Enable and start XUSBIO PLL HW control*/ 830 RD4(sc, XUSBIO_PLL_CFG0, ®); 831 reg &= ~XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL; 832 reg &= ~XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL; 833 reg |= XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET; 834 reg |= XUSBIO_PLL_CFG0_PADPLL_SLEEP_IDDQ; 835 reg &= ~XUSBIO_PLL_CFG0_SEQ_ENABLE; 836 WR4(sc, XUSBIO_PLL_CFG0, reg); 837 DELAY(10); 838 839 reg |= XUSBIO_PLL_CFG0_SEQ_ENABLE; 840 WR4(sc, XUSBIO_PLL_CFG0, reg); 841 842 843 /* Enable and start SATA PLL HW control */ 844 RD4(sc, SATA_PLL_CFG0, ®); 845 reg &= ~SATA_PLL_CFG0_PADPLL_RESET_SWCTL; 846 reg &= ~SATA_PLL_CFG0_PADPLL_RESET_OVERRIDE_VALUE; 847 reg |= SATA_PLL_CFG0_PADPLL_USE_LOCKDET; 848 reg |= SATA_PLL_CFG0_PADPLL_SLEEP_IDDQ; 849 reg &= ~SATA_PLL_CFG0_SEQ_IN_SWCTL; 850 reg &= ~SATA_PLL_CFG0_SEQ_RESET_INPUT_VALUE; 851 reg &= ~SATA_PLL_CFG0_SEQ_LANE_PD_INPUT_VALUE; 852 reg &= ~SATA_PLL_CFG0_SEQ_PADPLL_PD_INPUT_VALUE; 853 reg &= ~SATA_PLL_CFG0_SEQ_ENABLE; 854 WR4(sc, SATA_PLL_CFG0, reg); 855 DELAY(10); 856 reg |= SATA_PLL_CFG0_SEQ_ENABLE; 857 WR4(sc, SATA_PLL_CFG0, reg); 858 859 /* Enable HW control of PCIe PLL. */ 860 RD4(sc, PCIE_PLL_CFG, ®); 861 reg |= PCIE_PLL_CFG_SEQ_ENABLE; 862 WR4(sc, PCIE_PLL_CFG, reg); 863 864 return (0); 865 } 866 867 static int 868 tegra210_pll_set_gate(struct clknode *clknode, bool enable) 869 { 870 int rv; 871 struct pll_sc *sc; 872 873 sc = clknode_get_softc(clknode); 874 if (enable == 0) { 875 rv = pll_disable(sc); 876 return(rv); 877 } 878 879 if (sc->type == PLL_E) 880 rv = plle_enable(sc); 881 else 882 rv = pll_enable(sc); 883 return (rv); 884 } 885 886 static int 887 tegra210_pll_get_gate(struct clknode *clknode, bool *enabled) 888 { 889 uint32_t reg; 890 struct pll_sc *sc; 891 892 sc = clknode_get_softc(clknode); 893 RD4(sc, sc->base_reg, ®); 894 *enabled = reg & PLL_BASE_ENABLE ? true: false; 895 WR4(sc, sc->base_reg, reg); 896 return (0); 897 } 898 899 static int 900 pll_set_std(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags, 901 uint32_t m, uint32_t n, uint32_t p) 902 { 903 uint32_t reg; 904 struct mnp_bits *mnp_bits; 905 int rv; 906 907 mnp_bits = &sc->mnp_bits; 908 if (m >= (1 << mnp_bits->m_width)) 909 return (ERANGE); 910 if (n >= (1 << mnp_bits->n_width)) 911 return (ERANGE); 912 if (pdiv_to_reg(sc, p) >= (1 << mnp_bits->p_width)) 913 return (ERANGE); 914 915 if (flags & CLK_SET_DRYRUN) { 916 if (((flags & (CLK_SET_ROUND_UP | CLK_SET_ROUND_DOWN)) == 0) && 917 (*fout != (((fin / m) * n) /p))) 918 return (ERANGE); 919 920 *fout = ((fin / m) * n) /p; 921 922 return (0); 923 } 924 925 pll_disable(sc); 926 927 /* take pll out of IDDQ */ 928 if (sc->iddq_reg != 0) 929 MD4(sc, sc->iddq_reg, sc->iddq_mask, 0); 930 931 RD4(sc, sc->base_reg, ®); 932 reg = set_masked(reg, m, mnp_bits->m_shift, mnp_bits->m_width); 933 reg = set_masked(reg, n, mnp_bits->n_shift, mnp_bits->n_width); 934 reg = set_masked(reg, pdiv_to_reg(sc, p), mnp_bits->p_shift, 935 mnp_bits->p_width); 936 WR4(sc, sc->base_reg, reg); 937 938 /* Enable PLL. */ 939 RD4(sc, sc->base_reg, ®); 940 reg |= PLL_BASE_ENABLE; 941 WR4(sc, sc->base_reg, reg); 942 943 /* Enable lock detection. */ 944 RD4(sc, sc->misc_reg, ®); 945 reg |= sc->lock_enable; 946 WR4(sc, sc->misc_reg, reg); 947 948 rv = wait_for_lock(sc); 949 if (rv != 0) { 950 /* Disable PLL */ 951 RD4(sc, sc->base_reg, ®); 952 reg &= ~PLL_BASE_ENABLE; 953 WR4(sc, sc->base_reg, reg); 954 return (rv); 955 } 956 RD4(sc, sc->misc_reg, ®); 957 958 pll_enable(sc); 959 *fout = ((fin / m) * n) / p; 960 return 0; 961 } 962 963 static int 964 plla_set_freq(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags) 965 { 966 uint32_t m, n, p; 967 968 p = 1; 969 m = 3; 970 n = (*fout * p * m + fin / 2)/ fin; 971 dprintf("%s: m: %d, n: %d, p: %d\n", __func__, m, n, p); 972 return (pll_set_std(sc, fin, fout, flags, m, n, p)); 973 } 974 975 static int 976 pllc_set_freq(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags) 977 { 978 uint32_t m, n, p; 979 980 p = 2; 981 m = 3; 982 n = (*fout * p * m + fin / 2)/ fin; 983 dprintf("%s: m: %d, n: %d, p: %d\n", __func__, m, n, p); 984 return (pll_set_std( sc, fin, fout, flags, m, n, p)); 985 } 986 987 static int 988 pllc4_set_freq(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags) 989 { 990 uint32_t m, n, p; 991 992 p = 1; 993 m = 4; 994 n = (*fout * p * m + fin / 2)/ fin; 995 dprintf("%s: m: %d, n: %d, p: %d\n", __func__, m, n, p); 996 return (pll_set_std( sc, fin, fout, flags, m, n, p)); 997 } 998 999 static int 1000 plldp_set_freq(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags) 1001 { 1002 uint32_t m, n, p; 1003 1004 p = 1; 1005 m = 4; 1006 n = (*fout * p * m + fin / 2)/ fin; 1007 dprintf("%s: m: %d, n: %d, p: %d\n", __func__, m, n, p); 1008 return (pll_set_std( sc, fin, fout, flags, m, n, p)); 1009 } 1010 1011 1012 /* 1013 * PLLD2 is used as source for pixel clock for HDMI. 1014 * We must be able to set it frequency very flexibly and 1015 * precisely (within 5% tolerance limit allowed by HDMI specs). 1016 * 1017 * For this reason, it is necessary to search the full state space. 1018 * Fortunately, thanks to early cycle terminations, performance 1019 * is within acceptable limits. 1020 */ 1021 #define PLLD2_PFD_MIN 12000000 /* 12 MHz */ 1022 #define PLLD2_PFD_MAX 38400000 /* 38.4 MHz */ 1023 #define PLLD2_VCO_MIN 750000000 /* 750 MHz */ 1024 #define PLLD2_VCO_MAX 1500000000 /* 1.5 GHz */ 1025 1026 static int 1027 plld2_set_freq(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags) 1028 { 1029 uint32_t m, n, p; 1030 uint32_t best_m, best_n, best_p; 1031 uint64_t vco, pfd; 1032 int64_t err, best_err; 1033 struct mnp_bits *mnp_bits; 1034 struct pdiv_table *tbl; 1035 int p_idx, rv; 1036 1037 mnp_bits = &sc->mnp_bits; 1038 tbl = sc->pdiv_table; 1039 best_err = INT64_MAX; 1040 1041 for (p_idx = 0; tbl[p_idx].divider != 0; p_idx++) { 1042 p = tbl[p_idx].divider; 1043 1044 /* Check constraints */ 1045 vco = *fout * p; 1046 if (vco < PLLD2_VCO_MIN) 1047 continue; 1048 if (vco > PLLD2_VCO_MAX) 1049 break; 1050 1051 for (m = 1; m < (1 << mnp_bits->m_width); m++) { 1052 n = (*fout * p * m + fin / 2) / fin; 1053 1054 /* Check constraints */ 1055 if (n == 0) 1056 continue; 1057 if (n >= (1 << mnp_bits->n_width)) 1058 break; 1059 vco = (fin * n) / m; 1060 if (vco > PLLD2_VCO_MAX || vco < PLLD2_VCO_MIN) 1061 continue; 1062 pfd = fin / m; 1063 if (pfd > PLLD2_PFD_MAX || vco < PLLD2_PFD_MIN) 1064 continue; 1065 1066 /* Constraints passed, save best result */ 1067 err = *fout - vco / p; 1068 if (err < 0) 1069 err = -err; 1070 if (err < best_err) { 1071 best_err = err; 1072 best_p = p; 1073 best_m = m; 1074 best_n = n; 1075 } 1076 if (err == 0) 1077 goto done; 1078 } 1079 } 1080 done: 1081 /* 1082 * HDMI specification allows 5% pixel clock tolerance, 1083 * we will by a slightly stricter 1084 */ 1085 if (best_err > ((*fout * 100) / 4)) 1086 return (ERANGE); 1087 1088 if (flags & CLK_SET_DRYRUN) 1089 return (0); 1090 rv = pll_set_std(sc, fin, fout, flags, best_m, best_n, best_p); 1091 /* XXXX Panic for rv == ERANGE ? */ 1092 return (rv); 1093 } 1094 1095 static int 1096 pllrefe_set_freq(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags) 1097 { 1098 uint32_t m, n, p; 1099 1100 m = 1; 1101 p = 1; 1102 n = *fout * p * m / fin; 1103 dprintf("%s: m: %d, n: %d, p: %d\n", __func__, m, n, p); 1104 return (pll_set_std(sc, fin, fout, flags, m, n, p)); 1105 } 1106 1107 #define PLLX_PFD_MIN 12000000LL /* 12 MHz */ 1108 #define PLLX_PFD_MAX 38400000LL /* 38.4 MHz */ 1109 #define PLLX_VCO_MIN 900000000LL /* 0.9 GHz */ 1110 #define PLLX_VCO_MAX 3000000000LL /* 3 GHz */ 1111 1112 static int 1113 pllx_set_freq(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags) 1114 { 1115 struct mnp_bits *mnp_bits; 1116 uint32_t m, n, p; 1117 uint32_t old_m, old_n, old_p; 1118 uint32_t reg; 1119 int i, rv; 1120 1121 mnp_bits = &sc->mnp_bits; 1122 1123 get_divisors(sc, &old_m, &old_n, &old_p); 1124 old_p = reg_to_pdiv(sc, old_p); 1125 1126 /* Pre-divider is fixed, Compute post-divider */ 1127 m = old_m; 1128 p = 1; 1129 while ((*fout * p) < PLLX_VCO_MIN) 1130 p++; 1131 if ((*fout * p) > PLLX_VCO_MAX) 1132 return (ERANGE); 1133 1134 n = (*fout * p * m + fin / 2) / fin; 1135 dprintf("%s: m: %d, n: %d, p: %d\n", __func__, m, n, p); 1136 1137 if (m >= (1 << mnp_bits->m_width)) 1138 return (ERANGE); 1139 if (n >= (1 << mnp_bits->n_width)) 1140 return (ERANGE); 1141 if (pdiv_to_reg(sc, p) >= (1 << mnp_bits->p_width)) 1142 return (ERANGE); 1143 1144 if (flags & CLK_SET_DRYRUN) { 1145 if (((flags & (CLK_SET_ROUND_UP | CLK_SET_ROUND_DOWN)) == 0) && 1146 (*fout != (((fin / m) * n) /p))) 1147 return (ERANGE); 1148 *fout = ((fin / m) * n) /p; 1149 return (0); 1150 } 1151 1152 /* If new post-divider is bigger that original, set it now. */ 1153 if (p < old_p) { 1154 RD4(sc, sc->base_reg, ®); 1155 reg = set_masked(reg, pdiv_to_reg(sc, p), mnp_bits->p_shift, 1156 mnp_bits->p_width); 1157 WR4(sc, sc->base_reg, reg); 1158 } 1159 DELAY(100); 1160 1161 /* vvv Program dynamic VCO ramp. vvv */ 1162 /* 1 - disable dynamic ramp mode. */ 1163 RD4(sc, PLLX_MISC_2, ®); 1164 reg &= ~PLLX_MISC_2_EN_DYNRAMP; 1165 WR4(sc, PLLX_MISC_2, reg); 1166 1167 /* 2 - Setup new ndiv. */ 1168 RD4(sc, PLLX_MISC_2, ®); 1169 reg &= ~PLLX_MISC_2_NDIV_NEW(~0); 1170 reg |= PLLX_MISC_2_NDIV_NEW(n); 1171 WR4(sc, PLLX_MISC_2, reg); 1172 1173 /* 3 - enable dynamic ramp. */ 1174 RD4(sc, PLLX_MISC_2, ®); 1175 reg |= PLLX_MISC_2_EN_DYNRAMP; 1176 WR4(sc, PLLX_MISC_2, reg); 1177 1178 /* 4 - wait for done. */ 1179 for (i = PLL_LOCK_TIMEOUT / 10; i > 0; i--) { 1180 RD4(sc, PLLX_MISC_2, ®); 1181 if (reg & PLLX_MISC_2_DYNRAMP_DONE) 1182 break; 1183 DELAY(10); 1184 } 1185 if (i <= 0) { 1186 printf("PLL X dynamic ramp timedout\n"); 1187 return (ETIMEDOUT); 1188 } 1189 1190 /* 5 - copy new ndiv to base register. */ 1191 RD4(sc, sc->base_reg, ®); 1192 reg = set_masked(reg, n, mnp_bits->n_shift, 1193 mnp_bits->n_width); 1194 WR4(sc, sc->base_reg, reg); 1195 1196 /* 6 - disable dynamic ramp mode. */ 1197 RD4(sc, PLLX_MISC_2, ®); 1198 reg &= ~PLLX_MISC_2_EN_DYNRAMP; 1199 WR4(sc, PLLX_MISC_2, reg); 1200 1201 rv = wait_for_lock(sc); 1202 if (rv != 0) { 1203 printf("PLL X is not locked !!\n"); 1204 } 1205 /* ^^^ Dynamic ramp done. ^^^ */ 1206 1207 /* If new post-divider is smaller that original, set it. */ 1208 if (p > old_p) { 1209 RD4(sc, sc->base_reg, ®); 1210 reg = set_masked(reg, pdiv_to_reg(sc, p), mnp_bits->p_shift, 1211 mnp_bits->p_width); 1212 WR4(sc, sc->base_reg, reg); 1213 } 1214 1215 *fout = ((fin / m) * n) / p; 1216 return (0); 1217 } 1218 1219 /* Simplified setup for 38.4 MHz clock. */ 1220 #define PLLX_STEP_A 0x04 1221 #define PLLX_STEP_B 0x05 1222 static int 1223 pllx_init(struct pll_sc *sc) 1224 { 1225 uint32_t reg; 1226 1227 RD4(sc, PLLX_MISC, ®); 1228 reg = PLLX_MISC_LOCK_ENABLE; 1229 WR4(sc, PLLX_MISC, reg); 1230 1231 /* Setup dynamic ramp. */ 1232 reg = 0; 1233 reg |= PLLX_MISC_2_DYNRAMP_STEPA(PLLX_STEP_A); 1234 reg |= PLLX_MISC_2_DYNRAMP_STEPB(PLLX_STEP_B); 1235 WR4(sc, PLLX_MISC_2, reg); 1236 1237 /* Disable SDM. */ 1238 reg = 0; 1239 WR4(sc, PLLX_MISC_4, reg); 1240 WR4(sc, PLLX_MISC_5, reg); 1241 1242 return (0); 1243 } 1244 1245 static int 1246 tegra210_pll_set_freq(struct clknode *clknode, uint64_t fin, uint64_t *fout, 1247 int flags, int *stop) 1248 { 1249 *stop = 1; 1250 int rv; 1251 struct pll_sc *sc; 1252 1253 sc = clknode_get_softc(clknode); 1254 dprintf("%s: %s requested freq: %lu, input freq: %lu\n", __func__, 1255 clknode_get_name(clknode), *fout, fin); 1256 switch (sc->type) { 1257 case PLL_A: 1258 rv = plla_set_freq(sc, fin, fout, flags); 1259 break; 1260 1261 case PLL_C: 1262 case PLL_C2: 1263 case PLL_C3: 1264 rv = pllc_set_freq(sc, fin, fout, flags); 1265 break; 1266 1267 case PLL_C4: 1268 rv = pllc4_set_freq(sc, fin, fout, flags); 1269 break; 1270 1271 case PLL_D2: 1272 rv = plld2_set_freq(sc, fin, fout, flags); 1273 break; 1274 1275 case PLL_DP: 1276 rv = plldp_set_freq(sc, fin, fout, flags); 1277 break; 1278 1279 case PLL_REFE: 1280 rv = pllrefe_set_freq(sc, fin, fout, flags); 1281 break; 1282 1283 case PLL_X: 1284 rv = pllx_set_freq(sc, fin, fout, flags); 1285 break; 1286 1287 case PLL_U: 1288 if (*fout == 480000000) /* PLLU is fixed to 480 MHz */ 1289 rv = 0; 1290 else 1291 rv = ERANGE; 1292 break; 1293 default: 1294 rv = ENXIO; 1295 break; 1296 } 1297 1298 return (rv); 1299 } 1300 1301 1302 static int 1303 tegra210_pll_init(struct clknode *clk, device_t dev) 1304 { 1305 struct pll_sc *sc; 1306 uint32_t reg, rv; 1307 1308 sc = clknode_get_softc(clk); 1309 1310 if (sc->type == PLL_X) { 1311 rv = pllx_init(sc); 1312 if (rv != 0) 1313 return (rv); 1314 } 1315 1316 /* If PLL is enabled, enable lock detect too. */ 1317 RD4(sc, sc->base_reg, ®); 1318 if (reg & PLL_BASE_ENABLE) { 1319 RD4(sc, sc->misc_reg, ®); 1320 reg |= sc->lock_enable; 1321 WR4(sc, sc->misc_reg, reg); 1322 } 1323 if (sc->type == PLL_REFE) { 1324 RD4(sc, sc->misc_reg, ®); 1325 reg &= ~(1 << 29); /* Disable lock override */ 1326 WR4(sc, sc->misc_reg, reg); 1327 } 1328 clknode_init_parent_idx(clk, 0); 1329 return(0); 1330 } 1331 1332 static int 1333 tegra210_pll_recalc(struct clknode *clk, uint64_t *freq) 1334 { 1335 struct pll_sc *sc; 1336 uint32_t m, n, p, pr; 1337 uint32_t reg, misc_reg; 1338 int locked; 1339 1340 sc = clknode_get_softc(clk); 1341 1342 RD4(sc, sc->base_reg, ®); 1343 RD4(sc, sc->misc_reg, &misc_reg); 1344 1345 get_divisors(sc, &m, &n, &pr); 1346 1347 /* If VCO is directlu exposed, P divider is handled by external node */ 1348 if (sc->flags & PLL_FLAG_VCO_OUT) 1349 p = 1; 1350 else 1351 p = reg_to_pdiv(sc, pr); 1352 1353 locked = is_locked(sc); 1354 1355 dprintf("%s: %s (0x%08x, 0x%08x) - m: %d, n: %d, p: %d (%d): " 1356 "e: %d, r: %d, o: %d - %s\n", __func__, 1357 clknode_get_name(clk), reg, misc_reg, m, n, p, pr, 1358 (reg >> 30) & 1, (reg >> 29) & 1, (reg >> 28) & 1, 1359 locked ? "locked" : "unlocked"); 1360 1361 if ((m == 0) || (n == 0) || (p == 0)) { 1362 *freq = 0; 1363 return (EINVAL); 1364 } 1365 if (!locked) { 1366 *freq = 0; 1367 return (0); 1368 } 1369 *freq = ((*freq / m) * n) / p; 1370 return (0); 1371 } 1372 1373 static int 1374 pll_register(struct clkdom *clkdom, struct clk_pll_def *clkdef) 1375 { 1376 struct clknode *clk; 1377 struct pll_sc *sc; 1378 1379 clk = clknode_create(clkdom, &tegra210_pll_class, &clkdef->clkdef); 1380 if (clk == NULL) 1381 return (ENXIO); 1382 1383 sc = clknode_get_softc(clk); 1384 sc->clkdev = clknode_get_device(clk); 1385 sc->type = clkdef->type; 1386 sc->base_reg = clkdef->base_reg; 1387 sc->misc_reg = clkdef->misc_reg; 1388 sc->lock_enable = clkdef->lock_enable; 1389 sc->iddq_reg = clkdef->iddq_reg; 1390 sc->iddq_mask = clkdef->iddq_mask; 1391 sc->flags = clkdef->flags; 1392 sc->pdiv_table = clkdef->pdiv_table; 1393 sc->mnp_bits = clkdef->mnp_bits; 1394 clknode_register(clkdom, clk); 1395 return (0); 1396 } 1397 1398 static void config_utmi_pll(struct tegra210_car_softc *sc) 1399 { 1400 uint32_t reg; 1401 /* 1402 * XXX Simplified UTMIP settings for 38.4MHz base clock. 1403 */ 1404 #define ENABLE_DELAY_COUNT 0x00 1405 #define STABLE_COUNT 0x00 1406 #define ACTIVE_DELAY_COUNT 0x06 1407 #define XTAL_FREQ_COUNT 0x80 1408 1409 CLKDEV_READ_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, ®); 1410 reg &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE; 1411 CLKDEV_WRITE_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, reg); 1412 1413 CLKDEV_READ_4(sc->dev, UTMIP_PLL_CFG2, ®); 1414 reg &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0); 1415 reg |= UTMIP_PLL_CFG2_STABLE_COUNT(STABLE_COUNT); 1416 reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0); 1417 reg |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(ACTIVE_DELAY_COUNT); 1418 CLKDEV_WRITE_4(sc->dev, UTMIP_PLL_CFG2, reg); 1419 1420 CLKDEV_READ_4(sc->dev, UTMIP_PLL_CFG1, ®); 1421 reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0); 1422 reg |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(ENABLE_DELAY_COUNT); 1423 reg &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0); 1424 reg |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(XTAL_FREQ_COUNT); 1425 reg |= UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP; 1426 CLKDEV_WRITE_4(sc->dev, UTMIP_PLL_CFG1, reg); 1427 1428 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN; 1429 reg |= UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP; 1430 CLKDEV_WRITE_4(sc->dev, UTMIP_PLL_CFG1, reg); 1431 DELAY(20); 1432 1433 /* Setup samplers. */ 1434 CLKDEV_READ_4(sc->dev, UTMIP_PLL_CFG2, ®); 1435 reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERUP; 1436 reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERUP; 1437 reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERUP; 1438 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN; 1439 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN; 1440 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERDOWN; 1441 CLKDEV_WRITE_4(sc->dev, UTMIP_PLL_CFG2, reg); 1442 1443 /* Powerup UTMIP. */ 1444 CLKDEV_READ_4(sc->dev, UTMIP_PLL_CFG1, ®); 1445 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP; 1446 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN; 1447 CLKDEV_WRITE_4(sc->dev, UTMIP_PLL_CFG1, reg); 1448 DELAY(10); 1449 1450 /* Prepare UTMIP sequencer. */ 1451 CLKDEV_READ_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, ®); 1452 reg |= UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET; 1453 reg &= ~UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL; 1454 CLKDEV_WRITE_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, reg); 1455 DELAY(10); 1456 1457 CLKDEV_READ_4(sc->dev, XUSB_PLL_CFG0, ®); 1458 reg &= ~XUSB_PLL_CFG0_UTMIPLL_LOCK_DLY; 1459 CLKDEV_WRITE_4(sc->dev, XUSB_PLL_CFG0, reg); 1460 DELAY(10); 1461 1462 /* HW control of UTMIPLL. */ 1463 CLKDEV_READ_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, ®); 1464 reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE; 1465 CLKDEV_WRITE_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, reg); 1466 } 1467 1468 void 1469 tegra210_init_plls(struct tegra210_car_softc *sc) 1470 { 1471 int i, rv; 1472 1473 for (i = 0; i < nitems(tegra210_pll_sources); i++) { 1474 rv = clknode_mux_register(sc->clkdom, tegra210_pll_sources + i); 1475 if (rv != 0) 1476 panic("clk_mux_register failed"); 1477 } 1478 1479 for (i = 0; i < nitems(pll_clks); i++) { 1480 rv = pll_register(sc->clkdom, pll_clks + i); 1481 if (rv != 0) 1482 panic("pll_register failed"); 1483 } 1484 1485 config_utmi_pll(sc); 1486 1487 for (i = 0; i < nitems(tegra210_pll_fdivs); i++) { 1488 rv = clknode_fixed_register(sc->clkdom, tegra210_pll_fdivs + i); 1489 if (rv != 0) 1490 panic("clk_fixed_register failed"); 1491 } 1492 1493 for (i = 0; i < nitems(tegra210_pll_gates); i++) { 1494 rv = clknode_gate_register(sc->clkdom, tegra210_pll_gates + i); 1495 if (rv != 0) 1496 panic("clk_gate_register failed"); 1497 } 1498 1499 for (i = 0; i < nitems(tegra210_pll_divs); i++) { 1500 rv = clknode_div_register(sc->clkdom, tegra210_pll_divs + i); 1501 if (rv != 0) 1502 panic("clk_div_register failed"); 1503 } 1504 } 1505