1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright 2020 Michal Meloun <mmel@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/bus.h> 34 #include <sys/lock.h> 35 #include <sys/mutex.h> 36 #include <sys/rman.h> 37 38 #include <machine/bus.h> 39 40 #include <dev/extres/clk/clk_div.h> 41 #include <dev/extres/clk/clk_fixed.h> 42 #include <dev/extres/clk/clk_gate.h> 43 #include <dev/extres/clk/clk_mux.h> 44 45 #include <dt-bindings/clock/tegra210-car.h> 46 #include "tegra210_car.h" 47 48 #if 0 49 #define dprintf(...) printf(__VA_ARGS__) 50 #else 51 #define dprintf(...) 52 #endif 53 54 /* All PLLs. */ 55 enum pll_type { 56 PLL_M, 57 PLL_MB, 58 PLL_X, 59 PLL_C, 60 PLL_C2, 61 PLL_C3, 62 PLL_C4, 63 PLL_P, 64 PLL_A, 65 PLL_A1, 66 PLL_U, 67 PLL_D, 68 PLL_D2, 69 PLL_DP, 70 PLL_E, 71 PLL_REFE}; 72 /* Flags for PLLs */ 73 74 #define PLL_FLAG_PDIV_POWER2 0x01 /* P Divider is 2^n */ 75 #define PLL_FLAG_VCO_OUT 0x02 /* Output VCO directly */ 76 #define PLL_FLAG_HAVE_SDM 0x04 /* Have SDM implemented */ 77 #define PLL_FLAG_HAVE_SDA 0x04 /* Have SDA implemented */ 78 79 /* Common base register bits. */ 80 #define PLL_BASE_BYPASS (1U << 31) 81 #define PLL_BASE_ENABLE (1 << 30) 82 #define PLL_BASE_REFDISABLE (1 << 29) 83 #define PLL_BASE_LOCK (1 << 27) 84 85 #define PLLREFE_MISC_LOCK (1 << 27) 86 87 #define PLL_MISC_LOCK_ENABLE (1 << 18) 88 #define PLLM_LOCK_ENABLE (1 << 4) 89 #define PLLMB_LOCK_ENABLE (1 << 16) 90 #define PLLC_LOCK_ENABLE (1 << 24) 91 #define PLLC4_LOCK_ENABLE (1 << 30) 92 #define PLLA_LOCK_ENABLE (1 << 28) 93 #define PLLD2_LOCK_ENABLE (1 << 30) 94 #define PLLU_LOCK_ENABLE (1 << 29) 95 #define PLLREFE_LOCK_ENABLE (1 << 30) 96 #define PLLPD_LOCK_ENABLE (1 << 30) 97 #define PLLE_LOCK_ENABLE (1 << 9) 98 99 #define PLLM_IDDQ_BIT 5 100 #define PLLMB_IDDQ_BIT 17 101 #define PLLC_IDDQ_BIT 27 102 #define PLLC4_IDDQ_BIT 18 103 #define PLLP_IDDQ_BIT 3 104 #define PLLA_IDDQ_BIT 25 105 #define PLLA1_IDDQ_BIT 27 106 #define PLLU_IDDQ_BIT 31 107 #define PLLD_IDDQ_BIT 20 108 #define PLLD2_IDDQ_BIT 18 109 #define PLLX_IDDQ_BIT 3 110 #define PLLREFE_IDDQ_BIT 24 111 #define PLLDP_IDDQ_BIT 18 112 113 114 #define PLL_LOCK_TIMEOUT 5000 115 116 /* Post divider <-> register value mapping. */ 117 struct pdiv_table { 118 uint32_t divider; /* real divider */ 119 uint32_t value; /* register value */ 120 }; 121 122 /* Bits definition of M, N and P fields. */ 123 struct mnp_bits { 124 uint32_t m_width; 125 uint32_t n_width; 126 uint32_t p_width; 127 uint32_t m_shift; 128 uint32_t n_shift; 129 uint32_t p_shift; 130 }; 131 132 struct clk_pll_def { 133 struct clknode_init_def clkdef; 134 enum pll_type type; 135 uint32_t base_reg; 136 uint32_t misc_reg; 137 uint32_t lock_enable; 138 uint32_t iddq_reg; 139 uint32_t iddq_mask; 140 uint32_t flags; 141 struct pdiv_table *pdiv_table; 142 struct mnp_bits mnp_bits; 143 }; 144 145 #define PLIST(x) static const char *x[] 146 147 #define PLL(_id, cname, pname) \ 148 .clkdef.id = _id, \ 149 .clkdef.name = cname, \ 150 .clkdef.parent_names = (const char *[]){pname}, \ 151 .clkdef.parent_cnt = 1, \ 152 .clkdef.flags = CLK_NODE_STATIC_STRINGS 153 154 /* multiplexer for pll sources. */ 155 #define MUX(_id, cname, plists, o, s, w) \ 156 { \ 157 .clkdef.id = _id, \ 158 .clkdef.name = cname, \ 159 .clkdef.parent_names = plists, \ 160 .clkdef.parent_cnt = nitems(plists), \ 161 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ 162 .offset = o, \ 163 .shift = s, \ 164 .width = w, \ 165 } 166 167 /* Fractional divider (7.1) for PLL branch. */ 168 #define DIV7_1(_id, cname, plist, o, s) \ 169 { \ 170 .clkdef.id = _id, \ 171 .clkdef.name = cname, \ 172 .clkdef.parent_names = (const char *[]){plist}, \ 173 .clkdef.parent_cnt = 1, \ 174 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ 175 .offset = o, \ 176 .i_shift = (s) + 1, \ 177 .i_width = 7, \ 178 .f_shift = s, \ 179 .f_width = 1, \ 180 } 181 182 /* P divider (2^n). for PLL branch. */ 183 #define DIV5_E(_id, cname, plist, o, s) \ 184 { \ 185 .clkdef.id = _id, \ 186 .clkdef.name = cname, \ 187 .clkdef.parent_names = (const char *[]){plist}, \ 188 .clkdef.parent_cnt = 1, \ 189 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ 190 .offset = o, \ 191 .i_shift = s, \ 192 .i_width = 5, \ 193 } 194 195 /* P divider (2^n). for PLL branch. */ 196 #define DIV_TB(_id, cname, plist, o, s, n, table) \ 197 { \ 198 .clkdef.id = _id, \ 199 .clkdef.name = cname, \ 200 .clkdef.parent_names = (const char *[]){plist}, \ 201 .clkdef.parent_cnt = 1, \ 202 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ 203 .div_flags = CLK_DIV_WITH_TABLE | CLK_DIV_ZERO_BASED, \ 204 .offset = o, \ 205 .i_shift = s, \ 206 .i_width = n, \ 207 .div_table = table, \ 208 } 209 210 /* Standard gate. */ 211 #define GATE(_id, cname, plist, o, s) \ 212 { \ 213 .clkdef.id = _id, \ 214 .clkdef.name = cname, \ 215 .clkdef.parent_names = (const char *[]){plist}, \ 216 .clkdef.parent_cnt = 1, \ 217 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ 218 .offset = o, \ 219 .shift = s, \ 220 .mask = 1, \ 221 .on_value = 1, \ 222 .off_value = 0, \ 223 } 224 /* Gate for PLL branch. */ 225 #define GATE_PLL(_id, cname, plist, o, s) \ 226 { \ 227 .clkdef.id = _id, \ 228 .clkdef.name = cname, \ 229 .clkdef.parent_names = (const char *[]){plist}, \ 230 .clkdef.parent_cnt = 1, \ 231 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ 232 .offset = o, \ 233 .shift = s, \ 234 .mask = 3, \ 235 .on_value = 3, \ 236 .off_value = 0, \ 237 } 238 239 /* Fixed rate multipier/divider. */ 240 #define FACT(_id, cname, pname, _mult, _div) \ 241 { \ 242 .clkdef.id = _id, \ 243 .clkdef.name = cname, \ 244 .clkdef.parent_names = (const char *[]){pname}, \ 245 .clkdef.parent_cnt = 1, \ 246 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ 247 .mult = _mult, \ 248 .div = _div, \ 249 } 250 251 static struct pdiv_table qlin_map[] = { 252 { 1, 0}, 253 { 2, 1}, 254 { 3, 2}, 255 { 4, 3}, 256 { 5, 4}, 257 { 6, 5}, 258 { 8, 6}, 259 { 9, 7}, 260 {10, 8}, 261 {12, 9}, 262 {15, 10}, 263 {16, 11}, 264 {18, 12}, 265 {20, 13}, 266 {24, 14}, 267 {30, 15}, 268 {32, 16}, 269 { 0, 0}, 270 }; 271 272 static struct clk_pll_def pll_clks[] = { 273 /* PLLM: 880 MHz Clock source for EMC 2x clock */ 274 { 275 PLL(TEGRA210_CLK_PLL_M, "pllM_out0", "osc"), 276 .type = PLL_M, 277 .base_reg = PLLM_BASE, 278 .misc_reg = PLLM_MISC2, 279 .lock_enable = PLLM_LOCK_ENABLE, 280 .iddq_reg = PLLM_MISC2, 281 .iddq_mask = 1 << PLLM_IDDQ_BIT, 282 .pdiv_table = qlin_map, 283 .mnp_bits = {8, 8, 5, 0, 8, 20}, 284 }, 285 /* PLLMB: 880 MHz Clock source for EMC 2x clock */ 286 { 287 PLL(TEGRA210_CLK_PLL_M, "pllMB_out0", "osc"), 288 .type = PLL_MB, 289 .base_reg = PLLMB_BASE, 290 .misc_reg = PLLMB_MISC1, 291 .lock_enable = PLLMB_LOCK_ENABLE, 292 .iddq_reg = PLLMB_MISC1, 293 .iddq_mask = 1 << PLLMB_IDDQ_BIT, 294 .pdiv_table = qlin_map, 295 .mnp_bits = {8, 8, 5, 0, 8, 20}, 296 }, 297 /* PLLX: 1GHz Clock source for the fast CPU cluster and the shadow CPU */ 298 { 299 PLL(TEGRA210_CLK_PLL_X, "pllX_out0", "osc_div_clk"), 300 .type = PLL_X, 301 .base_reg = PLLX_BASE, 302 .misc_reg = PLLX_MISC, 303 .lock_enable = PLL_MISC_LOCK_ENABLE, 304 .iddq_reg = PLLX_MISC_3, 305 .iddq_mask = 1 << PLLX_IDDQ_BIT, 306 .pdiv_table = qlin_map, 307 .mnp_bits = {8, 8, 5, 0, 8, 20}, 308 }, 309 /* PLLC: 510 MHz Clock source for camera use */ 310 { 311 PLL(TEGRA210_CLK_PLL_C, "pllC_out0", "osc_div_clk"), 312 .type = PLL_C, 313 .base_reg = PLLC_BASE, 314 .misc_reg = PLLC_MISC_0, 315 .iddq_reg = PLLC_MISC_1, 316 .iddq_mask = 1 << PLLC_IDDQ_BIT, 317 .pdiv_table = qlin_map, 318 .mnp_bits = {8, 8, 5, 0, 10, 20}, 319 }, 320 /* PLLC2: 510 MHz Clock source for SE, VIC, TSECB, NVJPG scaling */ 321 { 322 PLL(TEGRA210_CLK_PLL_C2, "pllC2_out0", "osc_div_clk"), 323 .type = PLL_C2, 324 .base_reg = PLLC2_BASE, 325 .misc_reg = PLLC2_MISC_0, 326 .iddq_reg = PLLC2_MISC_1, 327 .iddq_mask = 1 << PLLC_IDDQ_BIT, 328 .pdiv_table = qlin_map, 329 .mnp_bits = {8, 8, 5, 0, 10, 20}, 330 }, 331 /* PLLC3: 510 MHz Clock source for NVENC, NVDEC scaling */ 332 { 333 PLL(TEGRA210_CLK_PLL_C3, "pllC3_out0", "osc_div_clk"), 334 .type = PLL_C3, 335 .base_reg = PLLC3_BASE, 336 .misc_reg = PLLC3_MISC_0, 337 .lock_enable = PLL_MISC_LOCK_ENABLE, 338 .iddq_reg = PLLC3_MISC_1, 339 .iddq_mask = 1 << PLLC_IDDQ_BIT, 340 .mnp_bits = {8, 8, 5, 0, 10, 20}, 341 }, 342 /* PLLC4: 600 MHz Clock source for SD/eMMC ans system busses */ 343 { 344 PLL(TEGRA210_CLK_PLL_C4, "pllC4", "pllC4_src"), 345 .type = PLL_C4, 346 .flags = PLL_FLAG_VCO_OUT, 347 .base_reg = PLLC4_BASE, 348 .misc_reg = PLLC4_MISC, 349 .lock_enable = PLLC4_LOCK_ENABLE, 350 .iddq_reg = PLLC4_BASE, 351 .iddq_mask = 1 << PLLC4_IDDQ_BIT, 352 .pdiv_table = qlin_map, 353 .mnp_bits = {8, 8, 5, 0, 8, 19}, 354 }, 355 /* PLLP: 408 MHz Clock source for most peripherals */ 356 { 357 /* 358 * VCO is directly exposed as pllP_out0, P div is used for 359 * pllP_out2 360 */ 361 PLL(TEGRA210_CLK_PLL_P, "pllP_out0", "osc_div_clk"), 362 .type = PLL_P, 363 .flags = PLL_FLAG_VCO_OUT, 364 .base_reg = PLLP_BASE, 365 .misc_reg = PLLP_MISC, 366 .lock_enable = PLL_MISC_LOCK_ENABLE, 367 .iddq_reg = PLLP_MISC, 368 .iddq_mask = 1 << PLLA_IDDQ_BIT, 369 .mnp_bits = {8, 8, 5, 0, 10, 20}, 370 }, 371 /* PLLA: Audio clock for precise codec sampling */ 372 { 373 PLL(TEGRA210_CLK_PLL_A, "pllA", "osc_div_clk"), 374 .type = PLL_A, 375 .base_reg = PLLA_BASE, 376 .misc_reg = PLLA_MISC, 377 .lock_enable = PLLA_LOCK_ENABLE, 378 .iddq_reg = PLLA_BASE, 379 .iddq_mask = 1 << PLLA_IDDQ_BIT, 380 .pdiv_table = qlin_map, 381 .mnp_bits = {8, 8, 5, 0, 8, 20}, 382 }, 383 /* PLLA1: Audio clock for ADSP */ 384 { 385 PLL(TEGRA210_CLK_PLL_A1, "pllA1_out0", "osc_div_clk"), 386 .type = PLL_A1, 387 .base_reg = PLLA1_BASE, 388 .misc_reg = PLLA1_MISC_1, 389 .iddq_reg = PLLA1_MISC_1, 390 .iddq_mask = 1 << PLLA_IDDQ_BIT, 391 .pdiv_table = qlin_map, 392 .mnp_bits = {8, 8, 5, 0, 8, 20}, 393 }, 394 /* PLLU: 480 MHz Clock source for USB PHY, provides 12/60/480 MHz */ 395 { 396 PLL(TEGRA210_CLK_PLL_U, "pllU", "osc_div_clk"), 397 .type = PLL_U, 398 .flags = PLL_FLAG_VCO_OUT | PLL_FLAG_HAVE_SDA, 399 .base_reg = PLLU_BASE, 400 .misc_reg = PLLU_MISC, 401 .lock_enable = PLLU_LOCK_ENABLE, 402 .iddq_reg = PLLU_MISC, 403 .iddq_mask = 1 << PLLU_IDDQ_BIT, 404 .pdiv_table = qlin_map, 405 .mnp_bits = {8, 8, 5, 0, 8, 16}, 406 }, 407 /* PLLD: 594 MHz Clock sources for the DSI and display subsystem */ 408 { 409 PLL(TEGRA210_CLK_PLL_D, "pllD_out", "osc_div_clk"), 410 .type = PLL_D, 411 .flags = PLL_FLAG_PDIV_POWER2, 412 .base_reg = PLLD_BASE, 413 .misc_reg = PLLD_MISC, 414 .lock_enable = PLL_MISC_LOCK_ENABLE, 415 .iddq_reg = PLLA1_MISC_1, 416 .iddq_mask = 1 << PLLA_IDDQ_BIT, 417 .mnp_bits = {8, 8, 3, 0, 11, 20}, 418 }, 419 /* PLLD2: 594 MHz Clock sources for the DSI and display subsystem */ 420 { 421 PLL(TEGRA210_CLK_PLL_D2, "pllD2_out", "pllD2_src"), 422 .type = PLL_D2, 423 .flags = PLL_FLAG_HAVE_SDM, 424 .base_reg = PLLD2_BASE, 425 .misc_reg = PLLD2_MISC, 426 .lock_enable = PLLD2_LOCK_ENABLE, 427 .iddq_reg = PLLD2_BASE, 428 .iddq_mask = 1 << PLLD_IDDQ_BIT, 429 .pdiv_table = qlin_map, 430 .mnp_bits = {8, 8, 5, 0, 8, 19}, 431 }, 432 /* PLLREFE: 624 Mhz*/ 433 { 434 PLL(0, "pllREFE", "osc_div_clk"), 435 .type = PLL_REFE, 436 .flags = PLL_FLAG_VCO_OUT, 437 .base_reg = PLLREFE_BASE, 438 .misc_reg = PLLREFE_MISC, 439 .lock_enable = PLLREFE_LOCK_ENABLE, 440 .iddq_reg = PLLREFE_MISC, 441 .iddq_mask = 1 << PLLREFE_IDDQ_BIT, 442 .pdiv_table = qlin_map, 443 .mnp_bits = {8, 8, 5, 0, 8, 16}, 444 }, 445 /* PLLE: 100 MHz reference clock for PCIe/SATA/USB 3.0 (spread spectrum) */ 446 { 447 PLL(TEGRA210_CLK_PLL_E, "pllE_out0", "pllE_src"), 448 .type = PLL_E, 449 .base_reg = PLLE_BASE, 450 .misc_reg = PLLE_MISC, 451 .lock_enable = PLLE_LOCK_ENABLE, 452 .pdiv_table = qlin_map, 453 .mnp_bits = {8, 8, 5, 0, 8, 24}, 454 }, 455 /* PLLDP: 270 MHz Clock source fordisplay SOR (spread spectrum) */ 456 { 457 PLL(0, "pllDP_out0", "pllDP_src"), 458 .type = PLL_DP, 459 .flags = PLL_FLAG_HAVE_SDM, 460 .base_reg = PLLDP_BASE, 461 .misc_reg = PLLDP_MISC, 462 .lock_enable = PLLPD_LOCK_ENABLE, 463 .iddq_reg = PLLDP_BASE, 464 .iddq_mask = 1 << PLLDP_IDDQ_BIT, 465 .pdiv_table = qlin_map, 466 .mnp_bits = {8, 8, 5, 0, 8, 19}, 467 }, 468 }; 469 470 /* Fixed rate dividers. */ 471 static struct clk_fixed_def tegra210_pll_fdivs[] = { 472 FACT(0, "pllP_UD", "pllP_out0", 1, 1), 473 FACT(0, "pllC_UD", "pllC_out0", 1, 1), 474 FACT(0, "pllD_UD", "pllD_out0", 1, 1), 475 FACT(0, "pllM_UD", "pllM_out0", 1, 1), 476 FACT(0, "pllMB_UD", "pllMB_out0", 1, 1), 477 FACT(TEGRA210_CLK_PLL_D_OUT0, "pllD_out0", "pllD_out", 1, 2), 478 479 FACT(0, "pllC4_out1", "pllC4", 1, 3), 480 FACT(0, "pllC4_out2", "pllC4", 1, 5), 481 FACT(0, "pllD2_out0", "pllD2_out", 1, 2), 482 483 /* Aliases used in super mux. */ 484 FACT(0, "pllX_out0_alias", "pllX_out0", 1, 1), 485 FACT(0, "dfllCPU_out_alias", "dfllCPU_out", 1, 1), 486 }; 487 488 /* MUXes for PLL sources. */ 489 PLIST(mux_pll_srcs) = {"osc_div_clk", NULL, "pllP_out0", NULL}; /* FIXME */ 490 PLIST(mux_plle_src1) = {"osc_div_clk", "pllP_out0"}; 491 PLIST(mux_plle_src) = {"pllE_src1", "pllREFE_out0"}; 492 static struct clk_mux_def tegra210_pll_sources[] = { 493 /* Core clocks. */ 494 MUX(0, "pllD2_src", mux_pll_srcs, PLLD2_BASE, 25, 2), 495 MUX(0, "pllDP_src", mux_pll_srcs, PLLDP_BASE, 25, 2), 496 MUX(0, "pllC4_src", mux_pll_srcs, PLLC4_BASE, 25, 2), 497 MUX(0, "pllE_src1", mux_plle_src1, PLLE_AUX, 2, 1), 498 MUX(0, "pllE_src", mux_plle_src, PLLE_AUX, 28, 1), 499 }; 500 501 /* Gates for PLL branches. */ 502 static struct clk_gate_def tegra210_pll_gates[] = { 503 /* Core clocks. */ 504 GATE_PLL(0, "pllC_out1", "pllC_out1_div", PLLC_OUT, 0), 505 506 GATE_PLL(0, "pllP_out1", "pllP_out1_div", PLLP_OUTA, 0), 507 GATE_PLL(0, "pllP_out3", "pllP_out3_div", PLLP_OUTB, 0), 508 GATE_PLL(TEGRA210_CLK_PLL_P_OUT4, "pllP_out4", "pllP_out4_div", PLLP_OUTB, 16), 509 GATE_PLL(0, "pllP_out5", "pllP_out5_div", PLLP_OUTC, 16), 510 511 GATE_PLL(0, "pllU_out1", "pllU_out1_div", PLLU_OUTA, 0), 512 GATE_PLL(0, "pllU_out2", "pllU_out2_div", PLLU_OUTA, 16), 513 GATE(0, "pllU_480", "pllU", PLLU_BASE, 22), 514 GATE(0, "pllU_60", "pllU_out2", PLLU_BASE, 23), 515 GATE(0, "pllU_48", "pllU_out1", PLLU_BASE, 25), 516 517 GATE_PLL(0, "pllREFE_out1", "pllREFE_out1_div", PLLREFE_OUT, 0), 518 GATE_PLL(0, "pllC4_out3", "pllC4_out3_div", PLLC4_OUT, 0), 519 520 GATE_PLL(0, "pllA_out0", "pllA_out0_div", PLLA_OUT, 0), 521 }; 522 523 struct clk_div_table tegra210_pll_pdiv_tbl[] = { 524 /* value , divider */ 525 { 0, 1 }, 526 { 1, 2 }, 527 { 2, 3 }, 528 { 3, 4 }, 529 { 4, 5 }, 530 { 5, 6 }, 531 { 6, 8 }, 532 { 7, 10 }, 533 { 8, 12 }, 534 { 9, 16 }, 535 {10, 12 }, 536 {11, 16 }, 537 {12, 20 }, 538 {13, 24 }, 539 {14, 32 }, 540 { 0, 0 }, 541 }; 542 543 /* Dividers for PLL branches. */ 544 static struct clk_div_def tegra210_pll_divs[] = { 545 /* Core clocks. */ 546 DIV7_1(0, "pllC_out1_div", "pllC_out0", PLLC_OUT, 8), 547 548 DIV7_1(0, "pllP_out1_div", "pllP_out0", PLLP_OUTA, 8), 549 DIV_TB(0, "pllP_out2", "pllP_out0", PLLP_BASE, 20, 5, tegra210_pll_pdiv_tbl), 550 DIV7_1(0, "pllP_out3_div", "pllP_out0", PLLP_OUTB, 8), 551 DIV7_1(0, "pllP_out4_div", "pllP_out0", PLLP_OUTB, 24), 552 DIV7_1(0, "pllP_out5_div", "pllP_out0", PLLP_OUTC, 24), 553 554 DIV_TB(0, "pllU_out0", "pllU", PLLU_BASE, 16, 5, tegra210_pll_pdiv_tbl), 555 DIV7_1(0, "pllU_out1_div", "pllU_out0", PLLU_OUTA, 8), 556 DIV7_1(0, "pllU_out2_div", "pllU_out0", PLLU_OUTA, 24), 557 558 DIV_TB(0, "pllREFE_out0", "pllREFE", PLLREFE_BASE, 16, 5, tegra210_pll_pdiv_tbl), 559 DIV7_1(0, "pllREFE_out1_div", "pllREFE", PLLREFE_OUT, 8), 560 561 DIV_TB(TEGRA210_CLK_PLL_C4_OUT0, 562 "pllC4_out0", "pllC4", PLLC4_BASE, 19, 5, tegra210_pll_pdiv_tbl), 563 DIV7_1(0, "pllC4_out3_div", "pllC4_out0", PLLC4_OUT, 8), 564 565 DIV7_1(0, "pllA_out0_div", "pllA", PLLA_OUT, 8), 566 567 }; 568 569 static int tegra210_pll_init(struct clknode *clk, device_t dev); 570 static int tegra210_pll_set_gate(struct clknode *clk, bool enable); 571 static int tegra210_pll_get_gate(struct clknode *clk, bool *enabled); 572 static int tegra210_pll_recalc(struct clknode *clk, uint64_t *freq); 573 static int tegra210_pll_set_freq(struct clknode *clknode, uint64_t fin, 574 uint64_t *fout, int flags, int *stop); 575 struct pll_sc { 576 device_t clkdev; 577 enum pll_type type; 578 uint32_t base_reg; 579 uint32_t misc_reg; 580 uint32_t lock_enable; 581 uint32_t iddq_reg; 582 uint32_t iddq_mask; 583 uint32_t flags; 584 struct pdiv_table *pdiv_table; 585 struct mnp_bits mnp_bits; 586 }; 587 588 static clknode_method_t tegra210_pll_methods[] = { 589 /* Device interface */ 590 CLKNODEMETHOD(clknode_init, tegra210_pll_init), 591 CLKNODEMETHOD(clknode_set_gate, tegra210_pll_set_gate), 592 CLKNODEMETHOD(clknode_get_gate, tegra210_pll_get_gate), 593 CLKNODEMETHOD(clknode_recalc_freq, tegra210_pll_recalc), 594 CLKNODEMETHOD(clknode_set_freq, tegra210_pll_set_freq), 595 CLKNODEMETHOD_END 596 }; 597 DEFINE_CLASS_1(tegra210_pll, tegra210_pll_class, tegra210_pll_methods, 598 sizeof(struct pll_sc), clknode_class); 599 600 static int 601 pll_enable(struct pll_sc *sc) 602 { 603 uint32_t reg; 604 605 606 RD4(sc, sc->base_reg, ®); 607 if (sc->type != PLL_E) 608 reg &= ~PLL_BASE_BYPASS; 609 reg |= PLL_BASE_ENABLE; 610 WR4(sc, sc->base_reg, reg); 611 return (0); 612 } 613 614 static int 615 pll_disable(struct pll_sc *sc) 616 { 617 uint32_t reg; 618 619 RD4(sc, sc->base_reg, ®); 620 if (sc->type != PLL_E) 621 reg |= PLL_BASE_BYPASS; 622 reg &= ~PLL_BASE_ENABLE; 623 WR4(sc, sc->base_reg, reg); 624 return (0); 625 } 626 627 static uint32_t 628 pdiv_to_reg(struct pll_sc *sc, uint32_t p_div) 629 { 630 struct pdiv_table *tbl; 631 632 tbl = sc->pdiv_table; 633 if (tbl == NULL) { 634 if (sc->flags & PLL_FLAG_PDIV_POWER2) 635 return (ffs(p_div) - 1); 636 else 637 return (p_div); 638 } 639 640 while (tbl->divider != 0) { 641 if (p_div <= tbl->divider) 642 return (tbl->value); 643 tbl++; 644 } 645 return (0xFFFFFFFF); 646 } 647 648 static uint32_t 649 reg_to_pdiv(struct pll_sc *sc, uint32_t reg) 650 { 651 struct pdiv_table *tbl; 652 653 tbl = sc->pdiv_table; 654 if (tbl == NULL) { 655 if (sc->flags & PLL_FLAG_PDIV_POWER2) 656 return (1 << reg); 657 else 658 return (reg == 0 ? 1: reg); 659 } 660 while (tbl->divider) { 661 if (reg == tbl->value) 662 return (tbl->divider); 663 tbl++; 664 } 665 return (0); 666 } 667 668 static uint32_t 669 get_masked(uint32_t val, uint32_t shift, uint32_t width) 670 { 671 672 return ((val >> shift) & ((1 << width) - 1)); 673 } 674 675 static uint32_t 676 set_masked(uint32_t val, uint32_t v, uint32_t shift, uint32_t width) 677 { 678 679 val &= ~(((1 << width) - 1) << shift); 680 val |= (v & ((1 << width) - 1)) << shift; 681 return (val); 682 } 683 684 static void 685 get_divisors(struct pll_sc *sc, uint32_t *m, uint32_t *n, uint32_t *p) 686 { 687 uint32_t val; 688 struct mnp_bits *mnp_bits; 689 690 mnp_bits = &sc->mnp_bits; 691 RD4(sc, sc->base_reg, &val); 692 *m = get_masked(val, mnp_bits->m_shift, mnp_bits->m_width); 693 *n = get_masked(val, mnp_bits->n_shift, mnp_bits->n_width); 694 *p = get_masked(val, mnp_bits->p_shift, mnp_bits->p_width); 695 } 696 697 static uint32_t 698 set_divisors(struct pll_sc *sc, uint32_t val, uint32_t m, uint32_t n, 699 uint32_t p) 700 { 701 struct mnp_bits *mnp_bits; 702 703 mnp_bits = &sc->mnp_bits; 704 val = set_masked(val, m, mnp_bits->m_shift, mnp_bits->m_width); 705 val = set_masked(val, n, mnp_bits->n_shift, mnp_bits->n_width); 706 val = set_masked(val, p, mnp_bits->p_shift, mnp_bits->p_width); 707 return (val); 708 } 709 710 static bool 711 is_locked(struct pll_sc *sc) 712 { 713 uint32_t reg; 714 715 switch (sc->type) { 716 case PLL_REFE: 717 RD4(sc, sc->misc_reg, ®); 718 reg &= PLLREFE_MISC_LOCK; 719 break; 720 721 case PLL_E: 722 RD4(sc, sc->misc_reg, ®); 723 reg &= PLLE_MISC_LOCK; 724 break; 725 726 default: 727 RD4(sc, sc->base_reg, ®); 728 reg &= PLL_BASE_LOCK; 729 break; 730 } 731 return (reg != 0); 732 } 733 734 static int 735 wait_for_lock(struct pll_sc *sc) 736 { 737 int i; 738 739 for (i = PLL_LOCK_TIMEOUT / 10; i > 0; i--) { 740 if (is_locked(sc)) 741 break; 742 DELAY(10); 743 } 744 if (i <= 0) { 745 printf("PLL lock timeout\n"); 746 return (ETIMEDOUT); 747 } 748 return (0); 749 } 750 751 static int 752 plle_enable(struct pll_sc *sc) 753 { 754 uint32_t reg; 755 int rv; 756 struct mnp_bits *mnp_bits; 757 uint32_t pll_m = 2; 758 uint32_t pll_n = 125; 759 uint32_t pll_cml = 14; 760 761 mnp_bits = &sc->mnp_bits; 762 763 /* Disable lock override. */ 764 RD4(sc, sc->base_reg, ®); 765 reg &= ~PLLE_BASE_LOCK_OVERRIDE; 766 WR4(sc, sc->base_reg, reg); 767 768 /* Enable SW control */ 769 RD4(sc, PLLE_AUX, ®); 770 reg |= PLLE_AUX_ENABLE_SWCTL; 771 reg &= ~PLLE_AUX_SEQ_ENABLE; 772 WR4(sc, PLLE_AUX, reg); 773 DELAY(10); 774 775 RD4(sc, sc->misc_reg, ®); 776 reg |= PLLE_MISC_LOCK_ENABLE; 777 reg |= PLLE_MISC_IDDQ_SWCTL; 778 reg &= ~PLLE_MISC_IDDQ_OVERRIDE_VALUE; 779 reg |= PLLE_MISC_PTS; 780 reg &= ~PLLE_MISC_VREG_BG_CTRL(~0); 781 reg &= ~PLLE_MISC_VREG_CTRL(~0); 782 WR4(sc, sc->misc_reg, reg); 783 DELAY(10); 784 785 RD4(sc, PLLE_SS_CNTL, ®); 786 reg |= PLLE_SS_CNTL_DISABLE; 787 WR4(sc, PLLE_SS_CNTL, reg); 788 789 RD4(sc, sc->base_reg, ®); 790 reg = set_divisors(sc, reg, pll_m, pll_n, pll_cml); 791 WR4(sc, sc->base_reg, reg); 792 DELAY(10); 793 794 pll_enable(sc); 795 rv = wait_for_lock(sc); 796 if (rv != 0) 797 return (rv); 798 799 RD4(sc, PLLE_SS_CNTL, ®); 800 reg &= ~PLLE_SS_CNTL_SSCINCINTRV(~0); 801 reg &= ~PLLE_SS_CNTL_SSCINC(~0); 802 reg &= ~PLLE_SS_CNTL_SSCINVERT; 803 reg &= ~PLLE_SS_CNTL_SSCCENTER; 804 reg &= ~PLLE_SS_CNTL_SSCMAX(~0); 805 reg |= PLLE_SS_CNTL_SSCINCINTRV(0x23); 806 reg |= PLLE_SS_CNTL_SSCINC(0x1); 807 reg |= PLLE_SS_CNTL_SSCMAX(0x21); 808 WR4(sc, PLLE_SS_CNTL, reg); 809 reg &= ~PLLE_SS_CNTL_SSCBYP; 810 reg &= ~PLLE_SS_CNTL_BYPASS_SS; 811 WR4(sc, PLLE_SS_CNTL, reg); 812 DELAY(10); 813 814 reg &= ~PLLE_SS_CNTL_INTERP_RESET; 815 WR4(sc, PLLE_SS_CNTL, reg); 816 DELAY(10); 817 818 /* HW control of brick pll. */ 819 RD4(sc, sc->misc_reg, ®); 820 reg &= ~PLLE_MISC_IDDQ_SWCTL; 821 WR4(sc, sc->misc_reg, reg); 822 823 RD4(sc, PLLE_AUX, ®); 824 reg |= PLLE_AUX_USE_LOCKDET; 825 reg |= PLLE_AUX_SS_SEQ_INCLUDE; 826 reg &= ~PLLE_AUX_ENABLE_SWCTL; 827 reg &= ~PLLE_AUX_SS_SWCTL; 828 WR4(sc, PLLE_AUX, reg); 829 reg |= PLLE_AUX_SEQ_START_STATE; 830 DELAY(10); 831 reg |= PLLE_AUX_SEQ_ENABLE; 832 WR4(sc, PLLE_AUX, reg); 833 834 /* Enable and start XUSBIO PLL HW control*/ 835 RD4(sc, XUSBIO_PLL_CFG0, ®); 836 reg &= ~XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL; 837 reg &= ~XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL; 838 reg |= XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET; 839 reg |= XUSBIO_PLL_CFG0_PADPLL_SLEEP_IDDQ; 840 reg &= ~XUSBIO_PLL_CFG0_SEQ_ENABLE; 841 WR4(sc, XUSBIO_PLL_CFG0, reg); 842 DELAY(10); 843 844 reg |= XUSBIO_PLL_CFG0_SEQ_ENABLE; 845 WR4(sc, XUSBIO_PLL_CFG0, reg); 846 847 848 /* Enable and start SATA PLL HW control */ 849 RD4(sc, SATA_PLL_CFG0, ®); 850 reg &= ~SATA_PLL_CFG0_PADPLL_RESET_SWCTL; 851 reg &= ~SATA_PLL_CFG0_PADPLL_RESET_OVERRIDE_VALUE; 852 reg |= SATA_PLL_CFG0_PADPLL_USE_LOCKDET; 853 reg |= SATA_PLL_CFG0_PADPLL_SLEEP_IDDQ; 854 reg &= ~SATA_PLL_CFG0_SEQ_IN_SWCTL; 855 reg &= ~SATA_PLL_CFG0_SEQ_RESET_INPUT_VALUE; 856 reg &= ~SATA_PLL_CFG0_SEQ_LANE_PD_INPUT_VALUE; 857 reg &= ~SATA_PLL_CFG0_SEQ_PADPLL_PD_INPUT_VALUE; 858 reg &= ~SATA_PLL_CFG0_SEQ_ENABLE; 859 WR4(sc, SATA_PLL_CFG0, reg); 860 DELAY(10); 861 reg |= SATA_PLL_CFG0_SEQ_ENABLE; 862 WR4(sc, SATA_PLL_CFG0, reg); 863 864 /* Enable HW control of PCIe PLL. */ 865 RD4(sc, PCIE_PLL_CFG, ®); 866 reg |= PCIE_PLL_CFG_SEQ_ENABLE; 867 WR4(sc, PCIE_PLL_CFG, reg); 868 869 return (0); 870 } 871 872 static int 873 tegra210_pll_set_gate(struct clknode *clknode, bool enable) 874 { 875 int rv; 876 struct pll_sc *sc; 877 878 sc = clknode_get_softc(clknode); 879 if (enable == 0) { 880 rv = pll_disable(sc); 881 return(rv); 882 } 883 884 if (sc->type == PLL_E) 885 rv = plle_enable(sc); 886 else 887 rv = pll_enable(sc); 888 return (rv); 889 } 890 891 static int 892 tegra210_pll_get_gate(struct clknode *clknode, bool *enabled) 893 { 894 uint32_t reg; 895 struct pll_sc *sc; 896 897 sc = clknode_get_softc(clknode); 898 RD4(sc, sc->base_reg, ®); 899 *enabled = reg & PLL_BASE_ENABLE ? true: false; 900 WR4(sc, sc->base_reg, reg); 901 return (0); 902 } 903 904 static int 905 pll_set_std(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags, 906 uint32_t m, uint32_t n, uint32_t p) 907 { 908 uint32_t reg; 909 struct mnp_bits *mnp_bits; 910 int rv; 911 912 mnp_bits = &sc->mnp_bits; 913 if (m >= (1 << mnp_bits->m_width)) 914 return (ERANGE); 915 if (n >= (1 << mnp_bits->n_width)) 916 return (ERANGE); 917 if (pdiv_to_reg(sc, p) >= (1 << mnp_bits->p_width)) 918 return (ERANGE); 919 920 if (flags & CLK_SET_DRYRUN) { 921 if (((flags & (CLK_SET_ROUND_UP | CLK_SET_ROUND_DOWN)) == 0) && 922 (*fout != (((fin / m) * n) /p))) 923 return (ERANGE); 924 925 *fout = ((fin / m) * n) /p; 926 927 return (0); 928 } 929 930 pll_disable(sc); 931 932 /* take pll out of IDDQ */ 933 if (sc->iddq_reg != 0) 934 MD4(sc, sc->iddq_reg, sc->iddq_mask, 0); 935 936 RD4(sc, sc->base_reg, ®); 937 reg = set_masked(reg, m, mnp_bits->m_shift, mnp_bits->m_width); 938 reg = set_masked(reg, n, mnp_bits->n_shift, mnp_bits->n_width); 939 reg = set_masked(reg, pdiv_to_reg(sc, p), mnp_bits->p_shift, 940 mnp_bits->p_width); 941 WR4(sc, sc->base_reg, reg); 942 943 /* Enable PLL. */ 944 RD4(sc, sc->base_reg, ®); 945 reg |= PLL_BASE_ENABLE; 946 WR4(sc, sc->base_reg, reg); 947 948 /* Enable lock detection. */ 949 RD4(sc, sc->misc_reg, ®); 950 reg |= sc->lock_enable; 951 WR4(sc, sc->misc_reg, reg); 952 953 rv = wait_for_lock(sc); 954 if (rv != 0) { 955 /* Disable PLL */ 956 RD4(sc, sc->base_reg, ®); 957 reg &= ~PLL_BASE_ENABLE; 958 WR4(sc, sc->base_reg, reg); 959 return (rv); 960 } 961 RD4(sc, sc->misc_reg, ®); 962 963 pll_enable(sc); 964 *fout = ((fin / m) * n) / p; 965 return 0; 966 } 967 968 static int 969 plla_set_freq(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags) 970 { 971 uint32_t m, n, p; 972 973 p = 1; 974 m = 3; 975 n = (*fout * p * m + fin / 2)/ fin; 976 dprintf("%s: m: %d, n: %d, p: %d\n", __func__, m, n, p); 977 return (pll_set_std(sc, fin, fout, flags, m, n, p)); 978 } 979 980 static int 981 pllc_set_freq(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags) 982 { 983 uint32_t m, n, p; 984 985 p = 2; 986 m = 3; 987 n = (*fout * p * m + fin / 2)/ fin; 988 dprintf("%s: m: %d, n: %d, p: %d\n", __func__, m, n, p); 989 return (pll_set_std( sc, fin, fout, flags, m, n, p)); 990 } 991 992 static int 993 pllc4_set_freq(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags) 994 { 995 uint32_t m, n, p; 996 997 p = 1; 998 m = 4; 999 n = (*fout * p * m + fin / 2)/ fin; 1000 dprintf("%s: m: %d, n: %d, p: %d\n", __func__, m, n, p); 1001 return (pll_set_std( sc, fin, fout, flags, m, n, p)); 1002 } 1003 1004 static int 1005 plldp_set_freq(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags) 1006 { 1007 uint32_t m, n, p; 1008 1009 p = 1; 1010 m = 4; 1011 n = (*fout * p * m + fin / 2)/ fin; 1012 dprintf("%s: m: %d, n: %d, p: %d\n", __func__, m, n, p); 1013 return (pll_set_std( sc, fin, fout, flags, m, n, p)); 1014 } 1015 1016 1017 /* 1018 * PLLD2 is used as source for pixel clock for HDMI. 1019 * We must be able to set it frequency very flexibly and 1020 * precisely (within 5% tolerance limit allowed by HDMI specs). 1021 * 1022 * For this reason, it is necessary to search the full state space. 1023 * Fortunately, thanks to early cycle terminations, performance 1024 * is within acceptable limits. 1025 */ 1026 #define PLLD2_PFD_MIN 12000000 /* 12 MHz */ 1027 #define PLLD2_PFD_MAX 38400000 /* 38.4 MHz */ 1028 #define PLLD2_VCO_MIN 750000000 /* 750 MHz */ 1029 #define PLLD2_VCO_MAX 1500000000 /* 1.5 GHz */ 1030 1031 static int 1032 plld2_set_freq(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags) 1033 { 1034 uint32_t m, n, p; 1035 uint32_t best_m, best_n, best_p; 1036 uint64_t vco, pfd; 1037 int64_t err, best_err; 1038 struct mnp_bits *mnp_bits; 1039 struct pdiv_table *tbl; 1040 int p_idx, rv; 1041 1042 mnp_bits = &sc->mnp_bits; 1043 tbl = sc->pdiv_table; 1044 best_err = INT64_MAX; 1045 1046 for (p_idx = 0; tbl[p_idx].divider != 0; p_idx++) { 1047 p = tbl[p_idx].divider; 1048 1049 /* Check constraints */ 1050 vco = *fout * p; 1051 if (vco < PLLD2_VCO_MIN) 1052 continue; 1053 if (vco > PLLD2_VCO_MAX) 1054 break; 1055 1056 for (m = 1; m < (1 << mnp_bits->m_width); m++) { 1057 n = (*fout * p * m + fin / 2) / fin; 1058 1059 /* Check constraints */ 1060 if (n == 0) 1061 continue; 1062 if (n >= (1 << mnp_bits->n_width)) 1063 break; 1064 vco = (fin * n) / m; 1065 if (vco > PLLD2_VCO_MAX || vco < PLLD2_VCO_MIN) 1066 continue; 1067 pfd = fin / m; 1068 if (pfd > PLLD2_PFD_MAX || vco < PLLD2_PFD_MIN) 1069 continue; 1070 1071 /* Constraints passed, save best result */ 1072 err = *fout - vco / p; 1073 if (err < 0) 1074 err = -err; 1075 if (err < best_err) { 1076 best_err = err; 1077 best_p = p; 1078 best_m = m; 1079 best_n = n; 1080 } 1081 if (err == 0) 1082 goto done; 1083 } 1084 } 1085 done: 1086 /* 1087 * HDMI specification allows 5% pixel clock tolerance, 1088 * we will by a slightly stricter 1089 */ 1090 if (best_err > ((*fout * 100) / 4)) 1091 return (ERANGE); 1092 1093 if (flags & CLK_SET_DRYRUN) 1094 return (0); 1095 rv = pll_set_std(sc, fin, fout, flags, best_m, best_n, best_p); 1096 /* XXXX Panic for rv == ERANGE ? */ 1097 return (rv); 1098 } 1099 1100 static int 1101 pllrefe_set_freq(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags) 1102 { 1103 uint32_t m, n, p; 1104 1105 m = 1; 1106 p = 1; 1107 n = *fout * p * m / fin; 1108 dprintf("%s: m: %d, n: %d, p: %d\n", __func__, m, n, p); 1109 return (pll_set_std(sc, fin, fout, flags, m, n, p)); 1110 } 1111 1112 #define PLLX_PFD_MIN 12000000LL /* 12 MHz */ 1113 #define PLLX_PFD_MAX 38400000LL /* 38.4 MHz */ 1114 #define PLLX_VCO_MIN 900000000LL /* 0.9 GHz */ 1115 #define PLLX_VCO_MAX 3000000000LL /* 3 GHz */ 1116 1117 static int 1118 pllx_set_freq(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags) 1119 { 1120 struct mnp_bits *mnp_bits; 1121 uint32_t m, n, p; 1122 uint32_t old_m, old_n, old_p; 1123 uint32_t reg; 1124 int i, rv; 1125 1126 mnp_bits = &sc->mnp_bits; 1127 1128 get_divisors(sc, &old_m, &old_n, &old_p); 1129 old_p = reg_to_pdiv(sc, old_p); 1130 1131 /* Pre-divider is fixed, Compute post-divider */ 1132 m = old_m; 1133 p = 1; 1134 while ((*fout * p) < PLLX_VCO_MIN) 1135 p++; 1136 if ((*fout * p) > PLLX_VCO_MAX) 1137 return (ERANGE); 1138 1139 n = (*fout * p * m + fin / 2) / fin; 1140 dprintf("%s: m: %d, n: %d, p: %d\n", __func__, m, n, p); 1141 1142 if (m >= (1 << mnp_bits->m_width)) 1143 return (ERANGE); 1144 if (n >= (1 << mnp_bits->n_width)) 1145 return (ERANGE); 1146 if (pdiv_to_reg(sc, p) >= (1 << mnp_bits->p_width)) 1147 return (ERANGE); 1148 1149 if (flags & CLK_SET_DRYRUN) { 1150 if (((flags & (CLK_SET_ROUND_UP | CLK_SET_ROUND_DOWN)) == 0) && 1151 (*fout != (((fin / m) * n) /p))) 1152 return (ERANGE); 1153 *fout = ((fin / m) * n) /p; 1154 return (0); 1155 } 1156 1157 /* If new post-divider is bigger that original, set it now. */ 1158 if (p < old_p) { 1159 RD4(sc, sc->base_reg, ®); 1160 reg = set_masked(reg, pdiv_to_reg(sc, p), mnp_bits->p_shift, 1161 mnp_bits->p_width); 1162 WR4(sc, sc->base_reg, reg); 1163 } 1164 DELAY(100); 1165 1166 /* vvv Program dynamic VCO ramp. vvv */ 1167 /* 1 - disable dynamic ramp mode. */ 1168 RD4(sc, PLLX_MISC_2, ®); 1169 reg &= ~PLLX_MISC_2_EN_DYNRAMP; 1170 WR4(sc, PLLX_MISC_2, reg); 1171 1172 /* 2 - Setup new ndiv. */ 1173 RD4(sc, PLLX_MISC_2, ®); 1174 reg &= ~PLLX_MISC_2_NDIV_NEW(~0); 1175 reg |= PLLX_MISC_2_NDIV_NEW(n); 1176 WR4(sc, PLLX_MISC_2, reg); 1177 1178 /* 3 - enable dynamic ramp. */ 1179 RD4(sc, PLLX_MISC_2, ®); 1180 reg |= PLLX_MISC_2_EN_DYNRAMP; 1181 WR4(sc, PLLX_MISC_2, reg); 1182 1183 /* 4 - wait for done. */ 1184 for (i = PLL_LOCK_TIMEOUT / 10; i > 0; i--) { 1185 RD4(sc, PLLX_MISC_2, ®); 1186 if (reg & PLLX_MISC_2_DYNRAMP_DONE) 1187 break; 1188 DELAY(10); 1189 } 1190 if (i <= 0) { 1191 printf("PLL X dynamic ramp timedout\n"); 1192 return (ETIMEDOUT); 1193 } 1194 1195 /* 5 - copy new ndiv to base register. */ 1196 RD4(sc, sc->base_reg, ®); 1197 reg = set_masked(reg, n, mnp_bits->n_shift, 1198 mnp_bits->n_width); 1199 WR4(sc, sc->base_reg, reg); 1200 1201 /* 6 - disable dynamic ramp mode. */ 1202 RD4(sc, PLLX_MISC_2, ®); 1203 reg &= ~PLLX_MISC_2_EN_DYNRAMP; 1204 WR4(sc, PLLX_MISC_2, reg); 1205 1206 rv = wait_for_lock(sc); 1207 if (rv != 0) { 1208 printf("PLL X is not locked !!\n"); 1209 } 1210 /* ^^^ Dynamic ramp done. ^^^ */ 1211 1212 /* If new post-divider is smaller that original, set it. */ 1213 if (p > old_p) { 1214 RD4(sc, sc->base_reg, ®); 1215 reg = set_masked(reg, pdiv_to_reg(sc, p), mnp_bits->p_shift, 1216 mnp_bits->p_width); 1217 WR4(sc, sc->base_reg, reg); 1218 } 1219 1220 *fout = ((fin / m) * n) / p; 1221 return (0); 1222 } 1223 1224 /* Simplified setup for 38.4 MHz clock. */ 1225 #define PLLX_STEP_A 0x04 1226 #define PLLX_STEP_B 0x05 1227 static int 1228 pllx_init(struct pll_sc *sc) 1229 { 1230 uint32_t reg; 1231 1232 RD4(sc, PLLX_MISC, ®); 1233 reg = PLLX_MISC_LOCK_ENABLE; 1234 WR4(sc, PLLX_MISC, reg); 1235 1236 /* Setup dynamic ramp. */ 1237 reg = 0; 1238 reg |= PLLX_MISC_2_DYNRAMP_STEPA(PLLX_STEP_A); 1239 reg |= PLLX_MISC_2_DYNRAMP_STEPB(PLLX_STEP_B); 1240 WR4(sc, PLLX_MISC_2, reg); 1241 1242 /* Disable SDM. */ 1243 reg = 0; 1244 WR4(sc, PLLX_MISC_4, reg); 1245 WR4(sc, PLLX_MISC_5, reg); 1246 1247 return (0); 1248 } 1249 1250 static int 1251 tegra210_pll_set_freq(struct clknode *clknode, uint64_t fin, uint64_t *fout, 1252 int flags, int *stop) 1253 { 1254 *stop = 1; 1255 int rv; 1256 struct pll_sc *sc; 1257 1258 sc = clknode_get_softc(clknode); 1259 dprintf("%s: %s requested freq: %lu, input freq: %lu\n", __func__, 1260 clknode_get_name(clknode), *fout, fin); 1261 switch (sc->type) { 1262 case PLL_A: 1263 rv = plla_set_freq(sc, fin, fout, flags); 1264 break; 1265 1266 case PLL_C: 1267 case PLL_C2: 1268 case PLL_C3: 1269 rv = pllc_set_freq(sc, fin, fout, flags); 1270 break; 1271 1272 case PLL_C4: 1273 rv = pllc4_set_freq(sc, fin, fout, flags); 1274 break; 1275 1276 case PLL_D2: 1277 rv = plld2_set_freq(sc, fin, fout, flags); 1278 break; 1279 1280 case PLL_DP: 1281 rv = plldp_set_freq(sc, fin, fout, flags); 1282 break; 1283 1284 case PLL_REFE: 1285 rv = pllrefe_set_freq(sc, fin, fout, flags); 1286 break; 1287 1288 case PLL_X: 1289 rv = pllx_set_freq(sc, fin, fout, flags); 1290 break; 1291 1292 case PLL_U: 1293 if (*fout == 480000000) /* PLLU is fixed to 480 MHz */ 1294 rv = 0; 1295 else 1296 rv = ERANGE; 1297 break; 1298 default: 1299 rv = ENXIO; 1300 break; 1301 } 1302 1303 return (rv); 1304 } 1305 1306 1307 static int 1308 tegra210_pll_init(struct clknode *clk, device_t dev) 1309 { 1310 struct pll_sc *sc; 1311 uint32_t reg, rv; 1312 1313 sc = clknode_get_softc(clk); 1314 1315 if (sc->type == PLL_X) { 1316 rv = pllx_init(sc); 1317 if (rv != 0) 1318 return (rv); 1319 } 1320 1321 /* If PLL is enabled, enable lock detect too. */ 1322 RD4(sc, sc->base_reg, ®); 1323 if (reg & PLL_BASE_ENABLE) { 1324 RD4(sc, sc->misc_reg, ®); 1325 reg |= sc->lock_enable; 1326 WR4(sc, sc->misc_reg, reg); 1327 } 1328 if (sc->type == PLL_REFE) { 1329 RD4(sc, sc->misc_reg, ®); 1330 reg &= ~(1 << 29); /* Disable lock override */ 1331 WR4(sc, sc->misc_reg, reg); 1332 } 1333 clknode_init_parent_idx(clk, 0); 1334 return(0); 1335 } 1336 1337 static int 1338 tegra210_pll_recalc(struct clknode *clk, uint64_t *freq) 1339 { 1340 struct pll_sc *sc; 1341 uint32_t m, n, p, pr; 1342 uint32_t reg, misc_reg; 1343 int locked; 1344 1345 sc = clknode_get_softc(clk); 1346 1347 RD4(sc, sc->base_reg, ®); 1348 RD4(sc, sc->misc_reg, &misc_reg); 1349 1350 get_divisors(sc, &m, &n, &pr); 1351 1352 /* If VCO is directlu exposed, P divider is handled by external node */ 1353 if (sc->flags & PLL_FLAG_VCO_OUT) 1354 p = 1; 1355 else 1356 p = reg_to_pdiv(sc, pr); 1357 1358 locked = is_locked(sc); 1359 1360 dprintf("%s: %s (0x%08x, 0x%08x) - m: %d, n: %d, p: %d (%d): " 1361 "e: %d, r: %d, o: %d - %s\n", __func__, 1362 clknode_get_name(clk), reg, misc_reg, m, n, p, pr, 1363 (reg >> 30) & 1, (reg >> 29) & 1, (reg >> 28) & 1, 1364 locked ? "locked" : "unlocked"); 1365 1366 if ((m == 0) || (n == 0) || (p == 0)) { 1367 *freq = 0; 1368 return (EINVAL); 1369 } 1370 if (!locked) { 1371 *freq = 0; 1372 return (0); 1373 } 1374 *freq = ((*freq / m) * n) / p; 1375 return (0); 1376 } 1377 1378 static int 1379 pll_register(struct clkdom *clkdom, struct clk_pll_def *clkdef) 1380 { 1381 struct clknode *clk; 1382 struct pll_sc *sc; 1383 1384 clk = clknode_create(clkdom, &tegra210_pll_class, &clkdef->clkdef); 1385 if (clk == NULL) 1386 return (ENXIO); 1387 1388 sc = clknode_get_softc(clk); 1389 sc->clkdev = clknode_get_device(clk); 1390 sc->type = clkdef->type; 1391 sc->base_reg = clkdef->base_reg; 1392 sc->misc_reg = clkdef->misc_reg; 1393 sc->lock_enable = clkdef->lock_enable; 1394 sc->iddq_reg = clkdef->iddq_reg; 1395 sc->iddq_mask = clkdef->iddq_mask; 1396 sc->flags = clkdef->flags; 1397 sc->pdiv_table = clkdef->pdiv_table; 1398 sc->mnp_bits = clkdef->mnp_bits; 1399 clknode_register(clkdom, clk); 1400 return (0); 1401 } 1402 1403 static void config_utmi_pll(struct tegra210_car_softc *sc) 1404 { 1405 uint32_t reg; 1406 /* 1407 * XXX Simplified UTMIP settings for 38.4MHz base clock. 1408 */ 1409 #define ENABLE_DELAY_COUNT 0x00 1410 #define STABLE_COUNT 0x00 1411 #define ACTIVE_DELAY_COUNT 0x06 1412 #define XTAL_FREQ_COUNT 0x80 1413 1414 CLKDEV_READ_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, ®); 1415 reg &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE; 1416 CLKDEV_WRITE_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, reg); 1417 1418 CLKDEV_READ_4(sc->dev, UTMIP_PLL_CFG2, ®); 1419 reg &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0); 1420 reg |= UTMIP_PLL_CFG2_STABLE_COUNT(STABLE_COUNT); 1421 reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0); 1422 reg |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(ACTIVE_DELAY_COUNT); 1423 CLKDEV_WRITE_4(sc->dev, UTMIP_PLL_CFG2, reg); 1424 1425 CLKDEV_READ_4(sc->dev, UTMIP_PLL_CFG1, ®); 1426 reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0); 1427 reg |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(ENABLE_DELAY_COUNT); 1428 reg &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0); 1429 reg |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(XTAL_FREQ_COUNT); 1430 reg |= UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP; 1431 CLKDEV_WRITE_4(sc->dev, UTMIP_PLL_CFG1, reg); 1432 1433 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN; 1434 reg |= UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP; 1435 CLKDEV_WRITE_4(sc->dev, UTMIP_PLL_CFG1, reg); 1436 DELAY(20); 1437 1438 /* Setup samplers. */ 1439 CLKDEV_READ_4(sc->dev, UTMIP_PLL_CFG2, ®); 1440 reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERUP; 1441 reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERUP; 1442 reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERUP; 1443 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN; 1444 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN; 1445 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERDOWN; 1446 CLKDEV_WRITE_4(sc->dev, UTMIP_PLL_CFG2, reg); 1447 1448 /* Powerup UTMIP. */ 1449 CLKDEV_READ_4(sc->dev, UTMIP_PLL_CFG1, ®); 1450 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP; 1451 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN; 1452 CLKDEV_WRITE_4(sc->dev, UTMIP_PLL_CFG1, reg); 1453 DELAY(10); 1454 1455 /* Prepare UTMIP sequencer. */ 1456 CLKDEV_READ_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, ®); 1457 reg |= UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET; 1458 reg &= ~UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL; 1459 CLKDEV_WRITE_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, reg); 1460 DELAY(10); 1461 1462 CLKDEV_READ_4(sc->dev, XUSB_PLL_CFG0, ®); 1463 reg &= ~XUSB_PLL_CFG0_UTMIPLL_LOCK_DLY; 1464 CLKDEV_WRITE_4(sc->dev, XUSB_PLL_CFG0, reg); 1465 DELAY(10); 1466 1467 /* HW control of UTMIPLL. */ 1468 CLKDEV_READ_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, ®); 1469 reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE; 1470 CLKDEV_WRITE_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, reg); 1471 } 1472 1473 void 1474 tegra210_init_plls(struct tegra210_car_softc *sc) 1475 { 1476 int i, rv; 1477 1478 for (i = 0; i < nitems(tegra210_pll_sources); i++) { 1479 rv = clknode_mux_register(sc->clkdom, tegra210_pll_sources + i); 1480 if (rv != 0) 1481 panic("clk_mux_register failed"); 1482 } 1483 1484 for (i = 0; i < nitems(pll_clks); i++) { 1485 rv = pll_register(sc->clkdom, pll_clks + i); 1486 if (rv != 0) 1487 panic("pll_register failed"); 1488 } 1489 1490 config_utmi_pll(sc); 1491 1492 for (i = 0; i < nitems(tegra210_pll_fdivs); i++) { 1493 rv = clknode_fixed_register(sc->clkdom, tegra210_pll_fdivs + i); 1494 if (rv != 0) 1495 panic("clk_fixed_register failed"); 1496 } 1497 1498 for (i = 0; i < nitems(tegra210_pll_gates); i++) { 1499 rv = clknode_gate_register(sc->clkdom, tegra210_pll_gates + i); 1500 if (rv != 0) 1501 panic("clk_gate_register failed"); 1502 } 1503 1504 for (i = 0; i < nitems(tegra210_pll_divs); i++) { 1505 rv = clknode_div_register(sc->clkdom, tegra210_pll_divs + i); 1506 if (rv != 0) 1507 panic("clk_div_register failed"); 1508 } 1509 } 1510