1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright 2020 Michal Meloun <mmel@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 #include <sys/param.h> 30 #include <sys/systm.h> 31 #include <sys/bus.h> 32 #include <sys/lock.h> 33 #include <sys/mutex.h> 34 #include <sys/rman.h> 35 36 #include <machine/bus.h> 37 38 #include <dev/extres/clk/clk.h> 39 40 #include <dt-bindings/clock/tegra210-car.h> 41 #include <dt-bindings/reset/tegra210-car.h> 42 43 #include "tegra210_car.h" 44 45 /* Bits in base register. */ 46 #define PERLCK_AMUX_MASK 0x0F 47 #define PERLCK_AMUX_SHIFT 16 48 #define PERLCK_AMUX_DIS (1 << 20) 49 #define PERLCK_UDIV_DIS (1 << 24) 50 #define PERLCK_ENA_MASK (1 << 28) 51 #define PERLCK_MUX_SHIFT 29 52 #define PERLCK_MUX_MASK 0x07 53 54 55 struct periph_def { 56 struct clknode_init_def clkdef; 57 uint32_t base_reg; 58 uint32_t div_width; 59 uint32_t div_mask; 60 uint32_t div_f_width; 61 uint32_t div_f_mask; 62 uint32_t flags; 63 }; 64 65 struct pgate_def { 66 struct clknode_init_def clkdef; 67 uint32_t idx; 68 uint32_t flags; 69 }; 70 #define PLIST(x) static const char *x[] 71 72 #define GATE(_id, cname, plist, _idx) \ 73 { \ 74 .clkdef.id = TEGRA210_CLK_##_id, \ 75 .clkdef.name = cname, \ 76 .clkdef.parent_names = (const char *[]){plist}, \ 77 .clkdef.parent_cnt = 1, \ 78 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ 79 .idx = _idx, \ 80 .flags = 0, \ 81 } 82 /* Sources for multiplexors. */ 83 PLIST(mux_N_N_c_N_p_N_a) = 84 {"bogus", NULL, "pllC_out0", NULL, 85 "pllP_out0", NULL, "pllA_out0", NULL}; 86 PLIST(mux_N_N_p_N_N_N_clkm) = 87 {NULL, NULL, "pllP_out0", NULL, 88 NULL, NULL, "clk_m", NULL}; 89 PLIST(mux_N_c_p_a1_c2_c3_clkm) = 90 {NULL, "pllC_out0", "pllP_out0", "pllA1_out0", 91 "pllC2_out0", "pllC3_out0", "clk_m", NULL}; 92 PLIST(mux_N_c_p_a1_c2_c3_clkm_c4) = 93 {NULL, "pllC_out0", "pllP_out0", "pllA1_out0", 94 "pllC2_out0", "pllC3_out0", "clk_m", "pllC4_out0"}; 95 PLIST(mux_N_c_p_clkm_N_c4_c4o1_c4o1) = 96 {NULL, "pllC_out0", "pllP_out0", "clk_m", 97 NULL, "pllC4_out0", "pllC4_out1", "pllC4_out1"}; 98 PLIST(mux_N_c_p_clkm_N_c4_c4o1_c4o2) = 99 {NULL, "pllC_out0", "pllP_out0", "clk_m", 100 NULL, "pllC4_out0", "pllC4_out1", "pllC4_out2"}; 101 102 PLIST(mux_N_c2_c_c3_p_N_a) = 103 {NULL, "pllC2_out0", "pllC_out0", "pllC3_out0", 104 "pllP_out0", NULL, "pllA_out0", NULL}; 105 PLIST(mux_N_c2_c_c3_p_clkm_a1_c4) = 106 {NULL, "pllC2_out0", "pllC_out0", "pllC3_out0", 107 "pllP_out0", "clk_m", "pllA1_out0", "pllC4_out0"}; 108 PLIST(mux_N_c2_c_c3_p_N_a1_clkm) = 109 {NULL, "pllC2_out0", "pllC_out0", "pllC3_out0", 110 "pllP_out0", NULL, "pllA1_out0", "clk_m"}; 111 112 PLIST(mux_a_N_audio_N_p_N_clkm) = 113 {"pllA_out0", NULL, "audio", NULL, 114 "pllP_out0", NULL, "clk_m"}; 115 PLIST(mux_a_N_audio0_N_p_N_clkm) = 116 {"pllA_out0", NULL, "audio0", NULL, 117 "pllP_out0", NULL, "clk_m"}; 118 PLIST(mux_a_N_audio1_N_p_N_clkm) = 119 {"pllA_out0", NULL, "audio1", NULL, 120 "pllP_out0", NULL, "clk_m"}; 121 PLIST(mux_a_N_audio2_N_p_N_clkm) = 122 {"pllA_out0", NULL, "audio2", NULL, 123 "pllP_out0", NULL, "clk_m"}; 124 PLIST(mux_a_N_audio3_N_p_N_clkm) = 125 {"pllA_out0", NULL, "audio3", NULL, 126 "pllP_out0", NULL, "clk_m"}; 127 PLIST(mux_a_N_audio4_N_p_N_clkm) = 128 {"pllA_out0", NULL, "audio4", NULL, 129 "pllP_out0", NULL, "clk_m"}; 130 PLIST(mux_a_audiod1_p_clkm) = 131 {"pllA_out0", "audiod1", "pllP_out0", "clk_m", 132 NULL, NULL, NULL, NULL}; 133 PLIST(mux_a_audiod2_p_clkm) = 134 {"pllA_out0", "audiod2", "pllP_out0", "clk_m", 135 NULL, NULL, NULL, NULL}; 136 PLIST(mux_a_audiod3_p_clkm) = 137 {"pllA_out0", "audiod3", "pllP_out0", "clk_m", 138 NULL, NULL, NULL, NULL}; 139 PLIST(mux_a_c4_c_c4o1_p_N_clkm_c4o2) = 140 {"pllA_out0", "pllC4_out0", "pllC_out0", "pllC4_out1", 141 "pllP_out0", NULL, "clk_m", "pllC4_out2"}; 142 143 PLIST(mux_a_clks_p_clkm_e) = 144 {"pllA_out0", "clk_s", "pllP_out0", "clk_m", 145 "pllE_out0"}; 146 PLIST(mux_c4o1_c2_c_c4_p_clkm_a_c4) = 147 {"pllC4_out1", "pllC2_out0", "pllC_out0", "pllC4_out0", 148 "pllP_out0", "clk_m","pllA_out0", "pllC4_out0", }; 149 150 PLIST(mux_m_c_p_clkm_mud_mbud_mb_pud) = 151 {"pllM_out0", "pllC_out0", "pllP_out0", "clk_m", 152 "pllM_UD", "pllMB_UD", "pllMB_out0", "pllP_UD"}; 153 PLIST(mux_p_N_N_c4o2_c4o1_N_clkm_c4) = 154 {"pllP_out0", NULL, NULL, "pllC4_out2", 155 "pllC4_out1", NULL, "clk_m", "pllC4_out0"}; 156 PLIST(mux_p_N_c_c4_c4o1_c4o2_clkm) = 157 {"pllP_out0", NULL, "pllC_out0", "pllC4_out0", 158 "pllC4_out1", "pllC4_out2", "clk_m"}; 159 PLIST(mux_p_N_c_c4_N_c4o1_clkm_c4o2) = 160 {"pllP_out0", NULL, "pllC_out0", "pllC4_out0", 161 NULL, "pllC4_out1", "clk_m", "pllC4_out2"}; 162 PLIST(mux_p_N_d_N_N_d2_clkm) = 163 {"pllP_out0", NULL, "pllD_out0", NULL, 164 NULL, "pllD2_out0", "clk_m"}; 165 PLIST(mux_p_N_clkm_N_clks_N_E) = 166 {"pllP_out0", NULL, "clk_m", NULL, 167 NULL, "clk_s", NULL, "pllE_out0"}; 168 PLIST(mux_p_c_c2_N_c2_N_clkm) = 169 {"pllP_out0", "pllC_out0", "pllC2_out0", NULL, 170 "pllC2_out0", NULL, "clk_m", NULL}; 171 PLIST(mux_p_co1_c_N_c4o2_c4o1_clkm_c4) = 172 {"pllP_out0", "pllC_out1", "pllC_out0", NULL, 173 "pllC4_out2", "pllC4_out1" ,"clk_m", "pllC4_out0"}; 174 PLIST(mux_p_c2_c_c3_N_a1_clkm_c4) = 175 {"pllP_out0", "pllC2_out0", "pllC_out0", "pllC3_out0", 176 NULL, "pllA1_out0", "clk_m", "pllC4_out0"}; 177 PLIST(mux_p_c2_c_c3_N_N_clkm) = 178 {"pllP_out0", "pllC2_out0", "pllC_out0", "pllC3_out0", 179 NULL, NULL, "clk_m", NULL}; 180 PLIST(mux_p_c2_c_c3_m_e_clkm) = 181 {"pllP_out0", "pllC2_out0", "pllC_out0", "pllC3_out0", 182 "pllM_out0", "pllE_out0", "clk_m"}; 183 PLIST(mux_p_c2_c_c4_N_c4o1_clkm_c4o2) = 184 {"pllP_out0", "pllC2_out0", "pllC4_out0", 185 NULL, "pllC4_out1", "clk_m", "pllC4_out2"}; 186 PLIST(mux_p_c2_c_c4_a_c4o1_clkm_c4o2) = 187 {"pllP_out0", "pllC2_out0", "pllC_out0", "pllC4_out0", 188 "pllA_out0", "pllC4_out1", "clk_m", "pllC4_out2"}; 189 PLIST(mux_p_c2_c_c4o2_c4o1_clks_clkm_c4) = 190 {"pllP_out0", "pllC2_out0", "pllC4_out2", 191 "pllC4_out1", "clk_s", "clk_m", "pllC4_out0"}; 192 193 PLIST(mux_p_c2_c_c4_c4o1_clkm_c4o2) = 194 {"pllP_out0", "pllC2_out0", "pllC_out0", "pllC4_out0", 195 "pllC4_out1", "clk_m", "pllC4_out2"}; 196 PLIST(mux_p_c2_c_c4_clkm_c4o1_c4o2) = 197 {"pllP_out0", "pllC2_out0", "pllC_out0", "pllC4_out0", 198 "clk_m", "pllC4_out1", "pllC4_out2"}; 199 PLIST(mux_p_c2_c_c4_clks_c4o1_clkm_c4o2) = 200 {"pllP_out0", "pllC2_out0", "pllC_out0", "pllC4_out0", 201 "clk_s", "pllC4_out1", "clk_m", "pllC4_out2"}; 202 PLIST(mux_p_c2_c_c4_clkm_c4o1_clks_c4o2) = 203 {"pllP_out0", "pllC2_out0", "pllC_out0", "pllC4_out0", 204 "clk_m", "pllC4_out1", "clk_s", "pllC4_out2"}; 205 PLIST(mux_p_c2_refe1_c3_m_a1_clkm_C4) = 206 {"pllP_out0", "pllC2_out0", "pllREFE_out1", "pllC3_out0", 207 "pllM_out0", "pllA1_out0", "clk_m", "pllC4_out0"}; 208 PLIST(mux_p_c4_c_c4o1_N_c4o2_clkm) = 209 {"pllP_out0", "pllC4_out0", "pllC_out0", "pllC4_out1", 210 NULL, "pllC4_out2", "clk_m", NULL}; 211 PLIST(mux_p_m_d_a_c_d2_clkm) = 212 {"pllP_out0", "pllM_out0", "pllD_out0", "pllA_out0", 213 "pllC_out0", "pllD2_out0", "clk_m"}; 214 PLIST(mux_p_po3_clkm_clks_a) = 215 {"pllP_out0", "pllP_out3", "clk_m", "clk_s", 216 "pllA_out0", NULL, NULL, NULL}; 217 218 PLIST(mux_po3_c_c2_clkm_p_c4_c4o1_c4o2) = 219 {"pllP_out3", "pllC_out0", "pllC2_out0", "clk_m", 220 "pllP_out0", "pllC4_out0", "pllC4_out1", "pllC4_out2"}; 221 222 PLIST(mux_clkm_p_N_N_N_refre) = 223 {"clk_m", "pllP_xusb", NULL, NULL, 224 NULL, "pllREFE_out0", NULL, NULL}; 225 PLIST(mux_clkm_N_u48_N_p_N_u480) = 226 {"clk_m", NULL, "pllU_48", NULL, 227 "pllP_out0", NULL, "pllU_480"}; 228 PLIST(mux_clkm_refe_clks_u480) = 229 {"clk_m", "pllREFE_out0", "clk_s", "pllU_480", 230 NULL, NULL, NULL, NULL}; 231 232 PLIST(mux_sep_audio) = 233 {"pllA_out0", "pllC4_out0", "pllC_out0", "pllC4_out0", 234 "pllP_out0", "pllC4_out0", "clk_m", NULL, 235 "spdif_in", "i2s1", "i2s2", "i2s3", 236 "i2s4", "i2s5", "pllA_out0", "ext_vimclk"}; 237 238 static uint32_t clk_enable_reg[] = { 239 CLK_OUT_ENB_L, 240 CLK_OUT_ENB_H, 241 CLK_OUT_ENB_U, 242 CLK_OUT_ENB_V, 243 CLK_OUT_ENB_W, 244 CLK_OUT_ENB_X, 245 CLK_OUT_ENB_Y, 246 }; 247 248 static uint32_t clk_reset_reg[] = { 249 RST_DEVICES_L, 250 RST_DEVICES_H, 251 RST_DEVICES_U, 252 RST_DEVICES_V, 253 RST_DEVICES_W, 254 RST_DEVICES_X, 255 RST_DEVICES_Y, 256 }; 257 258 #define L(n) ((0 * 32) + (n)) 259 #define H(n) ((1 * 32) + (n)) 260 #define U(n) ((2 * 32) + (n)) 261 #define V(n) ((3 * 32) + (n)) 262 #define W(n) ((4 * 32) + (n)) 263 #define X(n) ((5 * 32) + (n)) 264 #define Y(n) ((6 * 32) + (n)) 265 266 /* Clock IDs not yet defined in binding header file. */ 267 #define TEGRA210_CLK_STAT_MON H(5) 268 #define TEGRA210_CLK_IRAMA U(20) 269 #define TEGRA210_CLK_IRAMB U(21) 270 #define TEGRA210_CLK_IRAMC U(22) 271 #define TEGRA210_CLK_IRAMD U(23) 272 #define TEGRA210_CLK_CRAM2 U(24) 273 #define TEGRA210_CLK_M_DOUBLER U(26) 274 #define TEGRA210_CLK_DEVD2_OUT U(29) 275 #define TEGRA210_CLK_DEVD1_OUT U(30) 276 #define TEGRA210_CLK_CPUG V(0) 277 #define TEGRA210_CLK_ATOMICS V(16) 278 #define TEGRA210_CLK_PCIERX0 W(2) 279 #define TEGRA210_CLK_PCIERX1 W(3) 280 #define TEGRA210_CLK_PCIERX2 W(4) 281 #define TEGRA210_CLK_PCIERX3 W(5) 282 #define TEGRA210_CLK_PCIERX4 W(6) 283 #define TEGRA210_CLK_PCIERX5 W(7) 284 #define TEGRA210_CLK_PCIE2_IOBIST W(9) 285 #define TEGRA210_CLK_EMC_IOBIST W(10) 286 #define TEGRA210_CLK_SATA_IOBIST W(12) 287 #define TEGRA210_CLK_MIPI_IOBIST W(13) 288 #define TEGRA210_CLK_EMC_LATENCY W(29) 289 #define TEGRA210_CLK_MC1 W(30) 290 #define TEGRA210_CLK_ETR X(3) 291 #define TEGRA210_CLK_CAM_MCLK X(4) 292 #define TEGRA210_CLK_CAM_MCLK2 X(5) 293 #define TEGRA210_CLK_MC_CAPA X(7) 294 #define TEGRA210_CLK_MC_CBPA X(8) 295 #define TEGRA210_CLK_MC_CPU X(9) 296 #define TEGRA210_CLK_MC_BBC X(10) 297 #define TEGRA210_CLK_EMC_DLL X(14) 298 #define TEGRA210_CLK_UART_FST_MIPI_CAL X(17) 299 #define TEGRA210_CLK_HPLL_ADSP X(26) 300 #define TEGRA210_CLK_PLLP_ADSP X(27) 301 #define TEGRA210_CLK_PLLA_ADSP X(28) 302 #define TEGRA210_CLK_PLLG_REF X(29) 303 #define TEGRA210_CLK_AXIAP Y(4) 304 #define TEGRA210_CLK_MC_CDPA Y(8) 305 #define TEGRA210_CLK_MC_CCPA Y(9) 306 307 308 static struct pgate_def pgate_def[] = { 309 /* bank L -> 0-31 */ 310 GATE(ISPB, "ispb", "clk_m", L(3)), 311 GATE(RTC, "rtc", "clk_s", L(4)), 312 GATE(TIMER, "timer", "clk_m", L(5)), 313 GATE(UARTA, "uarta", "pc_uarta" , L(6)), 314 GATE(UARTB, "uartb", "pc_uartb", L(7)), 315 GATE(GPIO, "gpio", "clk_m", L(8)), 316 GATE(SDMMC2, "sdmmc2", "pc_sdmmc2", L(9)), 317 GATE(SPDIF_OUT, "spdif_out", "pc_spdif_out", L(10)), 318 GATE(SPDIF_IN, "spdif_in", "pc_spdif_in", L(10)), 319 GATE(I2S1, "i2s2", "pc_i2s2", L(11)), 320 GATE(I2C1, "i2c1", "pc_i2c1", L(12)), 321 GATE(SDMMC1, "sdmmc1", "pc_sdmmc1", L(14)), 322 GATE(SDMMC4, "sdmmc4", "pc_sdmmc4", L(15)), 323 GATE(PWM, "pwm", "pc_pwm", L(17)), 324 GATE(I2S2, "i2s3", "pc_i2s3", L(18)), 325 GATE(VI, "vi", "pc_vi", L(20)), 326 GATE(USBD, "usbd", "clk_m", L(22)), 327 GATE(ISP, "isp", "pc_isp", L(23)), 328 GATE(DISP2, "disp2", "pc_disp2", L(26)), 329 GATE(DISP1, "disp1", "pc_disp1", L(27)), 330 GATE(HOST1X, "host1x", "pc_host1x", L(28)), 331 GATE(I2S0, "i2s1", "pc_i2s1", L(30)), 332 333 /* bank H -> 32-63 */ 334 GATE(MC, "mem", "clk_m", H(0)), 335 GATE(AHBDMA, "ahbdma", "clk_m", H(1)), 336 GATE(APBDMA, "apbdma", "clk_m", H(2)), 337 GATE(STAT_MON, "stat_mon", "clk_s", H(5)), 338 GATE(PMC, "pmc", "clk_s", H(6)), 339 GATE(FUSE, "fuse", "clk_m", H(7)), 340 GATE(KFUSE, "kfuse", "clk_m", H(8)), 341 GATE(SBC1, "spi1", "pc_spi1", H(9)), 342 GATE(SBC2, "spi2", "pc_spi2", H(12)), 343 GATE(SBC3, "spi3", "pc_spi3", H(14)), 344 GATE(I2C5, "i2c5", "pc_i2c5", H(15)), 345 GATE(DSIA, "dsia", "pllD_dsi_csi", H(16)), 346 GATE(CSI, "csi", "pllP_out3", H(20)), 347 GATE(I2C2, "i2c2", "pc_i2c2", H(22)), 348 GATE(UARTC, "uartc", "pc_uartc", H(23)), 349 GATE(MIPI_CAL, "mipi_cal", "clk_m", H(24)), 350 GATE(EMC, "emc", "pc_emc", H(25)), 351 GATE(USB2, "usb2", "clk_m", H(26)), 352 GATE(BSEV, "bsev", "clk_m", H(31)), 353 354 /* bank U -> 64-95 */ 355 GATE(UARTD, "uartd", "pc_uartd", U(1)), 356 GATE(I2C3, "i2c3", "pc_i2c3", U(3)), 357 GATE(SBC4, "spi4", "pc_spi4", U(4)), 358 GATE(SDMMC3, "sdmmc3", "pc_sdmmc3", U(5)), 359 GATE(PCIE, "pcie", "clk_m", U(6)), 360 GATE(AFI, "afi", "clk_m", U(8)), 361 GATE(CSITE, "csite", "pc_csite", U(9)), 362 GATE(SOC_THERM, "soc_therm", "pc_soc_therm", U(14)), 363 GATE(DTV, "dtv", "clk_m", U(15)), 364 GATE(I2CSLOW, "i2c_slow", "pc_i2c_slow", U(17)), 365 GATE(DSIB, "dsib", "pllD_dsi_csi", U(18)), 366 GATE(TSEC, "tsec", "pc_tsec", U(19)), 367 GATE(IRAMA, "irama", "clk_m", U(20)), 368 GATE(IRAMB, "iramb", "clk_m", U(21)), 369 GATE(IRAMC, "iramc", "clk_m", U(22)), 370 GATE(IRAMD, "iramd", "clk_m", U(23)), 371 GATE(CRAM2, "cram2", "clk_m", U(24)), 372 GATE(XUSB_HOST, "xusb_host", "pc_xusb_core_host", U(25)), 373 GATE(M_DOUBLER, "m_doubler", "clk_m", U(26)), 374 GATE(CSUS, "sus_out", "clk_m", U(28)), 375 GATE(DEVD2_OUT, "devd2_out", "clk_m", U(29)), 376 GATE(DEVD1_OUT, "devd1_out", "clk_m", U(30)), 377 GATE(XUSB_DEV, "xusb_core_dev", "pc_xusb_core_dev", U(31)), 378 379 /* bank V -> 96-127 */ 380 GATE(CPUG, "cpug", "clk_m", V(0)), 381 GATE(MSELECT, "mselect", "pc_mselect", V(3)), 382 GATE(TSENSOR, "tsensor", "pc_tsensor", V(4)), 383 GATE(I2S4, "i2s5", "pc_i2s5", V(5)), 384 GATE(I2S3, "i2s4", "pc_i2s4", V(6)), 385 GATE(I2C4, "i2c4", "pc_i2c4", V(7)), 386 GATE(D_AUDIO, "ahub", "pc_ahub", V(10)), 387 GATE(APB2APE, "apb2ape", "clk_m", V(11)), 388 GATE(HDA2CODEC_2X, "hda2codec_2x", "pc_hda2codec_2x", V(15)), 389 GATE(ATOMICS, "atomics", "clk_m", V(16)), 390 GATE(SPDIF_2X, "spdif_doubler", "clk_m", V(22)), 391 GATE(ACTMON, "actmon", "pc_actmon", V(23)), 392 GATE(EXTERN1, "extperiph1", "pc_extperiph1", V(24)), 393 GATE(EXTERN2, "extperiph2", "pc_extperiph2", V(25)), 394 GATE(EXTERN3, "extperiph3", "pc_extperiph3", V(26)), 395 GATE(SATA_OOB, "sata_oob", "pc_sata_oob", V(27)), 396 GATE(SATA, "sata", "pc_sata", V(28)), 397 GATE(HDA, "hda", "pc_hda", V(29)), 398 399 /* bank W -> 128-159*/ 400 GATE(HDA2HDMI, "hda2hdmi", "clk_m", W(0)), 401 /* GATE(SATA_COLD, "sata_cold", "clk_m", W(1)),*/ /* Reset only */ 402 GATE(PCIERX0, "pcierx0", "clk_m", W(2)), 403 GATE(PCIERX1, "pcierx1", "clk_m", W(3)), 404 GATE(PCIERX2, "pcierx2", "clk_m", W(4)), 405 GATE(PCIERX3, "pcierx3", "clk_m", W(5)), 406 GATE(PCIERX4, "pcierx4", "clk_m", W(6)), 407 GATE(PCIERX5, "pcierx5", "clk_m", W(7)), 408 GATE(CEC, "cec", "clk_m", W(8)), 409 GATE(PCIE2_IOBIST, "pcie2_iobist", "clk_m", W(9)), 410 GATE(EMC_IOBIST, "emc_iobist", "clk_m", W(10)), 411 GATE(SATA_IOBIST, "sata_iobist", "clk_m", W(12)), 412 GATE(MIPI_IOBIST, "mipi_iobist", "clk_m", W(13)), 413 GATE(XUSB_GATE, "xusb_gate", "clk_m", W(15)), 414 GATE(CILAB, "cilab", "pc_cilab", W(16)), 415 GATE(CILCD, "cilcd", "pc_cilcd", W(17)), 416 GATE(CILE, "cilef", "pc_cilef", W(18)), 417 GATE(DSIALP, "dsia_lp", "pc_dsia_lp", W(19)), 418 GATE(DSIBLP, "dsib_lp", "pc_dsib_lp", W(20)), 419 GATE(ENTROPY, "entropy", "pc_entropy", W(21)), 420 GATE(DFLL_REF, "dvfs_ref", "pc_dvfs_ref", W(27)), 421 GATE(DFLL_SOC, "dvfs_soc", "pc_dvfs_soc", W(27)), 422 GATE(XUSB_SS, "xusb_ss", "pc_xusb_ss", W(28)), 423 GATE(EMC_LATENCY, "emc_latency", "pc_emc_latency", W(29)), 424 GATE(MC1, "mc1", "clk_m", W(30)), 425 426 /* bank X -> 160-191*/ 427 /*GATE(SPARE, "spare", "clk_m", X(0)), */ 428 GATE(DMIC1, "dmic1", "clk_m", X(1)), 429 GATE(DMIC2, "dmic2", "clk_m", X(2)), 430 GATE(ETR, "etr", "clk_m", X(3)), 431 GATE(CAM_MCLK, "CAM_MCLK", "clk_m", X(4)), 432 GATE(CAM_MCLK2, "CAM_MCLK2", "clk_m", X(5)), 433 GATE(I2C6, "i2c6", "pc_i2c6", X(6)), 434 GATE(MC_CAPA, "mc_capa", "clk_m", X(7)), 435 GATE(MC_CBPA, "mc_cbpa", "clk_m", X(8)), 436 GATE(MC_CPU, "mc_cpu", "clk_m", X(9)), 437 GATE(MC_BBC, "mc_bbc", "clk_m", X(10)), 438 GATE(VIM2_CLK, "vim2_clk", "clk_m", X(11)), 439 GATE(MIPIBIF, "mipibif", "clk_m", X(13)), 440 GATE(EMC_DLL, "emc_dll", "pc_emc_dll", X(14)), 441 GATE(UART_FST_MIPI_CAL, "uart_fst_mipi_cal", "clk_m", X(17)), 442 GATE(VIC03, "vic", "pc_vic", X(18)), 443 GATE(DPAUX, "dpaux", "dpaux_div", X(21)), 444 GATE(SOR0, "sor0", "pc_sor0", X(22)), 445 GATE(SOR1, "sor1", "pc_sor1", X(23)), 446 GATE(GPU, "gpu", "osc_div_clk", X(24)), 447 GATE(DBGAPB, "dbgapb", "clk_m", X(25)), 448 GATE(HPLL_ADSP, "hpll_adsp", "clk_m", X(26)), 449 GATE(PLLP_ADSP, "pllp_adsp", "clk_m", X(27)), 450 GATE(PLLA_ADSP, "plla_adsp", "clk_m", X(28)), 451 GATE(PLLG_REF, "pllg_ref", "clk_m", X(29)), 452 453 /* bank Y -> 192-224*/ 454 /* GATE(SPARE1, "spare1", "clk_m", Y(0)), */ 455 GATE(SDMMC_LEGACY, "sdmmc_legacy_tm", "pc_sdmmc_legacy_tm", Y(1)), 456 GATE(NVDEC, "nvdec", "pc_nvdec", Y(2)), 457 GATE(NVJPG, "nvjpg", "clk_m", Y(3)), 458 GATE(AXIAP, "axiap", "clk_m", Y(4)), 459 GATE(DMIC3, "dmic3", "clk_m", Y(5)), 460 GATE(APE, "ape", "clk_m", Y(6)), 461 GATE(ADSP, "adsp", "clk_m", Y(7)), 462 GATE(MC_CDPA, "mc_cdpa", "clk_m", Y(8)), 463 GATE(MC_CCPA, "mc_ccpa", "clk_m", Y(9)), 464 GATE(MAUD, "mc_maud", "clk_m", Y(10)), 465 GATE(TSECB, "tsecb", "clk_m", Y(14)), 466 GATE(DPAUX1, "dpaux1", "dpaux1_div", Y(15)), 467 GATE(VI_I2C, "vi_i2c", "clk_m", Y(16)), 468 GATE(HSIC_TRK, "hsic_trk", "clk_m", Y(17)), 469 GATE(USB2_TRK, "usb2_trk", "clk_m", Y(18)), 470 GATE(QSPI, "qspi", "clk_m", Y(19)), 471 GATE(UARTAPE, "uarape", "clk_m", Y(20)), 472 GATE(ADSP_NEON, "adspneon", "clk_m", Y(26)), 473 GATE(NVENC, "nvenc", "clk_m", Y(27)), 474 GATE(IQC2, "iqc2", "clk_m", Y(28)), 475 GATE(IQC1, "iqc1", "clk_m", Y(29)), 476 GATE(SOR_SAFE, "sor_safe", "sor_safe_div", Y(30)), 477 GATE(PLL_P_OUT_CPU, "pllp_out_cpu", "clk_m", Y(31)), 478 }; 479 480 /* Peripheral clock clock */ 481 #define DCF_HAVE_MUX 0x0100 /* Block with multipexor */ 482 #define DCF_HAVE_ENA 0x0200 /* Block with enable bit */ 483 #define DCF_HAVE_DIV 0x0400 /* Block with divider */ 484 485 /* Mark block with additional bits / functionality. */ 486 #define DCF_IS_MASK 0x00FF 487 #define DCF_IS_UART 0x0001 488 #define DCF_IS_VI 0x0002 489 #define DCF_IS_HOST1X 0x0003 490 #define DCF_IS_XUSB_SS 0x0004 491 #define DCF_IS_EMC_DLL 0x0005 492 #define DCF_IS_SATA 0x0006 493 #define DCF_IS_VIC 0x0007 494 #define DCF_IS_AHUB 0x0008 495 #define DCF_IS_SOR0 0x0009 496 #define DCF_IS_EMC 0x000A 497 #define DCF_IS_QSPI 0x000B 498 #define DCF_IS_EMC_SAFE 0x000C 499 /* Basic pheripheral clock */ 500 #define PER_CLK(_id, cn, pl, r, diw, fiw, f) \ 501 { \ 502 .clkdef.id = _id, \ 503 .clkdef.name = cn, \ 504 .clkdef.parent_names = pl, \ 505 .clkdef.parent_cnt = nitems(pl), \ 506 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ 507 .base_reg = r, \ 508 .div_width = diw, \ 509 .div_f_width = fiw, \ 510 .flags = f, \ 511 } 512 513 /* Mux with fractional 8.1 divider. */ 514 #define CLK_8_1(id, cn, pl, r, f) \ 515 PER_CLK(id, cn, pl, r, 8, 1, (f) | DCF_HAVE_MUX | DCF_HAVE_DIV) 516 /* Mux with integer 8bits divider. */ 517 #define CLK_8_0(id, cn, pl, r, f) \ 518 PER_CLK(id, cn, pl, r, 8, 0, (f) | DCF_HAVE_MUX | DCF_HAVE_DIV) 519 520 /* Mux with fractional 16.1 divider. */ 521 #define CLK16_1(id, cn, pl, r, f) \ 522 PER_CLK(id, cn, pl, r, 16, 1, (f) | DCF_HAVE_MUX | DCF_HAVE_DIV) 523 /* Mux with integer 16bits divider. */ 524 #define CLK16_0(id, cn, pl, r, f) \ 525 PER_CLK(id, cn, pl, r, 16, 0, (f) | DCF_HAVE_MUX | DCF_HAVE_DIV) 526 /* Mux wihout divider. */ 527 #define CLK_0_0(id, cn, pl, r, f) \ 528 PER_CLK(id, cn, pl, r, 0, 0, (f) | DCF_HAVE_MUX) 529 530 static struct periph_def periph_def[] = { 531 CLK_8_1(0, "pc_i2s2", mux_a_N_audio1_N_p_N_clkm, CLK_SOURCE_I2S2, DCF_HAVE_ENA), 532 CLK_8_1(0, "pc_i2s3", mux_a_N_audio2_N_p_N_clkm, CLK_SOURCE_I2S3, DCF_HAVE_ENA), 533 CLK_8_1(0, "pc_spdif_out", mux_a_N_audio_N_p_N_clkm, CLK_SOURCE_SPDIF_OUT, 0), 534 CLK_8_1(0, "pc_spdif_in", mux_p_c2_c_c4_clkm_c4o1_c4o2, CLK_SOURCE_SPDIF_IN, 0), 535 CLK_8_1(0, "pc_pwm", mux_p_c2_c_c4_clks_c4o1_clkm_c4o2, CLK_SOURCE_PWM, 0), 536 CLK_8_1(0, "pc_spi2", mux_p_c2_c_c4_N_c4o1_clkm_c4o2, CLK_SOURCE_SPI2, 0), 537 CLK_8_1(0, "pc_spi3", mux_p_c2_c_c4_N_c4o1_clkm_c4o2, CLK_SOURCE_SPI3, 0), 538 CLK16_0(0, "pc_i2c1", mux_p_c2_c_c4_N_c4o1_clkm_c4o2, CLK_SOURCE_I2C1, 0), 539 CLK16_0(0, "pc_i2c5", mux_p_c2_c_c4_N_c4o1_clkm_c4o2, CLK_SOURCE_I2C5, 0), 540 CLK_8_1(0, "pc_spi1", mux_p_c2_c_c4_N_c4o1_clkm_c4o2, CLK_SOURCE_SPI1, 0), 541 CLK_0_0(0, "pc_disp1", mux_p_N_d_N_N_d2_clkm, CLK_SOURCE_DISP1, 0), 542 CLK_0_0(0, "pc_disp2", mux_p_N_d_N_N_d2_clkm, CLK_SOURCE_DISP2, 0), 543 CLK_8_1(0, "pc_isp", mux_N_c_p_a1_c2_c3_clkm_c4, CLK_SOURCE_ISP, 0), 544 CLK_8_1(0, "pc_vi", mux_N_c2_c_c3_p_clkm_a1_c4, CLK_SOURCE_VI, DCF_IS_VI), 545 CLK_8_1(0, "pc_sdmmc1", mux_p_N_N_c4o2_c4o1_N_clkm_c4, CLK_SOURCE_SDMMC1, 0), 546 CLK_8_1(0, "pc_sdmmc2", mux_p_N_N_c4o2_c4o1_N_clkm_c4, CLK_SOURCE_SDMMC2, 0), 547 CLK_8_1(0, "pc_sdmmc4", mux_p_N_N_c4o2_c4o1_N_clkm_c4, CLK_SOURCE_SDMMC4, 0), 548 CLK16_1(0, "pc_uarta", mux_p_c2_c_c4_c4o1_clkm_c4o2, CLK_SOURCE_UARTA, DCF_IS_UART), 549 CLK16_1(0, "pc_uartb", mux_p_c2_c_c4_N_c4o1_clkm_c4o2, CLK_SOURCE_UARTB, DCF_IS_UART), 550 CLK_8_1(0, "pc_host1x", mux_c4o1_c2_c_c4_p_clkm_a_c4, CLK_SOURCE_HOST1X, DCF_IS_HOST1X), 551 CLK16_0(0, "pc_i2c2", mux_p_c2_c_c4_N_c4o1_clkm_c4o2, CLK_SOURCE_I2C2, 0), 552 CLK_8_1(0, "pc_emc", mux_m_c_p_clkm_mud_mbud_mb_pud, CLK_SOURCE_EMC, DCF_IS_EMC), 553 CLK16_1(0, "pc_uartc", mux_p_c2_c_c4_c4o1_clkm_c4o2, CLK_SOURCE_UARTC, DCF_IS_UART), 554 CLK_8_1(0, "pc_vi_sensor", mux_N_c2_c_c3_p_N_a, CLK_SOURCE_VI_SENSOR, 0), 555 CLK_8_1(0, "pc_spi4", mux_p_c2_c_c4_N_c4o1_clkm_c4o2, CLK_SOURCE_SPI4, 0), 556 CLK16_0(0, "pc_i2c3", mux_p_c2_c_c4_N_c4o1_clkm_c4o2, CLK_SOURCE_I2C3, 0), 557 CLK_8_1(0, "pc_sdmmc3", mux_p_c2_c_c3_m_e_clkm, CLK_SOURCE_SDMMC3, 0), 558 CLK16_1(0, "pc_uartd", mux_p_c2_c_c4_c4o1_clkm_c4o2, CLK_SOURCE_UARTD, DCF_IS_UART), 559 CLK_8_1(0, "pc_csite", mux_p_c2_refe1_c3_m_a1_clkm_C4, CLK_SOURCE_CSITE, 0), 560 CLK_8_1(0, "pc_i2s1", mux_a_N_audio0_N_p_N_clkm, CLK_SOURCE_I2S1, 0), 561 /* DTV xxx */ 562 CLK_8_1(0, "pc_tsec", mux_p_c2_c_c3_N_a1_clkm_c4, CLK_SOURCE_TSEC, 0), 563 /* SPARE2 */ 564 CLK_8_1(0, "pc_mselect", mux_p_c2_c_c4o2_c4o1_clks_clkm_c4, CLK_SOURCE_MSELECT, 0), 565 CLK_8_1(0, "pc_tsensor", mux_p_c2_c_c4_clkm_c4o1_clks_c4o2, CLK_SOURCE_TSENSOR, 0), 566 CLK_8_1(0, "pc_i2s4", mux_a_N_audio3_N_p_N_clkm, CLK_SOURCE_I2S3, DCF_HAVE_ENA), 567 CLK_8_1(0, "pc_i2s5", mux_a_N_audio4_N_p_N_clkm, CLK_SOURCE_I2S4, DCF_HAVE_ENA), 568 CLK16_0(0, "pc_i2c4", mux_p_c2_c_c4_N_c4o1_clkm_c4o2, CLK_SOURCE_I2C4, 0), 569 CLK_8_1(0, "pc_ahub", mux_sep_audio, CLK_SOURCE_AHUB, DCF_IS_AHUB), 570 CLK_8_1(0, "pc_hda2codec_2x", mux_p_c2_c_c4_a_c4o1_clkm_c4o2, CLK_SOURCE_HDA2CODEC_2X, 0), 571 CLK_8_1(0, "pc_actmon", mux_p_c2_c_c4_clks_c4o1_clkm_c4o2, CLK_SOURCE_ACTMON, 0), 572 CLK_8_1(0, "pc_extperiph1", mux_a_clks_p_clkm_e, CLK_SOURCE_EXTPERIPH1, 0), 573 CLK_8_1(0, "pc_extperiph2", mux_a_clks_p_clkm_e, CLK_SOURCE_EXTPERIPH2, 0), 574 CLK_8_1(0, "pc_extperiph3", mux_a_clks_p_clkm_e, CLK_SOURCE_EXTPERIPH3, 0), 575 CLK_8_1(0, "pc_i2c_slow", mux_p_c2_c_c4_clks_c4o1_clkm_c4o2, CLK_SOURCE_I2C_SLOW, 0), 576 /* SYS */ 577 CLK_8_1(0, "pc_ispb", mux_N_N_c_N_p_N_a, CLK_SOURCE_ISPB, 0), 578 CLK_8_1(0, "pc_sor1", mux_p_N_d_N_N_d2_clkm, CLK_SOURCE_SOR1, DCF_IS_SOR0), 579 CLK_8_1(0, "pc_sor0", mux_p_m_d_a_c_d2_clkm, CLK_SOURCE_SOR0, DCF_IS_SOR0), 580 CLK_8_1(0, "pc_sata_oob", mux_p_c4_c_c4o1_N_c4o2_clkm, CLK_SOURCE_SATA_OOB, 0), 581 CLK_8_1(0, "pc_sata", mux_p_N_c_c4_N_c4o1_clkm_c4o2, CLK_SOURCE_SATA, DCF_IS_SATA), 582 CLK_8_1(0, "pc_hda", mux_p_c2_c_c4_N_c4o1_clkm_c4o2, CLK_SOURCE_HDA, 0), 583 CLK_8_1(TEGRA210_CLK_XUSB_HOST_SRC, 584 "pc_xusb_core_host", mux_clkm_p_N_N_N_refre, CLK_SOURCE_XUSB_CORE_HOST, 0), 585 CLK_8_1(TEGRA210_CLK_XUSB_FALCON_SRC, 586 "pc_xusb_falcon", mux_clkm_p_N_N_N_refre, CLK_SOURCE_XUSB_FALCON, 0), 587 CLK_8_1(TEGRA210_CLK_XUSB_FS_SRC, 588 "pc_xusb_fs", mux_clkm_N_u48_N_p_N_u480, CLK_SOURCE_XUSB_FS, 0), 589 CLK_8_1(TEGRA210_CLK_XUSB_DEV_SRC, 590 "pc_xusb_core_dev", mux_clkm_p_N_N_N_refre, CLK_SOURCE_XUSB_CORE_DEV, 0), 591 CLK_8_1(TEGRA210_CLK_XUSB_SS_SRC, 592 "pc_xusb_ss", mux_clkm_refe_clks_u480, CLK_SOURCE_XUSB_SS, DCF_IS_XUSB_SS), 593 CLK_8_1(0, "pc_cilab", mux_p_N_c_c4_c4o1_c4o2_clkm, CLK_SOURCE_CILAB, 0), 594 CLK_8_1(0, "pc_cilcd", mux_p_N_c_c4_c4o1_c4o2_clkm, CLK_SOURCE_CILCD, 0), 595 CLK_8_1(0, "pc_cilef", mux_p_N_c_c4_c4o1_c4o2_clkm, CLK_SOURCE_CILEF, 0), 596 CLK_8_1(0, "pc_dsia_lp", mux_p_N_c_c4_c4o1_c4o2_clkm, CLK_SOURCE_DSIA_LP, 0), 597 CLK_8_1(0, "pc_dsib_lp", mux_p_N_c_c4_c4o1_c4o2_clkm, CLK_SOURCE_DSIB_LP, 0), 598 CLK_8_1(0, "pc_entropy", mux_p_N_clkm_N_clks_N_E, CLK_SOURCE_ENTROPY, 0), 599 CLK_8_1(0, "pc_dvfs_ref", mux_p_c2_c_c4_N_c4o1_clkm_c4o2, CLK_SOURCE_DVFS_REF, DCF_HAVE_ENA), 600 CLK_8_1(0, "pc_dvfs_soc", mux_p_c2_c_c4_N_c4o1_clkm_c4o2, CLK_SOURCE_DVFS_SOC, DCF_HAVE_ENA), 601 CLK_8_1(0, "pc_emc_latency", mux_N_c_p_clkm_N_c4_c4o1_c4o2, CLK_SOURCE_EMC_LATENCY, 0), 602 CLK_8_1(0, "pc_soc_therm", mux_N_c_p_clkm_N_c4_c4o1_c4o1, CLK_SOURCE_SOC_THERM, 0), 603 CLK_8_1(0, "pc_dmic1", mux_a_audiod1_p_clkm, CLK_SOURCE_DMIC1, 0), 604 CLK_8_1(0, "pc_dmic2", mux_a_audiod2_p_clkm, CLK_SOURCE_DMIC2, 0), 605 CLK_8_1(0, "pc_vi_sensor2", mux_N_c2_c_c3_p_N_a, CLK_SOURCE_VI_SENSOR2, 0), 606 CLK16_0(0, "pc_i2c6", mux_p_c2_c_c4_N_c4o1_clkm_c4o2, CLK_SOURCE_I2C6, 0), 607 /* MIPIBIF */ 608 CLK_8_1(0, "pc_emc_dll", mux_m_c_p_clkm_mud_mbud_mb_pud, CLK_SOURCE_EMC_DLL, DCF_IS_EMC_DLL), 609 CLK_8_1(0, "pc_uart_fst_mipi_cal", mux_p_c_c2_N_c2_N_clkm, CLK_SOURCE_UART_FST_MIPI_CAL, 0), 610 CLK_8_1(0, "pc_vic", mux_N_c_p_a1_c2_c3_clkm, CLK_SOURCE_VIC, DCF_IS_VIC), 611 612 CLK_8_1(0, "pc_sdmmc_legacy_tm", mux_po3_c_c2_clkm_p_c4_c4o1_c4o2, CLK_SOURCE_SDMMC_LEGACY_TM, 0), 613 CLK_8_1(0, "pc_nvdec", mux_N_c2_c_c3_p_N_a1_clkm, CLK_SOURCE_NVDEC, 0), 614 CLK_8_1(0, "pc_nvjpg", mux_N_c2_c_c3_p_N_a1_clkm, CLK_SOURCE_NVJPG, 0), 615 CLK_8_1(0, "pc_nvenc", mux_N_c2_c_c3_p_N_a1_clkm, CLK_SOURCE_NVENC, 0), 616 CLK_8_1(0, "pc_dmic3", mux_a_audiod3_p_clkm, CLK_SOURCE_DMIC3, 0), 617 CLK_8_1(0, "pc_ape", mux_a_c4_c_c4o1_p_N_clkm_c4o2, CLK_SOURCE_APE, 0), 618 CLK_8_1(0, "pc_qspi", mux_p_co1_c_N_c4o2_c4o1_clkm_c4, CLK_SOURCE_QSPI, DCF_IS_QSPI), 619 CLK_8_1(0, "pc_vi_i2c", mux_p_c2_c_c3_N_N_clkm, CLK_SOURCE_VI_I2C, 0), 620 /* USB2_HSIC_TRK */ 621 CLK_8_0(0, "pc_maud", mux_p_po3_clkm_clks_a, CLK_SOURCE_MAUD, 0), 622 CLK_8_1(0, "pc_tsecb", mux_p_c2_c_c3_N_a1_clkm_c4, CLK_SOURCE_TSECB, 0), 623 CLK_8_1(0, "pc_uartape", mux_p_c2_c_c3_N_N_clkm, CLK_SOURCE_UARTAPE, 0), 624 CLK_8_1(0, "pc_dbgapb", mux_N_N_p_N_N_N_clkm, CLK_SOURCE_DBGAPB, 0), 625 CLK_8_1(0, "pc_emc_safe", mux_m_c_p_clkm_mud_mbud_mb_pud, CLK_SOURCE_EMC_SAFE, DCF_IS_EMC_SAFE), 626 }; 627 628 static int periph_init(struct clknode *clk, device_t dev); 629 static int periph_recalc(struct clknode *clk, uint64_t *freq); 630 static int periph_set_freq(struct clknode *clk, uint64_t fin, 631 uint64_t *fout, int flags, int *stop); 632 static int periph_set_mux(struct clknode *clk, int idx); 633 634 struct periph_sc { 635 device_t clkdev; 636 uint32_t base_reg; 637 uint32_t div_shift; 638 uint32_t div_width; 639 uint32_t div_mask; 640 uint32_t div_f_width; 641 uint32_t div_f_mask; 642 uint32_t flags; 643 644 uint32_t divider; 645 int mux; 646 }; 647 648 static clknode_method_t periph_methods[] = { 649 /* Device interface */ 650 CLKNODEMETHOD(clknode_init, periph_init), 651 CLKNODEMETHOD(clknode_recalc_freq, periph_recalc), 652 CLKNODEMETHOD(clknode_set_freq, periph_set_freq), 653 CLKNODEMETHOD(clknode_set_mux, periph_set_mux), 654 CLKNODEMETHOD_END 655 }; 656 DEFINE_CLASS_1(tegra210_periph, tegra210_periph_class, periph_methods, 657 sizeof(struct periph_sc), clknode_class); 658 659 static int 660 periph_init(struct clknode *clk, device_t dev) 661 { 662 struct periph_sc *sc; 663 uint32_t reg; 664 sc = clknode_get_softc(clk); 665 666 DEVICE_LOCK(sc); 667 if (sc->flags & DCF_HAVE_ENA) 668 MD4(sc, sc->base_reg, PERLCK_ENA_MASK, PERLCK_ENA_MASK); 669 670 RD4(sc, sc->base_reg, ®); 671 DEVICE_UNLOCK(sc); 672 673 /* Stnadard mux. */ 674 if (sc->flags & DCF_HAVE_MUX) 675 sc->mux = (reg >> PERLCK_MUX_SHIFT) & PERLCK_MUX_MASK; 676 else 677 sc->mux = 0; 678 if (sc->flags & DCF_HAVE_DIV) 679 sc->divider = (reg & sc->div_mask) + 2; 680 else 681 sc->divider = 1; 682 if ((sc->flags & DCF_IS_MASK) == DCF_IS_UART) { 683 if (!(reg & PERLCK_UDIV_DIS)) 684 sc->divider = 2; 685 } 686 687 /* AUDIO MUX */ 688 if ((sc->flags & DCF_IS_MASK) == DCF_IS_AHUB) { 689 if (!(reg & PERLCK_AMUX_DIS) && (sc->mux == 7)) { 690 sc->mux = 8 + 691 ((reg >> PERLCK_AMUX_SHIFT) & PERLCK_MUX_MASK); 692 } 693 } 694 clknode_init_parent_idx(clk, sc->mux); 695 return(0); 696 } 697 698 static int 699 periph_set_mux(struct clknode *clk, int idx) 700 { 701 struct periph_sc *sc; 702 uint32_t reg; 703 704 705 sc = clknode_get_softc(clk); 706 if (!(sc->flags & DCF_HAVE_MUX)) 707 return (ENXIO); 708 709 sc->mux = idx; 710 DEVICE_LOCK(sc); 711 RD4(sc, sc->base_reg, ®); 712 reg &= ~(PERLCK_MUX_MASK << PERLCK_MUX_SHIFT); 713 if ((sc->flags & DCF_IS_MASK) == DCF_IS_AHUB) { 714 reg &= ~PERLCK_AMUX_DIS; 715 reg &= ~(PERLCK_MUX_MASK << PERLCK_AMUX_SHIFT); 716 717 if (idx <= 7) { 718 reg |= idx << PERLCK_MUX_SHIFT; 719 } else { 720 reg |= 7 << PERLCK_MUX_SHIFT; 721 reg |= (idx - 8) << PERLCK_AMUX_SHIFT; 722 } 723 } else { 724 reg |= idx << PERLCK_MUX_SHIFT; 725 } 726 WR4(sc, sc->base_reg, reg); 727 DEVICE_UNLOCK(sc); 728 729 return(0); 730 } 731 732 static int 733 periph_recalc(struct clknode *clk, uint64_t *freq) 734 { 735 struct periph_sc *sc; 736 uint32_t reg; 737 738 sc = clknode_get_softc(clk); 739 740 if (sc->flags & DCF_HAVE_DIV) { 741 DEVICE_LOCK(sc); 742 RD4(sc, sc->base_reg, ®); 743 DEVICE_UNLOCK(sc); 744 *freq = (*freq << sc->div_f_width) / sc->divider; 745 } 746 return (0); 747 } 748 749 static int 750 periph_set_freq(struct clknode *clk, uint64_t fin, uint64_t *fout, 751 int flags, int *stop) 752 { 753 struct periph_sc *sc; 754 uint64_t tmp, divider; 755 756 sc = clknode_get_softc(clk); 757 if (!(sc->flags & DCF_HAVE_DIV)) { 758 *stop = 0; 759 return (0); 760 } 761 762 tmp = fin << sc->div_f_width; 763 divider = tmp / *fout; 764 if ((tmp % *fout) != 0) 765 divider++; 766 767 if (divider < (1 << sc->div_f_width)) 768 divider = 1 << (sc->div_f_width - 1); 769 770 if (flags & CLK_SET_DRYRUN) { 771 if (((flags & (CLK_SET_ROUND_UP | CLK_SET_ROUND_DOWN)) == 0) && 772 (*fout != (tmp / divider))) 773 return (ERANGE); 774 } else { 775 DEVICE_LOCK(sc); 776 MD4(sc, sc->base_reg, sc->div_mask, 777 (divider - (1 << sc->div_f_width))); 778 DEVICE_UNLOCK(sc); 779 sc->divider = divider; 780 } 781 *fout = tmp / divider; 782 *stop = 1; 783 return (0); 784 } 785 786 static int 787 periph_register(struct clkdom *clkdom, struct periph_def *clkdef) 788 { 789 struct clknode *clk; 790 struct periph_sc *sc; 791 792 clk = clknode_create(clkdom, &tegra210_periph_class, &clkdef->clkdef); 793 if (clk == NULL) 794 return (1); 795 796 sc = clknode_get_softc(clk); 797 sc->clkdev = clknode_get_device(clk); 798 sc->base_reg = clkdef->base_reg; 799 sc->div_width = clkdef->div_width; 800 sc->div_mask = (1 <<clkdef->div_width) - 1; 801 sc->div_f_width = clkdef->div_f_width; 802 sc->div_f_mask = (1 <<clkdef->div_f_width) - 1; 803 sc->flags = clkdef->flags; 804 805 clknode_register(clkdom, clk); 806 return (0); 807 } 808 809 /* -------------------------------------------------------------------------- */ 810 static int pgate_init(struct clknode *clk, device_t dev); 811 static int pgate_set_gate(struct clknode *clk, bool enable); 812 static int pgate_get_gate(struct clknode *clk, bool *enabled); 813 814 struct pgate_sc { 815 device_t clkdev; 816 uint32_t idx; 817 uint32_t flags; 818 uint32_t enabled; 819 820 }; 821 822 static clknode_method_t pgate_methods[] = { 823 /* Device interface */ 824 CLKNODEMETHOD(clknode_init, pgate_init), 825 CLKNODEMETHOD(clknode_set_gate, pgate_set_gate), 826 CLKNODEMETHOD(clknode_get_gate, pgate_get_gate), 827 CLKNODEMETHOD_END 828 }; 829 DEFINE_CLASS_1(tegra210_pgate, tegra210_pgate_class, pgate_methods, 830 sizeof(struct pgate_sc), clknode_class); 831 832 static uint32_t 833 get_enable_reg(int idx) 834 { 835 KASSERT(idx / 32 < nitems(clk_enable_reg), 836 ("Invalid clock index for enable: %d", idx)); 837 return (clk_enable_reg[idx / 32]); 838 } 839 840 static uint32_t 841 get_reset_reg(int idx) 842 { 843 KASSERT(idx / 32 < nitems(clk_reset_reg), 844 ("Invalid clock index for reset: %d", idx)); 845 return (clk_reset_reg[idx / 32]); 846 } 847 848 static int 849 pgate_init(struct clknode *clk, device_t dev) 850 { 851 struct pgate_sc *sc; 852 uint32_t ena_reg, rst_reg, mask; 853 854 sc = clknode_get_softc(clk); 855 mask = 1 << (sc->idx % 32); 856 857 DEVICE_LOCK(sc); 858 RD4(sc, get_enable_reg(sc->idx), &ena_reg); 859 RD4(sc, get_reset_reg(sc->idx), &rst_reg); 860 DEVICE_UNLOCK(sc); 861 862 sc->enabled = ena_reg & mask ? 1 : 0; 863 clknode_init_parent_idx(clk, 0); 864 865 return(0); 866 } 867 868 static int 869 pgate_set_gate(struct clknode *clk, bool enable) 870 { 871 struct pgate_sc *sc; 872 uint32_t reg, mask, base_reg; 873 874 sc = clknode_get_softc(clk); 875 mask = 1 << (sc->idx % 32); 876 sc->enabled = enable; 877 base_reg = get_enable_reg(sc->idx); 878 879 DEVICE_LOCK(sc); 880 MD4(sc, base_reg, mask, enable ? mask : 0); 881 RD4(sc, base_reg, ®); 882 DEVICE_UNLOCK(sc); 883 884 DELAY(2); 885 return(0); 886 } 887 888 static int 889 pgate_get_gate(struct clknode *clk, bool *enabled) 890 { 891 struct pgate_sc *sc; 892 uint32_t reg, mask, base_reg; 893 894 sc = clknode_get_softc(clk); 895 mask = 1 << (sc->idx % 32); 896 base_reg = get_enable_reg(sc->idx); 897 898 DEVICE_LOCK(sc); 899 RD4(sc, base_reg, ®); 900 DEVICE_UNLOCK(sc); 901 *enabled = reg & mask ? true: false; 902 903 return(0); 904 } 905 906 int 907 tegra210_hwreset_by_idx(struct tegra210_car_softc *sc, intptr_t idx, bool reset) 908 { 909 uint32_t reg, mask, reset_reg; 910 911 CLKDEV_DEVICE_LOCK(sc->dev); 912 if (idx == TEGRA210_RST_DFLL_DVCO) { 913 CLKDEV_MODIFY_4(sc->dev, DFLL_BASE, DFLL_BASE_DVFS_DFLL_RESET, 914 reset ? DFLL_BASE_DVFS_DFLL_RESET : 0); 915 CLKDEV_READ_4(sc->dev, DFLL_BASE, ®); 916 } 917 if (idx == TEGRA210_RST_ADSP) { 918 reset_reg = (reset) ? RST_DEV_Y_SET: RST_DEV_Y_CLR; 919 mask = (0x1F << 22) |(1 << 7); 920 CLKDEV_WRITE_4(sc->dev, reset_reg, mask); 921 CLKDEV_READ_4(sc->dev, reset_reg, ®); 922 } else { 923 mask = 1 << (idx % 32); 924 reset_reg = get_reset_reg(idx); 925 926 CLKDEV_MODIFY_4(sc->dev, reset_reg, mask, reset ? mask : 0); 927 CLKDEV_READ_4(sc->dev, reset_reg, ®); 928 } 929 CLKDEV_DEVICE_UNLOCK(sc->dev); 930 931 return(0); 932 } 933 934 static int 935 pgate_register(struct clkdom *clkdom, struct pgate_def *clkdef) 936 { 937 struct clknode *clk; 938 struct pgate_sc *sc; 939 940 clk = clknode_create(clkdom, &tegra210_pgate_class, &clkdef->clkdef); 941 if (clk == NULL) 942 return (1); 943 944 sc = clknode_get_softc(clk); 945 sc->clkdev = clknode_get_device(clk); 946 sc->idx = clkdef->idx; 947 sc->flags = clkdef->flags; 948 949 clknode_register(clkdom, clk); 950 return (0); 951 } 952 953 void 954 tegra210_periph_clock(struct tegra210_car_softc *sc) 955 { 956 int i, rv; 957 958 for (i = 0; i < nitems(periph_def); i++) { 959 rv = periph_register(sc->clkdom, &periph_def[i]); 960 if (rv != 0) 961 panic("tegra210_periph_register failed"); 962 } 963 for (i = 0; i < nitems(pgate_def); i++) { 964 rv = pgate_register(sc->clkdom, &pgate_def[i]); 965 if (rv != 0) 966 panic("tegra210_pgate_register failed"); 967 } 968 969 } 970