1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright 2020 Michal Meloun <mmel@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 #include <sys/param.h> 30 #include <sys/systm.h> 31 #include <sys/bus.h> 32 #include <sys/kernel.h> 33 #include <sys/kobj.h> 34 #include <sys/module.h> 35 #include <sys/malloc.h> 36 #include <sys/rman.h> 37 #include <sys/lock.h> 38 #include <sys/mutex.h> 39 40 #include <machine/bus.h> 41 #include <machine/cpu.h> 42 43 #include <dev/extres/clk/clk_div.h> 44 #include <dev/extres/clk/clk_fixed.h> 45 #include <dev/extres/clk/clk_gate.h> 46 #include <dev/extres/clk/clk_mux.h> 47 #include <dev/extres/hwreset/hwreset.h> 48 #include <dev/ofw/openfirm.h> 49 #include <dev/ofw/ofw_bus.h> 50 #include <dev/ofw/ofw_bus_subr.h> 51 52 #include <dt-bindings/clock/tegra210-car.h> 53 54 #include "clkdev_if.h" 55 #include "hwreset_if.h" 56 #include "tegra210_car.h" 57 58 static struct ofw_compat_data compat_data[] = { 59 {"nvidia,tegra210-car", 1}, 60 {NULL, 0}, 61 }; 62 63 #define PLIST(x) static const char *x[] 64 65 /* Pure multiplexer. */ 66 #define MUX(_id, cname, plists, o, s, w) \ 67 { \ 68 .clkdef.id = _id, \ 69 .clkdef.name = cname, \ 70 .clkdef.parent_names = plists, \ 71 .clkdef.parent_cnt = nitems(plists), \ 72 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ 73 .offset = o, \ 74 .shift = s, \ 75 .width = w, \ 76 } 77 78 /* Fractional divider (7.1). */ 79 #define DIV7_1(_id, cname, plist, o, s) \ 80 { \ 81 .clkdef.id = _id, \ 82 .clkdef.name = cname, \ 83 .clkdef.parent_names = (const char *[]){plist}, \ 84 .clkdef.parent_cnt = 1, \ 85 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ 86 .offset = o, \ 87 .i_shift = (s) + 1, \ 88 .i_width = 7, \ 89 .f_shift = s, \ 90 .f_width = 1, \ 91 } 92 93 /* Integer divider. */ 94 #define DIV(_id, cname, plist, o, s, w, f) \ 95 { \ 96 .clkdef.id = _id, \ 97 .clkdef.name = cname, \ 98 .clkdef.parent_names = (const char *[]){plist}, \ 99 .clkdef.parent_cnt = 1, \ 100 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ 101 .offset = o, \ 102 .i_shift = s, \ 103 .i_width = w, \ 104 .div_flags = f, \ 105 } 106 107 /* Gate in PLL block. */ 108 #define GATE_PLL(_id, cname, plist, o, s) \ 109 { \ 110 .clkdef.id = _id, \ 111 .clkdef.name = cname, \ 112 .clkdef.parent_names = (const char *[]){plist}, \ 113 .clkdef.parent_cnt = 1, \ 114 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ 115 .offset = o, \ 116 .shift = s, \ 117 .mask = 3, \ 118 .on_value = 3, \ 119 .off_value = 0, \ 120 } 121 122 /* Standard gate. */ 123 #define GATE(_id, cname, plist, o, s) \ 124 { \ 125 .clkdef.id = _id, \ 126 .clkdef.name = cname, \ 127 .clkdef.parent_names = (const char *[]){plist}, \ 128 .clkdef.parent_cnt = 1, \ 129 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ 130 .offset = o, \ 131 .shift = s, \ 132 .mask = 1, \ 133 .on_value = 1, \ 134 .off_value = 0, \ 135 } 136 137 /* Inverted gate. */ 138 #define GATE_INV(_id, cname, plist, o, s) \ 139 { \ 140 .clkdef.id = _id, \ 141 .clkdef.name = cname, \ 142 .clkdef.parent_names = (const char *[]){plist}, \ 143 .clkdef.parent_cnt = 1, \ 144 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ 145 .offset = o, \ 146 .shift = s, \ 147 .mask = 1, \ 148 .on_value = 0, \ 149 .off_value = 1, \ 150 } 151 152 /* Fixed rate clock. */ 153 #define FRATE(_id, cname, _freq) \ 154 { \ 155 .clkdef.id = _id, \ 156 .clkdef.name = cname, \ 157 .clkdef.parent_names = NULL, \ 158 .clkdef.parent_cnt = 0, \ 159 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ 160 .freq = _freq, \ 161 } 162 163 /* Fixed rate multipier/divider. */ 164 #define FACT(_id, cname, pname, _mult, _div) \ 165 { \ 166 .clkdef.id = _id, \ 167 .clkdef.name = cname, \ 168 .clkdef.parent_names = (const char *[]){pname}, \ 169 .clkdef.parent_cnt = 1, \ 170 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ 171 .mult = _mult, \ 172 .div = _div, \ 173 } 174 175 static uint32_t osc_freqs[16] = { 176 [0] = 13000000, 177 [1] = 16800000, 178 [4] = 19200000, 179 [5] = 38400000, 180 [8] = 12000000, 181 [9] = 48000000, 182 }; 183 184 185 /* Parent lists. */ 186 PLIST(mux_xusb_hs) = {"xusb_ss_div2", "pllU_60", "pc_xusb_ss" }; 187 PLIST(mux_xusb_ssp) = {"xusb_ss", "osc_div_clk"}; 188 189 190 /* Clocks adjusted online. */ 191 static struct clk_fixed_def fixed_osc = 192 FRATE(TEGRA210_CLK_CLK_M, "osc", 38400000); 193 static struct clk_fixed_def fixed_clk_m = 194 FACT(0, "clk_m", "osc", 1, 1); 195 static struct clk_fixed_def fixed_osc_div = 196 FACT(0, "osc_div_clk", "osc", 1, 1); 197 198 static struct clk_fixed_def tegra210_fixed_clks[] = { 199 /* Core clocks. */ 200 FRATE(0, "bogus", 1), 201 FRATE(0, "clk_s", 32768), 202 203 /* Audio clocks. */ 204 FRATE(0, "vimclk_sync", 1), 205 FRATE(0, "i2s1_sync", 1), 206 FRATE(0, "i2s2_sync", 1), 207 FRATE(0, "i2s3_sync", 1), 208 FRATE(0, "i2s4_sync", 1), 209 FRATE(0, "i2s5_sync", 1), 210 FRATE(0, "spdif_in_sync", 1), 211 212 /* XUSB */ 213 FACT(TEGRA210_CLK_XUSB_SS_DIV2, "xusb_ss_div2", "xusb_ss", 1, 2), 214 215 /* SOR */ 216 FACT(0, "sor_safe_div", "pllP_out0", 1, 17), 217 FACT(0, "dpaux_div", "sor_safe", 1, 17), 218 FACT(0, "dpaux1_div", "sor_safe", 1, 17), 219 220 /* Not Yet Implemented */ 221 FRATE(0, "audio", 10000000), 222 FRATE(0, "audio0", 10000000), 223 FRATE(0, "audio1", 10000000), 224 FRATE(0, "audio2", 10000000), 225 FRATE(0, "audio3", 10000000), 226 FRATE(0, "audio4", 10000000), 227 FRATE(0, "ext_vimclk", 10000000), 228 FRATE(0, "audiod1", 10000000), 229 FRATE(0, "audiod2", 10000000), 230 FRATE(0, "audiod3", 10000000), 231 FRATE(0, "dfllCPU_out", 10000000), 232 233 }; 234 235 236 static struct clk_mux_def tegra210_mux_clks[] = { 237 /* USB. */ 238 MUX(TEGRA210_CLK_XUSB_HS_SRC, "xusb_hs", mux_xusb_hs, CLK_SOURCE_XUSB_SS, 25, 2), 239 MUX(0, "xusb_ssp", mux_xusb_ssp, CLK_SOURCE_XUSB_SS, 24, 1), 240 241 }; 242 243 244 static struct clk_gate_def tegra210_gate_clks[] = { 245 /* Base peripheral clocks. */ 246 GATE_INV(TEGRA210_CLK_HCLK, "hclk", "hclk_div", CLK_SYSTEM_RATE, 7), 247 GATE_INV(TEGRA210_CLK_PCLK, "pclk", "pclk_div", CLK_SYSTEM_RATE, 3), 248 GATE(TEGRA210_CLK_CML0, "cml0", "pllE_out0", PLLE_AUX, 0), 249 GATE(TEGRA210_CLK_CML1, "cml1", "pllE_out0", PLLE_AUX, 1), 250 GATE(0, "pllD_dsi_csi", "pllD_out0", PLLD_MISC, 21), 251 GATE(0, "pllP_hsio", "pllP_out0", PLLP_MISC1, 29), 252 GATE(0, "pllP_xusb", "pllP_hsio", PLLP_MISC1, 28), 253 }; 254 255 static struct clk_div_def tegra210_div_clks[] = { 256 /* Base peripheral clocks. */ 257 DIV(0, "hclk_div", "sclk", CLK_SYSTEM_RATE, 4, 2, 0), 258 DIV(0, "pclk_div", "hclk", CLK_SYSTEM_RATE, 0, 2, 0), 259 }; 260 261 /* Initial setup table. */ 262 static struct tegra210_init_item clk_init_table[] = { 263 /* clock, partent, frequency, enable */ 264 {"uarta", "pllP_out0", 408000000, 0}, 265 {"uartb", "pllP_out0", 408000000, 0}, 266 {"uartc", "pllP_out0", 408000000, 0}, 267 {"uartd", "pllP_out0", 408000000, 0}, 268 {"pllA", NULL, 564480000, 1}, 269 {"pllA_out0", NULL, 11289600, 1}, 270 {"extperiph1", "pllA_out0", 0, 1}, 271 {"i2s1", "pllA_out0", 11289600, 0}, 272 {"i2s2", "pllA_out0", 11289600, 0}, 273 {"i2s3", "pllA_out0", 11289600, 0}, 274 {"i2s4", "pllA_out0", 11289600, 0}, 275 {"i2s5", "pllA_out0", 11289600, 0}, 276 {"host1x", "pllP_out0", 136000000, 1}, 277 {"sclk", "pllP_out2", 102000000, 1}, 278 {"dvfs_soc", "pllP_out0", 51000000, 1}, 279 {"dvfs_ref", "pllP_out0", 51000000, 1}, 280 {"spi4", "pllP_out0", 12000000, 1}, 281 {"pllREFE", NULL, 672000000, 0}, 282 283 {"xusb", NULL, 0, 1}, 284 {"xusb_ss", "pllU_480", 120000000, 0}, 285 {"pc_xusb_fs", "pllU_48", 48000000, 0}, 286 {"xusb_hs", "pc_xusb_ss", 120000000, 0}, 287 {"xusb_ssp", "xusb_ss", 120000000, 0}, 288 {"pc_xusb_falcon", "pllP_xusb", 204000000, 0}, 289 {"pc_xusb_core_host", "pllP_xusb", 102000000, 0}, 290 {"pc_xusb_core_dev", "pllP_xusb", 102000000, 0}, 291 292 {"sata", "pllP_out0", 104000000, 0}, 293 {"sata_oob", "pllP_out0", 204000000, 0}, 294 {"emc", NULL, 0, 1}, 295 {"mselect", NULL, 0, 1}, 296 {"csite", NULL, 0, 1}, 297 298 {"dbgapb", NULL, 0, 1 }, 299 {"tsensor", "clk_m", 400000, 0}, 300 {"i2c1", "pllP_out0", 0, 0}, 301 {"i2c2", "pllP_out0", 0, 0}, 302 {"i2c3", "pllP_out0", 0, 0}, 303 {"i2c4", "pllP_out0", 0, 0}, 304 {"i2c5", "pllP_out0", 0, 0}, 305 {"i2c6", "pllP_out0", 0, 0}, 306 307 {"pllDP_out0", NULL, 270000000, 0}, 308 {"soc_therm", "pllP_out0", 51000000, 0}, 309 {"cclk_g", NULL, 0, 1}, 310 {"pllU_out1", NULL, 48000000, 1}, 311 {"pllU_out2", NULL, 60000000, 1}, 312 {"pllC4", NULL, 1000000000, 1}, 313 {"pllC4_out0", NULL, 1000000000, 1}, 314 }; 315 316 static void 317 init_divs(struct tegra210_car_softc *sc, struct clk_div_def *clks, int nclks) 318 { 319 int i, rv; 320 321 for (i = 0; i < nclks; i++) { 322 rv = clknode_div_register(sc->clkdom, clks + i); 323 if (rv != 0) 324 panic("clk_div_register failed"); 325 } 326 } 327 328 static void 329 init_gates(struct tegra210_car_softc *sc, struct clk_gate_def *clks, int nclks) 330 { 331 int i, rv; 332 333 334 for (i = 0; i < nclks; i++) { 335 rv = clknode_gate_register(sc->clkdom, clks + i); 336 if (rv != 0) 337 panic("clk_gate_register failed"); 338 } 339 } 340 341 static void 342 init_muxes(struct tegra210_car_softc *sc, struct clk_mux_def *clks, int nclks) 343 { 344 int i, rv; 345 346 347 for (i = 0; i < nclks; i++) { 348 rv = clknode_mux_register(sc->clkdom, clks + i); 349 if (rv != 0) 350 panic("clk_mux_register failed"); 351 } 352 } 353 354 static void 355 init_fixeds(struct tegra210_car_softc *sc, struct clk_fixed_def *clks, 356 int nclks) 357 { 358 int i, rv; 359 uint32_t val; 360 int osc_idx; 361 362 CLKDEV_READ_4(sc->dev, OSC_CTRL, &val); 363 osc_idx = OSC_CTRL_OSC_FREQ_GET(val); 364 fixed_osc.freq = osc_freqs[osc_idx]; 365 if (fixed_osc.freq == 0) 366 panic("Undefined input frequency"); 367 rv = clknode_fixed_register(sc->clkdom, &fixed_osc); 368 if (rv != 0) 369 panic("clk_fixed_register failed"); 370 371 fixed_osc_div.div = 1 << OSC_CTRL_PLL_REF_DIV_GET(val); 372 rv = clknode_fixed_register(sc->clkdom, &fixed_osc_div); 373 if (rv != 0) 374 panic("clk_fixed_register failed"); 375 376 CLKDEV_READ_4(sc->dev, SPARE_REG0, &val); 377 fixed_clk_m.div = SPARE_REG0_MDIV_GET(val) + 1; 378 rv = clknode_fixed_register(sc->clkdom, &fixed_clk_m); 379 if (rv != 0) 380 panic("clk_fixed_register failed"); 381 382 for (i = 0; i < nclks; i++) { 383 rv = clknode_fixed_register(sc->clkdom, clks + i); 384 if (rv != 0) 385 panic("clk_fixed_register failed"); 386 } 387 } 388 389 static void 390 postinit_clock(struct tegra210_car_softc *sc) 391 { 392 int i; 393 struct tegra210_init_item *tbl; 394 struct clknode *clknode; 395 int rv; 396 397 for (i = 0; i < nitems(clk_init_table); i++) { 398 tbl = &clk_init_table[i]; 399 400 clknode = clknode_find_by_name(tbl->name); 401 if (clknode == NULL) { 402 device_printf(sc->dev, "Cannot find clock %s\n", 403 tbl->name); 404 continue; 405 } 406 if (tbl->parent != NULL) { 407 rv = clknode_set_parent_by_name(clknode, tbl->parent); 408 if (rv != 0) { 409 device_printf(sc->dev, 410 "Cannot set parent for %s (to %s): %d\n", 411 tbl->name, tbl->parent, rv); 412 continue; 413 } 414 } 415 if (tbl->frequency != 0) { 416 rv = clknode_set_freq(clknode, tbl->frequency, 0 , 9999); 417 if (rv != 0) { 418 device_printf(sc->dev, 419 "Cannot set frequency for %s: %d\n", 420 tbl->name, rv); 421 continue; 422 } 423 } 424 if (tbl->enable!= 0) { 425 rv = clknode_enable(clknode); 426 if (rv != 0) { 427 device_printf(sc->dev, 428 "Cannot enable %s: %d\n", tbl->name, rv); 429 continue; 430 } 431 } 432 } 433 } 434 435 static void 436 register_clocks(device_t dev) 437 { 438 struct tegra210_car_softc *sc; 439 440 sc = device_get_softc(dev); 441 sc->clkdom = clkdom_create(dev); 442 if (sc->clkdom == NULL) 443 panic("clkdom == NULL"); 444 445 init_fixeds(sc, tegra210_fixed_clks, nitems(tegra210_fixed_clks)); 446 tegra210_init_plls(sc); 447 init_muxes(sc, tegra210_mux_clks, nitems(tegra210_mux_clks)); 448 init_divs(sc, tegra210_div_clks, nitems(tegra210_div_clks)); 449 init_gates(sc, tegra210_gate_clks, nitems(tegra210_gate_clks)); 450 tegra210_periph_clock(sc); 451 tegra210_super_mux_clock(sc); 452 clkdom_finit(sc->clkdom); 453 clkdom_xlock(sc->clkdom); 454 postinit_clock(sc); 455 clkdom_unlock(sc->clkdom); 456 if (bootverbose) 457 clkdom_dump(sc->clkdom); 458 } 459 460 static int 461 tegra210_car_clkdev_read_4(device_t dev, bus_addr_t addr, uint32_t *val) 462 { 463 struct tegra210_car_softc *sc; 464 465 sc = device_get_softc(dev); 466 *val = bus_read_4(sc->mem_res, addr); 467 return (0); 468 } 469 470 static int 471 tegra210_car_clkdev_write_4(device_t dev, bus_addr_t addr, uint32_t val) 472 { 473 struct tegra210_car_softc *sc; 474 475 sc = device_get_softc(dev); 476 bus_write_4(sc->mem_res, addr, val); 477 return (0); 478 } 479 480 static int 481 tegra210_car_clkdev_modify_4(device_t dev, bus_addr_t addr, uint32_t clear_mask, 482 uint32_t set_mask) 483 { 484 struct tegra210_car_softc *sc; 485 uint32_t reg; 486 487 sc = device_get_softc(dev); 488 reg = bus_read_4(sc->mem_res, addr); 489 reg &= ~clear_mask; 490 reg |= set_mask; 491 bus_write_4(sc->mem_res, addr, reg); 492 return (0); 493 } 494 495 static void 496 tegra210_car_clkdev_device_lock(device_t dev) 497 { 498 struct tegra210_car_softc *sc; 499 500 sc = device_get_softc(dev); 501 mtx_lock(&sc->mtx); 502 } 503 504 static void 505 tegra210_car_clkdev_device_unlock(device_t dev) 506 { 507 struct tegra210_car_softc *sc; 508 509 sc = device_get_softc(dev); 510 mtx_unlock(&sc->mtx); 511 } 512 513 static int 514 tegra210_car_detach(device_t dev) 515 { 516 517 device_printf(dev, "Error: Clock driver cannot be detached\n"); 518 return (EBUSY); 519 } 520 521 static int 522 tegra210_car_probe(device_t dev) 523 { 524 525 if (!ofw_bus_status_okay(dev)) 526 return (ENXIO); 527 528 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data != 0) { 529 device_set_desc(dev, "Tegra Clock Driver"); 530 return (BUS_PROBE_DEFAULT); 531 } 532 533 return (ENXIO); 534 } 535 536 static int 537 tegra210_car_attach(device_t dev) 538 { 539 struct tegra210_car_softc *sc = device_get_softc(dev); 540 int rid, rv; 541 542 sc->dev = dev; 543 544 mtx_init(&sc->mtx, device_get_nameunit(dev), NULL, MTX_DEF); 545 sc->type = ofw_bus_search_compatible(dev, compat_data)->ocd_data; 546 547 /* Resource setup. */ 548 rid = 0; 549 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 550 RF_ACTIVE); 551 if (!sc->mem_res) { 552 device_printf(dev, "cannot allocate memory resource\n"); 553 rv = ENXIO; 554 goto fail; 555 } 556 557 register_clocks(dev); 558 hwreset_register_ofw_provider(dev); 559 return (0); 560 561 fail: 562 if (sc->mem_res) 563 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res); 564 565 return (rv); 566 } 567 568 static int 569 tegra210_car_hwreset_assert(device_t dev, intptr_t id, bool value) 570 { 571 struct tegra210_car_softc *sc = device_get_softc(dev); 572 573 return (tegra210_hwreset_by_idx(sc, id, value)); 574 } 575 576 static device_method_t tegra210_car_methods[] = { 577 /* Device interface */ 578 DEVMETHOD(device_probe, tegra210_car_probe), 579 DEVMETHOD(device_attach, tegra210_car_attach), 580 DEVMETHOD(device_detach, tegra210_car_detach), 581 582 /* Clkdev interface*/ 583 DEVMETHOD(clkdev_read_4, tegra210_car_clkdev_read_4), 584 DEVMETHOD(clkdev_write_4, tegra210_car_clkdev_write_4), 585 DEVMETHOD(clkdev_modify_4, tegra210_car_clkdev_modify_4), 586 DEVMETHOD(clkdev_device_lock, tegra210_car_clkdev_device_lock), 587 DEVMETHOD(clkdev_device_unlock, tegra210_car_clkdev_device_unlock), 588 589 /* Reset interface */ 590 DEVMETHOD(hwreset_assert, tegra210_car_hwreset_assert), 591 592 DEVMETHOD_END 593 }; 594 595 static DEFINE_CLASS_0(car, tegra210_car_driver, tegra210_car_methods, 596 sizeof(struct tegra210_car_softc)); 597 EARLY_DRIVER_MODULE(tegra210_car, simplebus, tegra210_car_driver, NULL, NULL, 598 BUS_PASS_TIMER); 599