1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2020 Ruslan Bukin <br@bsdpad.com> 5 * 6 * This software was developed by SRI International and the University of 7 * Cambridge Computer Laboratory (Department of Computer Science and 8 * Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the 9 * DARPA SSITH research programme. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 */ 32 33 #ifndef _ARM64_IOMMU_SMMUREG_H_ 34 #define _ARM64_IOMMU_SMMUREG_H_ 35 36 #define SMMU_IDR0 0x000 37 #define IDR0_ST_LVL_S 27 38 #define IDR0_ST_LVL_M (0x3 << IDR0_ST_LVL_S) 39 #define IDR0_ST_LVL_LINEAR (0x0 << IDR0_ST_LVL_S) /* Linear Stream table*/ 40 #define IDR0_ST_LVL_2 (0x1 << IDR0_ST_LVL_S) /* 2-level Stream Table*/ 41 #define IDR0_ST_TERM_MODEL (1 << 26) /* Terminate model behavior */ 42 #define IDR0_STALL_MODEL_S 24 /* Stall model support */ 43 #define IDR0_STALL_MODEL_M (0x3 << IDR0_STALL_MODEL_S) 44 #define IDR0_STALL_MODEL_STALL (0x0 << IDR0_STALL_MODEL_S) /* Stall and Term*/ 45 #define IDR0_STALL_MODEL_FORCE (0x2 << IDR0_STALL_MODEL_S) /* Stall is forced*/ 46 #define IDR0_TTENDIAN_S 21 /* Endianness for translation table walks.*/ 47 #define IDR0_TTENDIAN_M (0x3 << IDR0_TTENDIAN_S) 48 #define IDR0_TTENDIAN_MIXED (0x0 << IDR0_TTENDIAN_S) 49 #define IDR0_TTENDIAN_LITTLE (0x2 << IDR0_TTENDIAN_S) 50 #define IDR0_TTENDIAN_BIG (0x3 << IDR0_TTENDIAN_S) 51 #define IDR0_VATOS (1 << 20) / * Virtual ATOS page interface */ 52 #define IDR0_CD2L (1 << 19) /* 2-level Context descriptor table*/ 53 #define IDR0_VMID16 (1 << 18) /* 16-bit VMID supported */ 54 #define IDR0_VMW (1 << 17) /* VMID wildcard-matching */ 55 #define IDR0_PRI (1 << 16) /* Page Request Interface supported*/ 56 #define IDR0_ATOS (1 << 15) /* Address Translation Operations */ 57 #define IDR0_SEV (1 << 14) /* WFE wake-up events */ 58 #define IDR0_MSI (1 << 13) /* Message Signalled Interrupts */ 59 #define IDR0_ASID16 (1 << 12) /* 16-bit ASID supported */ 60 #define IDR0_NS1ATS (1 << 11) /* Split-stage ATS not supported */ 61 #define IDR0_ATS (1 << 10) /* PCIe ATS supported by SMMU */ 62 #define IDR0_HYP (1 << 9) /* Hypervisor stage 1 contexts */ 63 #define IDR0_DORMHINT (1 << 8) /* Dormant hint supported */ 64 #define IDR0_HTTU_S 6 /* H/W transl. table A-flag and Dirty state */ 65 #define IDR0_HTTU_M (0x3 << IDR0_HTTU_S) 66 #define IDR0_HTTU_A (0x1 << IDR0_HTTU_S) /* Access flag (A-flag) */ 67 #define IDR0_HTTU_AD (0x2 << IDR0_HTTU_S) /* A-flag and Dirty State*/ 68 #define IDR0_BTM (1 << 5) /* Broadcast TLB Maintenance */ 69 #define IDR0_COHACC (1 << 4) /* Coherent access to translations*/ 70 #define IDR0_TTF_S 2 /* Translation Table Formats supported */ 71 #define IDR0_TTF_M (0x3 << IDR0_TTF_S) 72 #define IDR0_TTF_AA32 (0x1 << IDR0_TTF_S) /* AArch32 (LPAE) */ 73 #define IDR0_TTF_AA64 (0x2 << IDR0_TTF_S) /* AArch64 */ 74 #define IDR0_TTF_ALL (0x3 << IDR0_TTF_S) /* AArch32 and AArch64 */ 75 #define IDR0_S1P (1 << 1) /* Stage1 translation supported. */ 76 #define IDR0_S2P (1 << 0) /* Stage2 translation supported. */ 77 #define SMMU_IDR1 0x004 78 #define IDR1_TABLES_PRESET (1 << 30) /* Table base addresses fixed. */ 79 #define IDR1_QUEUES_PRESET (1 << 29) /* Queue base addresses fixed. */ 80 #define IDR1_REL (1 << 28) /* Relative base pointers */ 81 #define IDR1_ATTR_TYPES_OVR (1 << 27) /* Incoming attrs can be overridden*/ 82 #define IDR1_ATTR_PERMS_OVR (1 << 26) /* Incoming attrs can be overridden*/ 83 #define IDR1_CMDQS_S 21 /* Maximum number of Command queue entries*/ 84 #define IDR1_CMDQS_M (0x1f << IDR1_CMDQS_S) 85 #define IDR1_EVENTQS_S 16 /* Maximum number of Event queue entries */ 86 #define IDR1_EVENTQS_M (0x1f << IDR1_EVENTQS_S) 87 #define IDR1_PRIQS_S 11 /* Maximum number of PRI queue entries */ 88 #define IDR1_PRIQS_M (0x1f << IDR1_PRIQS_S) 89 #define IDR1_SSIDSIZE_S 6 /* Max bits of SubstreamID */ 90 #define IDR1_SSIDSIZE_M (0x1f << IDR1_SSIDSIZE_S) 91 #define IDR1_SIDSIZE_S 0 /* Max bits of StreamID */ 92 #define IDR1_SIDSIZE_M (0x3f << IDR1_SIDSIZE_S) 93 #define SMMU_IDR2 0x008 94 #define SMMU_IDR3 0x00C 95 #define IDR3_RIL (1 << 10) /* Range-based Invalidations. */ 96 #define SMMU_IDR4 0x010 97 #define SMMU_IDR5 0x014 98 #define IDR5_STALL_MAX_S 16 /* Max outstanding stalled transactions */ 99 #define IDR5_STALL_MAX_M (0xffff << IDR5_STALL_MAX_S) 100 #define IDR5_VAX_S 10 /* Virtual Address eXtend */ 101 #define IDR5_VAX_M (0x3 << IDR5_VAX_S) 102 #define IDR5_VAX_48 (0 << IDR5_VAX_S) 103 #define IDR5_VAX_52 (1 << IDR5_VAX_S) 104 #define IDR5_GRAN64K (1 << 6) /* 64KB translation granule */ 105 #define IDR5_GRAN16K (1 << 5) /* 16KB translation granule */ 106 #define IDR5_GRAN4K (1 << 4) /* 4KB translation granule */ 107 #define IDR5_OAS_S 0 /* Output Address Size */ 108 #define IDR5_OAS_M (0x7 << IDR5_OAS_S) 109 #define IDR5_OAS_32 (0x0 << IDR5_OAS_S) 110 #define IDR5_OAS_36 (0x1 << IDR5_OAS_S) 111 #define IDR5_OAS_40 (0x2 << IDR5_OAS_S) 112 #define IDR5_OAS_42 (0x3 << IDR5_OAS_S) 113 #define IDR5_OAS_44 (0x4 << IDR5_OAS_S) 114 #define IDR5_OAS_48 (0x5 << IDR5_OAS_S) 115 #define IDR5_OAS_52 (0x6 << IDR5_OAS_S) /* Reserved in SMMU v3.0 */ 116 #define SMMU_IIDR 0x018 117 #define SMMU_AIDR 0x01C 118 #define SMMU_CR0 0x020 119 #define CR0_VMW_S 6 /* VMID Wildcard */ 120 #define CR0_VMW_M (0x7 << CR0_VMW_S) 121 #define CR0_ATSCHK (1 << 4) /* ATS behavior: Safe mode */ 122 #define CR0_CMDQEN (1 << 3) /* Enable Command queue processing */ 123 #define CR0_EVENTQEN (1 << 2) /* Enable Event queue writes */ 124 #define CR0_PRIQEN (1 << 1) /* Enable PRI queue writes */ 125 #define CR0_SMMUEN (1 << 0) /* Non-secure SMMU enable */ 126 #define SMMU_CR0ACK 0x024 127 #define SMMU_CR1 0x028 128 #define CR1_TABLE_SH_S 10 /* Table access Shareability. */ 129 #define CR1_TABLE_SH_M (0x3 << CR1_TABLE_SH_S) 130 #define CR1_TABLE_SH_NS (0x0 << CR1_TABLE_SH_S) 131 #define CR1_TABLE_SH_OS (0x2 << CR1_TABLE_SH_S) 132 #define CR1_TABLE_SH_IS (0x3 << CR1_TABLE_SH_S) 133 #define CR1_TABLE_OC_S 8 /* Table access Outer Cacheability. */ 134 #define CR1_TABLE_OC_M (0x3 << CR1_TABLE_OC_S) 135 #define CR1_TABLE_OC_NC (0x0 << CR1_TABLE_OC_S) 136 #define CR1_TABLE_OC_WBC (0x1 << CR1_TABLE_OC_S) 137 #define CR1_TABLE_OC_WTC (0x2 << CR1_TABLE_OC_S) 138 #define CR1_TABLE_IC_S 6 /* Table access Inner Cacheability. */ 139 #define CR1_TABLE_IC_M (0x3 << CR1_TABLE_IC_S) 140 #define CR1_TABLE_IC_NC (0x0 << CR1_TABLE_IC_S) 141 #define CR1_TABLE_IC_WBC (0x1 << CR1_TABLE_IC_S) 142 #define CR1_TABLE_IC_WTC (0x2 << CR1_TABLE_IC_S) 143 #define CR1_QUEUE_SH_S 4 /* Queue access Shareability. */ 144 #define CR1_QUEUE_SH_M (0x3 << CR1_QUEUE_SH_S) 145 #define CR1_QUEUE_SH_NS (0x0 << CR1_QUEUE_SH_S) 146 #define CR1_QUEUE_SH_OS (0x2 << CR1_QUEUE_SH_S) 147 #define CR1_QUEUE_SH_IS (0x3 << CR1_QUEUE_SH_S) 148 #define CR1_QUEUE_OC_S 2 /* Queue access Outer Cacheability. */ 149 #define CR1_QUEUE_OC_M (0x3 << CR1_QUEUE_OC_S) 150 #define CR1_QUEUE_OC_NC (0x0 << CR1_QUEUE_OC_S) 151 #define CR1_QUEUE_OC_WBC (0x1 << CR1_QUEUE_OC_S) 152 #define CR1_QUEUE_OC_WTC (0x2 << CR1_QUEUE_OC_S) 153 #define CR1_QUEUE_IC_S 0 /* Queue access Inner Cacheability. */ 154 #define CR1_QUEUE_IC_M (0x3 << CR1_QUEUE_IC_S) 155 #define CR1_QUEUE_IC_NC (0x0 << CR1_QUEUE_IC_S) 156 #define CR1_QUEUE_IC_WBC (0x1 << CR1_QUEUE_IC_S) 157 #define CR1_QUEUE_IC_WTC (0x2 << CR1_QUEUE_IC_S) 158 #define SMMU_CR2 0x02C 159 #define CR2_PTM (1 << 2) /* Private TLB Maintenance. */ 160 #define CR2_RECINVSID (1 << 1) /* Record invalid SID. */ 161 #define CR2_E2H (1 << 0) /* Enable EL2-E2H translation regime */ 162 #define SMMU_STATUSR 0x040 163 #define SMMU_GBPA 0x044 164 #define SMMU_AGBPA 0x048 165 #define SMMU_IRQ_CTRL 0x050 166 #define IRQ_CTRL_EVENTQ_IRQEN (1 << 2) /* NS Event queue interrupts enabled.*/ 167 #define IRQ_CTRL_PRIQ_IRQEN (1 << 1) /* PRI queue interrupts are enabled.*/ 168 #define IRQ_CTRL_GERROR_IRQEN (1 << 0) /* Global errors int are enabled. */ 169 #define SMMU_IRQ_CTRLACK 0x054 170 #define SMMU_GERROR 0x060 171 #define SMMU_GERRORN 0x064 172 #define SMMU_GERROR_IRQ_CFG0 0x068 173 #define SMMU_GERROR_IRQ_CFG1 0x070 174 #define SMMU_GERROR_IRQ_CFG2 0x074 175 #define SMMU_STRTAB_BASE 0x080 176 #define STRTAB_BASE_RA (1UL << 62) /* Read-Allocate. */ 177 #define STRTAB_BASE_ADDR_S 6 /* Physical address of Stream table base */ 178 #define STRTAB_BASE_ADDR_M (0x3fffffffffffUL << STRTAB_BASE_ADDR_S) 179 #define SMMU_STRTAB_BASE_CFG 0x088 180 #define STRTAB_BASE_CFG_FMT_S 16 /* Format of Stream table. */ 181 #define STRTAB_BASE_CFG_FMT_M (0x3 << STRTAB_BASE_CFG_FMT_S) 182 #define STRTAB_BASE_CFG_FMT_LINEAR (0x0 << STRTAB_BASE_CFG_FMT_S) 183 #define STRTAB_BASE_CFG_FMT_2LVL (0x1 << STRTAB_BASE_CFG_FMT_S) 184 #define STRTAB_BASE_CFG_SPLIT_S 6 /* SID split point for 2lvl table. */ 185 #define STRTAB_BASE_CFG_SPLIT_M (0x1f << STRTAB_BASE_CFG_SPLIT_S) 186 #define STRTAB_BASE_CFG_SPLIT_4KB (6 << STRTAB_BASE_CFG_SPLIT_S) 187 #define STRTAB_BASE_CFG_SPLIT_16KB (8 << STRTAB_BASE_CFG_SPLIT_S) 188 #define STRTAB_BASE_CFG_SPLIT_64KB (10 << STRTAB_BASE_CFG_SPLIT_S) 189 #define STRTAB_BASE_CFG_LOG2SIZE_S 0 /* Table size as log2(entries) */ 190 #define STRTAB_BASE_CFG_LOG2SIZE_M (0x3f << STRTAB_BASE_CFG_LOG2SIZE_S) 191 #define SMMU_CMDQ_BASE 0x090 192 #define CMDQ_BASE_RA (1UL << 62) /* Read-Allocate. */ 193 #define Q_BASE_ADDR_S 5 /* PA of queue base */ 194 #define Q_BASE_ADDR_M (0x7fffffffffff << Q_BASE_ADDR_S) 195 #define Q_LOG2SIZE_S 0 /* Queue size as log2(entries) */ 196 #define Q_LOG2SIZE_M (0x1f << Q_LOG2SIZE_S) 197 #define SMMU_CMDQ_PROD 0x098 198 #define SMMU_CMDQ_CONS 0x09C 199 #define CMDQ_CONS_ERR_S 24 200 #define CMDQ_CONS_ERR_M (0x7f << CMDQ_CONS_ERR_S) 201 #define SMMU_EVENTQ_BASE 0x0A0 202 #define EVENTQ_BASE_WA (1UL << 62) /* Write-Allocate. */ 203 #define SMMU_EVENTQ_PROD 0x100A8 204 #define SMMU_EVENTQ_CONS 0x100AC 205 #define SMMU_EVENTQ_IRQ_CFG0 0x0B0 206 #define SMMU_EVENTQ_IRQ_CFG1 0x0B8 207 #define SMMU_EVENTQ_IRQ_CFG2 0x0BC 208 #define SMMU_PRIQ_BASE 0x0C0 209 #define PRIQ_BASE_WA (1UL < 62) /* Write-Allocate. */ 210 #define SMMU_PRIQ_PROD 0x100C8 211 #define SMMU_PRIQ_CONS 0x100CC 212 #define SMMU_PRIQ_IRQ_CFG0 0x0D0 213 #define SMMU_PRIQ_IRQ_CFG1 0x0D8 214 #define SMMU_PRIQ_IRQ_CFG2 0x0DC 215 #define SMMU_GATOS_CTRL 0x100 216 #define SMMU_GATOS_SID 0x108 217 #define SMMU_GATOS_ADDR 0x110 218 #define SMMU_GATOS_PAR 0x118 219 #define SMMU_VATOS_SEL 0x180 220 #define SMMU_S_IDR0 0x8000 221 #define SMMU_S_IDR1 0x8004 222 #define SMMU_S_IDR2 0x8008 223 #define SMMU_S_IDR3 0x800C 224 #define SMMU_S_IDR4 0x8010 225 #define SMMU_S_CR0 0x8020 226 #define SMMU_S_CR0ACK 0x8024 227 #define SMMU_S_CR1 0x8028 228 #define SMMU_S_CR2 0x802C 229 #define SMMU_S_INIT 0x803C 230 #define SMMU_S_GBPA 0x8044 231 #define SMMU_S_AGBPA 0x8048 232 #define SMMU_S_IRQ_CTRL 0x8050 233 #define SMMU_S_IRQ_CTRLACK 0x8054 234 #define SMMU_S_GERROR 0x8060 235 #define SMMU_S_GERRORN 0x8064 236 #define SMMU_S_GERROR_IRQ_CFG0 0x8068 237 #define SMMU_S_GERROR_IRQ_CFG1 0x8070 238 #define SMMU_S_GERROR_IRQ_CFG2 0x8074 239 #define SMMU_S_STRTAB_BASE 0x8080 240 #define SMMU_S_STRTAB_BASE_CFG 0x8088 241 #define SMMU_S_CMDQ_BASE 0x8090 242 #define SMMU_S_CMDQ_PROD 0x8098 243 #define SMMU_S_CMDQ_CONS 0x809C 244 #define SMMU_S_EVENTQ_BASE 0x80A0 245 #define SMMU_S_EVENTQ_PROD 0x80A8 246 #define SMMU_S_EVENTQ_CONS 0x80AC 247 #define SMMU_S_EVENTQ_IRQ_CFG0 0x80B0 248 #define SMMU_S_EVENTQ_IRQ_CFG1 0x80B8 249 #define SMMU_S_EVENTQ_IRQ_CFG2 0x80BC 250 #define SMMU_S_GATOS_CTRL 0x8100 251 #define SMMU_S_GATOS_SID 0x8108 252 #define SMMU_S_GATOS_ADDR 0x8110 253 #define SMMU_S_GATOS_PAR 0x8118 254 255 #define CMD_QUEUE_OPCODE_S 0 256 #define CMD_QUEUE_OPCODE_M (0xff << CMD_QUEUE_OPCODE_S) 257 258 #define CMD_PREFETCH_CONFIG 0x01 259 #define PREFETCH_0_SID_S 32 260 #define CMD_PREFETCH_ADDR 0x02 261 #define CMD_CFGI_STE 0x03 262 #define CFGI_0_STE_SID_S 32 263 #define CMD_CFGI_STE_RANGE 0x04 264 #define CFGI_1_STE_RANGE_S 0 265 #define CMD_CFGI_CD 0x05 266 #define CFGI_0_SSID_S 12 267 #define CFGI_1_LEAF_S 0 268 #define CMD_CFGI_CD_ALL 0x06 269 #define CMD_TLBI_NH_ALL 0x10 270 #define CMD_TLBI_NH_ASID 0x11 271 #define CMD_TLBI_NH_VA 0x12 272 #define TLBI_0_ASID_S 48 273 #define TLBI_1_LEAF (1 << 0) 274 #define TLBI_1_ADDR_S 12 275 #define TLBI_1_ADDR_M (0xfffffffffffff << TLBI_1_ADDR_S) 276 #define CMD_TLBI_NH_VAA 0x13 277 #define CMD_TLBI_EL3_ALL 0x18 278 #define CMD_TLBI_EL3_VA 0x1A 279 #define CMD_TLBI_EL2_ALL 0x20 280 #define CMD_TLBI_EL2_ASID 0x21 281 #define CMD_TLBI_EL2_VA 0x22 282 #define CMD_TLBI_EL2_VAA 0x23 283 #define CMD_TLBI_S12_VMALL 0x28 284 #define CMD_TLBI_S2_IPA 0x2A 285 #define CMD_TLBI_NSNH_ALL 0x30 286 #define CMD_ATC_INV 0x40 287 #define CMD_PRI_RESP 0x41 288 #define CMD_RESUME 0x44 289 #define CMD_STALL_TERM 0x45 290 #define CMD_SYNC 0x46 291 #define SYNC_0_CS_S 12 /* The ComplSignal */ 292 #define SYNC_0_CS_M (0x3 << SYNC_0_CS_S) 293 #define SYNC_0_CS_SIG_NONE (0x0 << SYNC_0_CS_S) 294 #define SYNC_0_CS_SIG_IRQ (0x1 << SYNC_0_CS_S) 295 #define SYNC_0_CS_SIG_SEV (0x2 << SYNC_0_CS_S) 296 #define SYNC_0_MSH_S 22 /* Shareability attribute for MSI write */ 297 #define SYNC_0_MSH_M (0x3 << SYNC_0_MSH_S) 298 #define SYNC_0_MSH_NS (0x0 << SYNC_0_MSH_S) /* Non-shareable */ 299 #define SYNC_0_MSH_OS (0x2 << SYNC_0_MSH_S) /* Outer Shareable */ 300 #define SYNC_0_MSH_IS (0x3 << SYNC_0_MSH_S) /* Inner Shareable */ 301 #define SYNC_0_MSIATTR_S 24 /* Write attribute for MSI */ 302 #define SYNC_0_MSIATTR_M (0xf << SYNC_0_MSIATTR_S) 303 #define SYNC_0_MSIATTR_OIWB (0xf << SYNC_0_MSIATTR_S) 304 #define SYNC_0_MSIDATA_S 32 305 #define SYNC_1_MSIADDRESS_S 2 306 #define SYNC_1_MSIADDRESS_M (0x3ffffffffffff << SYNC_1_MSIADDRESS_S) 307 #define STE0_VALID (1 << 0) /* Structure contents are valid. */ 308 #define STE0_CONFIG_S 1 309 #define STE0_CONFIG_M (0x7 << STE0_CONFIG_S) 310 #define STE0_CONFIG_ABORT (0x0 << STE0_CONFIG_S) 311 #define STE0_CONFIG_BYPASS (0x4 << STE0_CONFIG_S) 312 #define STE0_CONFIG_S1_TRANS (0x5 << STE0_CONFIG_S) 313 #define STE0_CONFIG_S2_TRANS (0x6 << STE0_CONFIG_S) 314 #define STE0_CONFIG_ALL_TRANS (0x7 << STE0_CONFIG_S) 315 #define STE0_S1FMT_S 4 316 #define STE0_S1FMT_M (0x3 << STE0_S1FMT_S) 317 #define STE0_S1FMT_LINEAR (0x0 << STE0_S1FMT_S) 318 #define STE0_S1FMT_4KB_L2 (0x1 << STE0_S1FMT_S) 319 #define STE0_S1FMT_64KB_L2 (0x2 << STE0_S1FMT_S) 320 #define STE0_S1CONTEXTPTR_S 6 321 #define STE0_S1CONTEXTPTR_M (0x3fffffffffff << STE0_S1CONTEXTPTR_S) 322 #define STE0_S1CDMAX_S 59 323 #define STE0_S1CDMAX_M (0x1f << STE0_S1CDMAX_S) 324 325 #define STE1_S1DSS_S 0 326 #define STE1_S1DSS_M (0x3 << STE1_S1DSS_S) 327 #define STE1_S1DSS_TERMINATE (0x0 << STE1_S1DSS_S) 328 #define STE1_S1DSS_BYPASS (0x1 << STE1_S1DSS_S) 329 #define STE1_S1DSS_SUBSTREAM0 (0x2 << STE1_S1DSS_S) 330 #define STE1_S1CIR_S 2 331 #define STE1_S1CIR_M (0x3 << STE1_S1CIR_S) 332 #define STE1_S1CIR_NC (0x0 << STE1_S1CIR_S) 333 #define STE1_S1CIR_WBRA (0x1 << STE1_S1CIR_S) 334 #define STE1_S1CIR_WT (0x2 << STE1_S1CIR_S) 335 #define STE1_S1CIR_WB (0x3 << STE1_S1CIR_S) 336 #define STE1_S1COR_S 4 337 #define STE1_S1COR_M (0x3 << STE1_S1COR_S) 338 #define STE1_S1COR_NC (0x0 << STE1_S1COR_S) 339 #define STE1_S1COR_WBRA (0x1 << STE1_S1COR_S) 340 #define STE1_S1COR_WT (0x2 << STE1_S1COR_S) 341 #define STE1_S1COR_WB (0x3 << STE1_S1COR_S) 342 #define STE1_S1CSH_S 6 343 #define STE1_S1CSH_NS (0x0 << STE1_S1CSH_S) 344 #define STE1_S1CSH_OS (0x2 << STE1_S1CSH_S) 345 #define STE1_S1CSH_IS (0x3 << STE1_S1CSH_S) 346 #define STE1_S2HWU59 (1 << 8) 347 #define STE1_S2HWU60 (1 << 9) 348 #define STE1_S2HWU61 (1 << 10) 349 #define STE1_S2HWU62 (1 << 11) 350 #define STE1_DRE (1 << 12) /* Destructive Read Enable. */ 351 #define STE1_CONT_S 13 /* Contiguous Hint */ 352 #define STE1_CONT_M (0xf << STE1_CONT_S) 353 #define STE1_DCP (1 << 17) /* Directed Cache Prefetch. */ 354 #define STE1_PPAR (1 << 18) /* PRI Page request Auto Responses */ 355 #define STE1_MEV (1 << 19) /* Merge Events */ 356 #define STE1_S1STALLD (1 << 27) /* Stage 1 Stall Disable */ 357 #define STE1_EATS_S 28 /* Enable PCIe ATS translation and traffic */ 358 #define STE1_EATS_M (0x3 << STE1_EATS_S) 359 #define STE1_EATS_ABORT (0x0 << STE1_EATS_S) 360 #define STE1_EATS_FULLATS (0x1 << STE1_EATS_S) /* Full ATS */ 361 #define STE1_EATS_S1 (0x2 << STE1_EATS_S) /* Split-stage ATS */ 362 #define STE1_STRW_S 30 /* StreamWorld control */ 363 #define STE1_STRW_M (0x3 << STE1_STRW_S) 364 #define STE1_STRW_NS_EL1 (0x0 << STE1_STRW_S) 365 #define STE1_STRW_NS_EL2 (0x2 << STE1_STRW_S) 366 #define STE1_MEMATTR_S 32 367 #define STE1_MTCFG (1 << 36) 368 #define STE1_ALLOCCFG_S 37 369 #define STE1_SHCFG_S 44 370 #define STE1_SHCFG_M (0x3UL << STE1_SHCFG_S) 371 #define STE1_SHCFG_NS (0x0UL << STE1_SHCFG_S) 372 #define STE1_SHCFG_INCOMING (0x1UL << STE1_SHCFG_S) 373 #define STE1_SHCFG_OS (0x2UL << STE1_SHCFG_S) 374 #define STE1_SHCFG_IS (0x3UL << STE1_SHCFG_S) 375 #define STE1_NSCFG_S 46 376 #define STE1_NSCFG_M (0x3UL << STE1_NSCFG_S) 377 #define STE1_NSCFG_SECURE (0x2UL << STE1_NSCFG_S) 378 #define STE1_NSCFG_NONSECURE (0x3UL << STE1_NSCFG_S) 379 #define STE1_PRIVCFG_S 48 380 #define STE1_INSTCFG_S 50 381 382 #define STE2_S2VMID_S 0 383 #define STE2_S2VMID_M (0xffff << STE2_S2VMID_S) 384 #define STE2_S2T0SZ_S 32 /* Size of IPA input region */ 385 #define STE2_S2T0SZ_M (0x3f << STE2_S2T0SZ_S) 386 #define STE2_S2SL0_S 38 /* Starting level of stage 2 tt walk */ 387 #define STE2_S2SL0_M (0x3 << STE2_S2SL0_S) 388 #define STE2_S2IR0_S 40 389 #define STE2_S2IR0_M (0x3 << STE2_S2IR0_S) 390 #define STE2_S2OR0_S 42 391 #define STE2_S2OR0_M (0x3 << STE2_S2OR0_S) 392 #define STE2_S2SH0_S 44 393 #define STE2_S2SH0_M (0x3 << STE2_S2SH0_S) 394 #define STE2_S2TG_S 46 395 #define STE2_S2TG_M (0x3 << STE2_S2TG_S) 396 #define STE2_S2PS_S 48 /* Physical address Size */ 397 #define STE2_S2PS_M (0x7 << STE2_S2PS_S) 398 #define STE2_S2AA64 (1 << 51) /* Stage 2 tt is AArch64 */ 399 #define STE2_S2ENDI (1 << 52) /* Stage 2 tt endianness */ 400 #define STE2_S2AFFD (1 << 53) /* Stage 2 Access Flag Fault Disable*/ 401 #define STE2_S2PTW (1 << 54) /* Protected Table Walk */ 402 #define STE2_S2S (1 << 57) 403 #define STE2_S2R (1 << 58) 404 405 #define STE3_S2TTB_S 4 /* Address of Translation Table base */ 406 #define STE3_S2TTB_M (0xffffffffffff << STE3_S2TTB_S) 407 408 #define CD0_T0SZ_S 0 /* VA region size covered by TT0. */ 409 #define CD0_T0SZ_M (0x3f << CD0_T0SZ_S) 410 #define CD0_TG0_S 6 /* TT0 Translation Granule size */ 411 #define CD0_TG0_M (0x3 << CD0_TG0_S) 412 #define CD0_TG0_4KB (0x0 << CD0_TG0_S) 413 #define CD0_TG0_64KB (0x1 << CD0_TG0_S) 414 #define CD0_TG0_16KB (0x2 << CD0_TG0_S) 415 #define CD0_IR0_S 8 /* Inner region Cacheability for TT0 access*/ 416 #define CD0_IR0_M (0x3 << CD0_IR0_S) 417 #define CD0_IR0_NC (0x0 << CD0_IR0_S) 418 #define CD0_IR0_WBC_RWA (0x1 << CD0_IR0_S) 419 #define CD0_IR0_WTC_RA (0x2 << CD0_IR0_S) 420 #define CD0_IR0_WBC_RA (0x3 << CD0_IR0_S) 421 #define CD0_OR0_S 10 /* Outer region Cacheability for TT0 access*/ 422 #define CD0_OR0_M (0x3 << CD0_OR0_S) 423 #define CD0_OR0_NC (0x0 << CD0_OR0_S) 424 #define CD0_OR0_WBC_RWA (0x1 << CD0_OR0_S) 425 #define CD0_OR0_WTC_RA (0x2 << CD0_OR0_S) 426 #define CD0_OR0_WBC_RA (0x3 << CD0_OR0_S) 427 #define CD0_SH0_S 12 /* Shareability for TT0 access */ 428 #define CD0_SH0_M (0x3 << CD0_SH0_S) 429 #define CD0_SH0_NS (0x0 << CD0_SH0_S) 430 #define CD0_SH0_OS (0x2 << CD0_SH0_S) /* Outer Shareable */ 431 #define CD0_SH0_IS (0x3 << CD0_SH0_S) /* Inner Shareable */ 432 #define CD0_EPD0 (1 << 14) /* TT0 walk disable */ 433 #define CD0_ENDI (1 << 15) /* Big Endian */ 434 #define CD0_T1SZ_S 16 /* VA region size covered by TT1 */ 435 #define CD0_T1SZ_M (0x3f << CD0_T1SZ_S) 436 #define CD0_TG1_S 22 /* TT1 Translation Granule size */ 437 #define CD0_TG1_M (0x3 << CD0_TG1_S) 438 #define CD0_TG1_4KB (0x2 << CD0_TG1_S) 439 #define CD0_TG1_64KB (0x3 << CD0_TG1_S) 440 #define CD0_TG1_16KB (0x1 << CD0_TG1_S) 441 #define CD0_IR1_S 24 /* Inner region Cacheability for TT1 access*/ 442 #define CD0_IR1_M (0x3 << CD0_IR1_S) 443 #define CD0_OR1_S 26 444 #define CD0_OR1_M (0x3 << CD0_OR1_S) 445 #define CD0_SH1_S 28 446 #define CD0_SH1_M (0x3 << CD0_SH1_S) 447 #define CD0_EPD1 (1UL << 30) /* TT1 tt walk disable*/ 448 #define CD0_VALID (1UL << 31) /* CD Valid. */ 449 #define CD0_IPS_S 32 /* Intermediate Physical Size */ 450 #define CD0_IPS_M (0x7UL << CD0_IPS_S) 451 #define CD0_IPS_32BITS (0x0UL << CD0_IPS_S) 452 #define CD0_IPS_36BITS (0x1UL << CD0_IPS_S) 453 #define CD0_IPS_40BITS (0x2UL << CD0_IPS_S) 454 #define CD0_IPS_42BITS (0x3UL << CD0_IPS_S) 455 #define CD0_IPS_44BITS (0x4UL << CD0_IPS_S) 456 #define CD0_IPS_48BITS (0x5UL << CD0_IPS_S) 457 #define CD0_IPS_52BITS (0x6UL << CD0_IPS_S) /* SMMUv3.1 only */ 458 #define CD0_AFFD (1UL << 35) /* Access Flag Fault Disable */ 459 #define CD0_WXN (1UL << 36) /* Write eXecute Never */ 460 #define CD0_UWXN (1UL << 37) /* Unprivileged Write eXecut Never*/ 461 #define CD0_TBI0 (1UL << 38) /* Top Byte Ignore for TTB0 */ 462 #define CD0_TBI1 (1UL << 39) /* Top Byte Ignore for TTB1 */ 463 #define CD0_PAN (1UL << 40) /* Privileged Access Never */ 464 #define CD0_AA64 (1UL << 41) /* TTB{0,1} is AArch64-format TT */ 465 #define CD0_HD (1UL << 42) 466 #define CD0_HA (1UL << 43) 467 #define CD0_S (1UL << 44) 468 #define CD0_R (1UL << 45) 469 #define CD0_A (1UL << 46) 470 #define CD0_ASET (1UL << 47) /* ASID Set. */ 471 #define CD0_ASID_S 48 /* Address Space Identifier */ 472 #define CD0_ASID_M (0xffff << CD0_ASID_S) 473 #define CD1_TTB0_S 4 /* Address of TT0 base. */ 474 #define CD1_TTB0_M (0xffffffffffff << CD1_TTB0_S) 475 476 #endif /* _ARM64_IOMMU_SMMUREG_H_ */ 477