1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2019-2020 Ruslan Bukin <br@bsdpad.com> 5 * 6 * This software was developed by SRI International and the University of 7 * Cambridge Computer Laboratory (Department of Computer Science and 8 * Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the 9 * DARPA SSITH research programme. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 */ 32 33 /* 34 * Hardware overview. 35 * 36 * An incoming transaction from a peripheral device has an address, size, 37 * attributes and StreamID. 38 * 39 * In case of PCI-based devices, StreamID is a PCI rid. 40 * 41 * The StreamID is used to select a Stream Table Entry (STE) in a Stream table, 42 * which contains per-device configuration. 43 * 44 * Stream table is a linear or 2-level walk table (this driver supports both). 45 * Note that a linear table could occupy 1GB or more of memory depending on 46 * sid_bits value. 47 * 48 * STE is used to locate a Context Descriptor, which is a struct in memory 49 * that describes stages of translation, translation table type, pointer to 50 * level 0 of page tables, ASID, etc. 51 * 52 * Hardware supports two stages of translation: Stage1 (S1) and Stage2 (S2): 53 * o S1 is used for the host machine traffic translation 54 * o S2 is for a hypervisor 55 * 56 * This driver enables S1 stage with standard AArch64 page tables. 57 * 58 * Note that SMMU does not share TLB with a main CPU. 59 * Command queue is used by this driver to Invalidate SMMU TLB, STE cache. 60 * 61 * An arm64 SoC could have more than one SMMU instance. 62 * ACPI IORT table describes which SMMU unit is assigned for a particular 63 * peripheral device. 64 * 65 * Queues. 66 * 67 * Register interface and Memory-based circular buffer queues are used 68 * to interface SMMU. 69 * 70 * These are a Command queue for commands to send to the SMMU and an Event 71 * queue for event/fault reports from the SMMU. Optionally PRI queue is 72 * designed for PCIe page requests reception. 73 * 74 * Note that not every hardware supports PRI services. For instance they were 75 * not found in Neoverse N1 SDP machine. 76 * (This drivers does not implement PRI queue.) 77 * 78 * All SMMU queues are arranged as circular buffers in memory. They are used 79 * in a producer-consumer fashion so that an output queue contains data 80 * produced by the SMMU and consumed by software. 81 * An input queue contains data produced by software, consumed by the SMMU. 82 * 83 * Interrupts. 84 * 85 * Interrupts are not required by this driver for normal operation. 86 * The standard wired interrupt is only triggered when an event comes from 87 * the SMMU, which is only in a case of errors (e.g. translation fault). 88 */ 89 90 #include "opt_platform.h" 91 #include "opt_acpi.h" 92 93 #include <sys/param.h> 94 #include <sys/bitstring.h> 95 #include <sys/bus.h> 96 #include <sys/kernel.h> 97 #include <sys/malloc.h> 98 #include <sys/mutex.h> 99 #include <sys/rman.h> 100 #include <sys/lock.h> 101 #include <sys/sysctl.h> 102 #include <sys/tree.h> 103 #include <sys/taskqueue.h> 104 #include <vm/vm.h> 105 #include <vm/vm_page.h> 106 #ifdef DEV_ACPI 107 #include <contrib/dev/acpica/include/acpi.h> 108 #include <dev/acpica/acpivar.h> 109 #endif 110 #include <dev/pci/pcireg.h> 111 #include <dev/pci/pcivar.h> 112 #include <dev/iommu/iommu.h> 113 #include <arm64/iommu/iommu_pmap.h> 114 115 #include <machine/bus.h> 116 117 #ifdef FDT 118 #include <dev/fdt/fdt_common.h> 119 #include <dev/ofw/ofw_bus.h> 120 #include <dev/ofw/ofw_bus_subr.h> 121 #endif 122 123 #include "iommu.h" 124 #include "iommu_if.h" 125 126 #include "smmureg.h" 127 #include "smmuvar.h" 128 129 #define STRTAB_L1_SZ_SHIFT 20 130 #define STRTAB_SPLIT 8 131 132 #define STRTAB_L1_DESC_L2PTR_M (0x3fffffffffff << 6) 133 #define STRTAB_L1_DESC_DWORDS 1 134 135 #define STRTAB_STE_DWORDS 8 136 137 #define CMDQ_ENTRY_DWORDS 2 138 #define EVTQ_ENTRY_DWORDS 4 139 #define PRIQ_ENTRY_DWORDS 2 140 141 #define CD_DWORDS 8 142 143 #define Q_WRP(q, p) ((p) & (1 << (q)->size_log2)) 144 #define Q_IDX(q, p) ((p) & ((1 << (q)->size_log2) - 1)) 145 #define Q_OVF(p) ((p) & (1 << 31)) /* Event queue overflowed */ 146 147 #define SMMU_Q_ALIGN (64 * 1024) 148 149 #define MAXADDR_48BIT 0xFFFFFFFFFFFFUL 150 #define MAXADDR_52BIT 0xFFFFFFFFFFFFFUL 151 152 static struct resource_spec smmu_spec[] = { 153 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 154 { SYS_RES_IRQ, 0, RF_ACTIVE }, 155 { SYS_RES_IRQ, 1, RF_ACTIVE | RF_OPTIONAL }, 156 { SYS_RES_IRQ, 2, RF_ACTIVE }, 157 { SYS_RES_IRQ, 3, RF_ACTIVE }, 158 RESOURCE_SPEC_END 159 }; 160 161 MALLOC_DEFINE(M_SMMU, "SMMU", SMMU_DEVSTR); 162 163 #define dprintf(fmt, ...) 164 165 struct smmu_event { 166 int ident; 167 char *str; 168 char *msg; 169 }; 170 171 static struct smmu_event events[] = { 172 { 0x01, "F_UUT", 173 "Unsupported Upstream Transaction."}, 174 { 0x02, "C_BAD_STREAMID", 175 "Transaction StreamID out of range."}, 176 { 0x03, "F_STE_FETCH", 177 "Fetch of STE caused external abort."}, 178 { 0x04, "C_BAD_STE", 179 "Used STE invalid."}, 180 { 0x05, "F_BAD_ATS_TREQ", 181 "Address Translation Request disallowed for a StreamID " 182 "and a PCIe ATS Translation Request received."}, 183 { 0x06, "F_STREAM_DISABLED", 184 "The STE of a transaction marks non-substream transactions " 185 "disabled."}, 186 { 0x07, "F_TRANSL_FORBIDDEN", 187 "An incoming PCIe transaction is marked Translated but " 188 "SMMU bypass is disallowed for this StreamID."}, 189 { 0x08, "C_BAD_SUBSTREAMID", 190 "Incoming SubstreamID present, but configuration is invalid."}, 191 { 0x09, "F_CD_FETCH", 192 "Fetch of CD caused external abort."}, 193 { 0x0a, "C_BAD_CD", 194 "Fetched CD invalid."}, 195 { 0x0b, "F_WALK_EABT", 196 "An external abort occurred fetching (or updating) " 197 "a translation table descriptor."}, 198 { 0x10, "F_TRANSLATION", 199 "Translation fault."}, 200 { 0x11, "F_ADDR_SIZE", 201 "Address Size fault."}, 202 { 0x12, "F_ACCESS", 203 "Access flag fault due to AF == 0 in a page or block TTD."}, 204 { 0x13, "F_PERMISSION", 205 "Permission fault occurred on page access."}, 206 { 0x20, "F_TLB_CONFLICT", 207 "A TLB conflict occurred because of the transaction."}, 208 { 0x21, "F_CFG_CONFLICT", 209 "A configuration cache conflict occurred due to " 210 "the transaction."}, 211 { 0x24, "E_PAGE_REQUEST", 212 "Speculative page request hint."}, 213 { 0x25, "F_VMS_FETCH", 214 "Fetch of VMS caused external abort."}, 215 { 0, NULL, NULL }, 216 }; 217 218 static int 219 smmu_q_has_space(struct smmu_queue *q) 220 { 221 222 /* 223 * See 6.3.27 SMMU_CMDQ_PROD 224 * 225 * There is space in the queue for additional commands if: 226 * SMMU_CMDQ_CONS.RD != SMMU_CMDQ_PROD.WR || 227 * SMMU_CMDQ_CONS.RD_WRAP == SMMU_CMDQ_PROD.WR_WRAP 228 */ 229 230 if (Q_IDX(q, q->lc.cons) != Q_IDX(q, q->lc.prod) || 231 Q_WRP(q, q->lc.cons) == Q_WRP(q, q->lc.prod)) 232 return (1); 233 234 return (0); 235 } 236 237 static int 238 smmu_q_empty(struct smmu_queue *q) 239 { 240 241 if (Q_IDX(q, q->lc.cons) == Q_IDX(q, q->lc.prod) && 242 Q_WRP(q, q->lc.cons) == Q_WRP(q, q->lc.prod)) 243 return (1); 244 245 return (0); 246 } 247 248 static int __unused 249 smmu_q_consumed(struct smmu_queue *q, uint32_t prod) 250 { 251 252 if ((Q_WRP(q, q->lc.cons) == Q_WRP(q, prod)) && 253 (Q_IDX(q, q->lc.cons) >= Q_IDX(q, prod))) 254 return (1); 255 256 if ((Q_WRP(q, q->lc.cons) != Q_WRP(q, prod)) && 257 (Q_IDX(q, q->lc.cons) <= Q_IDX(q, prod))) 258 return (1); 259 260 return (0); 261 } 262 263 static uint32_t 264 smmu_q_inc_cons(struct smmu_queue *q) 265 { 266 uint32_t cons; 267 uint32_t val; 268 269 cons = (Q_WRP(q, q->lc.cons) | Q_IDX(q, q->lc.cons)) + 1; 270 val = (Q_OVF(q->lc.cons) | Q_WRP(q, cons) | Q_IDX(q, cons)); 271 272 return (val); 273 } 274 275 static uint32_t 276 smmu_q_inc_prod(struct smmu_queue *q) 277 { 278 uint32_t prod; 279 uint32_t val; 280 281 prod = (Q_WRP(q, q->lc.prod) | Q_IDX(q, q->lc.prod)) + 1; 282 val = (Q_OVF(q->lc.prod) | Q_WRP(q, prod) | Q_IDX(q, prod)); 283 284 return (val); 285 } 286 287 static int 288 smmu_write_ack(struct smmu_softc *sc, uint32_t reg, 289 uint32_t reg_ack, uint32_t val) 290 { 291 uint32_t v; 292 int timeout; 293 294 timeout = 100000; 295 296 bus_write_4(sc->res[0], reg, val); 297 298 do { 299 v = bus_read_4(sc->res[0], reg_ack); 300 if (v == val) 301 break; 302 } while (timeout--); 303 304 if (timeout <= 0) { 305 device_printf(sc->dev, "Failed to write reg.\n"); 306 return (-1); 307 } 308 309 return (0); 310 } 311 312 static int 313 smmu_init_queue(struct smmu_softc *sc, struct smmu_queue *q, 314 uint32_t prod_off, uint32_t cons_off, uint32_t dwords) 315 { 316 int sz; 317 318 sz = (1 << q->size_log2) * dwords * 8; 319 320 /* Set up the command circular buffer */ 321 q->vaddr = contigmalloc(sz, M_SMMU, 322 M_WAITOK | M_ZERO, 0, (1ul << 48) - 1, SMMU_Q_ALIGN, 0); 323 if (q->vaddr == NULL) { 324 device_printf(sc->dev, "failed to allocate %d bytes\n", sz); 325 return (-1); 326 } 327 328 q->prod_off = prod_off; 329 q->cons_off = cons_off; 330 q->paddr = vtophys(q->vaddr); 331 332 q->base = CMDQ_BASE_RA | EVENTQ_BASE_WA | PRIQ_BASE_WA; 333 q->base |= q->paddr & Q_BASE_ADDR_M; 334 q->base |= q->size_log2 << Q_LOG2SIZE_S; 335 336 return (0); 337 } 338 339 static int 340 smmu_init_queues(struct smmu_softc *sc) 341 { 342 int err; 343 344 /* Command queue. */ 345 err = smmu_init_queue(sc, &sc->cmdq, 346 SMMU_CMDQ_PROD, SMMU_CMDQ_CONS, CMDQ_ENTRY_DWORDS); 347 if (err) 348 return (ENXIO); 349 350 /* Event queue. */ 351 err = smmu_init_queue(sc, &sc->evtq, 352 SMMU_EVENTQ_PROD, SMMU_EVENTQ_CONS, EVTQ_ENTRY_DWORDS); 353 if (err) 354 return (ENXIO); 355 356 if (!(sc->features & SMMU_FEATURE_PRI)) 357 return (0); 358 359 /* PRI queue. */ 360 err = smmu_init_queue(sc, &sc->priq, 361 SMMU_PRIQ_PROD, SMMU_PRIQ_CONS, PRIQ_ENTRY_DWORDS); 362 if (err) 363 return (ENXIO); 364 365 return (0); 366 } 367 368 /* 369 * Dump 2LVL or linear STE. 370 */ 371 static void 372 smmu_dump_ste(struct smmu_softc *sc, int sid) 373 { 374 struct smmu_strtab *strtab; 375 struct l1_desc *l1_desc; 376 uint64_t *ste, *l1; 377 int i; 378 379 strtab = &sc->strtab; 380 381 if (sc->features & SMMU_FEATURE_2_LVL_STREAM_TABLE) { 382 i = sid >> STRTAB_SPLIT; 383 l1 = (void *)((uint64_t)strtab->vaddr + 384 STRTAB_L1_DESC_DWORDS * 8 * i); 385 device_printf(sc->dev, "L1 ste == %lx\n", l1[0]); 386 387 l1_desc = &strtab->l1[i]; 388 ste = l1_desc->va; 389 if (ste == NULL) /* L2 is not initialized */ 390 return; 391 } else { 392 ste = (void *)((uint64_t)strtab->vaddr + 393 sid * (STRTAB_STE_DWORDS << 3)); 394 } 395 396 /* Dump L2 or linear STE. */ 397 for (i = 0; i < STRTAB_STE_DWORDS; i++) 398 device_printf(sc->dev, "ste[%d] == %lx\n", i, ste[i]); 399 } 400 401 static void __unused 402 smmu_dump_cd(struct smmu_softc *sc, struct smmu_cd *cd) 403 { 404 uint64_t *vaddr; 405 int i; 406 407 device_printf(sc->dev, "%s\n", __func__); 408 409 vaddr = cd->vaddr; 410 for (i = 0; i < CD_DWORDS; i++) 411 device_printf(sc->dev, "cd[%d] == %lx\n", i, vaddr[i]); 412 } 413 414 static void 415 smmu_evtq_dequeue(struct smmu_softc *sc, uint32_t *evt) 416 { 417 struct smmu_queue *evtq; 418 void *entry_addr; 419 420 evtq = &sc->evtq; 421 422 evtq->lc.val = bus_read_8(sc->res[0], evtq->prod_off); 423 entry_addr = (void *)((uint64_t)evtq->vaddr + 424 evtq->lc.cons * EVTQ_ENTRY_DWORDS * 8); 425 memcpy(evt, entry_addr, EVTQ_ENTRY_DWORDS * 8); 426 evtq->lc.cons = smmu_q_inc_cons(evtq); 427 bus_write_4(sc->res[0], evtq->cons_off, evtq->lc.cons); 428 } 429 430 static void 431 smmu_print_event(struct smmu_softc *sc, uint32_t *evt) 432 { 433 struct smmu_event *ev; 434 uintptr_t input_addr; 435 uint8_t event_id; 436 device_t dev; 437 int sid; 438 int i; 439 440 dev = sc->dev; 441 442 ev = NULL; 443 event_id = evt[0] & 0xff; 444 for (i = 0; events[i].ident != 0; i++) { 445 if (events[i].ident == event_id) { 446 ev = &events[i]; 447 break; 448 } 449 } 450 451 sid = evt[1]; 452 input_addr = evt[5]; 453 input_addr <<= 32; 454 input_addr |= evt[4]; 455 456 if (smmu_quirks_check(dev, sid, event_id, input_addr)) { 457 /* The event is known. Don't print anything. */ 458 return; 459 } 460 461 if (ev) { 462 device_printf(sc->dev, 463 "Event %s (%s) received.\n", ev->str, ev->msg); 464 } else 465 device_printf(sc->dev, "Event 0x%x received\n", event_id); 466 467 device_printf(sc->dev, "SID %x, Input Address: %jx\n", 468 sid, input_addr); 469 470 for (i = 0; i < 8; i++) 471 device_printf(sc->dev, "evt[%d] %x\n", i, evt[i]); 472 473 smmu_dump_ste(sc, sid); 474 } 475 476 static void 477 make_cmd(struct smmu_softc *sc, uint64_t *cmd, 478 struct smmu_cmdq_entry *entry) 479 { 480 481 memset(cmd, 0, CMDQ_ENTRY_DWORDS * 8); 482 cmd[0] = entry->opcode << CMD_QUEUE_OPCODE_S; 483 484 switch (entry->opcode) { 485 case CMD_TLBI_NH_VA: 486 cmd[0] |= (uint64_t)entry->tlbi.asid << TLBI_0_ASID_S; 487 cmd[1] = entry->tlbi.addr & TLBI_1_ADDR_M; 488 if (entry->tlbi.leaf) { 489 /* 490 * Leaf flag means that only cached entries 491 * for the last level of translation table walk 492 * are required to be invalidated. 493 */ 494 cmd[1] |= TLBI_1_LEAF; 495 } 496 break; 497 case CMD_TLBI_NH_ASID: 498 cmd[0] |= (uint64_t)entry->tlbi.asid << TLBI_0_ASID_S; 499 break; 500 case CMD_TLBI_NSNH_ALL: 501 case CMD_TLBI_NH_ALL: 502 case CMD_TLBI_EL2_ALL: 503 break; 504 case CMD_CFGI_CD: 505 cmd[0] |= ((uint64_t)entry->cfgi.ssid << CFGI_0_SSID_S); 506 /* FALLTROUGH */ 507 case CMD_CFGI_STE: 508 cmd[0] |= ((uint64_t)entry->cfgi.sid << CFGI_0_STE_SID_S); 509 cmd[1] |= ((uint64_t)entry->cfgi.leaf << CFGI_1_LEAF_S); 510 break; 511 case CMD_CFGI_STE_RANGE: 512 cmd[1] = (31 << CFGI_1_STE_RANGE_S); 513 break; 514 case CMD_SYNC: 515 cmd[0] |= SYNC_0_MSH_IS | SYNC_0_MSIATTR_OIWB; 516 if (entry->sync.msiaddr) { 517 cmd[0] |= SYNC_0_CS_SIG_IRQ; 518 cmd[1] |= (entry->sync.msiaddr & SYNC_1_MSIADDRESS_M); 519 } else 520 cmd[0] |= SYNC_0_CS_SIG_SEV; 521 break; 522 case CMD_PREFETCH_CONFIG: 523 cmd[0] |= ((uint64_t)entry->prefetch.sid << PREFETCH_0_SID_S); 524 break; 525 }; 526 } 527 528 static void 529 smmu_cmdq_enqueue_cmd(struct smmu_softc *sc, struct smmu_cmdq_entry *entry) 530 { 531 uint64_t cmd[CMDQ_ENTRY_DWORDS]; 532 struct smmu_queue *cmdq; 533 void *entry_addr; 534 535 cmdq = &sc->cmdq; 536 537 make_cmd(sc, cmd, entry); 538 539 SMMU_LOCK(sc); 540 541 /* Ensure that a space is available. */ 542 do { 543 cmdq->lc.cons = bus_read_4(sc->res[0], cmdq->cons_off); 544 } while (smmu_q_has_space(cmdq) == 0); 545 546 /* Write the command to the current prod entry. */ 547 entry_addr = (void *)((uint64_t)cmdq->vaddr + 548 Q_IDX(cmdq, cmdq->lc.prod) * CMDQ_ENTRY_DWORDS * 8); 549 memcpy(entry_addr, cmd, CMDQ_ENTRY_DWORDS * 8); 550 551 /* Increment prod index. */ 552 cmdq->lc.prod = smmu_q_inc_prod(cmdq); 553 bus_write_4(sc->res[0], cmdq->prod_off, cmdq->lc.prod); 554 555 SMMU_UNLOCK(sc); 556 } 557 558 static void __unused 559 smmu_poll_until_consumed(struct smmu_softc *sc, struct smmu_queue *q) 560 { 561 562 while (1) { 563 q->lc.val = bus_read_8(sc->res[0], q->prod_off); 564 if (smmu_q_empty(q)) 565 break; 566 cpu_spinwait(); 567 } 568 } 569 570 static int 571 smmu_sync(struct smmu_softc *sc) 572 { 573 struct smmu_cmdq_entry cmd; 574 struct smmu_queue *q; 575 uint32_t *base; 576 int timeout; 577 int prod; 578 579 q = &sc->cmdq; 580 prod = q->lc.prod; 581 582 /* Enqueue sync command. */ 583 cmd.opcode = CMD_SYNC; 584 cmd.sync.msiaddr = q->paddr + Q_IDX(q, prod) * CMDQ_ENTRY_DWORDS * 8; 585 smmu_cmdq_enqueue_cmd(sc, &cmd); 586 587 /* Wait for the sync completion. */ 588 base = (void *)((uint64_t)q->vaddr + 589 Q_IDX(q, prod) * CMDQ_ENTRY_DWORDS * 8); 590 591 /* 592 * It takes around 200 loops (6 instructions each) 593 * on Neoverse N1 to complete the sync. 594 */ 595 timeout = 10000; 596 597 do { 598 if (*base == 0) { 599 /* MSI write completed. */ 600 break; 601 } 602 cpu_spinwait(); 603 } while (timeout--); 604 605 if (timeout < 0) 606 device_printf(sc->dev, "Failed to sync\n"); 607 608 return (0); 609 } 610 611 static int 612 smmu_sync_cd(struct smmu_softc *sc, int sid, int ssid, bool leaf) 613 { 614 struct smmu_cmdq_entry cmd; 615 616 cmd.opcode = CMD_CFGI_CD; 617 cmd.cfgi.sid = sid; 618 cmd.cfgi.ssid = ssid; 619 cmd.cfgi.leaf = leaf; 620 smmu_cmdq_enqueue_cmd(sc, &cmd); 621 622 return (0); 623 } 624 625 static void 626 smmu_invalidate_all_sid(struct smmu_softc *sc) 627 { 628 struct smmu_cmdq_entry cmd; 629 630 /* Invalidate cached config */ 631 cmd.opcode = CMD_CFGI_STE_RANGE; 632 smmu_cmdq_enqueue_cmd(sc, &cmd); 633 smmu_sync(sc); 634 } 635 636 static void 637 smmu_tlbi_all(struct smmu_softc *sc) 638 { 639 struct smmu_cmdq_entry cmd; 640 641 /* Invalidate entire TLB */ 642 cmd.opcode = CMD_TLBI_NSNH_ALL; 643 smmu_cmdq_enqueue_cmd(sc, &cmd); 644 smmu_sync(sc); 645 } 646 647 static void 648 smmu_tlbi_asid(struct smmu_softc *sc, uint16_t asid) 649 { 650 struct smmu_cmdq_entry cmd; 651 652 /* Invalidate TLB for an ASID. */ 653 cmd.opcode = CMD_TLBI_NH_ASID; 654 cmd.tlbi.asid = asid; 655 smmu_cmdq_enqueue_cmd(sc, &cmd); 656 smmu_sync(sc); 657 } 658 659 static void 660 smmu_tlbi_va(struct smmu_softc *sc, vm_offset_t va, uint16_t asid) 661 { 662 struct smmu_cmdq_entry cmd; 663 664 /* Invalidate specific range */ 665 cmd.opcode = CMD_TLBI_NH_VA; 666 cmd.tlbi.asid = asid; 667 cmd.tlbi.vmid = 0; 668 cmd.tlbi.leaf = true; /* We change only L3. */ 669 cmd.tlbi.addr = va; 670 smmu_cmdq_enqueue_cmd(sc, &cmd); 671 } 672 673 static void 674 smmu_invalidate_sid(struct smmu_softc *sc, uint32_t sid) 675 { 676 struct smmu_cmdq_entry cmd; 677 678 /* Invalidate cached config */ 679 cmd.opcode = CMD_CFGI_STE; 680 cmd.cfgi.sid = sid; 681 smmu_cmdq_enqueue_cmd(sc, &cmd); 682 smmu_sync(sc); 683 } 684 685 static void 686 smmu_prefetch_sid(struct smmu_softc *sc, uint32_t sid) 687 { 688 struct smmu_cmdq_entry cmd; 689 690 cmd.opcode = CMD_PREFETCH_CONFIG; 691 cmd.prefetch.sid = sid; 692 smmu_cmdq_enqueue_cmd(sc, &cmd); 693 smmu_sync(sc); 694 } 695 696 /* 697 * Init STE in bypass mode. Traffic is not translated for the sid. 698 */ 699 static void 700 smmu_init_ste_bypass(struct smmu_softc *sc, uint32_t sid, uint64_t *ste) 701 { 702 uint64_t val; 703 704 val = STE0_VALID | STE0_CONFIG_BYPASS; 705 706 ste[1] = STE1_SHCFG_INCOMING | STE1_EATS_FULLATS; 707 ste[2] = 0; 708 ste[3] = 0; 709 ste[4] = 0; 710 ste[5] = 0; 711 ste[6] = 0; 712 ste[7] = 0; 713 714 smmu_invalidate_sid(sc, sid); 715 ste[0] = val; 716 dsb(sy); 717 smmu_invalidate_sid(sc, sid); 718 719 smmu_prefetch_sid(sc, sid); 720 } 721 722 /* 723 * Enable Stage1 (S1) translation for the sid. 724 */ 725 static int 726 smmu_init_ste_s1(struct smmu_softc *sc, struct smmu_cd *cd, 727 uint32_t sid, uint64_t *ste) 728 { 729 uint64_t val; 730 731 val = STE0_VALID; 732 733 /* S1 */ 734 ste[1] = STE1_EATS_FULLATS | 735 STE1_S1CSH_IS | 736 STE1_S1CIR_WBRA | 737 STE1_S1COR_WBRA | 738 STE1_STRW_NS_EL1; 739 ste[2] = 0; 740 ste[3] = 0; 741 ste[4] = 0; 742 ste[5] = 0; 743 ste[6] = 0; 744 ste[7] = 0; 745 746 if (sc->features & SMMU_FEATURE_STALL && 747 ((sc->features & SMMU_FEATURE_STALL_FORCE) == 0)) 748 ste[1] |= STE1_S1STALLD; 749 750 /* Configure STE */ 751 val |= (cd->paddr & STE0_S1CONTEXTPTR_M); 752 val |= STE0_CONFIG_S1_TRANS; 753 754 smmu_invalidate_sid(sc, sid); 755 756 /* The STE[0] has to be written in a single blast, last of all. */ 757 ste[0] = val; 758 dsb(sy); 759 760 smmu_invalidate_sid(sc, sid); 761 smmu_sync_cd(sc, sid, 0, true); 762 smmu_invalidate_sid(sc, sid); 763 764 /* The sid will be used soon most likely. */ 765 smmu_prefetch_sid(sc, sid); 766 767 return (0); 768 } 769 770 static uint64_t * 771 smmu_get_ste_addr(struct smmu_softc *sc, int sid) 772 { 773 struct smmu_strtab *strtab; 774 struct l1_desc *l1_desc; 775 uint64_t *addr; 776 777 strtab = &sc->strtab; 778 779 if (sc->features & SMMU_FEATURE_2_LVL_STREAM_TABLE) { 780 l1_desc = &strtab->l1[sid >> STRTAB_SPLIT]; 781 addr = l1_desc->va; 782 addr += (sid & ((1 << STRTAB_SPLIT) - 1)) * STRTAB_STE_DWORDS; 783 } else { 784 addr = (void *)((uint64_t)strtab->vaddr + 785 STRTAB_STE_DWORDS * 8 * sid); 786 }; 787 788 return (addr); 789 } 790 791 static int 792 smmu_init_ste(struct smmu_softc *sc, struct smmu_cd *cd, int sid, bool bypass) 793 { 794 uint64_t *addr; 795 796 addr = smmu_get_ste_addr(sc, sid); 797 798 if (bypass) 799 smmu_init_ste_bypass(sc, sid, addr); 800 else 801 smmu_init_ste_s1(sc, cd, sid, addr); 802 803 smmu_sync(sc); 804 805 return (0); 806 } 807 808 static void 809 smmu_deinit_ste(struct smmu_softc *sc, int sid) 810 { 811 uint64_t *ste; 812 813 ste = smmu_get_ste_addr(sc, sid); 814 ste[0] = 0; 815 816 smmu_invalidate_sid(sc, sid); 817 smmu_sync_cd(sc, sid, 0, true); 818 smmu_invalidate_sid(sc, sid); 819 820 smmu_sync(sc); 821 } 822 823 static int 824 smmu_init_cd(struct smmu_softc *sc, struct smmu_domain *domain) 825 { 826 vm_paddr_t paddr; 827 uint64_t *ptr; 828 uint64_t val; 829 vm_size_t size; 830 struct smmu_cd *cd; 831 struct smmu_pmap *p; 832 833 size = 1 * (CD_DWORDS << 3); 834 835 p = &domain->p; 836 cd = domain->cd = malloc(sizeof(struct smmu_cd), 837 M_SMMU, M_WAITOK | M_ZERO); 838 839 cd->vaddr = contigmalloc(size, M_SMMU, 840 M_WAITOK | M_ZERO, /* flags */ 841 0, /* low */ 842 (1ul << 40) - 1, /* high */ 843 size, /* alignment */ 844 0); /* boundary */ 845 if (cd->vaddr == NULL) { 846 device_printf(sc->dev, "Failed to allocate CD\n"); 847 return (ENXIO); 848 } 849 850 cd->paddr = vtophys(cd->vaddr); 851 852 ptr = cd->vaddr; 853 854 val = CD0_VALID; 855 val |= CD0_AA64; 856 val |= CD0_R; 857 val |= CD0_A; 858 val |= CD0_ASET; 859 val |= (uint64_t)domain->asid << CD0_ASID_S; 860 val |= CD0_TG0_4KB; 861 val |= CD0_EPD1; /* Disable TT1 */ 862 val |= ((64 - sc->ias) << CD0_T0SZ_S); 863 val |= CD0_IPS_48BITS; 864 865 paddr = p->sp_l0_paddr & CD1_TTB0_M; 866 KASSERT(paddr == p->sp_l0_paddr, ("bad allocation 1")); 867 868 ptr[1] = paddr; 869 ptr[2] = 0; 870 ptr[3] = MAIR_ATTR(MAIR_DEVICE_nGnRnE, VM_MEMATTR_DEVICE) | 871 MAIR_ATTR(MAIR_NORMAL_NC, VM_MEMATTR_UNCACHEABLE) | 872 MAIR_ATTR(MAIR_NORMAL_WB, VM_MEMATTR_WRITE_BACK) | 873 MAIR_ATTR(MAIR_NORMAL_WT, VM_MEMATTR_WRITE_THROUGH); 874 875 /* Install the CD. */ 876 ptr[0] = val; 877 878 return (0); 879 } 880 881 static int 882 smmu_init_strtab_linear(struct smmu_softc *sc) 883 { 884 struct smmu_strtab *strtab; 885 vm_paddr_t base; 886 uint32_t size; 887 uint64_t reg; 888 889 strtab = &sc->strtab; 890 strtab->num_l1_entries = (1 << sc->sid_bits); 891 892 size = strtab->num_l1_entries * (STRTAB_STE_DWORDS << 3); 893 894 if (bootverbose) 895 device_printf(sc->dev, 896 "%s: linear strtab size %d, num_l1_entries %d\n", 897 __func__, size, strtab->num_l1_entries); 898 899 strtab->vaddr = contigmalloc(size, M_SMMU, 900 M_WAITOK | M_ZERO, /* flags */ 901 0, /* low */ 902 (1ul << 48) - 1, /* high */ 903 size, /* alignment */ 904 0); /* boundary */ 905 if (strtab->vaddr == NULL) { 906 device_printf(sc->dev, "failed to allocate strtab\n"); 907 return (ENXIO); 908 } 909 910 reg = STRTAB_BASE_CFG_FMT_LINEAR; 911 reg |= sc->sid_bits << STRTAB_BASE_CFG_LOG2SIZE_S; 912 strtab->base_cfg = (uint32_t)reg; 913 914 base = vtophys(strtab->vaddr); 915 916 reg = base & STRTAB_BASE_ADDR_M; 917 KASSERT(reg == base, ("bad allocation 2")); 918 reg |= STRTAB_BASE_RA; 919 strtab->base = reg; 920 921 return (0); 922 } 923 924 static int 925 smmu_init_strtab_2lvl(struct smmu_softc *sc) 926 { 927 struct smmu_strtab *strtab; 928 vm_paddr_t base; 929 uint64_t reg_base; 930 uint32_t l1size; 931 uint32_t size; 932 uint32_t reg; 933 int sz; 934 935 strtab = &sc->strtab; 936 937 size = STRTAB_L1_SZ_SHIFT - (ilog2(STRTAB_L1_DESC_DWORDS) + 3); 938 size = min(size, sc->sid_bits - STRTAB_SPLIT); 939 strtab->num_l1_entries = (1 << size); 940 size += STRTAB_SPLIT; 941 942 l1size = strtab->num_l1_entries * (STRTAB_L1_DESC_DWORDS << 3); 943 944 if (bootverbose) 945 device_printf(sc->dev, 946 "%s: size %d, l1 entries %d, l1size %d\n", 947 __func__, size, strtab->num_l1_entries, l1size); 948 949 strtab->vaddr = contigmalloc(l1size, M_SMMU, 950 M_WAITOK | M_ZERO, /* flags */ 951 0, /* low */ 952 (1ul << 48) - 1, /* high */ 953 l1size, /* alignment */ 954 0); /* boundary */ 955 if (strtab->vaddr == NULL) { 956 device_printf(sc->dev, "Failed to allocate 2lvl strtab.\n"); 957 return (ENOMEM); 958 } 959 960 sz = strtab->num_l1_entries * sizeof(struct l1_desc); 961 962 strtab->l1 = malloc(sz, M_SMMU, M_WAITOK | M_ZERO); 963 964 reg = STRTAB_BASE_CFG_FMT_2LVL; 965 reg |= size << STRTAB_BASE_CFG_LOG2SIZE_S; 966 reg |= STRTAB_SPLIT << STRTAB_BASE_CFG_SPLIT_S; 967 strtab->base_cfg = (uint32_t)reg; 968 969 base = vtophys(strtab->vaddr); 970 971 reg_base = base & STRTAB_BASE_ADDR_M; 972 KASSERT(reg_base == base, ("bad allocation 3")); 973 reg_base |= STRTAB_BASE_RA; 974 strtab->base = reg_base; 975 976 return (0); 977 } 978 979 static int 980 smmu_init_strtab(struct smmu_softc *sc) 981 { 982 int error; 983 984 if (sc->features & SMMU_FEATURE_2_LVL_STREAM_TABLE) 985 error = smmu_init_strtab_2lvl(sc); 986 else 987 error = smmu_init_strtab_linear(sc); 988 989 return (error); 990 } 991 992 static int 993 smmu_init_l1_entry(struct smmu_softc *sc, int sid) 994 { 995 struct smmu_strtab *strtab; 996 struct l1_desc *l1_desc; 997 uint64_t *addr; 998 uint64_t val; 999 size_t size; 1000 int i; 1001 1002 strtab = &sc->strtab; 1003 l1_desc = &strtab->l1[sid >> STRTAB_SPLIT]; 1004 if (l1_desc->va) { 1005 /* Already allocated. */ 1006 return (0); 1007 } 1008 1009 size = 1 << (STRTAB_SPLIT + ilog2(STRTAB_STE_DWORDS) + 3); 1010 1011 l1_desc->span = STRTAB_SPLIT + 1; 1012 l1_desc->va = contigmalloc(size, M_SMMU, 1013 M_WAITOK | M_ZERO, /* flags */ 1014 0, /* low */ 1015 (1ul << 48) - 1, /* high */ 1016 size, /* alignment */ 1017 0); /* boundary */ 1018 if (l1_desc->va == NULL) { 1019 device_printf(sc->dev, "failed to allocate l2 entry\n"); 1020 return (ENXIO); 1021 } 1022 1023 l1_desc->pa = vtophys(l1_desc->va); 1024 1025 i = sid >> STRTAB_SPLIT; 1026 addr = (void *)((uint64_t)strtab->vaddr + 1027 STRTAB_L1_DESC_DWORDS * 8 * i); 1028 1029 /* Install the L1 entry. */ 1030 val = l1_desc->pa & STRTAB_L1_DESC_L2PTR_M; 1031 KASSERT(val == l1_desc->pa, ("bad allocation 4")); 1032 val |= l1_desc->span; 1033 *addr = val; 1034 1035 return (0); 1036 } 1037 1038 static void __unused 1039 smmu_deinit_l1_entry(struct smmu_softc *sc, int sid) 1040 { 1041 struct smmu_strtab *strtab; 1042 struct l1_desc *l1_desc; 1043 uint64_t *addr; 1044 int i; 1045 1046 strtab = &sc->strtab; 1047 1048 i = sid >> STRTAB_SPLIT; 1049 addr = (void *)((uint64_t)strtab->vaddr + 1050 STRTAB_L1_DESC_DWORDS * 8 * i); 1051 *addr = 0; 1052 1053 l1_desc = &strtab->l1[sid >> STRTAB_SPLIT]; 1054 free(l1_desc->va, M_SMMU); 1055 } 1056 1057 static int 1058 smmu_disable(struct smmu_softc *sc) 1059 { 1060 uint32_t reg; 1061 int error; 1062 1063 /* Disable SMMU */ 1064 reg = bus_read_4(sc->res[0], SMMU_CR0); 1065 reg &= ~CR0_SMMUEN; 1066 error = smmu_write_ack(sc, SMMU_CR0, SMMU_CR0ACK, reg); 1067 if (error) 1068 device_printf(sc->dev, "Could not disable SMMU.\n"); 1069 1070 return (0); 1071 } 1072 1073 static int 1074 smmu_event_intr(void *arg) 1075 { 1076 uint32_t evt[EVTQ_ENTRY_DWORDS * 2]; 1077 struct smmu_softc *sc; 1078 1079 sc = arg; 1080 1081 do { 1082 smmu_evtq_dequeue(sc, evt); 1083 smmu_print_event(sc, evt); 1084 } while (!smmu_q_empty(&sc->evtq)); 1085 1086 return (FILTER_HANDLED); 1087 } 1088 1089 static int __unused 1090 smmu_sync_intr(void *arg) 1091 { 1092 struct smmu_softc *sc; 1093 1094 sc = arg; 1095 1096 device_printf(sc->dev, "%s\n", __func__); 1097 1098 return (FILTER_HANDLED); 1099 } 1100 1101 static int 1102 smmu_gerr_intr(void *arg) 1103 { 1104 struct smmu_softc *sc; 1105 1106 sc = arg; 1107 1108 device_printf(sc->dev, "SMMU Global Error\n"); 1109 1110 return (FILTER_HANDLED); 1111 } 1112 1113 static int 1114 smmu_enable_interrupts(struct smmu_softc *sc) 1115 { 1116 uint32_t reg; 1117 int error; 1118 1119 /* Disable MSI. */ 1120 bus_write_8(sc->res[0], SMMU_GERROR_IRQ_CFG0, 0); 1121 bus_write_4(sc->res[0], SMMU_GERROR_IRQ_CFG1, 0); 1122 bus_write_4(sc->res[0], SMMU_GERROR_IRQ_CFG2, 0); 1123 1124 bus_write_8(sc->res[0], SMMU_EVENTQ_IRQ_CFG0, 0); 1125 bus_write_4(sc->res[0], SMMU_EVENTQ_IRQ_CFG1, 0); 1126 bus_write_4(sc->res[0], SMMU_EVENTQ_IRQ_CFG2, 0); 1127 1128 if (sc->features & CR0_PRIQEN) { 1129 bus_write_8(sc->res[0], SMMU_PRIQ_IRQ_CFG0, 0); 1130 bus_write_4(sc->res[0], SMMU_PRIQ_IRQ_CFG1, 0); 1131 bus_write_4(sc->res[0], SMMU_PRIQ_IRQ_CFG2, 0); 1132 } 1133 1134 /* Disable any interrupts. */ 1135 error = smmu_write_ack(sc, SMMU_IRQ_CTRL, SMMU_IRQ_CTRLACK, 0); 1136 if (error) { 1137 device_printf(sc->dev, "Could not disable interrupts.\n"); 1138 return (ENXIO); 1139 } 1140 1141 /* Enable interrupts. */ 1142 reg = IRQ_CTRL_EVENTQ_IRQEN | IRQ_CTRL_GERROR_IRQEN; 1143 if (sc->features & SMMU_FEATURE_PRI) 1144 reg |= IRQ_CTRL_PRIQ_IRQEN; 1145 1146 error = smmu_write_ack(sc, SMMU_IRQ_CTRL, SMMU_IRQ_CTRLACK, reg); 1147 if (error) { 1148 device_printf(sc->dev, "Could not enable interrupts.\n"); 1149 return (ENXIO); 1150 } 1151 1152 return (0); 1153 } 1154 1155 #ifdef DEV_ACPI 1156 static void 1157 smmu_configure_intr(struct smmu_softc *sc, struct resource *res) 1158 { 1159 struct intr_map_data_acpi *ad; 1160 struct intr_map_data *data; 1161 1162 data = rman_get_virtual(res); 1163 KASSERT(data != NULL, ("data is NULL")); 1164 1165 if (data->type == INTR_MAP_DATA_ACPI) { 1166 ad = (struct intr_map_data_acpi *)data; 1167 ad->trig = INTR_TRIGGER_EDGE; 1168 ad->pol = INTR_POLARITY_HIGH; 1169 } 1170 } 1171 #endif 1172 1173 static int 1174 smmu_setup_interrupts(struct smmu_softc *sc) 1175 { 1176 device_t dev; 1177 int error; 1178 1179 dev = sc->dev; 1180 1181 #ifdef DEV_ACPI 1182 /* 1183 * Configure SMMU interrupts as EDGE triggered manually 1184 * as ACPI tables carries no information for that. 1185 */ 1186 smmu_configure_intr(sc, sc->res[1]); 1187 /* PRIQ is not in use. */ 1188 smmu_configure_intr(sc, sc->res[3]); 1189 smmu_configure_intr(sc, sc->res[4]); 1190 #endif 1191 1192 error = bus_setup_intr(dev, sc->res[1], INTR_TYPE_MISC, 1193 smmu_event_intr, NULL, sc, &sc->intr_cookie[0]); 1194 if (error) { 1195 device_printf(dev, "Couldn't setup Event interrupt handler\n"); 1196 return (ENXIO); 1197 } 1198 1199 error = bus_setup_intr(dev, sc->res[4], INTR_TYPE_MISC, 1200 smmu_gerr_intr, NULL, sc, &sc->intr_cookie[2]); 1201 if (error) { 1202 device_printf(dev, "Couldn't setup Gerr interrupt handler\n"); 1203 return (ENXIO); 1204 } 1205 1206 return (0); 1207 } 1208 1209 static int 1210 smmu_reset(struct smmu_softc *sc) 1211 { 1212 struct smmu_cmdq_entry cmd; 1213 struct smmu_strtab *strtab; 1214 int error; 1215 int reg; 1216 1217 reg = bus_read_4(sc->res[0], SMMU_CR0); 1218 1219 if (reg & CR0_SMMUEN) 1220 device_printf(sc->dev, 1221 "%s: Warning: SMMU is enabled\n", __func__); 1222 1223 error = smmu_disable(sc); 1224 if (error) 1225 device_printf(sc->dev, 1226 "%s: Could not disable SMMU.\n", __func__); 1227 1228 if (smmu_enable_interrupts(sc) != 0) { 1229 device_printf(sc->dev, "Could not enable interrupts.\n"); 1230 return (ENXIO); 1231 } 1232 1233 reg = CR1_TABLE_SH_IS | 1234 CR1_TABLE_OC_WBC | 1235 CR1_TABLE_IC_WBC | 1236 CR1_QUEUE_SH_IS | 1237 CR1_QUEUE_OC_WBC | 1238 CR1_QUEUE_IC_WBC; 1239 bus_write_4(sc->res[0], SMMU_CR1, reg); 1240 1241 reg = CR2_PTM | CR2_RECINVSID | CR2_E2H; 1242 bus_write_4(sc->res[0], SMMU_CR2, reg); 1243 1244 /* Stream table. */ 1245 strtab = &sc->strtab; 1246 bus_write_8(sc->res[0], SMMU_STRTAB_BASE, strtab->base); 1247 bus_write_4(sc->res[0], SMMU_STRTAB_BASE_CFG, strtab->base_cfg); 1248 1249 /* Command queue. */ 1250 bus_write_8(sc->res[0], SMMU_CMDQ_BASE, sc->cmdq.base); 1251 bus_write_4(sc->res[0], SMMU_CMDQ_PROD, sc->cmdq.lc.prod); 1252 bus_write_4(sc->res[0], SMMU_CMDQ_CONS, sc->cmdq.lc.cons); 1253 1254 reg = CR0_CMDQEN; 1255 error = smmu_write_ack(sc, SMMU_CR0, SMMU_CR0ACK, reg); 1256 if (error) { 1257 device_printf(sc->dev, "Could not enable command queue\n"); 1258 return (ENXIO); 1259 } 1260 1261 /* Invalidate cached configuration. */ 1262 smmu_invalidate_all_sid(sc); 1263 1264 if (sc->features & SMMU_FEATURE_HYP) { 1265 cmd.opcode = CMD_TLBI_EL2_ALL; 1266 smmu_cmdq_enqueue_cmd(sc, &cmd); 1267 }; 1268 1269 /* Invalidate TLB. */ 1270 smmu_tlbi_all(sc); 1271 1272 /* Event queue */ 1273 bus_write_8(sc->res[0], SMMU_EVENTQ_BASE, sc->evtq.base); 1274 bus_write_4(sc->res[0], SMMU_EVENTQ_PROD, sc->evtq.lc.prod); 1275 bus_write_4(sc->res[0], SMMU_EVENTQ_CONS, sc->evtq.lc.cons); 1276 1277 reg |= CR0_EVENTQEN; 1278 error = smmu_write_ack(sc, SMMU_CR0, SMMU_CR0ACK, reg); 1279 if (error) { 1280 device_printf(sc->dev, "Could not enable event queue\n"); 1281 return (ENXIO); 1282 } 1283 1284 if (sc->features & SMMU_FEATURE_PRI) { 1285 /* PRI queue */ 1286 bus_write_8(sc->res[0], SMMU_PRIQ_BASE, sc->priq.base); 1287 bus_write_4(sc->res[0], SMMU_PRIQ_PROD, sc->priq.lc.prod); 1288 bus_write_4(sc->res[0], SMMU_PRIQ_CONS, sc->priq.lc.cons); 1289 1290 reg |= CR0_PRIQEN; 1291 error = smmu_write_ack(sc, SMMU_CR0, SMMU_CR0ACK, reg); 1292 if (error) { 1293 device_printf(sc->dev, "Could not enable PRI queue\n"); 1294 return (ENXIO); 1295 } 1296 } 1297 1298 if (sc->features & SMMU_FEATURE_ATS) { 1299 reg |= CR0_ATSCHK; 1300 error = smmu_write_ack(sc, SMMU_CR0, SMMU_CR0ACK, reg); 1301 if (error) { 1302 device_printf(sc->dev, "Could not enable ATS check.\n"); 1303 return (ENXIO); 1304 } 1305 } 1306 1307 reg |= CR0_SMMUEN; 1308 error = smmu_write_ack(sc, SMMU_CR0, SMMU_CR0ACK, reg); 1309 if (error) { 1310 device_printf(sc->dev, "Could not enable SMMU.\n"); 1311 return (ENXIO); 1312 } 1313 1314 return (0); 1315 } 1316 1317 static int 1318 smmu_check_features(struct smmu_softc *sc) 1319 { 1320 uint32_t reg; 1321 uint32_t val; 1322 1323 sc->features = 0; 1324 1325 reg = bus_read_4(sc->res[0], SMMU_IDR0); 1326 1327 if (reg & IDR0_ST_LVL_2) { 1328 if (bootverbose) 1329 device_printf(sc->dev, 1330 "2-level stream table supported.\n"); 1331 sc->features |= SMMU_FEATURE_2_LVL_STREAM_TABLE; 1332 } 1333 1334 if (reg & IDR0_CD2L) { 1335 if (bootverbose) 1336 device_printf(sc->dev, 1337 "2-level CD table supported.\n"); 1338 sc->features |= SMMU_FEATURE_2_LVL_CD; 1339 } 1340 1341 switch (reg & IDR0_TTENDIAN_M) { 1342 case IDR0_TTENDIAN_MIXED: 1343 if (bootverbose) 1344 device_printf(sc->dev, "Mixed endianness supported.\n"); 1345 sc->features |= SMMU_FEATURE_TT_LE; 1346 sc->features |= SMMU_FEATURE_TT_BE; 1347 break; 1348 case IDR0_TTENDIAN_LITTLE: 1349 if (bootverbose) 1350 device_printf(sc->dev, 1351 "Little endian supported only.\n"); 1352 sc->features |= SMMU_FEATURE_TT_LE; 1353 break; 1354 case IDR0_TTENDIAN_BIG: 1355 if (bootverbose) 1356 device_printf(sc->dev, "Big endian supported only.\n"); 1357 sc->features |= SMMU_FEATURE_TT_BE; 1358 break; 1359 default: 1360 device_printf(sc->dev, "Unsupported endianness.\n"); 1361 return (ENXIO); 1362 } 1363 1364 if (reg & IDR0_SEV) 1365 sc->features |= SMMU_FEATURE_SEV; 1366 1367 if (reg & IDR0_MSI) { 1368 if (bootverbose) 1369 device_printf(sc->dev, "MSI feature present.\n"); 1370 sc->features |= SMMU_FEATURE_MSI; 1371 } 1372 1373 if (reg & IDR0_HYP) { 1374 if (bootverbose) 1375 device_printf(sc->dev, "HYP feature present.\n"); 1376 sc->features |= SMMU_FEATURE_HYP; 1377 } 1378 1379 if (reg & IDR0_ATS) 1380 sc->features |= SMMU_FEATURE_ATS; 1381 1382 if (reg & IDR0_PRI) 1383 sc->features |= SMMU_FEATURE_PRI; 1384 1385 switch (reg & IDR0_STALL_MODEL_M) { 1386 case IDR0_STALL_MODEL_FORCE: 1387 /* Stall is forced. */ 1388 sc->features |= SMMU_FEATURE_STALL_FORCE; 1389 /* FALLTHROUGH */ 1390 case IDR0_STALL_MODEL_STALL: 1391 sc->features |= SMMU_FEATURE_STALL; 1392 break; 1393 } 1394 1395 /* Grab translation stages supported. */ 1396 if (reg & IDR0_S1P) { 1397 if (bootverbose) 1398 device_printf(sc->dev, 1399 "Stage 1 translation supported.\n"); 1400 sc->features |= SMMU_FEATURE_S1P; 1401 } 1402 if (reg & IDR0_S2P) { 1403 if (bootverbose) 1404 device_printf(sc->dev, 1405 "Stage 2 translation supported.\n"); 1406 sc->features |= SMMU_FEATURE_S2P; 1407 } 1408 1409 switch (reg & IDR0_TTF_M) { 1410 case IDR0_TTF_ALL: 1411 case IDR0_TTF_AA64: 1412 sc->ias = 40; 1413 break; 1414 default: 1415 device_printf(sc->dev, "No AArch64 table format support.\n"); 1416 return (ENXIO); 1417 } 1418 1419 if (reg & IDR0_ASID16) 1420 sc->asid_bits = 16; 1421 else 1422 sc->asid_bits = 8; 1423 1424 if (bootverbose) 1425 device_printf(sc->dev, "ASID bits %d\n", sc->asid_bits); 1426 1427 if (reg & IDR0_VMID16) 1428 sc->vmid_bits = 16; 1429 else 1430 sc->vmid_bits = 8; 1431 1432 reg = bus_read_4(sc->res[0], SMMU_IDR1); 1433 1434 if (reg & (IDR1_TABLES_PRESET | IDR1_QUEUES_PRESET | IDR1_REL)) { 1435 device_printf(sc->dev, 1436 "Embedded implementations not supported by this driver.\n"); 1437 return (ENXIO); 1438 } 1439 1440 val = (reg & IDR1_CMDQS_M) >> IDR1_CMDQS_S; 1441 sc->cmdq.size_log2 = val; 1442 if (bootverbose) 1443 device_printf(sc->dev, "CMD queue bits %d\n", val); 1444 1445 val = (reg & IDR1_EVENTQS_M) >> IDR1_EVENTQS_S; 1446 sc->evtq.size_log2 = val; 1447 if (bootverbose) 1448 device_printf(sc->dev, "EVENT queue bits %d\n", val); 1449 1450 if (sc->features & SMMU_FEATURE_PRI) { 1451 val = (reg & IDR1_PRIQS_M) >> IDR1_PRIQS_S; 1452 sc->priq.size_log2 = val; 1453 if (bootverbose) 1454 device_printf(sc->dev, "PRI queue bits %d\n", val); 1455 } 1456 1457 sc->ssid_bits = (reg & IDR1_SSIDSIZE_M) >> IDR1_SSIDSIZE_S; 1458 sc->sid_bits = (reg & IDR1_SIDSIZE_M) >> IDR1_SIDSIZE_S; 1459 1460 if (sc->sid_bits <= STRTAB_SPLIT) 1461 sc->features &= ~SMMU_FEATURE_2_LVL_STREAM_TABLE; 1462 1463 if (bootverbose) { 1464 device_printf(sc->dev, "SSID bits %d\n", sc->ssid_bits); 1465 device_printf(sc->dev, "SID bits %d\n", sc->sid_bits); 1466 } 1467 1468 /* IDR3 */ 1469 reg = bus_read_4(sc->res[0], SMMU_IDR3); 1470 if (reg & IDR3_RIL) 1471 sc->features |= SMMU_FEATURE_RANGE_INV; 1472 1473 /* IDR5 */ 1474 reg = bus_read_4(sc->res[0], SMMU_IDR5); 1475 1476 switch (reg & IDR5_OAS_M) { 1477 case IDR5_OAS_32: 1478 sc->oas = 32; 1479 break; 1480 case IDR5_OAS_36: 1481 sc->oas = 36; 1482 break; 1483 case IDR5_OAS_40: 1484 sc->oas = 40; 1485 break; 1486 case IDR5_OAS_42: 1487 sc->oas = 42; 1488 break; 1489 case IDR5_OAS_44: 1490 sc->oas = 44; 1491 break; 1492 case IDR5_OAS_48: 1493 sc->oas = 48; 1494 break; 1495 case IDR5_OAS_52: 1496 sc->oas = 52; 1497 break; 1498 } 1499 1500 sc->pgsizes = 0; 1501 if (reg & IDR5_GRAN64K) 1502 sc->pgsizes |= 64 * 1024; 1503 if (reg & IDR5_GRAN16K) 1504 sc->pgsizes |= 16 * 1024; 1505 if (reg & IDR5_GRAN4K) 1506 sc->pgsizes |= 4 * 1024; 1507 1508 if ((reg & IDR5_VAX_M) == IDR5_VAX_52) 1509 sc->features |= SMMU_FEATURE_VAX; 1510 1511 return (0); 1512 } 1513 1514 static void 1515 smmu_init_asids(struct smmu_softc *sc) 1516 { 1517 1518 sc->asid_set_size = (1 << sc->asid_bits); 1519 sc->asid_set = bit_alloc(sc->asid_set_size, M_SMMU, M_WAITOK); 1520 mtx_init(&sc->asid_set_mutex, "asid set", NULL, MTX_SPIN); 1521 } 1522 1523 static int 1524 smmu_asid_alloc(struct smmu_softc *sc, int *new_asid) 1525 { 1526 1527 mtx_lock_spin(&sc->asid_set_mutex); 1528 bit_ffc(sc->asid_set, sc->asid_set_size, new_asid); 1529 if (*new_asid == -1) { 1530 mtx_unlock_spin(&sc->asid_set_mutex); 1531 return (ENOMEM); 1532 } 1533 bit_set(sc->asid_set, *new_asid); 1534 mtx_unlock_spin(&sc->asid_set_mutex); 1535 1536 return (0); 1537 } 1538 1539 static void 1540 smmu_asid_free(struct smmu_softc *sc, int asid) 1541 { 1542 1543 mtx_lock_spin(&sc->asid_set_mutex); 1544 bit_clear(sc->asid_set, asid); 1545 mtx_unlock_spin(&sc->asid_set_mutex); 1546 } 1547 1548 /* 1549 * Device interface. 1550 */ 1551 int 1552 smmu_attach(device_t dev) 1553 { 1554 struct smmu_softc *sc; 1555 int error; 1556 1557 sc = device_get_softc(dev); 1558 sc->dev = dev; 1559 1560 mtx_init(&sc->sc_mtx, device_get_nameunit(sc->dev), "smmu", MTX_DEF); 1561 1562 error = smmu_setup_interrupts(sc); 1563 if (error) { 1564 bus_release_resources(dev, smmu_spec, sc->res); 1565 return (ENXIO); 1566 } 1567 1568 error = smmu_check_features(sc); 1569 if (error) { 1570 device_printf(dev, "Some features are required " 1571 "but not supported by hardware.\n"); 1572 return (ENXIO); 1573 } 1574 1575 smmu_init_asids(sc); 1576 1577 error = smmu_init_queues(sc); 1578 if (error) { 1579 device_printf(dev, "Couldn't allocate queues.\n"); 1580 return (ENXIO); 1581 } 1582 1583 error = smmu_init_strtab(sc); 1584 if (error) { 1585 device_printf(dev, "Couldn't allocate strtab.\n"); 1586 return (ENXIO); 1587 } 1588 1589 error = smmu_reset(sc); 1590 if (error) { 1591 device_printf(dev, "Couldn't reset SMMU.\n"); 1592 return (ENXIO); 1593 } 1594 1595 return (0); 1596 } 1597 1598 int 1599 smmu_detach(device_t dev) 1600 { 1601 struct smmu_softc *sc; 1602 1603 sc = device_get_softc(dev); 1604 1605 bus_release_resources(dev, smmu_spec, sc->res); 1606 1607 return (0); 1608 } 1609 1610 static int 1611 smmu_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1612 { 1613 struct smmu_softc *sc; 1614 1615 sc = device_get_softc(dev); 1616 1617 device_printf(sc->dev, "%s\n", __func__); 1618 1619 return (ENOENT); 1620 } 1621 1622 static int 1623 smmu_unmap(device_t dev, struct iommu_domain *iodom, 1624 vm_offset_t va, bus_size_t size) 1625 { 1626 struct smmu_domain *domain; 1627 struct smmu_softc *sc; 1628 int err; 1629 int i; 1630 1631 sc = device_get_softc(dev); 1632 1633 domain = (struct smmu_domain *)iodom; 1634 1635 err = 0; 1636 1637 dprintf("%s: %lx, %ld, domain %d\n", __func__, va, size, domain->asid); 1638 1639 for (i = 0; i < size; i += PAGE_SIZE) { 1640 if (smmu_pmap_remove(&domain->p, va) == 0) { 1641 /* pmap entry removed, invalidate TLB. */ 1642 smmu_tlbi_va(sc, va, domain->asid); 1643 } else { 1644 err = ENOENT; 1645 break; 1646 } 1647 va += PAGE_SIZE; 1648 } 1649 1650 smmu_sync(sc); 1651 1652 return (err); 1653 } 1654 1655 static int 1656 smmu_map(device_t dev, struct iommu_domain *iodom, 1657 vm_offset_t va, vm_page_t *ma, vm_size_t size, 1658 vm_prot_t prot) 1659 { 1660 struct smmu_domain *domain; 1661 struct smmu_softc *sc; 1662 vm_paddr_t pa; 1663 int error; 1664 int i; 1665 1666 sc = device_get_softc(dev); 1667 1668 domain = (struct smmu_domain *)iodom; 1669 1670 dprintf("%s: %lx -> %lx, %ld, domain %d\n", __func__, va, pa, size, 1671 domain->asid); 1672 1673 for (i = 0; size > 0; size -= PAGE_SIZE) { 1674 pa = VM_PAGE_TO_PHYS(ma[i++]); 1675 error = smmu_pmap_enter(&domain->p, va, pa, prot, 0); 1676 if (error) 1677 return (error); 1678 smmu_tlbi_va(sc, va, domain->asid); 1679 va += PAGE_SIZE; 1680 } 1681 1682 smmu_sync(sc); 1683 1684 return (0); 1685 } 1686 1687 static struct iommu_domain * 1688 smmu_domain_alloc(device_t dev, struct iommu_unit *iommu) 1689 { 1690 struct iommu_domain *iodom; 1691 struct smmu_domain *domain; 1692 struct smmu_unit *unit; 1693 struct smmu_softc *sc; 1694 int error; 1695 int new_asid; 1696 1697 sc = device_get_softc(dev); 1698 1699 unit = (struct smmu_unit *)iommu; 1700 1701 domain = malloc(sizeof(*domain), M_SMMU, M_WAITOK | M_ZERO); 1702 1703 error = smmu_asid_alloc(sc, &new_asid); 1704 if (error) { 1705 free(domain, M_SMMU); 1706 device_printf(sc->dev, 1707 "Could not allocate ASID for a new domain.\n"); 1708 return (NULL); 1709 } 1710 1711 domain->asid = (uint16_t)new_asid; 1712 1713 smmu_pmap_pinit(&domain->p); 1714 1715 error = smmu_init_cd(sc, domain); 1716 if (error) { 1717 free(domain, M_SMMU); 1718 device_printf(sc->dev, "Could not initialize CD\n"); 1719 return (NULL); 1720 } 1721 1722 smmu_tlbi_asid(sc, domain->asid); 1723 1724 LIST_INIT(&domain->ctx_list); 1725 1726 IOMMU_LOCK(iommu); 1727 LIST_INSERT_HEAD(&unit->domain_list, domain, next); 1728 IOMMU_UNLOCK(iommu); 1729 1730 iodom = &domain->iodom; 1731 1732 /* 1733 * Use 48-bit address space regardless of VAX bit 1734 * as we need 64k IOMMU_PAGE_SIZE for 52-bit space. 1735 */ 1736 iodom->end = MAXADDR_48BIT; 1737 1738 return (iodom); 1739 } 1740 1741 static void 1742 smmu_domain_free(device_t dev, struct iommu_domain *iodom) 1743 { 1744 struct smmu_domain *domain; 1745 struct smmu_softc *sc; 1746 struct smmu_cd *cd; 1747 1748 sc = device_get_softc(dev); 1749 1750 domain = (struct smmu_domain *)iodom; 1751 1752 LIST_REMOVE(domain, next); 1753 1754 cd = domain->cd; 1755 1756 smmu_pmap_remove_pages(&domain->p); 1757 smmu_pmap_release(&domain->p); 1758 1759 smmu_tlbi_asid(sc, domain->asid); 1760 smmu_asid_free(sc, domain->asid); 1761 1762 free(cd->vaddr, M_SMMU); 1763 free(cd, M_SMMU); 1764 1765 free(domain, M_SMMU); 1766 } 1767 1768 static int 1769 smmu_set_buswide(device_t dev, struct smmu_domain *domain, 1770 struct smmu_ctx *ctx) 1771 { 1772 struct smmu_softc *sc; 1773 int i; 1774 1775 sc = device_get_softc(dev); 1776 1777 for (i = 0; i < PCI_SLOTMAX; i++) 1778 smmu_init_ste(sc, domain->cd, (ctx->sid | i), ctx->bypass); 1779 1780 return (0); 1781 } 1782 1783 static int 1784 smmu_pci_get_sid(device_t child, u_int *xref0, u_int *sid0) 1785 { 1786 struct pci_id_ofw_iommu pi; 1787 int err; 1788 1789 err = pci_get_id(child, PCI_ID_OFW_IOMMU, (uintptr_t *)&pi); 1790 if (err == 0) { 1791 if (sid0) 1792 *sid0 = pi.id; 1793 if (xref0) 1794 *xref0 = pi.xref; 1795 } 1796 1797 return (err); 1798 } 1799 1800 static struct iommu_ctx * 1801 smmu_ctx_alloc(device_t dev, struct iommu_domain *iodom, device_t child, 1802 bool disabled) 1803 { 1804 struct smmu_domain *domain; 1805 struct smmu_ctx *ctx; 1806 1807 domain = (struct smmu_domain *)iodom; 1808 1809 ctx = malloc(sizeof(struct smmu_ctx), M_SMMU, M_WAITOK | M_ZERO); 1810 ctx->dev = child; 1811 ctx->domain = domain; 1812 if (disabled) 1813 ctx->bypass = true; 1814 1815 IOMMU_DOMAIN_LOCK(iodom); 1816 LIST_INSERT_HEAD(&domain->ctx_list, ctx, next); 1817 IOMMU_DOMAIN_UNLOCK(iodom); 1818 1819 return (&ctx->ioctx); 1820 } 1821 1822 static int 1823 smmu_ctx_init(device_t dev, struct iommu_ctx *ioctx) 1824 { 1825 struct smmu_domain *domain; 1826 struct iommu_domain *iodom; 1827 struct smmu_softc *sc; 1828 struct smmu_ctx *ctx; 1829 devclass_t pci_class; 1830 u_int sid; 1831 int err; 1832 1833 ctx = (struct smmu_ctx *)ioctx; 1834 1835 sc = device_get_softc(dev); 1836 1837 domain = ctx->domain; 1838 iodom = (struct iommu_domain *)domain; 1839 1840 pci_class = devclass_find("pci"); 1841 if (device_get_devclass(device_get_parent(ctx->dev)) == pci_class) { 1842 err = smmu_pci_get_sid(ctx->dev, NULL, &sid); 1843 if (err) 1844 return (err); 1845 1846 ioctx->rid = pci_get_rid(dev); 1847 ctx->sid = sid; 1848 ctx->vendor = pci_get_vendor(ctx->dev); 1849 ctx->device = pci_get_device(ctx->dev); 1850 } 1851 1852 if (sc->features & SMMU_FEATURE_2_LVL_STREAM_TABLE) { 1853 err = smmu_init_l1_entry(sc, ctx->sid); 1854 if (err) 1855 return (err); 1856 } 1857 1858 /* 1859 * Neoverse N1 SDP: 1860 * 0x800 xhci 1861 * 0x700 re 1862 * 0x600 sata 1863 */ 1864 1865 smmu_init_ste(sc, domain->cd, ctx->sid, ctx->bypass); 1866 1867 if (device_get_devclass(device_get_parent(ctx->dev)) == pci_class) 1868 if (iommu_is_buswide_ctx(iodom->iommu, pci_get_bus(ctx->dev))) 1869 smmu_set_buswide(dev, domain, ctx); 1870 1871 return (0); 1872 } 1873 1874 static void 1875 smmu_ctx_free(device_t dev, struct iommu_ctx *ioctx) 1876 { 1877 struct smmu_softc *sc; 1878 struct smmu_ctx *ctx; 1879 1880 IOMMU_ASSERT_LOCKED(ioctx->domain->iommu); 1881 1882 sc = device_get_softc(dev); 1883 ctx = (struct smmu_ctx *)ioctx; 1884 1885 smmu_deinit_ste(sc, ctx->sid); 1886 1887 LIST_REMOVE(ctx, next); 1888 1889 free(ctx, M_SMMU); 1890 } 1891 1892 struct smmu_ctx * 1893 smmu_ctx_lookup_by_sid(device_t dev, u_int sid) 1894 { 1895 struct smmu_softc *sc; 1896 struct smmu_domain *domain; 1897 struct smmu_unit *unit; 1898 struct smmu_ctx *ctx; 1899 1900 sc = device_get_softc(dev); 1901 1902 unit = &sc->unit; 1903 1904 LIST_FOREACH(domain, &unit->domain_list, next) { 1905 LIST_FOREACH(ctx, &domain->ctx_list, next) { 1906 if (ctx->sid == sid) 1907 return (ctx); 1908 } 1909 } 1910 1911 return (NULL); 1912 } 1913 1914 static struct iommu_ctx * 1915 smmu_ctx_lookup(device_t dev, device_t child) 1916 { 1917 struct iommu_unit *iommu __diagused; 1918 struct smmu_softc *sc; 1919 struct smmu_domain *domain; 1920 struct smmu_unit *unit; 1921 struct smmu_ctx *ctx; 1922 1923 sc = device_get_softc(dev); 1924 1925 unit = &sc->unit; 1926 iommu = &unit->iommu; 1927 1928 IOMMU_ASSERT_LOCKED(iommu); 1929 1930 LIST_FOREACH(domain, &unit->domain_list, next) { 1931 IOMMU_DOMAIN_LOCK(&domain->iodom); 1932 LIST_FOREACH(ctx, &domain->ctx_list, next) { 1933 if (ctx->dev == child) { 1934 IOMMU_DOMAIN_UNLOCK(&domain->iodom); 1935 return (&ctx->ioctx); 1936 } 1937 } 1938 IOMMU_DOMAIN_UNLOCK(&domain->iodom); 1939 } 1940 1941 return (NULL); 1942 } 1943 1944 static int 1945 smmu_find(device_t dev, device_t child) 1946 { 1947 struct smmu_softc *sc; 1948 u_int xref; 1949 int err; 1950 1951 sc = device_get_softc(dev); 1952 1953 err = smmu_pci_get_sid(child, &xref, NULL); 1954 if (err) 1955 return (ENOENT); 1956 1957 /* Check if xref is ours. */ 1958 if (xref != sc->xref) 1959 return (EFAULT); 1960 1961 return (0); 1962 } 1963 1964 #ifdef FDT 1965 static int 1966 smmu_ofw_md_data(device_t dev, struct iommu_ctx *ioctx, pcell_t *cells, 1967 int ncells) 1968 { 1969 struct smmu_ctx *ctx; 1970 1971 ctx = (struct smmu_ctx *)ioctx; 1972 1973 if (ncells != 1) 1974 return (-1); 1975 1976 ctx->sid = cells[0]; 1977 1978 return (0); 1979 } 1980 #endif 1981 1982 static device_method_t smmu_methods[] = { 1983 /* Device interface */ 1984 DEVMETHOD(device_detach, smmu_detach), 1985 1986 /* SMMU interface */ 1987 DEVMETHOD(iommu_find, smmu_find), 1988 DEVMETHOD(iommu_map, smmu_map), 1989 DEVMETHOD(iommu_unmap, smmu_unmap), 1990 DEVMETHOD(iommu_domain_alloc, smmu_domain_alloc), 1991 DEVMETHOD(iommu_domain_free, smmu_domain_free), 1992 DEVMETHOD(iommu_ctx_alloc, smmu_ctx_alloc), 1993 DEVMETHOD(iommu_ctx_init, smmu_ctx_init), 1994 DEVMETHOD(iommu_ctx_free, smmu_ctx_free), 1995 DEVMETHOD(iommu_ctx_lookup, smmu_ctx_lookup), 1996 #ifdef FDT 1997 DEVMETHOD(iommu_ofw_md_data, smmu_ofw_md_data), 1998 #endif 1999 2000 /* Bus interface */ 2001 DEVMETHOD(bus_read_ivar, smmu_read_ivar), 2002 2003 /* End */ 2004 DEVMETHOD_END 2005 }; 2006 2007 DEFINE_CLASS_0(smmu, smmu_driver, smmu_methods, sizeof(struct smmu_softc)); 2008