1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2019-2020 Ruslan Bukin <br@bsdpad.com> 5 * 6 * This software was developed by SRI International and the University of 7 * Cambridge Computer Laboratory (Department of Computer Science and 8 * Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the 9 * DARPA SSITH research programme. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 */ 32 33 /* 34 * Hardware overview. 35 * 36 * An incoming transaction from a peripheral device has an address, size, 37 * attributes and StreamID. 38 * 39 * In case of PCI-based devices, StreamID is a PCI rid. 40 * 41 * The StreamID is used to select a Stream Table Entry (STE) in a Stream table, 42 * which contains per-device configuration. 43 * 44 * Stream table is a linear or 2-level walk table (this driver supports both). 45 * Note that a linear table could occupy 1GB or more of memory depending on 46 * sid_bits value. 47 * 48 * STE is used to locate a Context Descriptor, which is a struct in memory 49 * that describes stages of translation, translation table type, pointer to 50 * level 0 of page tables, ASID, etc. 51 * 52 * Hardware supports two stages of translation: Stage1 (S1) and Stage2 (S2): 53 * o S1 is used for the host machine traffic translation 54 * o S2 is for a hypervisor 55 * 56 * This driver enables S1 stage with standard AArch64 page tables. 57 * 58 * Note that SMMU does not share TLB with a main CPU. 59 * Command queue is used by this driver to Invalidate SMMU TLB, STE cache. 60 * 61 * An arm64 SoC could have more than one SMMU instance. 62 * ACPI IORT table describes which SMMU unit is assigned for a particular 63 * peripheral device. 64 * 65 * Queues. 66 * 67 * Register interface and Memory-based circular buffer queues are used 68 * to inferface SMMU. 69 * 70 * These are a Command queue for commands to send to the SMMU and an Event 71 * queue for event/fault reports from the SMMU. Optionally PRI queue is 72 * designed for PCIe page requests reception. 73 * 74 * Note that not every hardware supports PRI services. For instance they were 75 * not found in Neoverse N1 SDP machine. 76 * (This drivers does not implement PRI queue.) 77 * 78 * All SMMU queues are arranged as circular buffers in memory. They are used 79 * in a producer-consumer fashion so that an output queue contains data 80 * produced by the SMMU and consumed by software. 81 * An input queue contains data produced by software, consumed by the SMMU. 82 * 83 * Interrupts. 84 * 85 * Interrupts are not required by this driver for normal operation. 86 * The standard wired interrupt is only triggered when an event comes from 87 * the SMMU, which is only in a case of errors (e.g. translation fault). 88 */ 89 90 #include "opt_platform.h" 91 #include "opt_acpi.h" 92 93 #include <sys/cdefs.h> 94 __FBSDID("$FreeBSD$"); 95 96 #include <sys/param.h> 97 #include <sys/bitstring.h> 98 #include <sys/bus.h> 99 #include <sys/kernel.h> 100 #include <sys/malloc.h> 101 #include <sys/mutex.h> 102 #include <sys/rman.h> 103 #include <sys/lock.h> 104 #include <sys/sysctl.h> 105 #include <sys/tree.h> 106 #include <sys/taskqueue.h> 107 #include <vm/vm.h> 108 #include <vm/vm_page.h> 109 #ifdef DEV_ACPI 110 #include <contrib/dev/acpica/include/acpi.h> 111 #include <dev/acpica/acpivar.h> 112 #endif 113 #include <dev/pci/pcireg.h> 114 #include <dev/pci/pcivar.h> 115 #include <dev/iommu/iommu.h> 116 #include <arm64/iommu/iommu_pmap.h> 117 118 #include <machine/bus.h> 119 120 #ifdef FDT 121 #include <dev/fdt/fdt_common.h> 122 #include <dev/ofw/ofw_bus.h> 123 #include <dev/ofw/ofw_bus_subr.h> 124 #endif 125 126 #include "iommu.h" 127 #include "iommu_if.h" 128 129 #include "smmureg.h" 130 #include "smmuvar.h" 131 132 #define STRTAB_L1_SZ_SHIFT 20 133 #define STRTAB_SPLIT 8 134 135 #define STRTAB_L1_DESC_L2PTR_M (0x3fffffffffff << 6) 136 #define STRTAB_L1_DESC_DWORDS 1 137 138 #define STRTAB_STE_DWORDS 8 139 140 #define CMDQ_ENTRY_DWORDS 2 141 #define EVTQ_ENTRY_DWORDS 4 142 #define PRIQ_ENTRY_DWORDS 2 143 144 #define CD_DWORDS 8 145 146 #define Q_WRP(q, p) ((p) & (1 << (q)->size_log2)) 147 #define Q_IDX(q, p) ((p) & ((1 << (q)->size_log2) - 1)) 148 #define Q_OVF(p) ((p) & (1 << 31)) /* Event queue overflowed */ 149 150 #define SMMU_Q_ALIGN (64 * 1024) 151 152 static struct resource_spec smmu_spec[] = { 153 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 154 { SYS_RES_IRQ, 0, RF_ACTIVE }, 155 { SYS_RES_IRQ, 1, RF_ACTIVE }, 156 { SYS_RES_IRQ, 2, RF_ACTIVE }, 157 { SYS_RES_IRQ, 3, RF_ACTIVE }, 158 RESOURCE_SPEC_END 159 }; 160 161 MALLOC_DEFINE(M_SMMU, "SMMU", SMMU_DEVSTR); 162 163 #define dprintf(fmt, ...) 164 165 struct smmu_event { 166 int ident; 167 char *str; 168 char *msg; 169 }; 170 171 static struct smmu_event events[] = { 172 { 0x01, "F_UUT", 173 "Unsupported Upstream Transaction."}, 174 { 0x02, "C_BAD_STREAMID", 175 "Transaction StreamID out of range."}, 176 { 0x03, "F_STE_FETCH", 177 "Fetch of STE caused external abort."}, 178 { 0x04, "C_BAD_STE", 179 "Used STE invalid."}, 180 { 0x05, "F_BAD_ATS_TREQ", 181 "Address Translation Request disallowed for a StreamID " 182 "and a PCIe ATS Translation Request received."}, 183 { 0x06, "F_STREAM_DISABLED", 184 "The STE of a transaction marks non-substream transactions " 185 "disabled."}, 186 { 0x07, "F_TRANSL_FORBIDDEN", 187 "An incoming PCIe transaction is marked Translated but " 188 "SMMU bypass is disallowed for this StreamID."}, 189 { 0x08, "C_BAD_SUBSTREAMID", 190 "Incoming SubstreamID present, but configuration is invalid."}, 191 { 0x09, "F_CD_FETCH", 192 "Fetch of CD caused external abort."}, 193 { 0x0a, "C_BAD_CD", 194 "Fetched CD invalid."}, 195 { 0x0b, "F_WALK_EABT", 196 "An external abort occurred fetching (or updating) " 197 "a translation table descriptor."}, 198 { 0x10, "F_TRANSLATION", 199 "Translation fault."}, 200 { 0x11, "F_ADDR_SIZE", 201 "Address Size fault."}, 202 { 0x12, "F_ACCESS", 203 "Access flag fault due to AF == 0 in a page or block TTD."}, 204 { 0x13, "F_PERMISSION", 205 "Permission fault occurred on page access."}, 206 { 0x20, "F_TLB_CONFLICT", 207 "A TLB conflict occurred because of the transaction."}, 208 { 0x21, "F_CFG_CONFLICT", 209 "A configuration cache conflict occurred due to " 210 "the transaction."}, 211 { 0x24, "E_PAGE_REQUEST", 212 "Speculative page request hint."}, 213 { 0x25, "F_VMS_FETCH", 214 "Fetch of VMS caused external abort."}, 215 { 0, NULL, NULL }, 216 }; 217 218 static int 219 smmu_q_has_space(struct smmu_queue *q) 220 { 221 222 /* 223 * See 6.3.27 SMMU_CMDQ_PROD 224 * 225 * There is space in the queue for additional commands if: 226 * SMMU_CMDQ_CONS.RD != SMMU_CMDQ_PROD.WR || 227 * SMMU_CMDQ_CONS.RD_WRAP == SMMU_CMDQ_PROD.WR_WRAP 228 */ 229 230 if (Q_IDX(q, q->lc.cons) != Q_IDX(q, q->lc.prod) || 231 Q_WRP(q, q->lc.cons) == Q_WRP(q, q->lc.prod)) 232 return (1); 233 234 return (0); 235 } 236 237 static int 238 smmu_q_empty(struct smmu_queue *q) 239 { 240 241 if (Q_IDX(q, q->lc.cons) == Q_IDX(q, q->lc.prod) && 242 Q_WRP(q, q->lc.cons) == Q_WRP(q, q->lc.prod)) 243 return (1); 244 245 return (0); 246 } 247 248 static int __unused 249 smmu_q_consumed(struct smmu_queue *q, uint32_t prod) 250 { 251 252 if ((Q_WRP(q, q->lc.cons) == Q_WRP(q, prod)) && 253 (Q_IDX(q, q->lc.cons) >= Q_IDX(q, prod))) 254 return (1); 255 256 if ((Q_WRP(q, q->lc.cons) != Q_WRP(q, prod)) && 257 (Q_IDX(q, q->lc.cons) <= Q_IDX(q, prod))) 258 return (1); 259 260 return (0); 261 } 262 263 static uint32_t 264 smmu_q_inc_cons(struct smmu_queue *q) 265 { 266 uint32_t cons; 267 uint32_t val; 268 269 cons = (Q_WRP(q, q->lc.cons) | Q_IDX(q, q->lc.cons)) + 1; 270 val = (Q_OVF(q->lc.cons) | Q_WRP(q, cons) | Q_IDX(q, cons)); 271 272 return (val); 273 } 274 275 static uint32_t 276 smmu_q_inc_prod(struct smmu_queue *q) 277 { 278 uint32_t prod; 279 uint32_t val; 280 281 prod = (Q_WRP(q, q->lc.prod) | Q_IDX(q, q->lc.prod)) + 1; 282 val = (Q_OVF(q->lc.prod) | Q_WRP(q, prod) | Q_IDX(q, prod)); 283 284 return (val); 285 } 286 287 static int 288 smmu_write_ack(struct smmu_softc *sc, uint32_t reg, 289 uint32_t reg_ack, uint32_t val) 290 { 291 uint32_t v; 292 int timeout; 293 294 timeout = 100000; 295 296 bus_write_4(sc->res[0], reg, val); 297 298 do { 299 v = bus_read_4(sc->res[0], reg_ack); 300 if (v == val) 301 break; 302 } while (timeout--); 303 304 if (timeout <= 0) { 305 device_printf(sc->dev, "Failed to write reg.\n"); 306 return (-1); 307 } 308 309 return (0); 310 } 311 312 static inline int 313 ilog2(long x) 314 { 315 316 KASSERT(x > 0 && powerof2(x), ("%s: invalid arg %ld", __func__, x)); 317 318 return (flsl(x) - 1); 319 } 320 321 static int 322 smmu_init_queue(struct smmu_softc *sc, struct smmu_queue *q, 323 uint32_t prod_off, uint32_t cons_off, uint32_t dwords) 324 { 325 int sz; 326 327 sz = (1 << q->size_log2) * dwords * 8; 328 329 /* Set up the command circular buffer */ 330 q->vaddr = contigmalloc(sz, M_SMMU, 331 M_WAITOK | M_ZERO, 0, (1ul << 48) - 1, SMMU_Q_ALIGN, 0); 332 if (q->vaddr == NULL) { 333 device_printf(sc->dev, "failed to allocate %d bytes\n", sz); 334 return (-1); 335 } 336 337 q->prod_off = prod_off; 338 q->cons_off = cons_off; 339 q->paddr = vtophys(q->vaddr); 340 341 q->base = CMDQ_BASE_RA | EVENTQ_BASE_WA | PRIQ_BASE_WA; 342 q->base |= q->paddr & Q_BASE_ADDR_M; 343 q->base |= q->size_log2 << Q_LOG2SIZE_S; 344 345 return (0); 346 } 347 348 static int 349 smmu_init_queues(struct smmu_softc *sc) 350 { 351 int err; 352 353 /* Command queue. */ 354 err = smmu_init_queue(sc, &sc->cmdq, 355 SMMU_CMDQ_PROD, SMMU_CMDQ_CONS, CMDQ_ENTRY_DWORDS); 356 if (err) 357 return (ENXIO); 358 359 /* Event queue. */ 360 err = smmu_init_queue(sc, &sc->evtq, 361 SMMU_EVENTQ_PROD, SMMU_EVENTQ_CONS, EVTQ_ENTRY_DWORDS); 362 if (err) 363 return (ENXIO); 364 365 if (!(sc->features & SMMU_FEATURE_PRI)) 366 return (0); 367 368 /* PRI queue. */ 369 err = smmu_init_queue(sc, &sc->priq, 370 SMMU_PRIQ_PROD, SMMU_PRIQ_CONS, PRIQ_ENTRY_DWORDS); 371 if (err) 372 return (ENXIO); 373 374 return (0); 375 } 376 377 /* 378 * Dump 2LVL or linear STE. 379 */ 380 static void 381 smmu_dump_ste(struct smmu_softc *sc, int sid) 382 { 383 struct smmu_strtab *strtab; 384 struct l1_desc *l1_desc; 385 uint64_t *ste, *l1; 386 int i; 387 388 strtab = &sc->strtab; 389 390 if (sc->features & SMMU_FEATURE_2_LVL_STREAM_TABLE) { 391 i = sid >> STRTAB_SPLIT; 392 l1 = (void *)((uint64_t)strtab->vaddr + 393 STRTAB_L1_DESC_DWORDS * 8 * i); 394 device_printf(sc->dev, "L1 ste == %lx\n", l1[0]); 395 396 l1_desc = &strtab->l1[i]; 397 ste = l1_desc->va; 398 if (ste == NULL) /* L2 is not initialized */ 399 return; 400 } else { 401 ste = (void *)((uint64_t)strtab->vaddr + 402 sid * (STRTAB_STE_DWORDS << 3)); 403 } 404 405 /* Dump L2 or linear STE. */ 406 for (i = 0; i < STRTAB_STE_DWORDS; i++) 407 device_printf(sc->dev, "ste[%d] == %lx\n", i, ste[i]); 408 } 409 410 static void __unused 411 smmu_dump_cd(struct smmu_softc *sc, struct smmu_cd *cd) 412 { 413 uint64_t *vaddr; 414 int i; 415 416 device_printf(sc->dev, "%s\n", __func__); 417 418 vaddr = cd->vaddr; 419 for (i = 0; i < CD_DWORDS; i++) 420 device_printf(sc->dev, "cd[%d] == %lx\n", i, vaddr[i]); 421 } 422 423 static void 424 smmu_evtq_dequeue(struct smmu_softc *sc, uint32_t *evt) 425 { 426 struct smmu_queue *evtq; 427 void *entry_addr; 428 429 evtq = &sc->evtq; 430 431 evtq->lc.val = bus_read_8(sc->res[0], evtq->prod_off); 432 entry_addr = (void *)((uint64_t)evtq->vaddr + 433 evtq->lc.cons * EVTQ_ENTRY_DWORDS * 8); 434 memcpy(evt, entry_addr, EVTQ_ENTRY_DWORDS * 8); 435 evtq->lc.cons = smmu_q_inc_cons(evtq); 436 bus_write_4(sc->res[0], evtq->cons_off, evtq->lc.cons); 437 } 438 439 static void 440 smmu_print_event(struct smmu_softc *sc, uint32_t *evt) 441 { 442 struct smmu_event *ev; 443 uintptr_t input_addr; 444 uint8_t event_id; 445 device_t dev; 446 int sid; 447 int i; 448 449 dev = sc->dev; 450 451 ev = NULL; 452 event_id = evt[0] & 0xff; 453 for (i = 0; events[i].ident != 0; i++) { 454 if (events[i].ident == event_id) { 455 ev = &events[i]; 456 break; 457 } 458 } 459 460 sid = evt[1]; 461 input_addr = evt[5]; 462 input_addr <<= 32; 463 input_addr |= evt[4]; 464 465 if (smmu_quirks_check(dev, sid, event_id, input_addr)) { 466 /* The event is known. Don't print anything. */ 467 return; 468 } 469 470 if (ev) { 471 device_printf(sc->dev, 472 "Event %s (%s) received.\n", ev->str, ev->msg); 473 } else 474 device_printf(sc->dev, "Event 0x%x received\n", event_id); 475 476 device_printf(sc->dev, "SID %x, Input Address: %jx\n", 477 sid, input_addr); 478 479 for (i = 0; i < 8; i++) 480 device_printf(sc->dev, "evt[%d] %x\n", i, evt[i]); 481 482 smmu_dump_ste(sc, sid); 483 } 484 485 static void 486 make_cmd(struct smmu_softc *sc, uint64_t *cmd, 487 struct smmu_cmdq_entry *entry) 488 { 489 490 memset(cmd, 0, CMDQ_ENTRY_DWORDS * 8); 491 cmd[0] = entry->opcode << CMD_QUEUE_OPCODE_S; 492 493 switch (entry->opcode) { 494 case CMD_TLBI_NH_VA: 495 cmd[0] |= (uint64_t)entry->tlbi.asid << TLBI_0_ASID_S; 496 cmd[1] = entry->tlbi.addr & TLBI_1_ADDR_M; 497 if (entry->tlbi.leaf) { 498 /* 499 * Leaf flag means that only cached entries 500 * for the last level of translation table walk 501 * are required to be invalidated. 502 */ 503 cmd[1] |= TLBI_1_LEAF; 504 } 505 break; 506 case CMD_TLBI_NH_ASID: 507 cmd[0] |= (uint64_t)entry->tlbi.asid << TLBI_0_ASID_S; 508 break; 509 case CMD_TLBI_NSNH_ALL: 510 case CMD_TLBI_NH_ALL: 511 case CMD_TLBI_EL2_ALL: 512 break; 513 case CMD_CFGI_CD: 514 cmd[0] |= ((uint64_t)entry->cfgi.ssid << CFGI_0_SSID_S); 515 /* FALLTROUGH */ 516 case CMD_CFGI_STE: 517 cmd[0] |= ((uint64_t)entry->cfgi.sid << CFGI_0_STE_SID_S); 518 cmd[1] |= ((uint64_t)entry->cfgi.leaf << CFGI_1_LEAF_S); 519 break; 520 case CMD_CFGI_STE_RANGE: 521 cmd[1] = (31 << CFGI_1_STE_RANGE_S); 522 break; 523 case CMD_SYNC: 524 cmd[0] |= SYNC_0_MSH_IS | SYNC_0_MSIATTR_OIWB; 525 if (entry->sync.msiaddr) { 526 cmd[0] |= SYNC_0_CS_SIG_IRQ; 527 cmd[1] |= (entry->sync.msiaddr & SYNC_1_MSIADDRESS_M); 528 } else 529 cmd[0] |= SYNC_0_CS_SIG_SEV; 530 break; 531 case CMD_PREFETCH_CONFIG: 532 cmd[0] |= ((uint64_t)entry->prefetch.sid << PREFETCH_0_SID_S); 533 break; 534 }; 535 } 536 537 static void 538 smmu_cmdq_enqueue_cmd(struct smmu_softc *sc, struct smmu_cmdq_entry *entry) 539 { 540 uint64_t cmd[CMDQ_ENTRY_DWORDS]; 541 struct smmu_queue *cmdq; 542 void *entry_addr; 543 544 cmdq = &sc->cmdq; 545 546 make_cmd(sc, cmd, entry); 547 548 SMMU_LOCK(sc); 549 550 /* Ensure that a space is available. */ 551 do { 552 cmdq->lc.cons = bus_read_4(sc->res[0], cmdq->cons_off); 553 } while (smmu_q_has_space(cmdq) == 0); 554 555 /* Write the command to the current prod entry. */ 556 entry_addr = (void *)((uint64_t)cmdq->vaddr + 557 Q_IDX(cmdq, cmdq->lc.prod) * CMDQ_ENTRY_DWORDS * 8); 558 memcpy(entry_addr, cmd, CMDQ_ENTRY_DWORDS * 8); 559 560 /* Increment prod index. */ 561 cmdq->lc.prod = smmu_q_inc_prod(cmdq); 562 bus_write_4(sc->res[0], cmdq->prod_off, cmdq->lc.prod); 563 564 SMMU_UNLOCK(sc); 565 } 566 567 static void __unused 568 smmu_poll_until_consumed(struct smmu_softc *sc, struct smmu_queue *q) 569 { 570 571 while (1) { 572 q->lc.val = bus_read_8(sc->res[0], q->prod_off); 573 if (smmu_q_empty(q)) 574 break; 575 cpu_spinwait(); 576 } 577 } 578 579 static int 580 smmu_sync(struct smmu_softc *sc) 581 { 582 struct smmu_cmdq_entry cmd; 583 struct smmu_queue *q; 584 uint32_t *base; 585 int timeout; 586 int prod; 587 588 q = &sc->cmdq; 589 prod = q->lc.prod; 590 591 /* Enqueue sync command. */ 592 cmd.opcode = CMD_SYNC; 593 cmd.sync.msiaddr = q->paddr + Q_IDX(q, prod) * CMDQ_ENTRY_DWORDS * 8; 594 smmu_cmdq_enqueue_cmd(sc, &cmd); 595 596 /* Wait for the sync completion. */ 597 base = (void *)((uint64_t)q->vaddr + 598 Q_IDX(q, prod) * CMDQ_ENTRY_DWORDS * 8); 599 600 /* 601 * It takes around 200 loops (6 instructions each) 602 * on Neoverse N1 to complete the sync. 603 */ 604 timeout = 10000; 605 606 do { 607 if (*base == 0) { 608 /* MSI write completed. */ 609 break; 610 } 611 cpu_spinwait(); 612 } while (timeout--); 613 614 if (timeout < 0) 615 device_printf(sc->dev, "Failed to sync\n"); 616 617 return (0); 618 } 619 620 static int 621 smmu_sync_cd(struct smmu_softc *sc, int sid, int ssid, bool leaf) 622 { 623 struct smmu_cmdq_entry cmd; 624 625 cmd.opcode = CMD_CFGI_CD; 626 cmd.cfgi.sid = sid; 627 cmd.cfgi.ssid = ssid; 628 cmd.cfgi.leaf = leaf; 629 smmu_cmdq_enqueue_cmd(sc, &cmd); 630 631 return (0); 632 } 633 634 static void 635 smmu_invalidate_all_sid(struct smmu_softc *sc) 636 { 637 struct smmu_cmdq_entry cmd; 638 639 /* Invalidate cached config */ 640 cmd.opcode = CMD_CFGI_STE_RANGE; 641 smmu_cmdq_enqueue_cmd(sc, &cmd); 642 smmu_sync(sc); 643 } 644 645 static void 646 smmu_tlbi_all(struct smmu_softc *sc) 647 { 648 struct smmu_cmdq_entry cmd; 649 650 /* Invalidate entire TLB */ 651 cmd.opcode = CMD_TLBI_NSNH_ALL; 652 smmu_cmdq_enqueue_cmd(sc, &cmd); 653 smmu_sync(sc); 654 } 655 656 static void 657 smmu_tlbi_asid(struct smmu_softc *sc, uint16_t asid) 658 { 659 struct smmu_cmdq_entry cmd; 660 661 /* Invalidate TLB for an ASID. */ 662 cmd.opcode = CMD_TLBI_NH_ASID; 663 cmd.tlbi.asid = asid; 664 smmu_cmdq_enqueue_cmd(sc, &cmd); 665 smmu_sync(sc); 666 } 667 668 static void 669 smmu_tlbi_va(struct smmu_softc *sc, vm_offset_t va, uint16_t asid) 670 { 671 struct smmu_cmdq_entry cmd; 672 673 /* Invalidate specific range */ 674 cmd.opcode = CMD_TLBI_NH_VA; 675 cmd.tlbi.asid = asid; 676 cmd.tlbi.vmid = 0; 677 cmd.tlbi.leaf = true; /* We change only L3. */ 678 cmd.tlbi.addr = va; 679 smmu_cmdq_enqueue_cmd(sc, &cmd); 680 } 681 682 static void 683 smmu_invalidate_sid(struct smmu_softc *sc, uint32_t sid) 684 { 685 struct smmu_cmdq_entry cmd; 686 687 /* Invalidate cached config */ 688 cmd.opcode = CMD_CFGI_STE; 689 cmd.cfgi.sid = sid; 690 smmu_cmdq_enqueue_cmd(sc, &cmd); 691 smmu_sync(sc); 692 } 693 694 static void 695 smmu_prefetch_sid(struct smmu_softc *sc, uint32_t sid) 696 { 697 struct smmu_cmdq_entry cmd; 698 699 cmd.opcode = CMD_PREFETCH_CONFIG; 700 cmd.prefetch.sid = sid; 701 smmu_cmdq_enqueue_cmd(sc, &cmd); 702 smmu_sync(sc); 703 } 704 705 /* 706 * Init STE in bypass mode. Traffic is not translated for the sid. 707 */ 708 static void 709 smmu_init_ste_bypass(struct smmu_softc *sc, uint32_t sid, uint64_t *ste) 710 { 711 uint64_t val; 712 713 val = STE0_VALID | STE0_CONFIG_BYPASS; 714 715 ste[1] = STE1_SHCFG_INCOMING | STE1_EATS_FULLATS; 716 ste[2] = 0; 717 ste[3] = 0; 718 ste[4] = 0; 719 ste[5] = 0; 720 ste[6] = 0; 721 ste[7] = 0; 722 723 smmu_invalidate_sid(sc, sid); 724 ste[0] = val; 725 dsb(sy); 726 smmu_invalidate_sid(sc, sid); 727 728 smmu_prefetch_sid(sc, sid); 729 } 730 731 /* 732 * Enable Stage1 (S1) translation for the sid. 733 */ 734 static int 735 smmu_init_ste_s1(struct smmu_softc *sc, struct smmu_cd *cd, 736 uint32_t sid, uint64_t *ste) 737 { 738 uint64_t val; 739 740 val = STE0_VALID; 741 742 /* S1 */ 743 ste[1] = STE1_EATS_FULLATS | 744 STE1_S1CSH_IS | 745 STE1_S1CIR_WBRA | 746 STE1_S1COR_WBRA | 747 STE1_STRW_NS_EL1; 748 ste[2] = 0; 749 ste[3] = 0; 750 ste[4] = 0; 751 ste[5] = 0; 752 ste[6] = 0; 753 ste[7] = 0; 754 755 if (sc->features & SMMU_FEATURE_STALL && 756 ((sc->features & SMMU_FEATURE_STALL_FORCE) == 0)) 757 ste[1] |= STE1_S1STALLD; 758 759 /* Configure STE */ 760 val |= (cd->paddr & STE0_S1CONTEXTPTR_M); 761 val |= STE0_CONFIG_S1_TRANS; 762 763 smmu_invalidate_sid(sc, sid); 764 765 /* The STE[0] has to be written in a single blast, last of all. */ 766 ste[0] = val; 767 dsb(sy); 768 769 smmu_invalidate_sid(sc, sid); 770 smmu_sync_cd(sc, sid, 0, true); 771 smmu_invalidate_sid(sc, sid); 772 773 /* The sid will be used soon most likely. */ 774 smmu_prefetch_sid(sc, sid); 775 776 return (0); 777 } 778 779 static int 780 smmu_init_ste(struct smmu_softc *sc, struct smmu_cd *cd, int sid, bool bypass) 781 { 782 struct smmu_strtab *strtab; 783 struct l1_desc *l1_desc; 784 uint64_t *addr; 785 786 strtab = &sc->strtab; 787 788 if (sc->features & SMMU_FEATURE_2_LVL_STREAM_TABLE) { 789 l1_desc = &strtab->l1[sid >> STRTAB_SPLIT]; 790 addr = l1_desc->va; 791 addr += (sid & ((1 << STRTAB_SPLIT) - 1)) * STRTAB_STE_DWORDS; 792 } else { 793 addr = (void *)((uint64_t)strtab->vaddr + 794 STRTAB_STE_DWORDS * 8 * sid); 795 }; 796 797 if (bypass) 798 smmu_init_ste_bypass(sc, sid, addr); 799 else 800 smmu_init_ste_s1(sc, cd, sid, addr); 801 802 smmu_sync(sc); 803 804 return (0); 805 } 806 807 static int 808 smmu_init_cd(struct smmu_softc *sc, struct smmu_domain *domain) 809 { 810 vm_paddr_t paddr; 811 uint64_t *ptr; 812 uint64_t val; 813 vm_size_t size; 814 struct smmu_cd *cd; 815 pmap_t p; 816 817 size = 1 * (CD_DWORDS << 3); 818 819 p = &domain->p; 820 cd = domain->cd = malloc(sizeof(struct smmu_cd), 821 M_SMMU, M_WAITOK | M_ZERO); 822 823 cd->vaddr = contigmalloc(size, M_SMMU, 824 M_WAITOK | M_ZERO, /* flags */ 825 0, /* low */ 826 (1ul << 40) - 1, /* high */ 827 size, /* alignment */ 828 0); /* boundary */ 829 if (cd->vaddr == NULL) { 830 device_printf(sc->dev, "Failed to allocate CD\n"); 831 return (ENXIO); 832 } 833 834 cd->size = size; 835 cd->paddr = vtophys(cd->vaddr); 836 837 ptr = cd->vaddr; 838 839 val = CD0_VALID; 840 val |= CD0_AA64; 841 val |= CD0_R; 842 val |= CD0_A; 843 val |= CD0_ASET; 844 val |= (uint64_t)domain->asid << CD0_ASID_S; 845 val |= CD0_TG0_4KB; 846 val |= CD0_EPD1; /* Disable TT1 */ 847 val |= ((64 - sc->ias) << CD0_T0SZ_S); 848 val |= CD0_IPS_48BITS; 849 850 paddr = p->pm_l0_paddr & CD1_TTB0_M; 851 KASSERT(paddr == p->pm_l0_paddr, ("bad allocation 1")); 852 853 ptr[1] = paddr; 854 ptr[2] = 0; 855 ptr[3] = MAIR_ATTR(MAIR_DEVICE_nGnRnE, VM_MEMATTR_DEVICE) | 856 MAIR_ATTR(MAIR_NORMAL_NC, VM_MEMATTR_UNCACHEABLE) | 857 MAIR_ATTR(MAIR_NORMAL_WB, VM_MEMATTR_WRITE_BACK) | 858 MAIR_ATTR(MAIR_NORMAL_WT, VM_MEMATTR_WRITE_THROUGH); 859 860 /* Install the CD. */ 861 ptr[0] = val; 862 863 return (0); 864 } 865 866 static int 867 smmu_init_strtab_linear(struct smmu_softc *sc) 868 { 869 struct smmu_strtab *strtab; 870 vm_paddr_t base; 871 uint32_t size; 872 uint64_t reg; 873 874 strtab = &sc->strtab; 875 strtab->num_l1_entries = (1 << sc->sid_bits); 876 877 size = strtab->num_l1_entries * (STRTAB_STE_DWORDS << 3); 878 879 if (bootverbose) 880 device_printf(sc->dev, 881 "%s: linear strtab size %d, num_l1_entries %d\n", 882 __func__, size, strtab->num_l1_entries); 883 884 strtab->vaddr = contigmalloc(size, M_SMMU, 885 M_WAITOK | M_ZERO, /* flags */ 886 0, /* low */ 887 (1ul << 48) - 1, /* high */ 888 size, /* alignment */ 889 0); /* boundary */ 890 if (strtab->vaddr == NULL) { 891 device_printf(sc->dev, "failed to allocate strtab\n"); 892 return (ENXIO); 893 } 894 895 reg = STRTAB_BASE_CFG_FMT_LINEAR; 896 reg |= sc->sid_bits << STRTAB_BASE_CFG_LOG2SIZE_S; 897 strtab->base_cfg = (uint32_t)reg; 898 899 base = vtophys(strtab->vaddr); 900 901 reg = base & STRTAB_BASE_ADDR_M; 902 KASSERT(reg == base, ("bad allocation 2")); 903 reg |= STRTAB_BASE_RA; 904 strtab->base = reg; 905 906 return (0); 907 } 908 909 static int 910 smmu_init_strtab_2lvl(struct smmu_softc *sc) 911 { 912 struct smmu_strtab *strtab; 913 vm_paddr_t base; 914 uint64_t reg_base; 915 uint32_t l1size; 916 uint32_t size; 917 uint32_t reg; 918 int sz; 919 920 strtab = &sc->strtab; 921 922 size = STRTAB_L1_SZ_SHIFT - (ilog2(STRTAB_L1_DESC_DWORDS) + 3); 923 size = min(size, sc->sid_bits - STRTAB_SPLIT); 924 strtab->num_l1_entries = (1 << size); 925 size += STRTAB_SPLIT; 926 927 l1size = strtab->num_l1_entries * (STRTAB_L1_DESC_DWORDS << 3); 928 929 if (bootverbose) 930 device_printf(sc->dev, 931 "%s: size %d, l1 entries %d, l1size %d\n", 932 __func__, size, strtab->num_l1_entries, l1size); 933 934 strtab->vaddr = contigmalloc(l1size, M_SMMU, 935 M_WAITOK | M_ZERO, /* flags */ 936 0, /* low */ 937 (1ul << 48) - 1, /* high */ 938 l1size, /* alignment */ 939 0); /* boundary */ 940 if (strtab->vaddr == NULL) { 941 device_printf(sc->dev, "Failed to allocate 2lvl strtab.\n"); 942 return (ENOMEM); 943 } 944 945 sz = strtab->num_l1_entries * sizeof(struct l1_desc); 946 947 strtab->l1 = malloc(sz, M_SMMU, M_WAITOK | M_ZERO); 948 if (strtab->l1 == NULL) { 949 contigfree(strtab->vaddr, l1size, M_SMMU); 950 return (ENOMEM); 951 } 952 953 reg = STRTAB_BASE_CFG_FMT_2LVL; 954 reg |= size << STRTAB_BASE_CFG_LOG2SIZE_S; 955 reg |= STRTAB_SPLIT << STRTAB_BASE_CFG_SPLIT_S; 956 strtab->base_cfg = (uint32_t)reg; 957 958 base = vtophys(strtab->vaddr); 959 960 reg_base = base & STRTAB_BASE_ADDR_M; 961 KASSERT(reg_base == base, ("bad allocation 3")); 962 reg_base |= STRTAB_BASE_RA; 963 strtab->base = reg_base; 964 965 return (0); 966 } 967 968 static int 969 smmu_init_strtab(struct smmu_softc *sc) 970 { 971 int error; 972 973 if (sc->features & SMMU_FEATURE_2_LVL_STREAM_TABLE) 974 error = smmu_init_strtab_2lvl(sc); 975 else 976 error = smmu_init_strtab_linear(sc); 977 978 return (error); 979 } 980 981 static int 982 smmu_init_l1_entry(struct smmu_softc *sc, int sid) 983 { 984 struct smmu_strtab *strtab; 985 struct l1_desc *l1_desc; 986 uint64_t *addr; 987 uint64_t val; 988 size_t size; 989 int i; 990 991 strtab = &sc->strtab; 992 l1_desc = &strtab->l1[sid >> STRTAB_SPLIT]; 993 994 size = 1 << (STRTAB_SPLIT + ilog2(STRTAB_STE_DWORDS) + 3); 995 996 l1_desc->span = STRTAB_SPLIT + 1; 997 l1_desc->size = size; 998 l1_desc->va = contigmalloc(size, M_SMMU, 999 M_WAITOK | M_ZERO, /* flags */ 1000 0, /* low */ 1001 (1ul << 48) - 1, /* high */ 1002 size, /* alignment */ 1003 0); /* boundary */ 1004 if (l1_desc->va == NULL) { 1005 device_printf(sc->dev, "failed to allocate l2 entry\n"); 1006 return (ENXIO); 1007 } 1008 1009 l1_desc->pa = vtophys(l1_desc->va); 1010 1011 i = sid >> STRTAB_SPLIT; 1012 addr = (void *)((uint64_t)strtab->vaddr + 1013 STRTAB_L1_DESC_DWORDS * 8 * i); 1014 1015 /* Install the L1 entry. */ 1016 val = l1_desc->pa & STRTAB_L1_DESC_L2PTR_M; 1017 KASSERT(val == l1_desc->pa, ("bad allocation 4")); 1018 val |= l1_desc->span; 1019 *addr = val; 1020 1021 return (0); 1022 } 1023 1024 static void 1025 smmu_deinit_l1_entry(struct smmu_softc *sc, int sid) 1026 { 1027 struct smmu_strtab *strtab; 1028 struct l1_desc *l1_desc; 1029 uint64_t *addr; 1030 int i; 1031 1032 strtab = &sc->strtab; 1033 1034 i = sid >> STRTAB_SPLIT; 1035 addr = (void *)((uint64_t)strtab->vaddr + 1036 STRTAB_L1_DESC_DWORDS * 8 * i); 1037 *addr = 0; 1038 1039 if (sc->features & SMMU_FEATURE_2_LVL_STREAM_TABLE) { 1040 l1_desc = &strtab->l1[sid >> STRTAB_SPLIT]; 1041 contigfree(l1_desc->va, l1_desc->size, M_SMMU); 1042 } 1043 } 1044 1045 static int 1046 smmu_disable(struct smmu_softc *sc) 1047 { 1048 uint32_t reg; 1049 int error; 1050 1051 /* Disable SMMU */ 1052 reg = bus_read_4(sc->res[0], SMMU_CR0); 1053 reg &= ~CR0_SMMUEN; 1054 error = smmu_write_ack(sc, SMMU_CR0, SMMU_CR0ACK, reg); 1055 if (error) 1056 device_printf(sc->dev, "Could not disable SMMU.\n"); 1057 1058 return (0); 1059 } 1060 1061 static int 1062 smmu_event_intr(void *arg) 1063 { 1064 uint32_t evt[EVTQ_ENTRY_DWORDS * 2]; 1065 struct smmu_softc *sc; 1066 1067 sc = arg; 1068 1069 do { 1070 smmu_evtq_dequeue(sc, evt); 1071 smmu_print_event(sc, evt); 1072 } while (!smmu_q_empty(&sc->evtq)); 1073 1074 return (FILTER_HANDLED); 1075 } 1076 1077 static int __unused 1078 smmu_sync_intr(void *arg) 1079 { 1080 struct smmu_softc *sc; 1081 1082 sc = arg; 1083 1084 device_printf(sc->dev, "%s\n", __func__); 1085 1086 return (FILTER_HANDLED); 1087 } 1088 1089 static int 1090 smmu_gerr_intr(void *arg) 1091 { 1092 struct smmu_softc *sc; 1093 1094 sc = arg; 1095 1096 device_printf(sc->dev, "SMMU Global Error\n"); 1097 1098 return (FILTER_HANDLED); 1099 } 1100 1101 static int 1102 smmu_enable_interrupts(struct smmu_softc *sc) 1103 { 1104 uint32_t reg; 1105 int error; 1106 1107 /* Disable MSI. */ 1108 bus_write_8(sc->res[0], SMMU_GERROR_IRQ_CFG0, 0); 1109 bus_write_4(sc->res[0], SMMU_GERROR_IRQ_CFG1, 0); 1110 bus_write_4(sc->res[0], SMMU_GERROR_IRQ_CFG2, 0); 1111 1112 bus_write_8(sc->res[0], SMMU_EVENTQ_IRQ_CFG0, 0); 1113 bus_write_4(sc->res[0], SMMU_EVENTQ_IRQ_CFG1, 0); 1114 bus_write_4(sc->res[0], SMMU_EVENTQ_IRQ_CFG2, 0); 1115 1116 if (sc->features & CR0_PRIQEN) { 1117 bus_write_8(sc->res[0], SMMU_PRIQ_IRQ_CFG0, 0); 1118 bus_write_4(sc->res[0], SMMU_PRIQ_IRQ_CFG1, 0); 1119 bus_write_4(sc->res[0], SMMU_PRIQ_IRQ_CFG2, 0); 1120 } 1121 1122 /* Disable any interrupts. */ 1123 error = smmu_write_ack(sc, SMMU_IRQ_CTRL, SMMU_IRQ_CTRLACK, 0); 1124 if (error) { 1125 device_printf(sc->dev, "Could not disable interrupts.\n"); 1126 return (ENXIO); 1127 } 1128 1129 /* Enable interrupts. */ 1130 reg = IRQ_CTRL_EVENTQ_IRQEN | IRQ_CTRL_GERROR_IRQEN; 1131 if (sc->features & SMMU_FEATURE_PRI) 1132 reg |= IRQ_CTRL_PRIQ_IRQEN; 1133 1134 error = smmu_write_ack(sc, SMMU_IRQ_CTRL, SMMU_IRQ_CTRLACK, reg); 1135 if (error) { 1136 device_printf(sc->dev, "Could not enable interrupts.\n"); 1137 return (ENXIO); 1138 } 1139 1140 return (0); 1141 } 1142 1143 #ifdef DEV_ACPI 1144 static void 1145 smmu_configure_intr(struct smmu_softc *sc, struct resource *res) 1146 { 1147 struct intr_map_data_acpi *ad; 1148 struct intr_map_data *data; 1149 1150 data = rman_get_virtual(res); 1151 KASSERT(data != NULL, ("data is NULL")); 1152 1153 if (data->type == INTR_MAP_DATA_ACPI) { 1154 ad = (struct intr_map_data_acpi *)data; 1155 ad->trig = INTR_TRIGGER_EDGE; 1156 ad->pol = INTR_POLARITY_HIGH; 1157 } 1158 } 1159 #endif 1160 1161 static int 1162 smmu_setup_interrupts(struct smmu_softc *sc) 1163 { 1164 device_t dev; 1165 int error; 1166 1167 dev = sc->dev; 1168 1169 #ifdef DEV_ACPI 1170 /* 1171 * Configure SMMU interrupts as EDGE triggered manually 1172 * as ACPI tables carries no information for that. 1173 */ 1174 smmu_configure_intr(sc, sc->res[1]); 1175 /* PRIQ is not in use. */ 1176 smmu_configure_intr(sc, sc->res[3]); 1177 smmu_configure_intr(sc, sc->res[4]); 1178 #endif 1179 1180 error = bus_setup_intr(dev, sc->res[1], INTR_TYPE_MISC, 1181 smmu_event_intr, NULL, sc, &sc->intr_cookie[0]); 1182 if (error) { 1183 device_printf(dev, "Couldn't setup Event interrupt handler\n"); 1184 return (ENXIO); 1185 } 1186 1187 error = bus_setup_intr(dev, sc->res[4], INTR_TYPE_MISC, 1188 smmu_gerr_intr, NULL, sc, &sc->intr_cookie[2]); 1189 if (error) { 1190 device_printf(dev, "Couldn't setup Gerr interrupt handler\n"); 1191 return (ENXIO); 1192 } 1193 1194 return (0); 1195 } 1196 1197 static int 1198 smmu_reset(struct smmu_softc *sc) 1199 { 1200 struct smmu_cmdq_entry cmd; 1201 struct smmu_strtab *strtab; 1202 int error; 1203 int reg; 1204 1205 reg = bus_read_4(sc->res[0], SMMU_CR0); 1206 1207 if (reg & CR0_SMMUEN) 1208 device_printf(sc->dev, 1209 "%s: Warning: SMMU is enabled\n", __func__); 1210 1211 error = smmu_disable(sc); 1212 if (error) 1213 device_printf(sc->dev, 1214 "%s: Could not disable SMMU.\n", __func__); 1215 1216 if (smmu_enable_interrupts(sc) != 0) { 1217 device_printf(sc->dev, "Could not enable interrupts.\n"); 1218 return (ENXIO); 1219 } 1220 1221 reg = CR1_TABLE_SH_IS | 1222 CR1_TABLE_OC_WBC | 1223 CR1_TABLE_IC_WBC | 1224 CR1_QUEUE_SH_IS | 1225 CR1_QUEUE_OC_WBC | 1226 CR1_QUEUE_IC_WBC; 1227 bus_write_4(sc->res[0], SMMU_CR1, reg); 1228 1229 reg = CR2_PTM | CR2_RECINVSID | CR2_E2H; 1230 bus_write_4(sc->res[0], SMMU_CR2, reg); 1231 1232 /* Stream table. */ 1233 strtab = &sc->strtab; 1234 bus_write_8(sc->res[0], SMMU_STRTAB_BASE, strtab->base); 1235 bus_write_4(sc->res[0], SMMU_STRTAB_BASE_CFG, strtab->base_cfg); 1236 1237 /* Command queue. */ 1238 bus_write_8(sc->res[0], SMMU_CMDQ_BASE, sc->cmdq.base); 1239 bus_write_4(sc->res[0], SMMU_CMDQ_PROD, sc->cmdq.lc.prod); 1240 bus_write_4(sc->res[0], SMMU_CMDQ_CONS, sc->cmdq.lc.cons); 1241 1242 reg = CR0_CMDQEN; 1243 error = smmu_write_ack(sc, SMMU_CR0, SMMU_CR0ACK, reg); 1244 if (error) { 1245 device_printf(sc->dev, "Could not enable command queue\n"); 1246 return (ENXIO); 1247 } 1248 1249 /* Invalidate cached configuration. */ 1250 smmu_invalidate_all_sid(sc); 1251 1252 if (sc->features & SMMU_FEATURE_HYP) { 1253 cmd.opcode = CMD_TLBI_EL2_ALL; 1254 smmu_cmdq_enqueue_cmd(sc, &cmd); 1255 }; 1256 1257 /* Invalidate TLB. */ 1258 smmu_tlbi_all(sc); 1259 1260 /* Event queue */ 1261 bus_write_8(sc->res[0], SMMU_EVENTQ_BASE, sc->evtq.base); 1262 bus_write_4(sc->res[0], SMMU_EVENTQ_PROD, sc->evtq.lc.prod); 1263 bus_write_4(sc->res[0], SMMU_EVENTQ_CONS, sc->evtq.lc.cons); 1264 1265 reg |= CR0_EVENTQEN; 1266 error = smmu_write_ack(sc, SMMU_CR0, SMMU_CR0ACK, reg); 1267 if (error) { 1268 device_printf(sc->dev, "Could not enable event queue\n"); 1269 return (ENXIO); 1270 } 1271 1272 if (sc->features & SMMU_FEATURE_PRI) { 1273 /* PRI queue */ 1274 bus_write_8(sc->res[0], SMMU_PRIQ_BASE, sc->priq.base); 1275 bus_write_4(sc->res[0], SMMU_PRIQ_PROD, sc->priq.lc.prod); 1276 bus_write_4(sc->res[0], SMMU_PRIQ_CONS, sc->priq.lc.cons); 1277 1278 reg |= CR0_PRIQEN; 1279 error = smmu_write_ack(sc, SMMU_CR0, SMMU_CR0ACK, reg); 1280 if (error) { 1281 device_printf(sc->dev, "Could not enable PRI queue\n"); 1282 return (ENXIO); 1283 } 1284 } 1285 1286 if (sc->features & SMMU_FEATURE_ATS) { 1287 reg |= CR0_ATSCHK; 1288 error = smmu_write_ack(sc, SMMU_CR0, SMMU_CR0ACK, reg); 1289 if (error) { 1290 device_printf(sc->dev, "Could not enable ATS check.\n"); 1291 return (ENXIO); 1292 } 1293 } 1294 1295 reg |= CR0_SMMUEN; 1296 error = smmu_write_ack(sc, SMMU_CR0, SMMU_CR0ACK, reg); 1297 if (error) { 1298 device_printf(sc->dev, "Could not enable SMMU.\n"); 1299 return (ENXIO); 1300 } 1301 1302 return (0); 1303 } 1304 1305 static int 1306 smmu_check_features(struct smmu_softc *sc) 1307 { 1308 uint32_t reg; 1309 uint32_t val; 1310 1311 sc->features = 0; 1312 1313 reg = bus_read_4(sc->res[0], SMMU_IDR0); 1314 1315 if (reg & IDR0_ST_LVL_2) { 1316 if (bootverbose) 1317 device_printf(sc->dev, 1318 "2-level stream table supported.\n"); 1319 sc->features |= SMMU_FEATURE_2_LVL_STREAM_TABLE; 1320 } 1321 1322 if (reg & IDR0_CD2L) { 1323 if (bootverbose) 1324 device_printf(sc->dev, 1325 "2-level CD table supported.\n"); 1326 sc->features |= SMMU_FEATURE_2_LVL_CD; 1327 } 1328 1329 switch (reg & IDR0_TTENDIAN_M) { 1330 case IDR0_TTENDIAN_MIXED: 1331 if (bootverbose) 1332 device_printf(sc->dev, "Mixed endianess supported.\n"); 1333 sc->features |= SMMU_FEATURE_TT_LE; 1334 sc->features |= SMMU_FEATURE_TT_BE; 1335 break; 1336 case IDR0_TTENDIAN_LITTLE: 1337 if (bootverbose) 1338 device_printf(sc->dev, 1339 "Little endian supported only.\n"); 1340 sc->features |= SMMU_FEATURE_TT_LE; 1341 break; 1342 case IDR0_TTENDIAN_BIG: 1343 if (bootverbose) 1344 device_printf(sc->dev, "Big endian supported only.\n"); 1345 sc->features |= SMMU_FEATURE_TT_BE; 1346 break; 1347 default: 1348 device_printf(sc->dev, "Unsupported endianness.\n"); 1349 return (ENXIO); 1350 } 1351 1352 if (reg & IDR0_SEV) 1353 sc->features |= SMMU_FEATURE_SEV; 1354 1355 if (reg & IDR0_MSI) { 1356 if (bootverbose) 1357 device_printf(sc->dev, "MSI feature present.\n"); 1358 sc->features |= SMMU_FEATURE_MSI; 1359 } 1360 1361 if (reg & IDR0_HYP) { 1362 if (bootverbose) 1363 device_printf(sc->dev, "HYP feature present.\n"); 1364 sc->features |= SMMU_FEATURE_HYP; 1365 } 1366 1367 if (reg & IDR0_ATS) 1368 sc->features |= SMMU_FEATURE_ATS; 1369 1370 if (reg & IDR0_PRI) 1371 sc->features |= SMMU_FEATURE_PRI; 1372 1373 switch (reg & IDR0_STALL_MODEL_M) { 1374 case IDR0_STALL_MODEL_FORCE: 1375 /* Stall is forced. */ 1376 sc->features |= SMMU_FEATURE_STALL_FORCE; 1377 /* FALLTHROUGH */ 1378 case IDR0_STALL_MODEL_STALL: 1379 sc->features |= SMMU_FEATURE_STALL; 1380 break; 1381 } 1382 1383 /* Grab translation stages supported. */ 1384 if (reg & IDR0_S1P) { 1385 if (bootverbose) 1386 device_printf(sc->dev, 1387 "Stage 1 translation supported.\n"); 1388 sc->features |= SMMU_FEATURE_S1P; 1389 } 1390 if (reg & IDR0_S2P) { 1391 if (bootverbose) 1392 device_printf(sc->dev, 1393 "Stage 2 translation supported.\n"); 1394 sc->features |= SMMU_FEATURE_S2P; 1395 } 1396 1397 switch (reg & IDR0_TTF_M) { 1398 case IDR0_TTF_ALL: 1399 case IDR0_TTF_AA64: 1400 sc->ias = 40; 1401 break; 1402 default: 1403 device_printf(sc->dev, "No AArch64 table format support.\n"); 1404 return (ENXIO); 1405 } 1406 1407 if (reg & IDR0_ASID16) 1408 sc->asid_bits = 16; 1409 else 1410 sc->asid_bits = 8; 1411 1412 if (bootverbose) 1413 device_printf(sc->dev, "ASID bits %d\n", sc->asid_bits); 1414 1415 if (reg & IDR0_VMID16) 1416 sc->vmid_bits = 16; 1417 else 1418 sc->vmid_bits = 8; 1419 1420 reg = bus_read_4(sc->res[0], SMMU_IDR1); 1421 1422 if (reg & (IDR1_TABLES_PRESET | IDR1_QUEUES_PRESET | IDR1_REL)) { 1423 device_printf(sc->dev, 1424 "Embedded implementations not supported by this driver.\n"); 1425 return (ENXIO); 1426 } 1427 1428 val = (reg & IDR1_CMDQS_M) >> IDR1_CMDQS_S; 1429 sc->cmdq.size_log2 = val; 1430 if (bootverbose) 1431 device_printf(sc->dev, "CMD queue bits %d\n", val); 1432 1433 val = (reg & IDR1_EVENTQS_M) >> IDR1_EVENTQS_S; 1434 sc->evtq.size_log2 = val; 1435 if (bootverbose) 1436 device_printf(sc->dev, "EVENT queue bits %d\n", val); 1437 1438 if (sc->features & SMMU_FEATURE_PRI) { 1439 val = (reg & IDR1_PRIQS_M) >> IDR1_PRIQS_S; 1440 sc->priq.size_log2 = val; 1441 if (bootverbose) 1442 device_printf(sc->dev, "PRI queue bits %d\n", val); 1443 } 1444 1445 sc->ssid_bits = (reg & IDR1_SSIDSIZE_M) >> IDR1_SSIDSIZE_S; 1446 sc->sid_bits = (reg & IDR1_SIDSIZE_M) >> IDR1_SIDSIZE_S; 1447 1448 if (sc->sid_bits <= STRTAB_SPLIT) 1449 sc->features &= ~SMMU_FEATURE_2_LVL_STREAM_TABLE; 1450 1451 if (bootverbose) { 1452 device_printf(sc->dev, "SSID bits %d\n", sc->ssid_bits); 1453 device_printf(sc->dev, "SID bits %d\n", sc->sid_bits); 1454 } 1455 1456 /* IDR3 */ 1457 reg = bus_read_4(sc->res[0], SMMU_IDR3); 1458 if (reg & IDR3_RIL) 1459 sc->features |= SMMU_FEATURE_RANGE_INV; 1460 1461 /* IDR5 */ 1462 reg = bus_read_4(sc->res[0], SMMU_IDR5); 1463 1464 switch (reg & IDR5_OAS_M) { 1465 case IDR5_OAS_32: 1466 sc->oas = 32; 1467 break; 1468 case IDR5_OAS_36: 1469 sc->oas = 36; 1470 break; 1471 case IDR5_OAS_40: 1472 sc->oas = 40; 1473 break; 1474 case IDR5_OAS_42: 1475 sc->oas = 42; 1476 break; 1477 case IDR5_OAS_44: 1478 sc->oas = 44; 1479 break; 1480 case IDR5_OAS_48: 1481 sc->oas = 48; 1482 break; 1483 case IDR5_OAS_52: 1484 sc->oas = 52; 1485 break; 1486 } 1487 1488 sc->pgsizes = 0; 1489 if (reg & IDR5_GRAN64K) 1490 sc->pgsizes |= 64 * 1024; 1491 if (reg & IDR5_GRAN16K) 1492 sc->pgsizes |= 16 * 1024; 1493 if (reg & IDR5_GRAN4K) 1494 sc->pgsizes |= 4 * 1024; 1495 1496 if ((reg & IDR5_VAX_M) == IDR5_VAX_52) 1497 sc->features |= SMMU_FEATURE_VAX; 1498 1499 return (0); 1500 } 1501 1502 static void 1503 smmu_init_asids(struct smmu_softc *sc) 1504 { 1505 1506 sc->asid_set_size = (1 << sc->asid_bits); 1507 sc->asid_set = bit_alloc(sc->asid_set_size, M_SMMU, M_WAITOK); 1508 mtx_init(&sc->asid_set_mutex, "asid set", NULL, MTX_SPIN); 1509 } 1510 1511 static int 1512 smmu_asid_alloc(struct smmu_softc *sc, int *new_asid) 1513 { 1514 1515 mtx_lock_spin(&sc->asid_set_mutex); 1516 bit_ffc(sc->asid_set, sc->asid_set_size, new_asid); 1517 if (*new_asid == -1) { 1518 mtx_unlock_spin(&sc->asid_set_mutex); 1519 return (ENOMEM); 1520 } 1521 bit_set(sc->asid_set, *new_asid); 1522 mtx_unlock_spin(&sc->asid_set_mutex); 1523 1524 return (0); 1525 } 1526 1527 static void 1528 smmu_asid_free(struct smmu_softc *sc, int asid) 1529 { 1530 1531 mtx_lock_spin(&sc->asid_set_mutex); 1532 bit_clear(sc->asid_set, asid); 1533 mtx_unlock_spin(&sc->asid_set_mutex); 1534 } 1535 1536 /* 1537 * Device interface. 1538 */ 1539 int 1540 smmu_attach(device_t dev) 1541 { 1542 struct smmu_softc *sc; 1543 int error; 1544 1545 sc = device_get_softc(dev); 1546 sc->dev = dev; 1547 1548 mtx_init(&sc->sc_mtx, device_get_nameunit(sc->dev), "smmu", MTX_DEF); 1549 1550 error = bus_alloc_resources(dev, smmu_spec, sc->res); 1551 if (error) { 1552 device_printf(dev, "Couldn't allocate resources.\n"); 1553 return (ENXIO); 1554 } 1555 1556 error = smmu_setup_interrupts(sc); 1557 if (error) { 1558 bus_release_resources(dev, smmu_spec, sc->res); 1559 return (ENXIO); 1560 } 1561 1562 error = smmu_check_features(sc); 1563 if (error) { 1564 device_printf(dev, "Some features are required " 1565 "but not supported by hardware.\n"); 1566 return (ENXIO); 1567 } 1568 1569 smmu_init_asids(sc); 1570 1571 error = smmu_init_queues(sc); 1572 if (error) { 1573 device_printf(dev, "Couldn't allocate queues.\n"); 1574 return (ENXIO); 1575 } 1576 1577 error = smmu_init_strtab(sc); 1578 if (error) { 1579 device_printf(dev, "Couldn't allocate strtab.\n"); 1580 return (ENXIO); 1581 } 1582 1583 error = smmu_reset(sc); 1584 if (error) { 1585 device_printf(dev, "Couldn't reset SMMU.\n"); 1586 return (ENXIO); 1587 } 1588 1589 return (0); 1590 } 1591 1592 int 1593 smmu_detach(device_t dev) 1594 { 1595 struct smmu_softc *sc; 1596 1597 sc = device_get_softc(dev); 1598 1599 bus_release_resources(dev, smmu_spec, sc->res); 1600 1601 return (0); 1602 } 1603 1604 static int 1605 smmu_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1606 { 1607 struct smmu_softc *sc; 1608 1609 sc = device_get_softc(dev); 1610 1611 device_printf(sc->dev, "%s\n", __func__); 1612 1613 return (ENOENT); 1614 } 1615 1616 static int 1617 smmu_unmap(device_t dev, struct iommu_domain *iodom, 1618 vm_offset_t va, bus_size_t size) 1619 { 1620 struct smmu_domain *domain; 1621 struct smmu_softc *sc; 1622 int err; 1623 int i; 1624 1625 sc = device_get_softc(dev); 1626 1627 domain = (struct smmu_domain *)iodom; 1628 1629 err = 0; 1630 1631 dprintf("%s: %lx, %ld, domain %d\n", __func__, va, size, domain->asid); 1632 1633 for (i = 0; i < size; i += PAGE_SIZE) { 1634 if (pmap_smmu_remove(&domain->p, va) == 0) { 1635 /* pmap entry removed, invalidate TLB. */ 1636 smmu_tlbi_va(sc, va, domain->asid); 1637 } else { 1638 err = ENOENT; 1639 break; 1640 } 1641 va += PAGE_SIZE; 1642 } 1643 1644 smmu_sync(sc); 1645 1646 return (err); 1647 } 1648 1649 static int 1650 smmu_map(device_t dev, struct iommu_domain *iodom, 1651 vm_offset_t va, vm_page_t *ma, vm_size_t size, 1652 vm_prot_t prot) 1653 { 1654 struct smmu_domain *domain; 1655 struct smmu_softc *sc; 1656 vm_paddr_t pa; 1657 int error; 1658 int i; 1659 1660 sc = device_get_softc(dev); 1661 1662 domain = (struct smmu_domain *)iodom; 1663 1664 dprintf("%s: %lx -> %lx, %ld, domain %d\n", __func__, va, pa, size, 1665 domain->asid); 1666 1667 for (i = 0; size > 0; size -= PAGE_SIZE) { 1668 pa = VM_PAGE_TO_PHYS(ma[i++]); 1669 error = pmap_smmu_enter(&domain->p, va, pa, prot, 0); 1670 if (error) 1671 return (error); 1672 smmu_tlbi_va(sc, va, domain->asid); 1673 va += PAGE_SIZE; 1674 } 1675 1676 smmu_sync(sc); 1677 1678 return (0); 1679 } 1680 1681 static struct iommu_domain * 1682 smmu_domain_alloc(device_t dev, struct iommu_unit *iommu) 1683 { 1684 struct smmu_domain *domain; 1685 struct smmu_unit *unit; 1686 struct smmu_softc *sc; 1687 int error; 1688 int new_asid; 1689 1690 sc = device_get_softc(dev); 1691 1692 unit = (struct smmu_unit *)iommu; 1693 1694 domain = malloc(sizeof(*domain), M_SMMU, M_WAITOK | M_ZERO); 1695 1696 error = smmu_asid_alloc(sc, &new_asid); 1697 if (error) { 1698 free(domain, M_SMMU); 1699 device_printf(sc->dev, 1700 "Could not allocate ASID for a new domain.\n"); 1701 return (NULL); 1702 } 1703 1704 domain->asid = (uint16_t)new_asid; 1705 1706 iommu_pmap_pinit(&domain->p); 1707 PMAP_LOCK_INIT(&domain->p); 1708 1709 error = smmu_init_cd(sc, domain); 1710 if (error) { 1711 free(domain, M_SMMU); 1712 device_printf(sc->dev, "Could not initialize CD\n"); 1713 return (NULL); 1714 } 1715 1716 smmu_tlbi_asid(sc, domain->asid); 1717 1718 LIST_INIT(&domain->ctx_list); 1719 1720 IOMMU_LOCK(iommu); 1721 LIST_INSERT_HEAD(&unit->domain_list, domain, next); 1722 IOMMU_UNLOCK(iommu); 1723 1724 return (&domain->iodom); 1725 } 1726 1727 static void 1728 smmu_domain_free(device_t dev, struct iommu_domain *iodom) 1729 { 1730 struct smmu_domain *domain; 1731 struct smmu_softc *sc; 1732 struct smmu_cd *cd; 1733 1734 sc = device_get_softc(dev); 1735 1736 domain = (struct smmu_domain *)iodom; 1737 1738 LIST_REMOVE(domain, next); 1739 1740 cd = domain->cd; 1741 1742 iommu_pmap_remove_pages(&domain->p); 1743 iommu_pmap_release(&domain->p); 1744 1745 smmu_tlbi_asid(sc, domain->asid); 1746 smmu_asid_free(sc, domain->asid); 1747 1748 contigfree(cd->vaddr, cd->size, M_SMMU); 1749 free(cd, M_SMMU); 1750 1751 free(domain, M_SMMU); 1752 } 1753 1754 static int 1755 smmu_set_buswide(device_t dev, struct smmu_domain *domain, 1756 struct smmu_ctx *ctx) 1757 { 1758 struct smmu_softc *sc; 1759 int i; 1760 1761 sc = device_get_softc(dev); 1762 1763 for (i = 0; i < PCI_SLOTMAX; i++) 1764 smmu_init_ste(sc, domain->cd, (ctx->sid | i), ctx->bypass); 1765 1766 return (0); 1767 } 1768 1769 static struct iommu_ctx * 1770 smmu_ctx_alloc(device_t dev, struct iommu_domain *iodom, device_t child, 1771 bool disabled) 1772 { 1773 struct smmu_domain *domain; 1774 struct smmu_softc *sc; 1775 struct smmu_ctx *ctx; 1776 #ifdef DEV_ACPI 1777 uint16_t rid; 1778 u_int xref; 1779 int seg; 1780 #else 1781 struct pci_id_ofw_iommu pi; 1782 #endif 1783 u_int sid; 1784 int err; 1785 1786 sc = device_get_softc(dev); 1787 domain = (struct smmu_domain *)iodom; 1788 1789 #ifdef DEV_ACPI 1790 seg = pci_get_domain(child); 1791 rid = pci_get_rid(child); 1792 err = acpi_iort_map_pci_smmuv3(seg, rid, &xref, &sid); 1793 #else 1794 err = pci_get_id(child, PCI_ID_OFW_IOMMU, (uintptr_t *)&pi); 1795 sid = pi.id; 1796 #endif 1797 if (err != 0) 1798 return (NULL); 1799 1800 if (sc->features & SMMU_FEATURE_2_LVL_STREAM_TABLE) { 1801 err = smmu_init_l1_entry(sc, sid); 1802 if (err) 1803 return (NULL); 1804 } 1805 1806 ctx = malloc(sizeof(struct smmu_ctx), M_SMMU, M_WAITOK | M_ZERO); 1807 ctx->vendor = pci_get_vendor(child); 1808 ctx->device = pci_get_device(child); 1809 ctx->dev = child; 1810 ctx->sid = sid; 1811 ctx->domain = domain; 1812 if (disabled) 1813 ctx->bypass = true; 1814 1815 /* 1816 * Neoverse N1 SDP: 1817 * 0x800 xhci 1818 * 0x700 re 1819 * 0x600 sata 1820 */ 1821 1822 smmu_init_ste(sc, domain->cd, ctx->sid, ctx->bypass); 1823 1824 if (iommu_is_buswide_ctx(iodom->iommu, pci_get_bus(ctx->dev))) 1825 smmu_set_buswide(dev, domain, ctx); 1826 1827 IOMMU_DOMAIN_LOCK(iodom); 1828 LIST_INSERT_HEAD(&domain->ctx_list, ctx, next); 1829 IOMMU_DOMAIN_UNLOCK(iodom); 1830 1831 return (&ctx->ioctx); 1832 } 1833 1834 static void 1835 smmu_ctx_free(device_t dev, struct iommu_ctx *ioctx) 1836 { 1837 struct smmu_softc *sc; 1838 struct smmu_ctx *ctx; 1839 1840 IOMMU_ASSERT_LOCKED(ioctx->domain->iommu); 1841 1842 sc = device_get_softc(dev); 1843 ctx = (struct smmu_ctx *)ioctx; 1844 1845 smmu_deinit_l1_entry(sc, ctx->sid); 1846 1847 LIST_REMOVE(ctx, next); 1848 1849 free(ctx, M_SMMU); 1850 } 1851 1852 struct smmu_ctx * 1853 smmu_ctx_lookup_by_sid(device_t dev, u_int sid) 1854 { 1855 struct smmu_softc *sc; 1856 struct smmu_domain *domain; 1857 struct smmu_unit *unit; 1858 struct smmu_ctx *ctx; 1859 1860 sc = device_get_softc(dev); 1861 1862 unit = &sc->unit; 1863 1864 LIST_FOREACH(domain, &unit->domain_list, next) { 1865 LIST_FOREACH(ctx, &domain->ctx_list, next) { 1866 if (ctx->sid == sid) 1867 return (ctx); 1868 } 1869 } 1870 1871 return (NULL); 1872 } 1873 1874 static struct iommu_ctx * 1875 smmu_ctx_lookup(device_t dev, device_t child) 1876 { 1877 struct iommu_unit *iommu __diagused; 1878 struct smmu_softc *sc; 1879 struct smmu_domain *domain; 1880 struct smmu_unit *unit; 1881 struct smmu_ctx *ctx; 1882 1883 sc = device_get_softc(dev); 1884 1885 unit = &sc->unit; 1886 iommu = &unit->iommu; 1887 1888 IOMMU_ASSERT_LOCKED(iommu); 1889 1890 LIST_FOREACH(domain, &unit->domain_list, next) { 1891 IOMMU_DOMAIN_LOCK(&domain->iodom); 1892 LIST_FOREACH(ctx, &domain->ctx_list, next) { 1893 if (ctx->dev == child) { 1894 IOMMU_DOMAIN_UNLOCK(&domain->iodom); 1895 return (&ctx->ioctx); 1896 } 1897 } 1898 IOMMU_DOMAIN_UNLOCK(&domain->iodom); 1899 } 1900 1901 return (NULL); 1902 } 1903 1904 static int 1905 smmu_find(device_t dev, device_t child) 1906 { 1907 struct smmu_softc *sc; 1908 u_int xref; 1909 int error; 1910 #ifdef DEV_ACPI 1911 uint16_t rid; 1912 int seg; 1913 u_int sid; 1914 #else 1915 phandle_t node; 1916 uint64_t base, size; 1917 struct pci_id_ofw_iommu pi; 1918 #endif 1919 1920 sc = device_get_softc(dev); 1921 1922 #ifdef DEV_ACPI 1923 rid = pci_get_rid(child); 1924 seg = pci_get_domain(child); 1925 #endif 1926 1927 /* 1928 * Find an xref of an IOMMU controller that serves traffic for dev. 1929 */ 1930 #ifdef DEV_ACPI 1931 error = acpi_iort_map_pci_smmuv3(seg, rid, &xref, &sid); 1932 if (error) { 1933 /* Could not find reference to an SMMU device. */ 1934 return (ENOENT); 1935 } 1936 #else 1937 error = pci_get_id(child, PCI_ID_OFW_IOMMU, (uintptr_t *)&pi); 1938 if (error) { 1939 /* Could not find reference to an SMMU device. */ 1940 return (ENOENT); 1941 } 1942 1943 /* Our xref is memory base address. */ 1944 node = OF_node_from_xref(pi.xref); 1945 fdt_regsize(node, &base, &size); 1946 xref = base; 1947 #endif 1948 1949 /* Check if xref is ours. */ 1950 if (xref != sc->xref) 1951 return (EFAULT); 1952 1953 return (0); 1954 } 1955 1956 static device_method_t smmu_methods[] = { 1957 /* Device interface */ 1958 DEVMETHOD(device_detach, smmu_detach), 1959 1960 /* SMMU interface */ 1961 DEVMETHOD(iommu_find, smmu_find), 1962 DEVMETHOD(iommu_map, smmu_map), 1963 DEVMETHOD(iommu_unmap, smmu_unmap), 1964 DEVMETHOD(iommu_domain_alloc, smmu_domain_alloc), 1965 DEVMETHOD(iommu_domain_free, smmu_domain_free), 1966 DEVMETHOD(iommu_ctx_alloc, smmu_ctx_alloc), 1967 DEVMETHOD(iommu_ctx_free, smmu_ctx_free), 1968 DEVMETHOD(iommu_ctx_lookup, smmu_ctx_lookup), 1969 1970 /* Bus interface */ 1971 DEVMETHOD(bus_read_ivar, smmu_read_ivar), 1972 1973 /* End */ 1974 DEVMETHOD_END 1975 }; 1976 1977 DEFINE_CLASS_0(smmu, smmu_driver, smmu_methods, sizeof(struct smmu_softc)); 1978