1*f17c4e38SRuslan Bukin /*- 2*f17c4e38SRuslan Bukin * Copyright (c) 2014 Andrew Turner 3*f17c4e38SRuslan Bukin * Copyright (c) 2014-2015 The FreeBSD Foundation 4*f17c4e38SRuslan Bukin * All rights reserved. 5*f17c4e38SRuslan Bukin * 6*f17c4e38SRuslan Bukin * This software was developed by Andrew Turner under 7*f17c4e38SRuslan Bukin * sponsorship from the FreeBSD Foundation. 8*f17c4e38SRuslan Bukin * 9*f17c4e38SRuslan Bukin * Redistribution and use in source and binary forms, with or without 10*f17c4e38SRuslan Bukin * modification, are permitted provided that the following conditions 11*f17c4e38SRuslan Bukin * are met: 12*f17c4e38SRuslan Bukin * 1. Redistributions of source code must retain the above copyright 13*f17c4e38SRuslan Bukin * notice, this list of conditions and the following disclaimer. 14*f17c4e38SRuslan Bukin * 2. Redistributions in binary form must reproduce the above copyright 15*f17c4e38SRuslan Bukin * notice, this list of conditions and the following disclaimer in the 16*f17c4e38SRuslan Bukin * documentation and/or other materials provided with the distribution. 17*f17c4e38SRuslan Bukin * 18*f17c4e38SRuslan Bukin * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19*f17c4e38SRuslan Bukin * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20*f17c4e38SRuslan Bukin * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21*f17c4e38SRuslan Bukin * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22*f17c4e38SRuslan Bukin * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23*f17c4e38SRuslan Bukin * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24*f17c4e38SRuslan Bukin * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25*f17c4e38SRuslan Bukin * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26*f17c4e38SRuslan Bukin * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27*f17c4e38SRuslan Bukin * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28*f17c4e38SRuslan Bukin * SUCH DAMAGE. 29*f17c4e38SRuslan Bukin */ 30*f17c4e38SRuslan Bukin 31*f17c4e38SRuslan Bukin #ifndef _ARM64_IOMMU_IOMMU_PTE_H_ 32*f17c4e38SRuslan Bukin #define _ARM64_IOMMU_IOMMU_PTE_H_ 33*f17c4e38SRuslan Bukin 34*f17c4e38SRuslan Bukin /* Level 0 table, 512GiB per entry */ 35*f17c4e38SRuslan Bukin #define IOMMU_L0_SHIFT 39 36*f17c4e38SRuslan Bukin #define IOMMU_L0_INVAL 0x0 /* An invalid address */ 37*f17c4e38SRuslan Bukin /* 0x1 Level 0 doesn't support block translation */ 38*f17c4e38SRuslan Bukin /* 0x2 also marks an invalid address */ 39*f17c4e38SRuslan Bukin #define IOMMU_L0_TABLE 0x3 /* A next-level table */ 40*f17c4e38SRuslan Bukin 41*f17c4e38SRuslan Bukin /* Level 1 table, 1GiB per entry */ 42*f17c4e38SRuslan Bukin #define IOMMU_L1_SHIFT 30 43*f17c4e38SRuslan Bukin #define IOMMU_L1_INVAL IOMMU_L0_INVAL 44*f17c4e38SRuslan Bukin #define IOMMU_L1_BLOCK 0x1 45*f17c4e38SRuslan Bukin #define IOMMU_L1_TABLE IOMMU_L0_TABLE 46*f17c4e38SRuslan Bukin 47*f17c4e38SRuslan Bukin /* Level 2 table, 2MiB per entry */ 48*f17c4e38SRuslan Bukin #define IOMMU_L2_SHIFT 21 49*f17c4e38SRuslan Bukin #define IOMMU_L2_INVAL IOMMU_L1_INVAL 50*f17c4e38SRuslan Bukin #define IOMMU_L2_BLOCK IOMMU_L1_BLOCK 51*f17c4e38SRuslan Bukin #define IOMMU_L2_TABLE IOMMU_L1_TABLE 52*f17c4e38SRuslan Bukin 53*f17c4e38SRuslan Bukin /* Level 3 table, 4KiB per entry */ 54*f17c4e38SRuslan Bukin #define IOMMU_L3_SHIFT 12 55*f17c4e38SRuslan Bukin #define IOMMU_L3_SIZE (1 << IOMMU_L3_SHIFT) 56*f17c4e38SRuslan Bukin #define IOMMU_L3_SHIFT 12 57*f17c4e38SRuslan Bukin #define IOMMU_L3_INVAL 0x0 58*f17c4e38SRuslan Bukin /* 0x1 is reserved */ 59*f17c4e38SRuslan Bukin /* 0x2 also marks an invalid address */ 60*f17c4e38SRuslan Bukin #define IOMMU_L3_PAGE 0x3 61*f17c4e38SRuslan Bukin #define IOMMU_L3_BLOCK IOMMU_L2_BLOCK /* Mali GPU only. */ 62*f17c4e38SRuslan Bukin 63*f17c4e38SRuslan Bukin #define IOMMU_L0_ENTRIES_SHIFT 9 64*f17c4e38SRuslan Bukin #define IOMMU_L0_ENTRIES (1 << IOMMU_L0_ENTRIES_SHIFT) 65*f17c4e38SRuslan Bukin #define IOMMU_L0_ADDR_MASK (IOMMU_L0_ENTRIES - 1) 66*f17c4e38SRuslan Bukin 67*f17c4e38SRuslan Bukin #define IOMMU_Ln_ENTRIES_SHIFT 9 68*f17c4e38SRuslan Bukin #define IOMMU_Ln_ENTRIES (1 << IOMMU_Ln_ENTRIES_SHIFT) 69*f17c4e38SRuslan Bukin #define IOMMU_Ln_ADDR_MASK (IOMMU_Ln_ENTRIES - 1) 70*f17c4e38SRuslan Bukin #define IOMMU_Ln_TABLE_MASK ((1 << 12) - 1) 71*f17c4e38SRuslan Bukin 72*f17c4e38SRuslan Bukin #endif /* !_ARM64_IOMMU_IOMMU_PTE_H_ */ 73