xref: /freebsd/sys/arm64/include/db_machdep.h (revision cfd6422a5217410fbd66f7a7a8a64d9d85e61229)
1 /*-
2  * Copyright (c) 2014 Andrew Turner
3  * Copyright (c) 2014-2015 The FreeBSD Foundation
4  * All rights reserved.
5  *
6  * This software was developed by Semihalf under
7  * sponsorship from the FreeBSD Foundation.
8  *
9  * Redistribution and use in source and binary forms, with or without
10  * modification, are permitted provided that the following conditions
11  * are met:
12  * 1. Redistributions of source code must retain the above copyright
13  *    notice, this list of conditions and the following disclaimer.
14  * 2. Redistributions in binary form must reproduce the above copyright
15  *    notice, this list of conditions and the following disclaimer in the
16  *    documentation and/or other materials provided with the distribution.
17  *
18  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28  * SUCH DAMAGE.
29  *
30  * $FreeBSD$
31  */
32 
33 #ifndef	_MACHINE_DB_MACHDEP_H_
34 #define	_MACHINE_DB_MACHDEP_H_
35 
36 #include <machine/armreg.h>
37 #include <machine/frame.h>
38 #include <machine/trap.h>
39 
40 #define	T_BREAKPOINT	(EXCP_BRK)
41 #define	T_WATCHPOINT	(EXCP_WATCHPT_EL1)
42 
43 typedef vm_offset_t	db_addr_t;
44 typedef long		db_expr_t;
45 
46 #define	PC_REGS()	((db_addr_t)kdb_thrctx->pcb_lr)
47 
48 #define	BKPT_INST	(0xd4200000)
49 #define	BKPT_SIZE	(4)
50 #define	BKPT_SET(inst)	(BKPT_INST)
51 
52 #define	BKPT_SKIP do {							\
53 	kdb_frame->tf_elr += BKPT_SIZE; \
54 } while (0)
55 
56 #define	db_clear_single_step	kdb_cpu_clear_singlestep
57 #define	db_set_single_step	kdb_cpu_set_singlestep
58 
59 #define	IS_BREAKPOINT_TRAP(type, code)	(type == T_BREAKPOINT)
60 #define	IS_WATCHPOINT_TRAP(type, code)	(type == T_WATCHPOINT)
61 
62 #define	inst_trap_return(ins)	(0)
63 /* ret */
64 #define	inst_return(ins)	(((ins) & 0xfffffc1fu) == 0xd65f0000)
65 #define	inst_call(ins)		(((ins) & 0xfc000000u) == 0x94000000u || /* BL */ \
66 				 ((ins) & 0xfffffc1fu) == 0xd63f0000u) /* BLR */
67 
68 #define	inst_load(ins) ({							\
69 	uint32_t tmp_instr = db_get_value(PC_REGS(), sizeof(uint32_t), FALSE);	\
70 	is_load_instr(tmp_instr);						\
71 })
72 
73 #define	inst_store(ins) ({							\
74 	uint32_t tmp_instr = db_get_value(PC_REGS(), sizeof(uint32_t), FALSE);	\
75 	is_store_instr(tmp_instr);						\
76 })
77 
78 #define	is_load_instr(ins)	((((ins) & 0x3b000000u) == 0x18000000u) || /* literal */ \
79 				 (((ins) & 0x3f400000u) == 0x08400000u) ||  /* exclusive */ \
80 				 (((ins) & 0x3bc00000u) == 0x28400000u) || /* no-allocate pair */ \
81 				 ((((ins) & 0x3b200c00u) == 0x38000400u) && \
82 				  (((ins) & 0x3be00c00u) != 0x38000400u) && \
83 				  (((ins) & 0xffe00c00u) != 0x3c800400u)) || /* immediate post-indexed */ \
84 				 ((((ins) & 0x3b200c00u) == 0x38000c00u) && \
85 				  (((ins) & 0x3be00c00u) != 0x38000c00u) && \
86 				  (((ins) & 0xffe00c00u) != 0x3c800c00u)) || /* immediate pre-indexed */ \
87 				 ((((ins) & 0x3b200c00u) == 0x38200800u) && \
88 				  (((ins) & 0x3be00c00u) != 0x38200800u) && \
89 				  (((ins) & 0xffe00c00u) != 0x3ca00c80u)) || /* register offset */ \
90 				 ((((ins) & 0x3b200c00u) == 0x38000800u) && \
91 				  (((ins) & 0x3be00c00u) != 0x38000800u)) || /* unprivileged */ \
92 				 ((((ins) & 0x3b200c00u) == 0x38000000u) && \
93 				  (((ins) & 0x3be00c00u) != 0x38000000u) && \
94 				  (((ins) & 0xffe00c00u) != 0x3c800000u)) ||  /* unscaled immediate */ \
95 				 ((((ins) & 0x3b000000u) == 0x39000000u) && \
96 				  (((ins) & 0x3bc00000u) != 0x39000000u) && \
97 				  (((ins) & 0xffc00000u) != 0x3d800000u)) &&  /* unsigned immediate */ \
98 				 (((ins) & 0x3bc00000u) == 0x28400000u) || /* pair (offset) */ \
99 				 (((ins) & 0x3bc00000u) == 0x28c00000u) || /* pair (post-indexed) */ \
100 				 (((ins) & 0x3bc00000u) == 0x29800000u)) /* pair (pre-indexed) */
101 
102 #define	is_store_instr(ins)	((((ins) & 0x3f400000u) == 0x08000000u) || /* exclusive */ \
103 				 (((ins) & 0x3bc00000u) == 0x28000000u) || /* no-allocate pair */ \
104 				 ((((ins) & 0x3be00c00u) == 0x38000400u) || \
105 				  (((ins) & 0xffe00c00u) == 0x3c800400u)) || /* immediate post-indexed */ \
106 				 ((((ins) & 0x3be00c00u) == 0x38000c00u) || \
107 				  (((ins) & 0xffe00c00u) == 0x3c800c00u)) || /* immediate pre-indexed */ \
108 				 ((((ins) & 0x3be00c00u) == 0x38200800u) || \
109 				  (((ins) & 0xffe00c00u) == 0x3ca00800u)) || /* register offset */ \
110 				 (((ins) & 0x3be00c00u) == 0x38000800u) ||  /* unprivileged */ \
111 				 ((((ins) & 0x3be00c00u) == 0x38000000u) || \
112 				  (((ins) & 0xffe00c00u) == 0x3c800000u)) ||  /* unscaled immediate */ \
113 				 ((((ins) & 0x3bc00000u) == 0x39000000u) || \
114 				  (((ins) & 0xffc00000u) == 0x3d800000u)) ||  /* unsigned immediate */ \
115 				 (((ins) & 0x3bc00000u) == 0x28000000u) || /* pair (offset) */ \
116 				 (((ins) & 0x3bc00000u) == 0x28800000u) || /* pair (post-indexed) */ \
117 				 (((ins) & 0x3bc00000u) == 0x29800000u)) /* pair (pre-indexed) */
118 
119 #define	next_instr_address(pc, bd)	((bd) ? (pc) : ((pc) + 4))
120 
121 #define	DB_ELFSIZE		64
122 
123 #endif /* !_MACHINE_DB_MACHDEP_H_ */
124