xref: /freebsd/sys/arm64/include/cpu.h (revision d8000daa92a4cdf940348f483861d52fa3cbf91d)
1 /*-
2  * Copyright (c) 1990 The Regents of the University of California.
3  * Copyright (c) 2014 The FreeBSD Foundation
4  * All rights reserved.
5  *
6  * This code is derived from software contributed to Berkeley by
7  * William Jolitz.
8  *
9  * Portions of this software were developed by Andrew Turner
10  * under sponsorship from the FreeBSD Foundation
11  *
12  * Redistribution and use in source and binary forms, with or without
13  * modification, are permitted provided that the following conditions
14  * are met:
15  * 1. Redistributions of source code must retain the above copyright
16  *    notice, this list of conditions and the following disclaimer.
17  * 2. Redistributions in binary form must reproduce the above copyright
18  *    notice, this list of conditions and the following disclaimer in the
19  *    documentation and/or other materials provided with the distribution.
20  * 3. Neither the name of the University nor the names of its contributors
21  *    may be used to endorse or promote products derived from this software
22  *    without specific prior written permission.
23  *
24  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
25  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
28  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
30  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34  * SUCH DAMAGE.
35  *
36  *	from: @(#)cpu.h 5.4 (Berkeley) 5/9/91
37  *	from: FreeBSD: src/sys/i386/include/cpu.h,v 1.62 2001/06/29
38  * $FreeBSD$
39  */
40 
41 #ifndef _MACHINE_CPU_H_
42 #define	_MACHINE_CPU_H_
43 
44 #include <machine/atomic.h>
45 #include <machine/frame.h>
46 #include <machine/armreg.h>
47 
48 #define	TRAPF_PC(tfp)		((tfp)->tf_lr)
49 #define	TRAPF_USERMODE(tfp)	(((tfp)->tf_elr & (1ul << 63)) == 0)
50 
51 #define	cpu_getstack(td)	((td)->td_frame->tf_sp)
52 #define	cpu_setstack(td, sp)	((td)->td_frame->tf_sp = (sp))
53 #define	cpu_spinwait()		/* nothing */
54 
55 /* Extract CPU affinity levels 0-3 */
56 #define	CPU_AFF0(mpidr)	(u_int)(((mpidr) >> 0) & 0xff)
57 #define	CPU_AFF1(mpidr)	(u_int)(((mpidr) >> 8) & 0xff)
58 #define	CPU_AFF2(mpidr)	(u_int)(((mpidr) >> 16) & 0xff)
59 #define	CPU_AFF3(mpidr)	(u_int)(((mpidr) >> 32) & 0xff)
60 #define	CPU_AFF_MASK	0xff00ffffffUL	/* Mask affinity fields in MPIDR_EL1 */
61 
62 #ifdef _KERNEL
63 
64 #define	CPU_IMPL_ARM		0x41
65 #define	CPU_IMPL_BROADCOM	0x42
66 #define	CPU_IMPL_CAVIUM		0x43
67 #define	CPU_IMPL_DEC		0x44
68 #define	CPU_IMPL_INFINEON	0x49
69 #define	CPU_IMPL_FREESCALE	0x4D
70 #define	CPU_IMPL_NVIDIA		0x4E
71 #define	CPU_IMPL_APM		0x50
72 #define	CPU_IMPL_QUALCOMM	0x51
73 #define	CPU_IMPL_MARVELL	0x56
74 #define	CPU_IMPL_INTEL		0x69
75 
76 #define	CPU_PART_THUNDER	0x0A1
77 #define	CPU_PART_FOUNDATION	0xD00
78 #define	CPU_PART_CORTEX_A53	0xD03
79 #define	CPU_PART_CORTEX_A57	0xD07
80 
81 #define	CPU_REV_THUNDER_1_0	0x00
82 #define	CPU_REV_THUNDER_1_1	0x01
83 
84 #define	CPU_IMPL(midr)	(((midr) >> 24) & 0xff)
85 #define	CPU_PART(midr)	(((midr) >> 4) & 0xfff)
86 #define	CPU_VAR(midr)	(((midr) >> 20) & 0xf)
87 #define	CPU_REV(midr)	(((midr) >> 0) & 0xf)
88 
89 #define	CPU_IMPL_TO_MIDR(val)	(((val) & 0xff) << 24)
90 #define	CPU_PART_TO_MIDR(val)	(((val) & 0xfff) << 4)
91 #define	CPU_VAR_TO_MIDR(val)	(((val) & 0xf) << 20)
92 #define	CPU_REV_TO_MIDR(val)	(((val) & 0xf) << 0)
93 
94 #define	CPU_IMPL_MASK	(0xff << 24)
95 #define	CPU_PART_MASK	(0xfff << 4)
96 #define	CPU_VAR_MASK	(0xf << 20)
97 #define	CPU_REV_MASK	(0xf << 0)
98 
99 #define	CPU_ID_RAW(impl, part, var, rev)		\
100     (CPU_IMPL_TO_MIDR((impl)) |				\
101     CPU_PART_TO_MIDR((part)) | CPU_VAR_TO_MIDR((var)) |	\
102     CPU_REV_TO_MIDR((rev)))
103 
104 #define	CPU_MATCH(mask, impl, part, var, rev)		\
105     (((mask) & PCPU_GET(midr)) ==			\
106     ((mask) & CPU_ID_RAW((impl), (part), (var), (rev))))
107 
108 #define	CPU_MATCH_RAW(mask, devid)			\
109     (((mask) & PCPU_GET(midr)) == ((mask) & (devid)))
110 
111 /*
112  * Chip-specific errata. This defines are intended to be
113  * booleans used within if statements. When an appropriate
114  * kernel option is disabled, these defines must be defined
115  * as 0 to allow the compiler to remove a dead code thus
116  * produce better optimized kernel image.
117  */
118 /*
119  * Vendor:	Cavium
120  * Chip:	ThunderX
121  * Revision(s):	Pass 1.0, Pass 1.1
122  */
123 #ifdef THUNDERX_PASS_1_1_ERRATA
124 #define	CPU_MATCH_ERRATA_CAVIUM_THUNDER_1_1				\
125     (CPU_MATCH(CPU_IMPL_MASK | CPU_PART_MASK | CPU_REV_MASK,		\
126     CPU_IMPL_CAVIUM, CPU_PART_THUNDER, 0, CPU_REV_THUNDER_1_0) ||	\
127     CPU_MATCH(CPU_IMPL_MASK | CPU_PART_MASK | CPU_REV_MASK,		\
128     CPU_IMPL_CAVIUM, CPU_PART_THUNDER, 0, CPU_REV_THUNDER_1_1))
129 #else
130 #define	CPU_MATCH_ERRATA_CAVIUM_THUNDER_1_1	0
131 #endif
132 
133 
134 extern char btext[];
135 extern char etext[];
136 
137 extern uint64_t __cpu_affinity[];
138 
139 void	cpu_halt(void) __dead2;
140 void	cpu_reset(void) __dead2;
141 void	fork_trampoline(void);
142 void	identify_cpu(void);
143 void	swi_vm(void *v);
144 
145 #define	CPU_AFFINITY(cpu)	__cpu_affinity[(cpu)]
146 
147 static __inline uint64_t
148 get_cyclecount(void)
149 {
150 	uint64_t ret;
151 
152 	ret = READ_SPECIALREG(cntvct_el0);
153 
154 	return (ret);
155 }
156 
157 #define	ADDRESS_TRANSLATE_FUNC(stage)				\
158 static inline uint64_t						\
159 arm64_address_translate_ ##stage (uint64_t addr)		\
160 {								\
161 	uint64_t ret;						\
162 								\
163 	__asm __volatile(					\
164 	    "at " __STRING(stage) ", %1 \n"					\
165 	    "mrs %0, par_el1" : "=r"(ret) : "r"(addr));		\
166 								\
167 	return (ret);						\
168 }
169 
170 ADDRESS_TRANSLATE_FUNC(s1e0r)
171 ADDRESS_TRANSLATE_FUNC(s1e0w)
172 ADDRESS_TRANSLATE_FUNC(s1e1r)
173 ADDRESS_TRANSLATE_FUNC(s1e1w)
174 
175 #endif
176 
177 #endif /* !_MACHINE_CPU_H_ */
178