1 /*- 2 * Copyright (c) 1990 The Regents of the University of California. 3 * Copyright (c) 2014-2016 The FreeBSD Foundation 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to Berkeley by 7 * William Jolitz. 8 * 9 * Portions of this software were developed by Andrew Turner 10 * under sponsorship from the FreeBSD Foundation 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * from: @(#)cpu.h 5.4 (Berkeley) 5/9/91 37 * from: FreeBSD: src/sys/i386/include/cpu.h,v 1.62 2001/06/29 38 * $FreeBSD$ 39 */ 40 41 #ifdef __arm__ 42 #include <arm/cpu.h> 43 #else /* !__arm__ */ 44 45 #ifndef _MACHINE_CPU_H_ 46 #define _MACHINE_CPU_H_ 47 48 #include <machine/atomic.h> 49 #include <machine/frame.h> 50 #include <machine/armreg.h> 51 52 #define TRAPF_PC(tfp) ((tfp)->tf_elr) 53 #define TRAPF_USERMODE(tfp) (((tfp)->tf_spsr & PSR_M_MASK) == PSR_M_EL0t) 54 55 #define cpu_getstack(td) ((td)->td_frame->tf_sp) 56 #define cpu_setstack(td, sp) ((td)->td_frame->tf_sp = (sp)) 57 #define cpu_spinwait() __asm __volatile("yield" ::: "memory") 58 #define cpu_lock_delay() DELAY(1) 59 60 /* Extract CPU affinity levels 0-3 */ 61 #define CPU_AFF0(mpidr) (u_int)(((mpidr) >> 0) & 0xff) 62 #define CPU_AFF1(mpidr) (u_int)(((mpidr) >> 8) & 0xff) 63 #define CPU_AFF2(mpidr) (u_int)(((mpidr) >> 16) & 0xff) 64 #define CPU_AFF3(mpidr) (u_int)(((mpidr) >> 32) & 0xff) 65 #define CPU_AFF0_MASK 0xffUL 66 #define CPU_AFF1_MASK 0xff00UL 67 #define CPU_AFF2_MASK 0xff0000UL 68 #define CPU_AFF3_MASK 0xff00000000UL 69 #define CPU_AFF_MASK (CPU_AFF0_MASK | CPU_AFF1_MASK | \ 70 CPU_AFF2_MASK| CPU_AFF3_MASK) /* Mask affinity fields in MPIDR_EL1 */ 71 72 #ifdef _KERNEL 73 74 #define CPU_IMPL_ARM 0x41 75 #define CPU_IMPL_BROADCOM 0x42 76 #define CPU_IMPL_CAVIUM 0x43 77 #define CPU_IMPL_DEC 0x44 78 #define CPU_IMPL_FUJITSU 0x46 79 #define CPU_IMPL_INFINEON 0x49 80 #define CPU_IMPL_FREESCALE 0x4D 81 #define CPU_IMPL_NVIDIA 0x4E 82 #define CPU_IMPL_APM 0x50 83 #define CPU_IMPL_QUALCOMM 0x51 84 #define CPU_IMPL_MARVELL 0x56 85 #define CPU_IMPL_APPLE 0x61 86 #define CPU_IMPL_INTEL 0x69 87 #define CPU_IMPL_AMPERE 0xC0 88 89 /* ARM Part numbers */ 90 #define CPU_PART_FOUNDATION 0xD00 91 #define CPU_PART_CORTEX_A34 0xD02 92 #define CPU_PART_CORTEX_A53 0xD03 93 #define CPU_PART_CORTEX_A35 0xD04 94 #define CPU_PART_CORTEX_A55 0xD05 95 #define CPU_PART_CORTEX_A65 0xD06 96 #define CPU_PART_CORTEX_A57 0xD07 97 #define CPU_PART_CORTEX_A72 0xD08 98 #define CPU_PART_CORTEX_A73 0xD09 99 #define CPU_PART_CORTEX_A75 0xD0A 100 #define CPU_PART_CORTEX_A76 0xD0B 101 #define CPU_PART_NEOVERSE_N1 0xD0C 102 #define CPU_PART_CORTEX_A77 0xD0D 103 #define CPU_PART_CORTEX_A76AE 0xD0E 104 #define CPU_PART_AEM_V8 0xD0F 105 #define CPU_PART_NEOVERSE_V1 0xD40 106 #define CPU_PART_CORTEX_A78 0xD41 107 #define CPU_PART_CORTEX_A65AE 0xD43 108 #define CPU_PART_CORTEX_X1 0xD44 109 #define CPU_PART_CORTEX_A510 0xD46 110 #define CPU_PART_CORTEX_A710 0xD47 111 #define CPU_PART_CORTEX_X2 0xD48 112 #define CPU_PART_NEOVERSE_N2 0xD49 113 #define CPU_PART_NEOVERSE_E1 0xD4A 114 #define CPU_PART_CORTEX_A78C 0xD4B 115 #define CPU_PART_CORTEX_X1C 0xD4C 116 #define CPU_PART_CORTEX_A715 0xD4D 117 #define CPU_PART_CORTEX_X3 0xD4E 118 #define CPU_PART_NEOVERSE_V2 0xD4F 119 120 /* Cavium Part numbers */ 121 #define CPU_PART_THUNDERX 0x0A1 122 #define CPU_PART_THUNDERX_81XX 0x0A2 123 #define CPU_PART_THUNDERX_83XX 0x0A3 124 #define CPU_PART_THUNDERX2 0x0AF 125 126 #define CPU_REV_THUNDERX_1_0 0x00 127 #define CPU_REV_THUNDERX_1_1 0x01 128 129 #define CPU_REV_THUNDERX2_0 0x00 130 131 /* APM / Ampere Part Number */ 132 #define CPU_PART_EMAG8180 0x000 133 134 /* Qualcomm */ 135 #define CPU_PART_KRYO400_GOLD 0x804 136 #define CPU_PART_KRYO400_SILVER 0x805 137 138 #define CPU_IMPL(midr) (((midr) >> 24) & 0xff) 139 #define CPU_PART(midr) (((midr) >> 4) & 0xfff) 140 #define CPU_VAR(midr) (((midr) >> 20) & 0xf) 141 #define CPU_ARCH(midr) (((midr) >> 16) & 0xf) 142 #define CPU_REV(midr) (((midr) >> 0) & 0xf) 143 144 #define CPU_IMPL_TO_MIDR(val) (((val) & 0xff) << 24) 145 #define CPU_PART_TO_MIDR(val) (((val) & 0xfff) << 4) 146 #define CPU_VAR_TO_MIDR(val) (((val) & 0xf) << 20) 147 #define CPU_ARCH_TO_MIDR(val) (((val) & 0xf) << 16) 148 #define CPU_REV_TO_MIDR(val) (((val) & 0xf) << 0) 149 150 #define CPU_IMPL_MASK (0xff << 24) 151 #define CPU_PART_MASK (0xfff << 4) 152 #define CPU_VAR_MASK (0xf << 20) 153 #define CPU_ARCH_MASK (0xf << 16) 154 #define CPU_REV_MASK (0xf << 0) 155 156 #define CPU_ID_RAW(impl, part, var, rev) \ 157 (CPU_IMPL_TO_MIDR((impl)) | \ 158 CPU_PART_TO_MIDR((part)) | CPU_VAR_TO_MIDR((var)) | \ 159 CPU_REV_TO_MIDR((rev))) 160 161 #define CPU_MATCH(mask, impl, part, var, rev) \ 162 (((mask) & PCPU_GET(midr)) == \ 163 ((mask) & CPU_ID_RAW((impl), (part), (var), (rev)))) 164 165 #define CPU_MATCH_RAW(mask, devid) \ 166 (((mask) & PCPU_GET(midr)) == ((mask) & (devid))) 167 168 /* 169 * Chip-specific errata. This defines are intended to be 170 * booleans used within if statements. When an appropriate 171 * kernel option is disabled, these defines must be defined 172 * as 0 to allow the compiler to remove a dead code thus 173 * produce better optimized kernel image. 174 */ 175 /* 176 * Vendor: Cavium 177 * Chip: ThunderX 178 * Revision(s): Pass 1.0, Pass 1.1 179 */ 180 #ifdef THUNDERX_PASS_1_1_ERRATA 181 #define CPU_MATCH_ERRATA_CAVIUM_THUNDERX_1_1 \ 182 (CPU_MATCH(CPU_IMPL_MASK | CPU_PART_MASK | CPU_REV_MASK, \ 183 CPU_IMPL_CAVIUM, CPU_PART_THUNDERX, 0, CPU_REV_THUNDERX_1_0) || \ 184 CPU_MATCH(CPU_IMPL_MASK | CPU_PART_MASK | CPU_REV_MASK, \ 185 CPU_IMPL_CAVIUM, CPU_PART_THUNDERX, 0, CPU_REV_THUNDERX_1_1)) 186 #else 187 #define CPU_MATCH_ERRATA_CAVIUM_THUNDERX_1_1 0 188 #endif 189 190 extern char btext[]; 191 extern char etext[]; 192 193 extern uint64_t __cpu_affinity[]; 194 195 struct arm64_addr_mask; 196 extern struct arm64_addr_mask elf64_addr_mask; 197 198 void cpu_halt(void) __dead2; 199 void cpu_reset(void) __dead2; 200 void fork_trampoline(void); 201 void identify_cache(uint64_t); 202 void identify_cpu(u_int); 203 void install_cpu_errata(void); 204 205 /* Pointer Authentication Code (PAC) support */ 206 void ptrauth_init(void); 207 void ptrauth_fork(struct thread *, struct thread *); 208 void ptrauth_exec(struct thread *); 209 void ptrauth_copy_thread(struct thread *, struct thread *); 210 void ptrauth_thread_alloc(struct thread *); 211 void ptrauth_thread0(struct thread *); 212 #ifdef SMP 213 void ptrauth_mp_start(uint64_t); 214 #endif 215 216 /* Functions to read the sanitised view of the special registers */ 217 void update_special_regs(u_int); 218 bool extract_user_id_field(u_int, u_int, uint8_t *); 219 bool get_kernel_reg(u_int, uint64_t *); 220 bool get_kernel_reg_masked(u_int, uint64_t *, uint64_t); 221 222 void cpu_desc_init(void); 223 224 #define CPU_AFFINITY(cpu) __cpu_affinity[(cpu)] 225 #define CPU_CURRENT_SOCKET \ 226 (CPU_AFF2(CPU_AFFINITY(PCPU_GET(cpuid)))) 227 228 static __inline uint64_t 229 get_cyclecount(void) 230 { 231 uint64_t ret; 232 233 ret = READ_SPECIALREG(cntvct_el0); 234 235 return (ret); 236 } 237 238 #define ADDRESS_TRANSLATE_FUNC(stage) \ 239 static inline uint64_t \ 240 arm64_address_translate_ ##stage (uint64_t addr) \ 241 { \ 242 uint64_t ret; \ 243 \ 244 __asm __volatile( \ 245 "at " __STRING(stage) ", %1 \n" \ 246 "isb \n" \ 247 "mrs %0, par_el1" : "=r"(ret) : "r"(addr)); \ 248 \ 249 return (ret); \ 250 } 251 252 ADDRESS_TRANSLATE_FUNC(s1e0r) 253 ADDRESS_TRANSLATE_FUNC(s1e0w) 254 ADDRESS_TRANSLATE_FUNC(s1e1r) 255 ADDRESS_TRANSLATE_FUNC(s1e1w) 256 257 #endif 258 259 #endif /* !_MACHINE_CPU_H_ */ 260 261 #endif /* !__arm__ */ 262