1 /*- 2 * Copyright (c) 1990 The Regents of the University of California. 3 * Copyright (c) 2014-2016 The FreeBSD Foundation 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to Berkeley by 7 * William Jolitz. 8 * 9 * Portions of this software were developed by Andrew Turner 10 * under sponsorship from the FreeBSD Foundation 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * from: @(#)cpu.h 5.4 (Berkeley) 5/9/91 37 * from: FreeBSD: src/sys/i386/include/cpu.h,v 1.62 2001/06/29 38 * $FreeBSD$ 39 */ 40 41 #ifndef _MACHINE_CPU_H_ 42 #define _MACHINE_CPU_H_ 43 44 #include <machine/atomic.h> 45 #include <machine/frame.h> 46 #include <machine/armreg.h> 47 48 #define TRAPF_PC(tfp) ((tfp)->tf_elr) 49 #define TRAPF_USERMODE(tfp) (((tfp)->tf_spsr & PSR_M_MASK) == PSR_M_EL0t) 50 51 #define cpu_getstack(td) ((td)->td_frame->tf_sp) 52 #define cpu_setstack(td, sp) ((td)->td_frame->tf_sp = (sp)) 53 #define cpu_spinwait() __asm __volatile("yield" ::: "memory") 54 #define cpu_lock_delay() DELAY(1) 55 56 /* Extract CPU affinity levels 0-3 */ 57 #define CPU_AFF0(mpidr) (u_int)(((mpidr) >> 0) & 0xff) 58 #define CPU_AFF1(mpidr) (u_int)(((mpidr) >> 8) & 0xff) 59 #define CPU_AFF2(mpidr) (u_int)(((mpidr) >> 16) & 0xff) 60 #define CPU_AFF3(mpidr) (u_int)(((mpidr) >> 32) & 0xff) 61 #define CPU_AFF0_MASK 0xffUL 62 #define CPU_AFF1_MASK 0xff00UL 63 #define CPU_AFF2_MASK 0xff0000UL 64 #define CPU_AFF3_MASK 0xff00000000UL 65 #define CPU_AFF_MASK (CPU_AFF0_MASK | CPU_AFF1_MASK | \ 66 CPU_AFF2_MASK| CPU_AFF3_MASK) /* Mask affinity fields in MPIDR_EL1 */ 67 68 #ifdef _KERNEL 69 70 #define CPU_IMPL_ARM 0x41 71 #define CPU_IMPL_BROADCOM 0x42 72 #define CPU_IMPL_CAVIUM 0x43 73 #define CPU_IMPL_DEC 0x44 74 #define CPU_IMPL_FUJITSU 0x46 75 #define CPU_IMPL_INFINEON 0x49 76 #define CPU_IMPL_FREESCALE 0x4D 77 #define CPU_IMPL_NVIDIA 0x4E 78 #define CPU_IMPL_APM 0x50 79 #define CPU_IMPL_QUALCOMM 0x51 80 #define CPU_IMPL_MARVELL 0x56 81 #define CPU_IMPL_APPLE 0x61 82 #define CPU_IMPL_INTEL 0x69 83 #define CPU_IMPL_AMPERE 0xC0 84 85 /* ARM Part numbers */ 86 #define CPU_PART_FOUNDATION 0xD00 87 #define CPU_PART_CORTEX_A34 0xD02 88 #define CPU_PART_CORTEX_A53 0xD03 89 #define CPU_PART_CORTEX_A35 0xD04 90 #define CPU_PART_CORTEX_A55 0xD05 91 #define CPU_PART_CORTEX_A65 0xD06 92 #define CPU_PART_CORTEX_A57 0xD07 93 #define CPU_PART_CORTEX_A72 0xD08 94 #define CPU_PART_CORTEX_A73 0xD09 95 #define CPU_PART_CORTEX_A75 0xD0A 96 #define CPU_PART_CORTEX_A76 0xD0B 97 #define CPU_PART_NEOVERSE_N1 0xD0C 98 #define CPU_PART_CORTEX_A77 0xD0D 99 #define CPU_PART_CORTEX_A76AE 0xD0E 100 #define CPU_PART_AEM_V8 0xD0F 101 #define CPU_PART_NEOVERSE_V1 0xD40 102 #define CPU_PART_CORTEX_A78 0xD41 103 #define CPU_PART_CORTEX_A65AE 0xD43 104 #define CPU_PART_CORTEX_X1 0xD44 105 #define CPU_PART_CORTEX_A510 0xD46 106 #define CPU_PART_CORTEX_A710 0xD47 107 #define CPU_PART_CORTEX_X2 0xD48 108 #define CPU_PART_NEOVERSE_N2 0xD49 109 #define CPU_PART_NEOVERSE_E1 0xD4A 110 #define CPU_PART_CORTEX_A78C 0xD4B 111 #define CPU_PART_CORTEX_X1C 0xD4C 112 #define CPU_PART_CORTEX_A715 0xD4D 113 #define CPU_PART_CORTEX_X3 0xD4E 114 115 /* Cavium Part numbers */ 116 #define CPU_PART_THUNDERX 0x0A1 117 #define CPU_PART_THUNDERX_81XX 0x0A2 118 #define CPU_PART_THUNDERX_83XX 0x0A3 119 #define CPU_PART_THUNDERX2 0x0AF 120 121 #define CPU_REV_THUNDERX_1_0 0x00 122 #define CPU_REV_THUNDERX_1_1 0x01 123 124 #define CPU_REV_THUNDERX2_0 0x00 125 126 /* APM / Ampere Part Number */ 127 #define CPU_PART_EMAG8180 0x000 128 129 #define CPU_IMPL(midr) (((midr) >> 24) & 0xff) 130 #define CPU_PART(midr) (((midr) >> 4) & 0xfff) 131 #define CPU_VAR(midr) (((midr) >> 20) & 0xf) 132 #define CPU_REV(midr) (((midr) >> 0) & 0xf) 133 134 #define CPU_IMPL_TO_MIDR(val) (((val) & 0xff) << 24) 135 #define CPU_PART_TO_MIDR(val) (((val) & 0xfff) << 4) 136 #define CPU_VAR_TO_MIDR(val) (((val) & 0xf) << 20) 137 #define CPU_REV_TO_MIDR(val) (((val) & 0xf) << 0) 138 139 #define CPU_IMPL_MASK (0xff << 24) 140 #define CPU_PART_MASK (0xfff << 4) 141 #define CPU_VAR_MASK (0xf << 20) 142 #define CPU_REV_MASK (0xf << 0) 143 144 #define CPU_ID_RAW(impl, part, var, rev) \ 145 (CPU_IMPL_TO_MIDR((impl)) | \ 146 CPU_PART_TO_MIDR((part)) | CPU_VAR_TO_MIDR((var)) | \ 147 CPU_REV_TO_MIDR((rev))) 148 149 #define CPU_MATCH(mask, impl, part, var, rev) \ 150 (((mask) & PCPU_GET(midr)) == \ 151 ((mask) & CPU_ID_RAW((impl), (part), (var), (rev)))) 152 153 #define CPU_MATCH_RAW(mask, devid) \ 154 (((mask) & PCPU_GET(midr)) == ((mask) & (devid))) 155 156 /* 157 * Chip-specific errata. This defines are intended to be 158 * booleans used within if statements. When an appropriate 159 * kernel option is disabled, these defines must be defined 160 * as 0 to allow the compiler to remove a dead code thus 161 * produce better optimized kernel image. 162 */ 163 /* 164 * Vendor: Cavium 165 * Chip: ThunderX 166 * Revision(s): Pass 1.0, Pass 1.1 167 */ 168 #ifdef THUNDERX_PASS_1_1_ERRATA 169 #define CPU_MATCH_ERRATA_CAVIUM_THUNDERX_1_1 \ 170 (CPU_MATCH(CPU_IMPL_MASK | CPU_PART_MASK | CPU_REV_MASK, \ 171 CPU_IMPL_CAVIUM, CPU_PART_THUNDERX, 0, CPU_REV_THUNDERX_1_0) || \ 172 CPU_MATCH(CPU_IMPL_MASK | CPU_PART_MASK | CPU_REV_MASK, \ 173 CPU_IMPL_CAVIUM, CPU_PART_THUNDERX, 0, CPU_REV_THUNDERX_1_1)) 174 #else 175 #define CPU_MATCH_ERRATA_CAVIUM_THUNDERX_1_1 0 176 #endif 177 178 extern char btext[]; 179 extern char etext[]; 180 181 extern uint64_t __cpu_affinity[]; 182 183 struct arm64_addr_mask; 184 extern struct arm64_addr_mask elf64_addr_mask; 185 186 void cpu_halt(void) __dead2; 187 void cpu_reset(void) __dead2; 188 void fork_trampoline(void); 189 void identify_cache(uint64_t); 190 void identify_cpu(u_int); 191 void install_cpu_errata(void); 192 193 /* Pointer Authentication Code (PAC) support */ 194 void ptrauth_init(void); 195 void ptrauth_fork(struct thread *, struct thread *); 196 void ptrauth_exec(struct thread *); 197 void ptrauth_copy_thread(struct thread *, struct thread *); 198 void ptrauth_thread_alloc(struct thread *); 199 void ptrauth_thread0(struct thread *); 200 #ifdef SMP 201 void ptrauth_mp_start(uint64_t); 202 #endif 203 204 /* Pointer Authentication Code (PAC) support */ 205 void ptrauth_init(void); 206 void ptrauth_fork(struct thread *, struct thread *); 207 void ptrauth_exec(struct thread *); 208 void ptrauth_copy_thread(struct thread *, struct thread *); 209 void ptrauth_thread_alloc(struct thread *); 210 void ptrauth_thread0(struct thread *); 211 #ifdef SMP 212 void ptrauth_mp_start(uint64_t); 213 #endif 214 215 /* Functions to read the sanitised view of the special registers */ 216 void update_special_regs(u_int); 217 bool extract_user_id_field(u_int, u_int, uint8_t *); 218 bool get_kernel_reg(u_int, uint64_t *); 219 220 #define CPU_AFFINITY(cpu) __cpu_affinity[(cpu)] 221 #define CPU_CURRENT_SOCKET \ 222 (CPU_AFF2(CPU_AFFINITY(PCPU_GET(cpuid)))) 223 224 static __inline uint64_t 225 get_cyclecount(void) 226 { 227 uint64_t ret; 228 229 ret = READ_SPECIALREG(cntvct_el0); 230 231 return (ret); 232 } 233 234 #define ADDRESS_TRANSLATE_FUNC(stage) \ 235 static inline uint64_t \ 236 arm64_address_translate_ ##stage (uint64_t addr) \ 237 { \ 238 uint64_t ret; \ 239 \ 240 __asm __volatile( \ 241 "at " __STRING(stage) ", %1 \n" \ 242 "isb \n" \ 243 "mrs %0, par_el1" : "=r"(ret) : "r"(addr)); \ 244 \ 245 return (ret); \ 246 } 247 248 ADDRESS_TRANSLATE_FUNC(s1e0r) 249 ADDRESS_TRANSLATE_FUNC(s1e0w) 250 ADDRESS_TRANSLATE_FUNC(s1e1r) 251 ADDRESS_TRANSLATE_FUNC(s1e1w) 252 253 #endif 254 255 #endif /* !_MACHINE_CPU_H_ */ 256