1 /*- 2 * Copyright (c) 2013, 2014 Andrew Turner 3 * Copyright (c) 2015,2021 The FreeBSD Foundation 4 * 5 * Portions of this software were developed by Andrew Turner 6 * under sponsorship from the FreeBSD Foundation. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD$ 30 */ 31 32 #ifndef _MACHINE_ARMREG_H_ 33 #define _MACHINE_ARMREG_H_ 34 35 #define INSN_SIZE 4 36 37 #define MRS_MASK 0xfff00000 38 #define MRS_VALUE 0xd5300000 39 #define MRS_SPECIAL(insn) ((insn) & 0x000fffe0) 40 #define MRS_REGISTER(insn) ((insn) & 0x0000001f) 41 #define MRS_Op0_SHIFT 19 42 #define MRS_Op0_MASK 0x00080000 43 #define MRS_Op1_SHIFT 16 44 #define MRS_Op1_MASK 0x00070000 45 #define MRS_CRn_SHIFT 12 46 #define MRS_CRn_MASK 0x0000f000 47 #define MRS_CRm_SHIFT 8 48 #define MRS_CRm_MASK 0x00000f00 49 #define MRS_Op2_SHIFT 5 50 #define MRS_Op2_MASK 0x000000e0 51 #define MRS_Rt_SHIFT 0 52 #define MRS_Rt_MASK 0x0000001f 53 #define __MRS_REG(op0, op1, crn, crm, op2) \ 54 (((op0) << MRS_Op0_SHIFT) | ((op1) << MRS_Op1_SHIFT) | \ 55 ((crn) << MRS_CRn_SHIFT) | ((crm) << MRS_CRm_SHIFT) | \ 56 ((op2) << MRS_Op2_SHIFT)) 57 #define MRS_REG(reg) \ 58 __MRS_REG(reg##_op0, reg##_op1, reg##_CRn, reg##_CRm, reg##_op2) 59 60 #define __MRS_REG_ALT_NAME(op0, op1, crn, crm, op2) \ 61 S##op0##_##op1##_C##crn##_C##crm##_##op2 62 #define _MRS_REG_ALT_NAME(op0, op1, crn, crm, op2) \ 63 __MRS_REG_ALT_NAME(op0, op1, crn, crm, op2) 64 #define MRS_REG_ALT_NAME(reg) \ 65 _MRS_REG_ALT_NAME(reg##_op0, reg##_op1, reg##_CRn, reg##_CRm, reg##_op2) 66 67 68 #define READ_SPECIALREG(reg) \ 69 ({ uint64_t _val; \ 70 __asm __volatile("mrs %0, " __STRING(reg) : "=&r" (_val)); \ 71 _val; \ 72 }) 73 #define WRITE_SPECIALREG(reg, _val) \ 74 __asm __volatile("msr " __STRING(reg) ", %0" : : "r"((uint64_t)_val)) 75 76 #define UL(x) UINT64_C(x) 77 78 /* CCSIDR_EL1 - Cache Size ID Register */ 79 #define CCSIDR_NumSets_MASK 0x0FFFE000 80 #define CCSIDR_NumSets64_MASK 0x00FFFFFF00000000 81 #define CCSIDR_NumSets_SHIFT 13 82 #define CCSIDR_NumSets64_SHIFT 32 83 #define CCSIDR_Assoc_MASK 0x00001FF8 84 #define CCSIDR_Assoc64_MASK 0x0000000000FFFFF8 85 #define CCSIDR_Assoc_SHIFT 3 86 #define CCSIDR_Assoc64_SHIFT 3 87 #define CCSIDR_LineSize_MASK 0x7 88 #define CCSIDR_NSETS(idr) \ 89 (((idr) & CCSIDR_NumSets_MASK) >> CCSIDR_NumSets_SHIFT) 90 #define CCSIDR_ASSOC(idr) \ 91 (((idr) & CCSIDR_Assoc_MASK) >> CCSIDR_Assoc_SHIFT) 92 #define CCSIDR_NSETS_64(idr) \ 93 (((idr) & CCSIDR_NumSets64_MASK) >> CCSIDR_NumSets64_SHIFT) 94 #define CCSIDR_ASSOC_64(idr) \ 95 (((idr) & CCSIDR_Assoc64_MASK) >> CCSIDR_Assoc64_SHIFT) 96 97 /* CLIDR_EL1 - Cache level ID register */ 98 #define CLIDR_CTYPE_MASK 0x7 /* Cache type mask bits */ 99 #define CLIDR_CTYPE_IO 0x1 /* Instruction only */ 100 #define CLIDR_CTYPE_DO 0x2 /* Data only */ 101 #define CLIDR_CTYPE_ID 0x3 /* Split instruction and data */ 102 #define CLIDR_CTYPE_UNIFIED 0x4 /* Unified */ 103 104 /* CNTP_CTL_EL0 - Counter-timer Physical Timer Control register */ 105 #define CNTP_CTL_EL0 MRS_REG(CNTP_CTL_EL0) 106 #define CNTP_CTL_EL0_op0 3 107 #define CNTP_CTL_EL0_op1 3 108 #define CNTP_CTL_EL0_CRn 14 109 #define CNTP_CTL_EL0_CRm 2 110 #define CNTP_CTL_EL0_op2 1 111 #define CNTP_CTL_ENABLE (1 << 0) 112 #define CNTP_CTL_IMASK (1 << 1) 113 #define CNTP_CTL_ISTATUS (1 << 2) 114 115 /* CNTP_CVAL_EL0 - Counter-timer Physical Timer CompareValue register */ 116 #define CNTP_CVAL_EL0 MRS_REG(CNTP_CVAL_EL0) 117 #define CNTP_CVAL_EL0_op0 3 118 #define CNTP_CVAL_EL0_op1 3 119 #define CNTP_CVAL_EL0_CRn 14 120 #define CNTP_CVAL_EL0_CRm 2 121 #define CNTP_CVAL_EL0_op2 2 122 123 /* CNTP_TVAL_EL0 - Counter-timer Physical Timer TimerValue register */ 124 #define CNTP_TVAL_EL0 MRS_REG(CNTP_TVAL_EL0) 125 #define CNTP_TVAL_EL0_op0 3 126 #define CNTP_TVAL_EL0_op1 3 127 #define CNTP_TVAL_EL0_CRn 14 128 #define CNTP_TVAL_EL0_CRm 2 129 #define CNTP_TVAL_EL0_op2 0 130 131 /* CNTPCT_EL0 - Counter-timer Physical Count register */ 132 #define CNTPCT_EL0 MRS_REG(CNTPCT_EL0) 133 #define CNTPCT_EL0_op0 3 134 #define CNTPCT_EL0_op1 3 135 #define CNTPCT_EL0_CRn 14 136 #define CNTPCT_EL0_CRm 0 137 #define CNTPCT_EL0_op2 1 138 139 /* CPACR_EL1 */ 140 #define CPACR_ZEN_MASK (0x3 << 16) 141 #define CPACR_ZEN_TRAP_ALL1 (0x0 << 16) /* Traps from EL0 and EL1 */ 142 #define CPACR_ZEN_TRAP_EL0 (0x1 << 16) /* Traps from EL0 */ 143 #define CPACR_ZEN_TRAP_ALL2 (0x2 << 16) /* Traps from EL0 and EL1 */ 144 #define CPACR_ZEN_TRAP_NONE (0x3 << 16) /* No traps */ 145 #define CPACR_FPEN_MASK (0x3 << 20) 146 #define CPACR_FPEN_TRAP_ALL1 (0x0 << 20) /* Traps from EL0 and EL1 */ 147 #define CPACR_FPEN_TRAP_EL0 (0x1 << 20) /* Traps from EL0 */ 148 #define CPACR_FPEN_TRAP_ALL2 (0x2 << 20) /* Traps from EL0 and EL1 */ 149 #define CPACR_FPEN_TRAP_NONE (0x3 << 20) /* No traps */ 150 #define CPACR_TTA (0x1 << 28) 151 152 /* CSSELR_EL1 - Cache size selection register */ 153 #define CSSELR_Level(i) (i << 1) 154 #define CSSELR_InD 0x00000001 155 156 /* CTR_EL0 - Cache Type Register */ 157 #define CTR_RES1 (1 << 31) 158 #define CTR_TminLine_SHIFT 32 159 #define CTR_TminLine_MASK (UL(0x3f) << CTR_TminLine_SHIFT) 160 #define CTR_TminLine_VAL(reg) ((reg) & CTR_TminLine_MASK) 161 #define CTR_DIC_SHIFT 29 162 #define CTR_DIC_MASK (0x1 << CTR_DIC_SHIFT) 163 #define CTR_DIC_VAL(reg) ((reg) & CTR_DIC_MASK) 164 #define CTR_IDC_SHIFT 28 165 #define CTR_IDC_MASK (0x1 << CTR_IDC_SHIFT) 166 #define CTR_IDC_VAL(reg) ((reg) & CTR_IDC_MASK) 167 #define CTR_CWG_SHIFT 24 168 #define CTR_CWG_MASK (0xf << CTR_CWG_SHIFT) 169 #define CTR_CWG_VAL(reg) ((reg) & CTR_CWG_MASK) 170 #define CTR_CWG_SIZE(reg) (4 << (CTR_CWG_VAL(reg) >> CTR_CWG_SHIFT)) 171 #define CTR_ERG_SHIFT 20 172 #define CTR_ERG_MASK (0xf << CTR_ERG_SHIFT) 173 #define CTR_ERG_VAL(reg) ((reg) & CTR_ERG_MASK) 174 #define CTR_ERG_SIZE(reg) (4 << (CTR_ERG_VAL(reg) >> CTR_ERG_SHIFT)) 175 #define CTR_DLINE_SHIFT 16 176 #define CTR_DLINE_MASK (0xf << CTR_DLINE_SHIFT) 177 #define CTR_DLINE_VAL(reg) ((reg) & CTR_DLINE_MASK) 178 #define CTR_DLINE_SIZE(reg) (4 << (CTR_DLINE_VAL(reg) >> CTR_DLINE_SHIFT)) 179 #define CTR_L1IP_SHIFT 14 180 #define CTR_L1IP_MASK (0x3 << CTR_L1IP_SHIFT) 181 #define CTR_L1IP_VAL(reg) ((reg) & CTR_L1IP_MASK) 182 #define CTR_L1IP_VPIPT (0 << CTR_L1IP_SHIFT) 183 #define CTR_L1IP_AIVIVT (1 << CTR_L1IP_SHIFT) 184 #define CTR_L1IP_VIPT (2 << CTR_L1IP_SHIFT) 185 #define CTR_L1IP_PIPT (3 << CTR_L1IP_SHIFT) 186 #define CTR_ILINE_SHIFT 0 187 #define CTR_ILINE_MASK (0xf << CTR_ILINE_SHIFT) 188 #define CTR_ILINE_VAL(reg) ((reg) & CTR_ILINE_MASK) 189 #define CTR_ILINE_SIZE(reg) (4 << (CTR_ILINE_VAL(reg) >> CTR_ILINE_SHIFT)) 190 191 /* DAIFSet/DAIFClear */ 192 #define DAIF_D (1 << 3) 193 #define DAIF_A (1 << 2) 194 #define DAIF_I (1 << 1) 195 #define DAIF_F (1 << 0) 196 #define DAIF_ALL (DAIF_D | DAIF_A | DAIF_I | DAIF_F) 197 #define DAIF_INTR (DAIF_I) /* All exceptions that pass */ 198 /* through the intr framework */ 199 200 /* DBGBCR<n>_EL1 - Debug Breakpoint Control Registers */ 201 #define DBGBCR_EL1_op0 2 202 #define DBGBCR_EL1_op1 0 203 #define DBGBCR_EL1_CRn 0 204 /* DBGBCR_EL1_CRm indicates which watchpoint this register is for */ 205 #define DBGBCR_EL1_op2 5 206 #define DBGBCR_EN 0x1 207 #define DBGBCR_PMC_SHIFT 1 208 #define DBGBCR_PMC (0x3 << DBGBCR_PMC_SHIFT) 209 #define DBGBCR_PMC_EL1 (0x1 << DBGBCR_PMC_SHIFT) 210 #define DBGBCR_PMC_EL0 (0x2 << DBGBCR_PMC_SHIFT) 211 #define DBGBCR_BAS_SHIFT 5 212 #define DBGBCR_BAS (0xf << DBGBCR_BAS_SHIFT) 213 #define DBGBCR_HMC_SHIFT 13 214 #define DBGBCR_HMC (0x1 << DBGBCR_HMC_SHIFT) 215 #define DBGBCR_SSC_SHIFT 14 216 #define DBGBCR_SSC (0x3 << DBGBCR_SSC_SHIFT) 217 #define DBGBCR_LBN_SHIFT 16 218 #define DBGBCR_LBN (0xf << DBGBCR_LBN_SHIFT) 219 #define DBGBCR_BT_SHIFT 20 220 #define DBGBCR_BT (0xf << DBGBCR_BT_SHIFT) 221 222 /* DBGBVR<n>_EL1 - Debug Breakpoint Value Registers */ 223 #define DBGBVR_EL1_op0 2 224 #define DBGBVR_EL1_op1 0 225 #define DBGBVR_EL1_CRn 0 226 /* DBGBVR_EL1_CRm indicates which watchpoint this register is for */ 227 #define DBGBVR_EL1_op2 4 228 229 /* DBGWCR<n>_EL1 - Debug Watchpoint Control Registers */ 230 #define DBGWCR_EL1_op0 2 231 #define DBGWCR_EL1_op1 0 232 #define DBGWCR_EL1_CRn 0 233 /* DBGWCR_EL1_CRm indicates which watchpoint this register is for */ 234 #define DBGWCR_EL1_op2 7 235 #define DBGWCR_EN 0x1 236 #define DBGWCR_PAC_SHIFT 1 237 #define DBGWCR_PAC (0x3 << DBGWCR_PAC_SHIFT) 238 #define DBGWCR_PAC_EL1 (0x1 << DBGWCR_PAC_SHIFT) 239 #define DBGWCR_PAC_EL0 (0x2 << DBGWCR_PAC_SHIFT) 240 #define DBGWCR_LSC_SHIFT 3 241 #define DBGWCR_LSC (0x3 << DBGWCR_LSC_SHIFT) 242 #define DBGWCR_BAS_SHIFT 5 243 #define DBGWCR_BAS (0xff << DBGWCR_BAS_SHIFT) 244 #define DBGWCR_HMC_SHIFT 13 245 #define DBGWCR_HMC (0x1 << DBGWCR_HMC_SHIFT) 246 #define DBGWCR_SSC_SHIFT 14 247 #define DBGWCR_SSC (0x3 << DBGWCR_SSC_SHIFT) 248 #define DBGWCR_LBN_SHIFT 16 249 #define DBGWCR_LBN (0xf << DBGWCR_LBN_SHIFT) 250 #define DBGWCR_WT_SHIFT 20 251 #define DBGWCR_WT (0x1 << DBGWCR_WT_SHIFT) 252 #define DBGWCR_MASK_SHIFT 24 253 #define DBGWCR_MASK (0x1f << DBGWCR_MASK_SHIFT) 254 255 /* DBGWVR<n>_EL1 - Debug Watchpoint Value Registers */ 256 #define DBGWVR_EL1_op0 2 257 #define DBGWVR_EL1_op1 0 258 #define DBGWVR_EL1_CRn 0 259 /* DBGWVR_EL1_CRm indicates which watchpoint this register is for */ 260 #define DBGWVR_EL1_op2 6 261 262 /* DCZID_EL0 - Data Cache Zero ID register */ 263 #define DCZID_DZP (1 << 4) /* DC ZVA prohibited if non-0 */ 264 #define DCZID_BS_SHIFT 0 265 #define DCZID_BS_MASK (0xf << DCZID_BS_SHIFT) 266 #define DCZID_BS_SIZE(reg) (((reg) & DCZID_BS_MASK) >> DCZID_BS_SHIFT) 267 268 /* DBGAUTHSTATUS_EL1 */ 269 #define DBGAUTHSTATUS_EL1 MRS_REG(DBGAUTHSTATUS_EL1) 270 #define DBGAUTHSTATUS_EL1_op0 2 271 #define DBGAUTHSTATUS_EL1_op1 0 272 #define DBGAUTHSTATUS_EL1_CRn 7 273 #define DBGAUTHSTATUS_EL1_CRm 14 274 #define DBGAUTHSTATUS_EL1_op2 6 275 276 /* DBGCLAIMCLR_EL1 */ 277 #define DBGCLAIMCLR_EL1 MRS_REG(DBGCLAIMCLR_EL1) 278 #define DBGCLAIMCLR_EL1_op0 2 279 #define DBGCLAIMCLR_EL1_op1 0 280 #define DBGCLAIMCLR_EL1_CRn 7 281 #define DBGCLAIMCLR_EL1_CRm 9 282 #define DBGCLAIMCLR_EL1_op2 6 283 284 /* DBGCLAIMSET_EL1 */ 285 #define DBGCLAIMSET_EL1 MRS_REG(DBGCLAIMSET_EL1) 286 #define DBGCLAIMSET_EL1_op0 2 287 #define DBGCLAIMSET_EL1_op1 0 288 #define DBGCLAIMSET_EL1_CRn 7 289 #define DBGCLAIMSET_EL1_CRm 8 290 #define DBGCLAIMSET_EL1_op2 6 291 292 /* DBGPRCR_EL1 */ 293 #define DBGPRCR_EL1 MRS_REG(DBGPRCR_EL1) 294 #define DBGPRCR_EL1_op0 2 295 #define DBGPRCR_EL1_op1 0 296 #define DBGPRCR_EL1_CRn 1 297 #define DBGPRCR_EL1_CRm 4 298 #define DBGPRCR_EL1_op2 4 299 300 /* ESR_ELx */ 301 #define ESR_ELx_ISS_MASK 0x01ffffff 302 #define ISS_FP_TFV_SHIFT 23 303 #define ISS_FP_TFV (0x01 << ISS_FP_TFV_SHIFT) 304 #define ISS_FP_IOF 0x01 305 #define ISS_FP_DZF 0x02 306 #define ISS_FP_OFF 0x04 307 #define ISS_FP_UFF 0x08 308 #define ISS_FP_IXF 0x10 309 #define ISS_FP_IDF 0x80 310 #define ISS_INSN_FnV (0x01 << 10) 311 #define ISS_INSN_EA (0x01 << 9) 312 #define ISS_INSN_S1PTW (0x01 << 7) 313 #define ISS_INSN_IFSC_MASK (0x1f << 0) 314 315 #define ISS_MSR_DIR_SHIFT 0 316 #define ISS_MSR_DIR (0x01 << ISS_MSR_DIR_SHIFT) 317 #define ISS_MSR_Rt_SHIFT 5 318 #define ISS_MSR_Rt_MASK (0x1f << ISS_MSR_Rt_SHIFT) 319 #define ISS_MSR_Rt(x) (((x) & ISS_MSR_Rt_MASK) >> ISS_MSR_Rt_SHIFT) 320 #define ISS_MSR_CRm_SHIFT 1 321 #define ISS_MSR_CRm_MASK (0xf << ISS_MSR_CRm_SHIFT) 322 #define ISS_MSR_CRm(x) (((x) & ISS_MSR_CRm_MASK) >> ISS_MSR_CRm_SHIFT) 323 #define ISS_MSR_CRn_SHIFT 10 324 #define ISS_MSR_CRn_MASK (0xf << ISS_MSR_CRn_SHIFT) 325 #define ISS_MSR_CRn(x) (((x) & ISS_MSR_CRn_MASK) >> ISS_MSR_CRn_SHIFT) 326 #define ISS_MSR_OP1_SHIFT 14 327 #define ISS_MSR_OP1_MASK (0x7 << ISS_MSR_OP1_SHIFT) 328 #define ISS_MSR_OP1(x) (((x) & ISS_MSR_OP1_MASK) >> ISS_MSR_OP1_SHIFT) 329 #define ISS_MSR_OP2_SHIFT 17 330 #define ISS_MSR_OP2_MASK (0x7 << ISS_MSR_OP2_SHIFT) 331 #define ISS_MSR_OP2(x) (((x) & ISS_MSR_OP2_MASK) >> ISS_MSR_OP2_SHIFT) 332 #define ISS_MSR_OP0_SHIFT 20 333 #define ISS_MSR_OP0_MASK (0x3 << ISS_MSR_OP0_SHIFT) 334 #define ISS_MSR_OP0(x) (((x) & ISS_MSR_OP0_MASK) >> ISS_MSR_OP0_SHIFT) 335 #define ISS_MSR_REG_MASK \ 336 (ISS_MSR_OP0_MASK | ISS_MSR_OP2_MASK | ISS_MSR_OP1_MASK | \ 337 ISS_MSR_CRn_MASK | ISS_MSR_CRm_MASK) 338 339 #define ISS_DATA_ISV_SHIFT 24 340 #define ISS_DATA_ISV (0x01 << ISS_DATA_ISV_SHIFT) 341 #define ISS_DATA_SAS_SHIFT 22 342 #define ISS_DATA_SAS_MASK (0x03 << ISS_DATA_SAS_SHIFT) 343 #define ISS_DATA_SSE_SHIFT 21 344 #define ISS_DATA_SSE (0x01 << ISS_DATA_SSE_SHIFT) 345 #define ISS_DATA_SRT_SHIFT 16 346 #define ISS_DATA_SRT_MASK (0x1f << ISS_DATA_SRT_SHIFT) 347 #define ISS_DATA_SF (0x01 << 15) 348 #define ISS_DATA_AR (0x01 << 14) 349 #define ISS_DATA_FnV (0x01 << 10) 350 #define ISS_DATA_EA (0x01 << 9) 351 #define ISS_DATA_CM (0x01 << 8) 352 #define ISS_DATA_S1PTW (0x01 << 7) 353 #define ISS_DATA_WnR_SHIFT 6 354 #define ISS_DATA_WnR (0x01 << ISS_DATA_WnR_SHIFT) 355 #define ISS_DATA_DFSC_MASK (0x3f << 0) 356 #define ISS_DATA_DFSC_ASF_L0 (0x00 << 0) 357 #define ISS_DATA_DFSC_ASF_L1 (0x01 << 0) 358 #define ISS_DATA_DFSC_ASF_L2 (0x02 << 0) 359 #define ISS_DATA_DFSC_ASF_L3 (0x03 << 0) 360 #define ISS_DATA_DFSC_TF_L0 (0x04 << 0) 361 #define ISS_DATA_DFSC_TF_L1 (0x05 << 0) 362 #define ISS_DATA_DFSC_TF_L2 (0x06 << 0) 363 #define ISS_DATA_DFSC_TF_L3 (0x07 << 0) 364 #define ISS_DATA_DFSC_AFF_L1 (0x09 << 0) 365 #define ISS_DATA_DFSC_AFF_L2 (0x0a << 0) 366 #define ISS_DATA_DFSC_AFF_L3 (0x0b << 0) 367 #define ISS_DATA_DFSC_PF_L1 (0x0d << 0) 368 #define ISS_DATA_DFSC_PF_L2 (0x0e << 0) 369 #define ISS_DATA_DFSC_PF_L3 (0x0f << 0) 370 #define ISS_DATA_DFSC_EXT (0x10 << 0) 371 #define ISS_DATA_DFSC_EXT_L0 (0x14 << 0) 372 #define ISS_DATA_DFSC_EXT_L1 (0x15 << 0) 373 #define ISS_DATA_DFSC_EXT_L2 (0x16 << 0) 374 #define ISS_DATA_DFSC_EXT_L3 (0x17 << 0) 375 #define ISS_DATA_DFSC_ECC (0x18 << 0) 376 #define ISS_DATA_DFSC_ECC_L0 (0x1c << 0) 377 #define ISS_DATA_DFSC_ECC_L1 (0x1d << 0) 378 #define ISS_DATA_DFSC_ECC_L2 (0x1e << 0) 379 #define ISS_DATA_DFSC_ECC_L3 (0x1f << 0) 380 #define ISS_DATA_DFSC_ALIGN (0x21 << 0) 381 #define ISS_DATA_DFSC_TLB_CONFLICT (0x30 << 0) 382 #define ESR_ELx_IL (0x01 << 25) 383 #define ESR_ELx_EC_SHIFT 26 384 #define ESR_ELx_EC_MASK (0x3f << 26) 385 #define ESR_ELx_EXCEPTION(esr) (((esr) & ESR_ELx_EC_MASK) >> ESR_ELx_EC_SHIFT) 386 #define EXCP_UNKNOWN 0x00 /* Unkwn exception */ 387 #define EXCP_TRAP_WFI_WFE 0x01 /* Trapped WFI or WFE */ 388 #define EXCP_FP_SIMD 0x07 /* VFP/SIMD trap */ 389 #define EXCP_ILL_STATE 0x0e /* Illegal execution state */ 390 #define EXCP_SVC32 0x11 /* SVC trap for AArch32 */ 391 #define EXCP_SVC64 0x15 /* SVC trap for AArch64 */ 392 #define EXCP_HVC 0x16 /* HVC trap */ 393 #define EXCP_MSR 0x18 /* MSR/MRS trap */ 394 #define EXCP_SVE 0x19 /* SVE trap */ 395 #define EXCP_FPAC 0x1c /* Faulting PAC trap */ 396 #define EXCP_INSN_ABORT_L 0x20 /* Instruction abort, from lower EL */ 397 #define EXCP_INSN_ABORT 0x21 /* Instruction abort, from same EL */ 398 #define EXCP_PC_ALIGN 0x22 /* PC alignment fault */ 399 #define EXCP_DATA_ABORT_L 0x24 /* Data abort, from lower EL */ 400 #define EXCP_DATA_ABORT 0x25 /* Data abort, from same EL */ 401 #define EXCP_SP_ALIGN 0x26 /* SP slignment fault */ 402 #define EXCP_TRAP_FP 0x2c /* Trapped FP exception */ 403 #define EXCP_SERROR 0x2f /* SError interrupt */ 404 #define EXCP_BRKPT_EL0 0x30 /* Hardware breakpoint, from same EL */ 405 #define EXCP_SOFTSTP_EL0 0x32 /* Software Step, from lower EL */ 406 #define EXCP_SOFTSTP_EL1 0x33 /* Software Step, from same EL */ 407 #define EXCP_WATCHPT_EL0 0x34 /* Watchpoint, from lower EL */ 408 #define EXCP_WATCHPT_EL1 0x35 /* Watchpoint, from same EL */ 409 #define EXCP_BRKPT_32 0x38 /* 32bits breakpoint */ 410 #define EXCP_BRK 0x3c /* Breakpoint */ 411 412 /* ICC_CTLR_EL1 */ 413 #define ICC_CTLR_EL1_EOIMODE (1U << 1) 414 415 /* ICC_IAR1_EL1 */ 416 #define ICC_IAR1_EL1_SPUR (0x03ff) 417 418 /* ICC_IGRPEN0_EL1 */ 419 #define ICC_IGRPEN0_EL1_EN (1U << 0) 420 421 /* ICC_PMR_EL1 */ 422 #define ICC_PMR_EL1_PRIO_MASK (0xFFUL) 423 424 /* ICC_SGI1R_EL1 */ 425 #define ICC_SGI1R_EL1 MRS_REG(ICC_SGI1R_EL1) 426 #define ICC_SGI1R_EL1_op0 3 427 #define ICC_SGI1R_EL1_op1 0 428 #define ICC_SGI1R_EL1_CRn 12 429 #define ICC_SGI1R_EL1_CRm 11 430 #define ICC_SGI1R_EL1_op2 5 431 #define ICC_SGI1R_EL1_TL_SHIFT 0 432 #define ICC_SGI1R_EL1_TL_MASK (0xffffUL << ICC_SGI1R_EL1_TL_SHIFT) 433 #define ICC_SGI1R_EL1_TL_VAL(x) ((x) & ICC_SGI1R_EL1_TL_MASK) 434 #define ICC_SGI1R_EL1_AFF1_SHIFT 16 435 #define ICC_SGI1R_EL1_AFF1_MASK (0xfful << ICC_SGI1R_EL1_AFF1_SHIFT) 436 #define ICC_SGI1R_EL1_AFF1_VAL(x) ((x) & ICC_SGI1R_EL1_AFF1_MASK) 437 #define ICC_SGI1R_EL1_SGIID_SHIFT 24 438 #define ICC_SGI1R_EL1_SGIID_MASK (0xfUL << ICC_SGI1R_EL1_SGIID_SHIFT) 439 #define ICC_SGI1R_EL1_SGIID_VAL(x) ((x) & ICC_SGI1R_EL1_SGIID_MASK) 440 #define ICC_SGI1R_EL1_AFF2_SHIFT 32 441 #define ICC_SGI1R_EL1_AFF2_MASK (0xfful << ICC_SGI1R_EL1_AFF2_SHIFT) 442 #define ICC_SGI1R_EL1_AFF2_VAL(x) ((x) & ICC_SGI1R_EL1_AFF2_MASK) 443 #define ICC_SGI1R_EL1_RS_SHIFT 44 444 #define ICC_SGI1R_EL1_RS_MASK (0xful << ICC_SGI1R_EL1_RS_SHIFT) 445 #define ICC_SGI1R_EL1_RS_VAL(x) ((x) & ICC_SGI1R_EL1_RS_MASK) 446 #define ICC_SGI1R_EL1_AFF3_SHIFT 48 447 #define ICC_SGI1R_EL1_AFF3_MASK (0xfful << ICC_SGI1R_EL1_AFF3_SHIFT) 448 #define ICC_SGI1R_EL1_AFF3_VAL(x) ((x) & ICC_SGI1R_EL1_AFF3_MASK) 449 #define ICC_SGI1R_EL1_IRM (0x1UL << 40) 450 451 /* ICC_SRE_EL1 */ 452 #define ICC_SRE_EL1_SRE (1U << 0) 453 454 /* ID_AA64AFR0_EL1 */ 455 #define ID_AA64AFR0_EL1 MRS_REG(ID_AA64AFR0_EL1) 456 #define ID_AA64AFR0_EL1_op0 3 457 #define ID_AA64AFR0_EL1_op1 0 458 #define ID_AA64AFR0_EL1_CRn 0 459 #define ID_AA64AFR0_EL1_CRm 5 460 #define ID_AA64AFR0_EL1_op2 4 461 462 /* ID_AA64AFR1_EL1 */ 463 #define ID_AA64AFR1_EL1 MRS_REG(ID_AA64AFR1_EL1) 464 #define ID_AA64AFR1_EL1_op0 3 465 #define ID_AA64AFR1_EL1_op1 0 466 #define ID_AA64AFR1_EL1_CRn 0 467 #define ID_AA64AFR1_EL1_CRm 5 468 #define ID_AA64AFR1_EL1_op2 5 469 470 /* ID_AA64DFR0_EL1 */ 471 #define ID_AA64DFR0_EL1 MRS_REG(ID_AA64DFR0_EL1) 472 #define ID_AA64DFR0_EL1_op0 0x3 473 #define ID_AA64DFR0_EL1_op1 0x0 474 #define ID_AA64DFR0_EL1_CRn 0x0 475 #define ID_AA64DFR0_EL1_CRm 0x5 476 #define ID_AA64DFR0_EL1_op2 0x0 477 #define ID_AA64DFR0_DebugVer_SHIFT 0 478 #define ID_AA64DFR0_DebugVer_MASK (UL(0xf) << ID_AA64DFR0_DebugVer_SHIFT) 479 #define ID_AA64DFR0_DebugVer_VAL(x) ((x) & ID_AA64DFR0_DebugVer_MASK) 480 #define ID_AA64DFR0_DebugVer_8 (UL(0x6) << ID_AA64DFR0_DebugVer_SHIFT) 481 #define ID_AA64DFR0_DebugVer_8_VHE (UL(0x7) << ID_AA64DFR0_DebugVer_SHIFT) 482 #define ID_AA64DFR0_DebugVer_8_2 (UL(0x8) << ID_AA64DFR0_DebugVer_SHIFT) 483 #define ID_AA64DFR0_DebugVer_8_4 (UL(0x9) << ID_AA64DFR0_DebugVer_SHIFT) 484 #define ID_AA64DFR0_TraceVer_SHIFT 4 485 #define ID_AA64DFR0_TraceVer_MASK (UL(0xf) << ID_AA64DFR0_TraceVer_SHIFT) 486 #define ID_AA64DFR0_TraceVer_VAL(x) ((x) & ID_AA64DFR0_TraceVer_MASK) 487 #define ID_AA64DFR0_TraceVer_NONE (UL(0x0) << ID_AA64DFR0_TraceVer_SHIFT) 488 #define ID_AA64DFR0_TraceVer_IMPL (UL(0x1) << ID_AA64DFR0_TraceVer_SHIFT) 489 #define ID_AA64DFR0_PMUVer_SHIFT 8 490 #define ID_AA64DFR0_PMUVer_MASK (UL(0xf) << ID_AA64DFR0_PMUVer_SHIFT) 491 #define ID_AA64DFR0_PMUVer_VAL(x) ((x) & ID_AA64DFR0_PMUVer_MASK) 492 #define ID_AA64DFR0_PMUVer_NONE (UL(0x0) << ID_AA64DFR0_PMUVer_SHIFT) 493 #define ID_AA64DFR0_PMUVer_3 (UL(0x1) << ID_AA64DFR0_PMUVer_SHIFT) 494 #define ID_AA64DFR0_PMUVer_3_1 (UL(0x4) << ID_AA64DFR0_PMUVer_SHIFT) 495 #define ID_AA64DFR0_PMUVer_3_4 (UL(0x5) << ID_AA64DFR0_PMUVer_SHIFT) 496 #define ID_AA64DFR0_PMUVer_3_5 (UL(0x6) << ID_AA64DFR0_PMUVer_SHIFT) 497 #define ID_AA64DFR0_PMUVer_IMPL (UL(0xf) << ID_AA64DFR0_PMUVer_SHIFT) 498 #define ID_AA64DFR0_BRPs_SHIFT 12 499 #define ID_AA64DFR0_BRPs_MASK (UL(0xf) << ID_AA64DFR0_BRPs_SHIFT) 500 #define ID_AA64DFR0_BRPs_VAL(x) \ 501 ((((x) >> ID_AA64DFR0_BRPs_SHIFT) & 0xf) + 1) 502 #define ID_AA64DFR0_WRPs_SHIFT 20 503 #define ID_AA64DFR0_WRPs_MASK (UL(0xf) << ID_AA64DFR0_WRPs_SHIFT) 504 #define ID_AA64DFR0_WRPs_VAL(x) \ 505 ((((x) >> ID_AA64DFR0_WRPs_SHIFT) & 0xf) + 1) 506 #define ID_AA64DFR0_CTX_CMPs_SHIFT 28 507 #define ID_AA64DFR0_CTX_CMPs_MASK (UL(0xf) << ID_AA64DFR0_CTX_CMPs_SHIFT) 508 #define ID_AA64DFR0_CTX_CMPs_VAL(x) \ 509 ((((x) >> ID_AA64DFR0_CTX_CMPs_SHIFT) & 0xf) + 1) 510 #define ID_AA64DFR0_PMSVer_SHIFT 32 511 #define ID_AA64DFR0_PMSVer_MASK (UL(0xf) << ID_AA64DFR0_PMSVer_SHIFT) 512 #define ID_AA64DFR0_PMSVer_VAL(x) ((x) & ID_AA64DFR0_PMSVer_MASK) 513 #define ID_AA64DFR0_PMSVer_NONE (UL(0x0) << ID_AA64DFR0_PMSVer_SHIFT) 514 #define ID_AA64DFR0_PMSVer_SPE (UL(0x1) << ID_AA64DFR0_PMSVer_SHIFT) 515 #define ID_AA64DFR0_PMSVer_SPE_8_3 (UL(0x2) << ID_AA64DFR0_PMSVer_SHIFT) 516 #define ID_AA64DFR0_DoubleLock_SHIFT 36 517 #define ID_AA64DFR0_DoubleLock_MASK (UL(0xf) << ID_AA64DFR0_DoubleLock_SHIFT) 518 #define ID_AA64DFR0_DoubleLock_VAL(x) ((x) & ID_AA64DFR0_DoubleLock_MASK) 519 #define ID_AA64DFR0_DoubleLock_IMPL (UL(0x0) << ID_AA64DFR0_DoubleLock_SHIFT) 520 #define ID_AA64DFR0_DoubleLock_NONE (UL(0xf) << ID_AA64DFR0_DoubleLock_SHIFT) 521 #define ID_AA64DFR0_TraceFilt_SHIFT 40 522 #define ID_AA64DFR0_TraceFilt_MASK (UL(0xf) << ID_AA64DFR0_TraceFilt_SHIFT) 523 #define ID_AA64DFR0_TraceFilt_VAL(x) ((x) & ID_AA64DFR0_TraceFilt_MASK) 524 #define ID_AA64DFR0_TraceFilt_NONE (UL(0x0) << ID_AA64DFR0_TraceFilt_SHIFT) 525 #define ID_AA64DFR0_TraceFilt_8_4 (UL(0x1) << ID_AA64DFR0_TraceFilt_SHIFT) 526 527 /* ID_AA64DFR1_EL1 */ 528 #define ID_AA64DFR1_EL1 MRS_REG(ID_AA64DFR1_EL1) 529 #define ID_AA64DFR1_EL1_op0 3 530 #define ID_AA64DFR1_EL1_op1 0 531 #define ID_AA64DFR1_EL1_CRn 0 532 #define ID_AA64DFR1_EL1_CRm 5 533 #define ID_AA64DFR1_EL1_op2 1 534 535 /* ID_AA64ISAR0_EL1 */ 536 #define ID_AA64ISAR0_EL1 MRS_REG(ID_AA64ISAR0_EL1) 537 #define ID_AA64ISAR0_EL1_op0 0x3 538 #define ID_AA64ISAR0_EL1_op1 0x0 539 #define ID_AA64ISAR0_EL1_CRn 0x0 540 #define ID_AA64ISAR0_EL1_CRm 0x6 541 #define ID_AA64ISAR0_EL1_op2 0x0 542 #define ID_AA64ISAR0_AES_SHIFT 4 543 #define ID_AA64ISAR0_AES_MASK (UL(0xf) << ID_AA64ISAR0_AES_SHIFT) 544 #define ID_AA64ISAR0_AES_VAL(x) ((x) & ID_AA64ISAR0_AES_MASK) 545 #define ID_AA64ISAR0_AES_NONE (UL(0x0) << ID_AA64ISAR0_AES_SHIFT) 546 #define ID_AA64ISAR0_AES_BASE (UL(0x1) << ID_AA64ISAR0_AES_SHIFT) 547 #define ID_AA64ISAR0_AES_PMULL (UL(0x2) << ID_AA64ISAR0_AES_SHIFT) 548 #define ID_AA64ISAR0_SHA1_SHIFT 8 549 #define ID_AA64ISAR0_SHA1_MASK (UL(0xf) << ID_AA64ISAR0_SHA1_SHIFT) 550 #define ID_AA64ISAR0_SHA1_VAL(x) ((x) & ID_AA64ISAR0_SHA1_MASK) 551 #define ID_AA64ISAR0_SHA1_NONE (UL(0x0) << ID_AA64ISAR0_SHA1_SHIFT) 552 #define ID_AA64ISAR0_SHA1_BASE (UL(0x1) << ID_AA64ISAR0_SHA1_SHIFT) 553 #define ID_AA64ISAR0_SHA2_SHIFT 12 554 #define ID_AA64ISAR0_SHA2_MASK (UL(0xf) << ID_AA64ISAR0_SHA2_SHIFT) 555 #define ID_AA64ISAR0_SHA2_VAL(x) ((x) & ID_AA64ISAR0_SHA2_MASK) 556 #define ID_AA64ISAR0_SHA2_NONE (UL(0x0) << ID_AA64ISAR0_SHA2_SHIFT) 557 #define ID_AA64ISAR0_SHA2_BASE (UL(0x1) << ID_AA64ISAR0_SHA2_SHIFT) 558 #define ID_AA64ISAR0_SHA2_512 (UL(0x2) << ID_AA64ISAR0_SHA2_SHIFT) 559 #define ID_AA64ISAR0_CRC32_SHIFT 16 560 #define ID_AA64ISAR0_CRC32_MASK (UL(0xf) << ID_AA64ISAR0_CRC32_SHIFT) 561 #define ID_AA64ISAR0_CRC32_VAL(x) ((x) & ID_AA64ISAR0_CRC32_MASK) 562 #define ID_AA64ISAR0_CRC32_NONE (UL(0x0) << ID_AA64ISAR0_CRC32_SHIFT) 563 #define ID_AA64ISAR0_CRC32_BASE (UL(0x1) << ID_AA64ISAR0_CRC32_SHIFT) 564 #define ID_AA64ISAR0_Atomic_SHIFT 20 565 #define ID_AA64ISAR0_Atomic_MASK (UL(0xf) << ID_AA64ISAR0_Atomic_SHIFT) 566 #define ID_AA64ISAR0_Atomic_VAL(x) ((x) & ID_AA64ISAR0_Atomic_MASK) 567 #define ID_AA64ISAR0_Atomic_NONE (UL(0x0) << ID_AA64ISAR0_Atomic_SHIFT) 568 #define ID_AA64ISAR0_Atomic_IMPL (UL(0x2) << ID_AA64ISAR0_Atomic_SHIFT) 569 #define ID_AA64ISAR0_RDM_SHIFT 28 570 #define ID_AA64ISAR0_RDM_MASK (UL(0xf) << ID_AA64ISAR0_RDM_SHIFT) 571 #define ID_AA64ISAR0_RDM_VAL(x) ((x) & ID_AA64ISAR0_RDM_MASK) 572 #define ID_AA64ISAR0_RDM_NONE (UL(0x0) << ID_AA64ISAR0_RDM_SHIFT) 573 #define ID_AA64ISAR0_RDM_IMPL (UL(0x1) << ID_AA64ISAR0_RDM_SHIFT) 574 #define ID_AA64ISAR0_SHA3_SHIFT 32 575 #define ID_AA64ISAR0_SHA3_MASK (UL(0xf) << ID_AA64ISAR0_SHA3_SHIFT) 576 #define ID_AA64ISAR0_SHA3_VAL(x) ((x) & ID_AA64ISAR0_SHA3_MASK) 577 #define ID_AA64ISAR0_SHA3_NONE (UL(0x0) << ID_AA64ISAR0_SHA3_SHIFT) 578 #define ID_AA64ISAR0_SHA3_IMPL (UL(0x1) << ID_AA64ISAR0_SHA3_SHIFT) 579 #define ID_AA64ISAR0_SM3_SHIFT 36 580 #define ID_AA64ISAR0_SM3_MASK (UL(0xf) << ID_AA64ISAR0_SM3_SHIFT) 581 #define ID_AA64ISAR0_SM3_VAL(x) ((x) & ID_AA64ISAR0_SM3_MASK) 582 #define ID_AA64ISAR0_SM3_NONE (UL(0x0) << ID_AA64ISAR0_SM3_SHIFT) 583 #define ID_AA64ISAR0_SM3_IMPL (UL(0x1) << ID_AA64ISAR0_SM3_SHIFT) 584 #define ID_AA64ISAR0_SM4_SHIFT 40 585 #define ID_AA64ISAR0_SM4_MASK (UL(0xf) << ID_AA64ISAR0_SM4_SHIFT) 586 #define ID_AA64ISAR0_SM4_VAL(x) ((x) & ID_AA64ISAR0_SM4_MASK) 587 #define ID_AA64ISAR0_SM4_NONE (UL(0x0) << ID_AA64ISAR0_SM4_SHIFT) 588 #define ID_AA64ISAR0_SM4_IMPL (UL(0x1) << ID_AA64ISAR0_SM4_SHIFT) 589 #define ID_AA64ISAR0_DP_SHIFT 44 590 #define ID_AA64ISAR0_DP_MASK (UL(0xf) << ID_AA64ISAR0_DP_SHIFT) 591 #define ID_AA64ISAR0_DP_VAL(x) ((x) & ID_AA64ISAR0_DP_MASK) 592 #define ID_AA64ISAR0_DP_NONE (UL(0x0) << ID_AA64ISAR0_DP_SHIFT) 593 #define ID_AA64ISAR0_DP_IMPL (UL(0x1) << ID_AA64ISAR0_DP_SHIFT) 594 #define ID_AA64ISAR0_FHM_SHIFT 48 595 #define ID_AA64ISAR0_FHM_MASK (UL(0xf) << ID_AA64ISAR0_FHM_SHIFT) 596 #define ID_AA64ISAR0_FHM_VAL(x) ((x) & ID_AA64ISAR0_FHM_MASK) 597 #define ID_AA64ISAR0_FHM_NONE (UL(0x0) << ID_AA64ISAR0_FHM_SHIFT) 598 #define ID_AA64ISAR0_FHM_IMPL (UL(0x1) << ID_AA64ISAR0_FHM_SHIFT) 599 #define ID_AA64ISAR0_TS_SHIFT 52 600 #define ID_AA64ISAR0_TS_MASK (UL(0xf) << ID_AA64ISAR0_TS_SHIFT) 601 #define ID_AA64ISAR0_TS_VAL(x) ((x) & ID_AA64ISAR0_TS_MASK) 602 #define ID_AA64ISAR0_TS_NONE (UL(0x0) << ID_AA64ISAR0_TS_SHIFT) 603 #define ID_AA64ISAR0_TS_CondM_8_4 (UL(0x1) << ID_AA64ISAR0_TS_SHIFT) 604 #define ID_AA64ISAR0_TS_CondM_8_5 (UL(0x2) << ID_AA64ISAR0_TS_SHIFT) 605 #define ID_AA64ISAR0_TLB_SHIFT 56 606 #define ID_AA64ISAR0_TLB_MASK (UL(0xf) << ID_AA64ISAR0_TLB_SHIFT) 607 #define ID_AA64ISAR0_TLB_VAL(x) ((x) & ID_AA64ISAR0_TLB_MASK) 608 #define ID_AA64ISAR0_TLB_NONE (UL(0x0) << ID_AA64ISAR0_TLB_SHIFT) 609 #define ID_AA64ISAR0_TLB_TLBIOS (UL(0x1) << ID_AA64ISAR0_TLB_SHIFT) 610 #define ID_AA64ISAR0_TLB_TLBIOSR (UL(0x2) << ID_AA64ISAR0_TLB_SHIFT) 611 #define ID_AA64ISAR0_RNDR_SHIFT 60 612 #define ID_AA64ISAR0_RNDR_MASK (UL(0xf) << ID_AA64ISAR0_RNDR_SHIFT) 613 #define ID_AA64ISAR0_RNDR_VAL(x) ((x) & ID_AA64ISAR0_RNDR_MASK) 614 #define ID_AA64ISAR0_RNDR_NONE (UL(0x0) << ID_AA64ISAR0_RNDR_SHIFT) 615 #define ID_AA64ISAR0_RNDR_IMPL (UL(0x1) << ID_AA64ISAR0_RNDR_SHIFT) 616 617 /* ID_AA64ISAR1_EL1 */ 618 #define ID_AA64ISAR1_EL1 MRS_REG(ID_AA64ISAR1_EL1) 619 #define ID_AA64ISAR1_EL1_op0 0x3 620 #define ID_AA64ISAR1_EL1_op1 0x0 621 #define ID_AA64ISAR1_EL1_CRn 0x0 622 #define ID_AA64ISAR1_EL1_CRm 0x6 623 #define ID_AA64ISAR1_EL1_op2 0x1 624 #define ID_AA64ISAR1_DPB_SHIFT 0 625 #define ID_AA64ISAR1_DPB_MASK (UL(0xf) << ID_AA64ISAR1_DPB_SHIFT) 626 #define ID_AA64ISAR1_DPB_VAL(x) ((x) & ID_AA64ISAR1_DPB_MASK) 627 #define ID_AA64ISAR1_DPB_NONE (UL(0x0) << ID_AA64ISAR1_DPB_SHIFT) 628 #define ID_AA64ISAR1_DPB_DCCVAP (UL(0x1) << ID_AA64ISAR1_DPB_SHIFT) 629 #define ID_AA64ISAR1_DPB_DCCVADP (UL(0x2) << ID_AA64ISAR1_DPB_SHIFT) 630 #define ID_AA64ISAR1_APA_SHIFT 4 631 #define ID_AA64ISAR1_APA_MASK (UL(0xf) << ID_AA64ISAR1_APA_SHIFT) 632 #define ID_AA64ISAR1_APA_VAL(x) ((x) & ID_AA64ISAR1_APA_MASK) 633 #define ID_AA64ISAR1_APA_NONE (UL(0x0) << ID_AA64ISAR1_APA_SHIFT) 634 #define ID_AA64ISAR1_APA_PAC (UL(0x1) << ID_AA64ISAR1_APA_SHIFT) 635 #define ID_AA64ISAR1_APA_EPAC (UL(0x2) << ID_AA64ISAR1_APA_SHIFT) 636 #define ID_AA64ISAR1_APA_EPAC2 (UL(0x3) << ID_AA64ISAR1_APA_SHIFT) 637 #define ID_AA64ISAR1_APA_FPAC (UL(0x4) << ID_AA64ISAR1_APA_SHIFT) 638 #define ID_AA64ISAR1_APA_FPAC_COMBINED (UL(0x5) << ID_AA64ISAR1_APA_SHIFT) 639 #define ID_AA64ISAR1_API_SHIFT 8 640 #define ID_AA64ISAR1_API_MASK (UL(0xf) << ID_AA64ISAR1_API_SHIFT) 641 #define ID_AA64ISAR1_API_VAL(x) ((x) & ID_AA64ISAR1_API_MASK) 642 #define ID_AA64ISAR1_API_NONE (UL(0x0) << ID_AA64ISAR1_API_SHIFT) 643 #define ID_AA64ISAR1_API_PAC (UL(0x1) << ID_AA64ISAR1_API_SHIFT) 644 #define ID_AA64ISAR1_API_EPAC (UL(0x2) << ID_AA64ISAR1_API_SHIFT) 645 #define ID_AA64ISAR1_API_EPAC2 (UL(0x3) << ID_AA64ISAR1_API_SHIFT) 646 #define ID_AA64ISAR1_API_FPAC (UL(0x4) << ID_AA64ISAR1_API_SHIFT) 647 #define ID_AA64ISAR1_API_FPAC_COMBINED (UL(0x5) << ID_AA64ISAR1_API_SHIFT) 648 #define ID_AA64ISAR1_JSCVT_SHIFT 12 649 #define ID_AA64ISAR1_JSCVT_MASK (UL(0xf) << ID_AA64ISAR1_JSCVT_SHIFT) 650 #define ID_AA64ISAR1_JSCVT_VAL(x) ((x) & ID_AA64ISAR1_JSCVT_MASK) 651 #define ID_AA64ISAR1_JSCVT_NONE (UL(0x0) << ID_AA64ISAR1_JSCVT_SHIFT) 652 #define ID_AA64ISAR1_JSCVT_IMPL (UL(0x1) << ID_AA64ISAR1_JSCVT_SHIFT) 653 #define ID_AA64ISAR1_FCMA_SHIFT 16 654 #define ID_AA64ISAR1_FCMA_MASK (UL(0xf) << ID_AA64ISAR1_FCMA_SHIFT) 655 #define ID_AA64ISAR1_FCMA_VAL(x) ((x) & ID_AA64ISAR1_FCMA_MASK) 656 #define ID_AA64ISAR1_FCMA_NONE (UL(0x0) << ID_AA64ISAR1_FCMA_SHIFT) 657 #define ID_AA64ISAR1_FCMA_IMPL (UL(0x1) << ID_AA64ISAR1_FCMA_SHIFT) 658 #define ID_AA64ISAR1_LRCPC_SHIFT 20 659 #define ID_AA64ISAR1_LRCPC_MASK (UL(0xf) << ID_AA64ISAR1_LRCPC_SHIFT) 660 #define ID_AA64ISAR1_LRCPC_VAL(x) ((x) & ID_AA64ISAR1_LRCPC_MASK) 661 #define ID_AA64ISAR1_LRCPC_NONE (UL(0x0) << ID_AA64ISAR1_LRCPC_SHIFT) 662 #define ID_AA64ISAR1_LRCPC_RCPC_8_3 (UL(0x1) << ID_AA64ISAR1_LRCPC_SHIFT) 663 #define ID_AA64ISAR1_LRCPC_RCPC_8_4 (UL(0x2) << ID_AA64ISAR1_LRCPC_SHIFT) 664 #define ID_AA64ISAR1_GPA_SHIFT 24 665 #define ID_AA64ISAR1_GPA_MASK (UL(0xf) << ID_AA64ISAR1_GPA_SHIFT) 666 #define ID_AA64ISAR1_GPA_VAL(x) ((x) & ID_AA64ISAR1_GPA_MASK) 667 #define ID_AA64ISAR1_GPA_NONE (UL(0x0) << ID_AA64ISAR1_GPA_SHIFT) 668 #define ID_AA64ISAR1_GPA_IMPL (UL(0x1) << ID_AA64ISAR1_GPA_SHIFT) 669 #define ID_AA64ISAR1_GPI_SHIFT 28 670 #define ID_AA64ISAR1_GPI_MASK (UL(0xf) << ID_AA64ISAR1_GPI_SHIFT) 671 #define ID_AA64ISAR1_GPI_VAL(x) ((x) & ID_AA64ISAR1_GPI_MASK) 672 #define ID_AA64ISAR1_GPI_NONE (UL(0x0) << ID_AA64ISAR1_GPI_SHIFT) 673 #define ID_AA64ISAR1_GPI_IMPL (UL(0x1) << ID_AA64ISAR1_GPI_SHIFT) 674 #define ID_AA64ISAR1_FRINTTS_SHIFT 32 675 #define ID_AA64ISAR1_FRINTTS_MASK (UL(0xf) << ID_AA64ISAR1_FRINTTS_SHIFT) 676 #define ID_AA64ISAR1_FRINTTS_VAL(x) ((x) & ID_AA64ISAR1_FRINTTS_MASK) 677 #define ID_AA64ISAR1_FRINTTS_NONE (UL(0x0) << ID_AA64ISAR1_FRINTTS_SHIFT) 678 #define ID_AA64ISAR1_FRINTTS_IMPL (UL(0x1) << ID_AA64ISAR1_FRINTTS_SHIFT) 679 #define ID_AA64ISAR1_SB_SHIFT 36 680 #define ID_AA64ISAR1_SB_MASK (UL(0xf) << ID_AA64ISAR1_SB_SHIFT) 681 #define ID_AA64ISAR1_SB_VAL(x) ((x) & ID_AA64ISAR1_SB_MASK) 682 #define ID_AA64ISAR1_SB_NONE (UL(0x0) << ID_AA64ISAR1_SB_SHIFT) 683 #define ID_AA64ISAR1_SB_IMPL (UL(0x1) << ID_AA64ISAR1_SB_SHIFT) 684 #define ID_AA64ISAR1_SPECRES_SHIFT 40 685 #define ID_AA64ISAR1_SPECRES_MASK (UL(0xf) << ID_AA64ISAR1_SPECRES_SHIFT) 686 #define ID_AA64ISAR1_SPECRES_VAL(x) ((x) & ID_AA64ISAR1_SPECRES_MASK) 687 #define ID_AA64ISAR1_SPECRES_NONE (UL(0x0) << ID_AA64ISAR1_SPECRES_SHIFT) 688 #define ID_AA64ISAR1_SPECRES_IMPL (UL(0x1) << ID_AA64ISAR1_SPECRES_SHIFT) 689 #define ID_AA64ISAR1_BF16_SHIFT 44 690 #define ID_AA64ISAR1_BF16_MASK (UL(0xf) << ID_AA64ISAR1_BF16_SHIFT) 691 #define ID_AA64ISAR1_BF16_VAL(x) ((x) & ID_AA64ISAR1_BF16_MASK) 692 #define ID_AA64ISAR1_BF16_NONE (UL(0x0) << ID_AA64ISAR1_BF16_SHIFT) 693 #define ID_AA64ISAR1_BF16_IMPL (UL(0x1) << ID_AA64ISAR1_BF16_SHIFT) 694 #define ID_AA64ISAR1_DGH_SHIFT 48 695 #define ID_AA64ISAR1_DGH_MASK (UL(0xf) << ID_AA64ISAR1_DGH_SHIFT) 696 #define ID_AA64ISAR1_DGH_VAL(x) ((x) & ID_AA64ISAR1_DGH_MASK) 697 #define ID_AA64ISAR1_DGH_NONE (UL(0x0) << ID_AA64ISAR1_DGH_SHIFT) 698 #define ID_AA64ISAR1_DGH_IMPL (UL(0x1) << ID_AA64ISAR1_DGH_SHIFT) 699 #define ID_AA64ISAR1_I8MM_SHIFT 52 700 #define ID_AA64ISAR1_I8MM_MASK (UL(0xf) << ID_AA64ISAR1_I8MM_SHIFT) 701 #define ID_AA64ISAR1_I8MM_VAL(x) ((x) & ID_AA64ISAR1_I8MM_MASK) 702 #define ID_AA64ISAR1_I8MM_NONE (UL(0x0) << ID_AA64ISAR1_I8MM_SHIFT) 703 #define ID_AA64ISAR1_I8MM_IMPL (UL(0x1) << ID_AA64ISAR1_I8MM_SHIFT) 704 705 /* ID_AA64ISAR2_EL1 */ 706 #define ID_AA64ISAR2_EL1 MRS_REG(ID_AA64ISAR2_EL1) 707 #define ID_AA64ISAR2_EL1_op0 3 708 #define ID_AA64ISAR2_EL1_op1 0 709 #define ID_AA64ISAR2_EL1_CRn 0 710 #define ID_AA64ISAR2_EL1_CRm 6 711 #define ID_AA64ISAR2_EL1_op2 2 712 #define ID_AA64ISAR2_WFxT_SHIFT 0 713 #define ID_AA64ISAR2_WFxT_MASK (UL(0xf) << ID_AA64ISAR2_WFxT_SHIFT) 714 #define ID_AA64ISAR2_WFxT_VAL(x) ((x) & ID_AA64ISAR2_WFxT_MASK) 715 #define ID_AA64ISAR2_WFxT_NONE (UL(0x0) << ID_AA64ISAR2_WFxT_SHIFT) 716 #define ID_AA64ISAR2_WFxT_IMPL (UL(0x1) << ID_AA64ISAR2_WFxT_SHIFT) 717 #define ID_AA64ISAR2_RPRES_SHIFT 4 718 #define ID_AA64ISAR2_RPRES_MASK (UL(0xf) << ID_AA64ISAR2_RPRES_SHIFT) 719 #define ID_AA64ISAR2_RPRES_VAL(x) ((x) & ID_AA64ISAR2_RPRES_MASK) 720 #define ID_AA64ISAR2_RPRES_NONE (UL(0x0) << ID_AA64ISAR2_RPRES_SHIFT) 721 #define ID_AA64ISAR2_RPRES_IMPL (UL(0x1) << ID_AA64ISAR2_RPRES_SHIFT) 722 #define ID_AA64ISAR2_GPA3_SHIFT 8 723 #define ID_AA64ISAR2_GPA3_MASK (UL(0xf) << ID_AA64ISAR2_GPA3_SHIFT) 724 #define ID_AA64ISAR2_GPA3_VAL(x) ((x) & ID_AA64ISAR2_GPA3_MASK) 725 #define ID_AA64ISAR2_GPA3_NONE (UL(0x0) << ID_AA64ISAR2_GPA3_SHIFT) 726 #define ID_AA64ISAR2_GPA3_IMPL (UL(0x1) << ID_AA64ISAR2_GPA3_SHIFT) 727 #define ID_AA64ISAR2_APA3_SHIFT 12 728 #define ID_AA64ISAR2_APA3_MASK (UL(0xf) << ID_AA64ISAR2_APA3_SHIFT) 729 #define ID_AA64ISAR2_APA3_VAL(x) ((x) & ID_AA64ISAR2_APA3_MASK) 730 #define ID_AA64ISAR2_APA3_NONE (UL(0x0) << ID_AA64ISAR2_APA3_SHIFT) 731 #define ID_AA64ISAR2_APA3_PAC (UL(0x1) << ID_AA64ISAR2_APA3_SHIFT) 732 #define ID_AA64ISAR2_APA3_EPAC (UL(0x2) << ID_AA64ISAR2_APA3_SHIFT) 733 #define ID_AA64ISAR2_APA3_EPAC2 (UL(0x3) << ID_AA64ISAR2_APA3_SHIFT) 734 #define ID_AA64ISAR2_APA3_FPAC (UL(0x4) << ID_AA64ISAR2_APA3_SHIFT) 735 #define ID_AA64ISAR2_APA3_FPAC_COMBINED (UL(0x5) << ID_AA64ISAR2_APA3_SHIFT) 736 #define ID_AA64ISAR2_MOPS_SHIFT 16 737 #define ID_AA64ISAR2_MOPS_MASK (UL(0xf) << ID_AA64ISAR2_MOPS_SHIFT) 738 #define ID_AA64ISAR2_MOPS_VAL(x) ((x) & ID_AA64ISAR2_MOPS_MASK) 739 #define ID_AA64ISAR2_MOPS_NONE (UL(0x0) << ID_AA64ISAR2_MOPS_SHIFT) 740 #define ID_AA64ISAR2_MOPS_IMPL (UL(0x1) << ID_AA64ISAR2_MOPS_SHIFT) 741 #define ID_AA64ISAR2_BC_SHIFT 20 742 #define ID_AA64ISAR2_BC_MASK (UL(0xf) << ID_AA64ISAR2_BC_SHIFT) 743 #define ID_AA64ISAR2_BC_VAL(x) ((x) & ID_AA64ISAR2_BC_MASK) 744 #define ID_AA64ISAR2_BC_NONE (UL(0x0) << ID_AA64ISAR2_BC_SHIFT) 745 #define ID_AA64ISAR2_BC_IMPL (UL(0x1) << ID_AA64ISAR2_BC_SHIFT) 746 #define ID_AA64ISAR2_PAC_frac_SHIFT 28 747 #define ID_AA64ISAR2_PAC_frac_MASK (UL(0xf) << ID_AA64ISAR2_PAC_frac_SHIFT) 748 #define ID_AA64ISAR2_PAC_frac_VAL(x) ((x) & ID_AA64ISAR2_PAC_frac_MASK) 749 #define ID_AA64ISAR2_PAC_frac_NONE (UL(0x0) << ID_AA64ISAR2_PAC_frac_SHIFT) 750 #define ID_AA64ISAR2_PAC_frac_IMPL (UL(0x1) << ID_AA64ISAR2_PAC_frac_SHIFT) 751 752 /* ID_AA64MMFR0_EL1 */ 753 #define ID_AA64MMFR0_EL1 MRS_REG(ID_AA64MMFR0_EL1) 754 #define ID_AA64MMFR0_EL1_op0 0x3 755 #define ID_AA64MMFR0_EL1_op1 0x0 756 #define ID_AA64MMFR0_EL1_CRn 0x0 757 #define ID_AA64MMFR0_EL1_CRm 0x7 758 #define ID_AA64MMFR0_EL1_op2 0x0 759 #define ID_AA64MMFR0_PARange_SHIFT 0 760 #define ID_AA64MMFR0_PARange_MASK (UL(0xf) << ID_AA64MMFR0_PARange_SHIFT) 761 #define ID_AA64MMFR0_PARange_VAL(x) ((x) & ID_AA64MMFR0_PARange_MASK) 762 #define ID_AA64MMFR0_PARange_4G (UL(0x0) << ID_AA64MMFR0_PARange_SHIFT) 763 #define ID_AA64MMFR0_PARange_64G (UL(0x1) << ID_AA64MMFR0_PARange_SHIFT) 764 #define ID_AA64MMFR0_PARange_1T (UL(0x2) << ID_AA64MMFR0_PARange_SHIFT) 765 #define ID_AA64MMFR0_PARange_4T (UL(0x3) << ID_AA64MMFR0_PARange_SHIFT) 766 #define ID_AA64MMFR0_PARange_16T (UL(0x4) << ID_AA64MMFR0_PARange_SHIFT) 767 #define ID_AA64MMFR0_PARange_256T (UL(0x5) << ID_AA64MMFR0_PARange_SHIFT) 768 #define ID_AA64MMFR0_PARange_4P (UL(0x6) << ID_AA64MMFR0_PARange_SHIFT) 769 #define ID_AA64MMFR0_ASIDBits_SHIFT 4 770 #define ID_AA64MMFR0_ASIDBits_MASK (UL(0xf) << ID_AA64MMFR0_ASIDBits_SHIFT) 771 #define ID_AA64MMFR0_ASIDBits_VAL(x) ((x) & ID_AA64MMFR0_ASIDBits_MASK) 772 #define ID_AA64MMFR0_ASIDBits_8 (UL(0x0) << ID_AA64MMFR0_ASIDBits_SHIFT) 773 #define ID_AA64MMFR0_ASIDBits_16 (UL(0x2) << ID_AA64MMFR0_ASIDBits_SHIFT) 774 #define ID_AA64MMFR0_BigEnd_SHIFT 8 775 #define ID_AA64MMFR0_BigEnd_MASK (UL(0xf) << ID_AA64MMFR0_BigEnd_SHIFT) 776 #define ID_AA64MMFR0_BigEnd_VAL(x) ((x) & ID_AA64MMFR0_BigEnd_MASK) 777 #define ID_AA64MMFR0_BigEnd_FIXED (UL(0x0) << ID_AA64MMFR0_BigEnd_SHIFT) 778 #define ID_AA64MMFR0_BigEnd_MIXED (UL(0x1) << ID_AA64MMFR0_BigEnd_SHIFT) 779 #define ID_AA64MMFR0_SNSMem_SHIFT 12 780 #define ID_AA64MMFR0_SNSMem_MASK (UL(0xf) << ID_AA64MMFR0_SNSMem_SHIFT) 781 #define ID_AA64MMFR0_SNSMem_VAL(x) ((x) & ID_AA64MMFR0_SNSMem_MASK) 782 #define ID_AA64MMFR0_SNSMem_NONE (UL(0x0) << ID_AA64MMFR0_SNSMem_SHIFT) 783 #define ID_AA64MMFR0_SNSMem_DISTINCT (UL(0x1) << ID_AA64MMFR0_SNSMem_SHIFT) 784 #define ID_AA64MMFR0_BigEndEL0_SHIFT 16 785 #define ID_AA64MMFR0_BigEndEL0_MASK (UL(0xf) << ID_AA64MMFR0_BigEndEL0_SHIFT) 786 #define ID_AA64MMFR0_BigEndEL0_VAL(x) ((x) & ID_AA64MMFR0_BigEndEL0_MASK) 787 #define ID_AA64MMFR0_BigEndEL0_FIXED (UL(0x0) << ID_AA64MMFR0_BigEndEL0_SHIFT) 788 #define ID_AA64MMFR0_BigEndEL0_MIXED (UL(0x1) << ID_AA64MMFR0_BigEndEL0_SHIFT) 789 #define ID_AA64MMFR0_TGran16_SHIFT 20 790 #define ID_AA64MMFR0_TGran16_MASK (UL(0xf) << ID_AA64MMFR0_TGran16_SHIFT) 791 #define ID_AA64MMFR0_TGran16_VAL(x) ((x) & ID_AA64MMFR0_TGran16_MASK) 792 #define ID_AA64MMFR0_TGran16_NONE (UL(0x0) << ID_AA64MMFR0_TGran16_SHIFT) 793 #define ID_AA64MMFR0_TGran16_IMPL (UL(0x1) << ID_AA64MMFR0_TGran16_SHIFT) 794 #define ID_AA64MMFR0_TGran64_SHIFT 24 795 #define ID_AA64MMFR0_TGran64_MASK (UL(0xf) << ID_AA64MMFR0_TGran64_SHIFT) 796 #define ID_AA64MMFR0_TGran64_VAL(x) ((x) & ID_AA64MMFR0_TGran64_MASK) 797 #define ID_AA64MMFR0_TGran64_IMPL (UL(0x0) << ID_AA64MMFR0_TGran64_SHIFT) 798 #define ID_AA64MMFR0_TGran64_NONE (UL(0xf) << ID_AA64MMFR0_TGran64_SHIFT) 799 #define ID_AA64MMFR0_TGran4_SHIFT 28 800 #define ID_AA64MMFR0_TGran4_MASK (UL(0xf) << ID_AA64MMFR0_TGran4_SHIFT) 801 #define ID_AA64MMFR0_TGran4_VAL(x) ((x) & ID_AA64MMFR0_TGran4_MASK) 802 #define ID_AA64MMFR0_TGran4_IMPL (UL(0x0) << ID_AA64MMFR0_TGran4_SHIFT) 803 #define ID_AA64MMFR0_TGran4_NONE (UL(0xf) << ID_AA64MMFR0_TGran4_SHIFT) 804 #define ID_AA64MMFR0_TGran16_2_SHIFT 32 805 #define ID_AA64MMFR0_TGran16_2_MASK (UL(0xf) << ID_AA64MMFR0_TGran16_2_SHIFT) 806 #define ID_AA64MMFR0_TGran16_2_VAL(x) ((x) & ID_AA64MMFR0_TGran16_2_MASK) 807 #define ID_AA64MMFR0_TGran16_2_TGran16 (UL(0x0) << ID_AA64MMFR0_TGran16_2_SHIFT) 808 #define ID_AA64MMFR0_TGran16_2_NONE (UL(0x1) << ID_AA64MMFR0_TGran16_2_SHIFT) 809 #define ID_AA64MMFR0_TGran16_2_IMPL (UL(0x2) << ID_AA64MMFR0_TGran16_2_SHIFT) 810 #define ID_AA64MMFR0_TGran64_2_SHIFT 36 811 #define ID_AA64MMFR0_TGran64_2_MASK (UL(0xf) << ID_AA64MMFR0_TGran64_2_SHIFT) 812 #define ID_AA64MMFR0_TGran64_2_VAL(x) ((x) & ID_AA64MMFR0_TGran64_2_MASK) 813 #define ID_AA64MMFR0_TGran64_2_TGran64 (UL(0x0) << ID_AA64MMFR0_TGran64_2_SHIFT) 814 #define ID_AA64MMFR0_TGran64_2_NONE (UL(0x1) << ID_AA64MMFR0_TGran64_2_SHIFT) 815 #define ID_AA64MMFR0_TGran64_2_IMPL (UL(0x2) << ID_AA64MMFR0_TGran64_2_SHIFT) 816 #define ID_AA64MMFR0_TGran4_2_SHIFT 40 817 #define ID_AA64MMFR0_TGran4_2_MASK (UL(0xf) << ID_AA64MMFR0_TGran4_2_SHIFT) 818 #define ID_AA64MMFR0_TGran4_2_VAL(x) ((x) & ID_AA64MMFR0_TGran4_2_MASK) 819 #define ID_AA64MMFR0_TGran4_2_TGran4 (UL(0x0) << ID_AA64MMFR0_TGran4_2_SHIFT) 820 #define ID_AA64MMFR0_TGran4_2_NONE (UL(0x1) << ID_AA64MMFR0_TGran4_2_SHIFT) 821 #define ID_AA64MMFR0_TGran4_2_IMPL (UL(0x2) << ID_AA64MMFR0_TGran4_2_SHIFT) 822 #define ID_AA64MMFR0_ExS_SHIFT 44 823 #define ID_AA64MMFR0_ExS_MASK (UL(0xf) << ID_AA64MMFR0_ExS_SHIFT) 824 #define ID_AA64MMFR0_ExS_VAL(x) ((x) & ID_AA64MMFR0_ExS_MASK) 825 #define ID_AA64MMFR0_ExS_ALL (UL(0x0) << ID_AA64MMFR0_ExS_SHIFT) 826 #define ID_AA64MMFR0_ExS_IMPL (UL(0x1) << ID_AA64MMFR0_ExS_SHIFT) 827 828 /* ID_AA64MMFR1_EL1 */ 829 #define ID_AA64MMFR1_EL1 MRS_REG(ID_AA64MMFR1_EL1) 830 #define ID_AA64MMFR1_EL1_op0 0x3 831 #define ID_AA64MMFR1_EL1_op1 0x0 832 #define ID_AA64MMFR1_EL1_CRn 0x0 833 #define ID_AA64MMFR1_EL1_CRm 0x7 834 #define ID_AA64MMFR1_EL1_op2 0x1 835 #define ID_AA64MMFR1_HAFDBS_SHIFT 0 836 #define ID_AA64MMFR1_HAFDBS_MASK (UL(0xf) << ID_AA64MMFR1_HAFDBS_SHIFT) 837 #define ID_AA64MMFR1_HAFDBS_VAL(x) ((x) & ID_AA64MMFR1_HAFDBS_MASK) 838 #define ID_AA64MMFR1_HAFDBS_NONE (UL(0x0) << ID_AA64MMFR1_HAFDBS_SHIFT) 839 #define ID_AA64MMFR1_HAFDBS_AF (UL(0x1) << ID_AA64MMFR1_HAFDBS_SHIFT) 840 #define ID_AA64MMFR1_HAFDBS_AF_DBS (UL(0x2) << ID_AA64MMFR1_HAFDBS_SHIFT) 841 #define ID_AA64MMFR1_VMIDBits_SHIFT 4 842 #define ID_AA64MMFR1_VMIDBits_MASK (UL(0xf) << ID_AA64MMFR1_VMIDBits_SHIFT) 843 #define ID_AA64MMFR1_VMIDBits_VAL(x) ((x) & ID_AA64MMFR1_VMIDBits_MASK) 844 #define ID_AA64MMFR1_VMIDBits_8 (UL(0x0) << ID_AA64MMFR1_VMIDBits_SHIFT) 845 #define ID_AA64MMFR1_VMIDBits_16 (UL(0x2) << ID_AA64MMFR1_VMIDBits_SHIFT) 846 #define ID_AA64MMFR1_VH_SHIFT 8 847 #define ID_AA64MMFR1_VH_MASK (UL(0xf) << ID_AA64MMFR1_VH_SHIFT) 848 #define ID_AA64MMFR1_VH_VAL(x) ((x) & ID_AA64MMFR1_VH_MASK) 849 #define ID_AA64MMFR1_VH_NONE (UL(0x0) << ID_AA64MMFR1_VH_SHIFT) 850 #define ID_AA64MMFR1_VH_IMPL (UL(0x1) << ID_AA64MMFR1_VH_SHIFT) 851 #define ID_AA64MMFR1_HPDS_SHIFT 12 852 #define ID_AA64MMFR1_HPDS_MASK (UL(0xf) << ID_AA64MMFR1_HPDS_SHIFT) 853 #define ID_AA64MMFR1_HPDS_VAL(x) ((x) & ID_AA64MMFR1_HPDS_MASK) 854 #define ID_AA64MMFR1_HPDS_NONE (UL(0x0) << ID_AA64MMFR1_HPDS_SHIFT) 855 #define ID_AA64MMFR1_HPDS_HPD (UL(0x1) << ID_AA64MMFR1_HPDS_SHIFT) 856 #define ID_AA64MMFR1_HPDS_TTPBHA (UL(0x2) << ID_AA64MMFR1_HPDS_SHIFT) 857 #define ID_AA64MMFR1_LO_SHIFT 16 858 #define ID_AA64MMFR1_LO_MASK (UL(0xf) << ID_AA64MMFR1_LO_SHIFT) 859 #define ID_AA64MMFR1_LO_VAL(x) ((x) & ID_AA64MMFR1_LO_MASK) 860 #define ID_AA64MMFR1_LO_NONE (UL(0x0) << ID_AA64MMFR1_LO_SHIFT) 861 #define ID_AA64MMFR1_LO_IMPL (UL(0x1) << ID_AA64MMFR1_LO_SHIFT) 862 #define ID_AA64MMFR1_PAN_SHIFT 20 863 #define ID_AA64MMFR1_PAN_MASK (UL(0xf) << ID_AA64MMFR1_PAN_SHIFT) 864 #define ID_AA64MMFR1_PAN_VAL(x) ((x) & ID_AA64MMFR1_PAN_MASK) 865 #define ID_AA64MMFR1_PAN_NONE (UL(0x0) << ID_AA64MMFR1_PAN_SHIFT) 866 #define ID_AA64MMFR1_PAN_IMPL (UL(0x1) << ID_AA64MMFR1_PAN_SHIFT) 867 #define ID_AA64MMFR1_PAN_ATS1E1 (UL(0x2) << ID_AA64MMFR1_PAN_SHIFT) 868 #define ID_AA64MMFR1_SpecSEI_SHIFT 24 869 #define ID_AA64MMFR1_SpecSEI_MASK (UL(0xf) << ID_AA64MMFR1_SpecSEI_SHIFT) 870 #define ID_AA64MMFR1_SpecSEI_VAL(x) ((x) & ID_AA64MMFR1_SpecSEI_MASK) 871 #define ID_AA64MMFR1_SpecSEI_NONE (UL(0x0) << ID_AA64MMFR1_SpecSEI_SHIFT) 872 #define ID_AA64MMFR1_SpecSEI_IMPL (UL(0x1) << ID_AA64MMFR1_SpecSEI_SHIFT) 873 #define ID_AA64MMFR1_XNX_SHIFT 28 874 #define ID_AA64MMFR1_XNX_MASK (UL(0xf) << ID_AA64MMFR1_XNX_SHIFT) 875 #define ID_AA64MMFR1_XNX_VAL(x) ((x) & ID_AA64MMFR1_XNX_MASK) 876 #define ID_AA64MMFR1_XNX_NONE (UL(0x0) << ID_AA64MMFR1_XNX_SHIFT) 877 #define ID_AA64MMFR1_XNX_IMPL (UL(0x1) << ID_AA64MMFR1_XNX_SHIFT) 878 879 /* ID_AA64MMFR2_EL1 */ 880 #define ID_AA64MMFR2_EL1 MRS_REG(ID_AA64MMFR2_EL1) 881 #define ID_AA64MMFR2_EL1_op0 0x3 882 #define ID_AA64MMFR2_EL1_op1 0x0 883 #define ID_AA64MMFR2_EL1_CRn 0x0 884 #define ID_AA64MMFR2_EL1_CRm 0x7 885 #define ID_AA64MMFR2_EL1_op2 0x2 886 #define ID_AA64MMFR2_CnP_SHIFT 0 887 #define ID_AA64MMFR2_CnP_MASK (UL(0xf) << ID_AA64MMFR2_CnP_SHIFT) 888 #define ID_AA64MMFR2_CnP_VAL(x) ((x) & ID_AA64MMFR2_CnP_MASK) 889 #define ID_AA64MMFR2_CnP_NONE (UL(0x0) << ID_AA64MMFR2_CnP_SHIFT) 890 #define ID_AA64MMFR2_CnP_IMPL (UL(0x1) << ID_AA64MMFR2_CnP_SHIFT) 891 #define ID_AA64MMFR2_UAO_SHIFT 4 892 #define ID_AA64MMFR2_UAO_MASK (UL(0xf) << ID_AA64MMFR2_UAO_SHIFT) 893 #define ID_AA64MMFR2_UAO_VAL(x) ((x) & ID_AA64MMFR2_UAO_MASK) 894 #define ID_AA64MMFR2_UAO_NONE (UL(0x0) << ID_AA64MMFR2_UAO_SHIFT) 895 #define ID_AA64MMFR2_UAO_IMPL (UL(0x1) << ID_AA64MMFR2_UAO_SHIFT) 896 #define ID_AA64MMFR2_LSM_SHIFT 8 897 #define ID_AA64MMFR2_LSM_MASK (UL(0xf) << ID_AA64MMFR2_LSM_SHIFT) 898 #define ID_AA64MMFR2_LSM_VAL(x) ((x) & ID_AA64MMFR2_LSM_MASK) 899 #define ID_AA64MMFR2_LSM_NONE (UL(0x0) << ID_AA64MMFR2_LSM_SHIFT) 900 #define ID_AA64MMFR2_LSM_IMPL (UL(0x1) << ID_AA64MMFR2_LSM_SHIFT) 901 #define ID_AA64MMFR2_IESB_SHIFT 12 902 #define ID_AA64MMFR2_IESB_MASK (UL(0xf) << ID_AA64MMFR2_IESB_SHIFT) 903 #define ID_AA64MMFR2_IESB_VAL(x) ((x) & ID_AA64MMFR2_IESB_MASK) 904 #define ID_AA64MMFR2_IESB_NONE (UL(0x0) << ID_AA64MMFR2_IESB_SHIFT) 905 #define ID_AA64MMFR2_IESB_IMPL (UL(0x1) << ID_AA64MMFR2_IESB_SHIFT) 906 #define ID_AA64MMFR2_VARange_SHIFT 16 907 #define ID_AA64MMFR2_VARange_MASK (UL(0xf) << ID_AA64MMFR2_VARange_SHIFT) 908 #define ID_AA64MMFR2_VARange_VAL(x) ((x) & ID_AA64MMFR2_VARange_MASK) 909 #define ID_AA64MMFR2_VARange_48 (UL(0x0) << ID_AA64MMFR2_VARange_SHIFT) 910 #define ID_AA64MMFR2_VARange_52 (UL(0x1) << ID_AA64MMFR2_VARange_SHIFT) 911 #define ID_AA64MMFR2_CCIDX_SHIFT 20 912 #define ID_AA64MMFR2_CCIDX_MASK (UL(0xf) << ID_AA64MMFR2_CCIDX_SHIFT) 913 #define ID_AA64MMFR2_CCIDX_VAL(x) ((x) & ID_AA64MMFR2_CCIDX_MASK) 914 #define ID_AA64MMFR2_CCIDX_32 (UL(0x0) << ID_AA64MMFR2_CCIDX_SHIFT) 915 #define ID_AA64MMFR2_CCIDX_64 (UL(0x1) << ID_AA64MMFR2_CCIDX_SHIFT) 916 #define ID_AA64MMFR2_NV_SHIFT 24 917 #define ID_AA64MMFR2_NV_MASK (UL(0xf) << ID_AA64MMFR2_NV_SHIFT) 918 #define ID_AA64MMFR2_NV_VAL(x) ((x) & ID_AA64MMFR2_NV_MASK) 919 #define ID_AA64MMFR2_NV_NONE (UL(0x0) << ID_AA64MMFR2_NV_SHIFT) 920 #define ID_AA64MMFR2_NV_8_3 (UL(0x1) << ID_AA64MMFR2_NV_SHIFT) 921 #define ID_AA64MMFR2_NV_8_4 (UL(0x2) << ID_AA64MMFR2_NV_SHIFT) 922 #define ID_AA64MMFR2_ST_SHIFT 28 923 #define ID_AA64MMFR2_ST_MASK (UL(0xf) << ID_AA64MMFR2_ST_SHIFT) 924 #define ID_AA64MMFR2_ST_VAL(x) ((x) & ID_AA64MMFR2_ST_MASK) 925 #define ID_AA64MMFR2_ST_NONE (UL(0x0) << ID_AA64MMFR2_ST_SHIFT) 926 #define ID_AA64MMFR2_ST_IMPL (UL(0x1) << ID_AA64MMFR2_ST_SHIFT) 927 #define ID_AA64MMFR2_AT_SHIFT 32 928 #define ID_AA64MMFR2_AT_MASK (UL(0xf) << ID_AA64MMFR2_AT_SHIFT) 929 #define ID_AA64MMFR2_AT_VAL(x) ((x) & ID_AA64MMFR2_AT_MASK) 930 #define ID_AA64MMFR2_AT_NONE (UL(0x0) << ID_AA64MMFR2_AT_SHIFT) 931 #define ID_AA64MMFR2_AT_IMPL (UL(0x1) << ID_AA64MMFR2_AT_SHIFT) 932 #define ID_AA64MMFR2_IDS_SHIFT 36 933 #define ID_AA64MMFR2_IDS_MASK (UL(0xf) << ID_AA64MMFR2_IDS_SHIFT) 934 #define ID_AA64MMFR2_IDS_VAL(x) ((x) & ID_AA64MMFR2_IDS_MASK) 935 #define ID_AA64MMFR2_IDS_NONE (UL(0x0) << ID_AA64MMFR2_IDS_SHIFT) 936 #define ID_AA64MMFR2_IDS_IMPL (UL(0x1) << ID_AA64MMFR2_IDS_SHIFT) 937 #define ID_AA64MMFR2_FWB_SHIFT 40 938 #define ID_AA64MMFR2_FWB_MASK (UL(0xf) << ID_AA64MMFR2_FWB_SHIFT) 939 #define ID_AA64MMFR2_FWB_VAL(x) ((x) & ID_AA64MMFR2_FWB_MASK) 940 #define ID_AA64MMFR2_FWB_NONE (UL(0x0) << ID_AA64MMFR2_FWB_SHIFT) 941 #define ID_AA64MMFR2_FWB_IMPL (UL(0x1) << ID_AA64MMFR2_FWB_SHIFT) 942 #define ID_AA64MMFR2_TTL_SHIFT 48 943 #define ID_AA64MMFR2_TTL_MASK (UL(0xf) << ID_AA64MMFR2_TTL_SHIFT) 944 #define ID_AA64MMFR2_TTL_VAL(x) ((x) & ID_AA64MMFR2_TTL_MASK) 945 #define ID_AA64MMFR2_TTL_NONE (UL(0x0) << ID_AA64MMFR2_TTL_SHIFT) 946 #define ID_AA64MMFR2_TTL_IMPL (UL(0x1) << ID_AA64MMFR2_TTL_SHIFT) 947 #define ID_AA64MMFR2_BBM_SHIFT 52 948 #define ID_AA64MMFR2_BBM_MASK (UL(0xf) << ID_AA64MMFR2_BBM_SHIFT) 949 #define ID_AA64MMFR2_BBM_VAL(x) ((x) & ID_AA64MMFR2_BBM_MASK) 950 #define ID_AA64MMFR2_BBM_LEVEL0 (UL(0x0) << ID_AA64MMFR2_BBM_SHIFT) 951 #define ID_AA64MMFR2_BBM_LEVEL1 (UL(0x1) << ID_AA64MMFR2_BBM_SHIFT) 952 #define ID_AA64MMFR2_BBM_LEVEL2 (UL(0x2) << ID_AA64MMFR2_BBM_SHIFT) 953 #define ID_AA64MMFR2_EVT_SHIFT 56 954 #define ID_AA64MMFR2_EVT_MASK (UL(0xf) << ID_AA64MMFR2_EVT_SHIFT) 955 #define ID_AA64MMFR2_EVT_VAL(x) ((x) & ID_AA64MMFR2_EVT_MASK) 956 #define ID_AA64MMFR2_EVT_NONE (UL(0x0) << ID_AA64MMFR2_EVT_SHIFT) 957 #define ID_AA64MMFR2_EVT_8_2 (UL(0x1) << ID_AA64MMFR2_EVT_SHIFT) 958 #define ID_AA64MMFR2_EVT_8_5 (UL(0x2) << ID_AA64MMFR2_EVT_SHIFT) 959 #define ID_AA64MMFR2_E0PD_SHIFT 60 960 #define ID_AA64MMFR2_E0PD_MASK (UL(0xf) << ID_AA64MMFR2_E0PD_SHIFT) 961 #define ID_AA64MMFR2_E0PD_VAL(x) ((x) & ID_AA64MMFR2_E0PD_MASK) 962 #define ID_AA64MMFR2_E0PD_NONE (UL(0x0) << ID_AA64MMFR2_E0PD_SHIFT) 963 #define ID_AA64MMFR2_E0PD_IMPL (UL(0x1) << ID_AA64MMFR2_E0PD_SHIFT) 964 965 /* ID_AA64PFR0_EL1 */ 966 #define ID_AA64PFR0_EL1 MRS_REG(ID_AA64PFR0_EL1) 967 #define ID_AA64PFR0_EL1_op0 0x3 968 #define ID_AA64PFR0_EL1_op1 0x0 969 #define ID_AA64PFR0_EL1_CRn 0x0 970 #define ID_AA64PFR0_EL1_CRm 0x4 971 #define ID_AA64PFR0_EL1_op2 0x0 972 #define ID_AA64PFR0_EL0_SHIFT 0 973 #define ID_AA64PFR0_EL0_MASK (UL(0xf) << ID_AA64PFR0_EL0_SHIFT) 974 #define ID_AA64PFR0_EL0_VAL(x) ((x) & ID_AA64PFR0_EL0_MASK) 975 #define ID_AA64PFR0_EL0_64 (UL(0x1) << ID_AA64PFR0_EL0_SHIFT) 976 #define ID_AA64PFR0_EL0_64_32 (UL(0x2) << ID_AA64PFR0_EL0_SHIFT) 977 #define ID_AA64PFR0_EL1_SHIFT 4 978 #define ID_AA64PFR0_EL1_MASK (UL(0xf) << ID_AA64PFR0_EL1_SHIFT) 979 #define ID_AA64PFR0_EL1_VAL(x) ((x) & ID_AA64PFR0_EL1_MASK) 980 #define ID_AA64PFR0_EL1_64 (UL(0x1) << ID_AA64PFR0_EL1_SHIFT) 981 #define ID_AA64PFR0_EL1_64_32 (UL(0x2) << ID_AA64PFR0_EL1_SHIFT) 982 #define ID_AA64PFR0_EL2_SHIFT 8 983 #define ID_AA64PFR0_EL2_MASK (UL(0xf) << ID_AA64PFR0_EL2_SHIFT) 984 #define ID_AA64PFR0_EL2_VAL(x) ((x) & ID_AA64PFR0_EL2_MASK) 985 #define ID_AA64PFR0_EL2_NONE (UL(0x0) << ID_AA64PFR0_EL2_SHIFT) 986 #define ID_AA64PFR0_EL2_64 (UL(0x1) << ID_AA64PFR0_EL2_SHIFT) 987 #define ID_AA64PFR0_EL2_64_32 (UL(0x2) << ID_AA64PFR0_EL2_SHIFT) 988 #define ID_AA64PFR0_EL3_SHIFT 12 989 #define ID_AA64PFR0_EL3_MASK (UL(0xf) << ID_AA64PFR0_EL3_SHIFT) 990 #define ID_AA64PFR0_EL3_VAL(x) ((x) & ID_AA64PFR0_EL3_MASK) 991 #define ID_AA64PFR0_EL3_NONE (UL(0x0) << ID_AA64PFR0_EL3_SHIFT) 992 #define ID_AA64PFR0_EL3_64 (UL(0x1) << ID_AA64PFR0_EL3_SHIFT) 993 #define ID_AA64PFR0_EL3_64_32 (UL(0x2) << ID_AA64PFR0_EL3_SHIFT) 994 #define ID_AA64PFR0_FP_SHIFT 16 995 #define ID_AA64PFR0_FP_MASK (UL(0xf) << ID_AA64PFR0_FP_SHIFT) 996 #define ID_AA64PFR0_FP_VAL(x) ((x) & ID_AA64PFR0_FP_MASK) 997 #define ID_AA64PFR0_FP_IMPL (UL(0x0) << ID_AA64PFR0_FP_SHIFT) 998 #define ID_AA64PFR0_FP_HP (UL(0x1) << ID_AA64PFR0_FP_SHIFT) 999 #define ID_AA64PFR0_FP_NONE (UL(0xf) << ID_AA64PFR0_FP_SHIFT) 1000 #define ID_AA64PFR0_AdvSIMD_SHIFT 20 1001 #define ID_AA64PFR0_AdvSIMD_MASK (UL(0xf) << ID_AA64PFR0_AdvSIMD_SHIFT) 1002 #define ID_AA64PFR0_AdvSIMD_VAL(x) ((x) & ID_AA64PFR0_AdvSIMD_MASK) 1003 #define ID_AA64PFR0_AdvSIMD_IMPL (UL(0x0) << ID_AA64PFR0_AdvSIMD_SHIFT) 1004 #define ID_AA64PFR0_AdvSIMD_HP (UL(0x1) << ID_AA64PFR0_AdvSIMD_SHIFT) 1005 #define ID_AA64PFR0_AdvSIMD_NONE (UL(0xf) << ID_AA64PFR0_AdvSIMD_SHIFT) 1006 #define ID_AA64PFR0_GIC_BITS 0x4 /* Number of bits in GIC field */ 1007 #define ID_AA64PFR0_GIC_SHIFT 24 1008 #define ID_AA64PFR0_GIC_MASK (UL(0xf) << ID_AA64PFR0_GIC_SHIFT) 1009 #define ID_AA64PFR0_GIC_VAL(x) ((x) & ID_AA64PFR0_GIC_MASK) 1010 #define ID_AA64PFR0_GIC_CPUIF_NONE (UL(0x0) << ID_AA64PFR0_GIC_SHIFT) 1011 #define ID_AA64PFR0_GIC_CPUIF_EN (UL(0x1) << ID_AA64PFR0_GIC_SHIFT) 1012 #define ID_AA64PFR0_GIC_CPUIF_4_1 (UL(0x3) << ID_AA64PFR0_GIC_SHIFT) 1013 #define ID_AA64PFR0_RAS_SHIFT 28 1014 #define ID_AA64PFR0_RAS_MASK (UL(0xf) << ID_AA64PFR0_RAS_SHIFT) 1015 #define ID_AA64PFR0_RAS_VAL(x) ((x) & ID_AA64PFR0_RAS_MASK) 1016 #define ID_AA64PFR0_RAS_NONE (UL(0x0) << ID_AA64PFR0_RAS_SHIFT) 1017 #define ID_AA64PFR0_RAS_IMPL (UL(0x1) << ID_AA64PFR0_RAS_SHIFT) 1018 #define ID_AA64PFR0_RAS_8_4 (UL(0x2) << ID_AA64PFR0_RAS_SHIFT) 1019 #define ID_AA64PFR0_SVE_SHIFT 32 1020 #define ID_AA64PFR0_SVE_MASK (UL(0xf) << ID_AA64PFR0_SVE_SHIFT) 1021 #define ID_AA64PFR0_SVE_VAL(x) ((x) & ID_AA64PFR0_SVE_MASK) 1022 #define ID_AA64PFR0_SVE_NONE (UL(0x0) << ID_AA64PFR0_SVE_SHIFT) 1023 #define ID_AA64PFR0_SVE_IMPL (UL(0x1) << ID_AA64PFR0_SVE_SHIFT) 1024 #define ID_AA64PFR0_SEL2_SHIFT 36 1025 #define ID_AA64PFR0_SEL2_MASK (UL(0xf) << ID_AA64PFR0_SEL2_SHIFT) 1026 #define ID_AA64PFR0_SEL2_VAL(x) ((x) & ID_AA64PFR0_SEL2_MASK) 1027 #define ID_AA64PFR0_SEL2_NONE (UL(0x0) << ID_AA64PFR0_SEL2_SHIFT) 1028 #define ID_AA64PFR0_SEL2_IMPL (UL(0x1) << ID_AA64PFR0_SEL2_SHIFT) 1029 #define ID_AA64PFR0_MPAM_SHIFT 40 1030 #define ID_AA64PFR0_MPAM_MASK (UL(0xf) << ID_AA64PFR0_MPAM_SHIFT) 1031 #define ID_AA64PFR0_MPAM_VAL(x) ((x) & ID_AA64PFR0_MPAM_MASK) 1032 #define ID_AA64PFR0_MPAM_NONE (UL(0x0) << ID_AA64PFR0_MPAM_SHIFT) 1033 #define ID_AA64PFR0_MPAM_IMPL (UL(0x1) << ID_AA64PFR0_MPAM_SHIFT) 1034 #define ID_AA64PFR0_AMU_SHIFT 44 1035 #define ID_AA64PFR0_AMU_MASK (UL(0xf) << ID_AA64PFR0_AMU_SHIFT) 1036 #define ID_AA64PFR0_AMU_VAL(x) ((x) & ID_AA64PFR0_AMU_MASK) 1037 #define ID_AA64PFR0_AMU_NONE (UL(0x0) << ID_AA64PFR0_AMU_SHIFT) 1038 #define ID_AA64PFR0_AMU_V1 (UL(0x1) << ID_AA64PFR0_AMU_SHIFT) 1039 #define ID_AA64PFR0_DIT_SHIFT 48 1040 #define ID_AA64PFR0_DIT_MASK (UL(0xf) << ID_AA64PFR0_DIT_SHIFT) 1041 #define ID_AA64PFR0_DIT_VAL(x) ((x) & ID_AA64PFR0_DIT_MASK) 1042 #define ID_AA64PFR0_DIT_NONE (UL(0x0) << ID_AA64PFR0_DIT_SHIFT) 1043 #define ID_AA64PFR0_DIT_PSTATE (UL(0x1) << ID_AA64PFR0_DIT_SHIFT) 1044 #define ID_AA64PFR0_CSV2_SHIFT 56 1045 #define ID_AA64PFR0_CSV2_MASK (UL(0xf) << ID_AA64PFR0_CSV2_SHIFT) 1046 #define ID_AA64PFR0_CSV2_VAL(x) ((x) & ID_AA64PFR0_CSV2_MASK) 1047 #define ID_AA64PFR0_CSV2_NONE (UL(0x0) << ID_AA64PFR0_CSV2_SHIFT) 1048 #define ID_AA64PFR0_CSV2_ISOLATED (UL(0x1) << ID_AA64PFR0_CSV2_SHIFT) 1049 #define ID_AA64PFR0_CSV2_SCXTNUM (UL(0x2) << ID_AA64PFR0_CSV2_SHIFT) 1050 #define ID_AA64PFR0_CSV3_SHIFT 60 1051 #define ID_AA64PFR0_CSV3_MASK (UL(0xf) << ID_AA64PFR0_CSV3_SHIFT) 1052 #define ID_AA64PFR0_CSV3_VAL(x) ((x) & ID_AA64PFR0_CSV3_MASK) 1053 #define ID_AA64PFR0_CSV3_NONE (UL(0x0) << ID_AA64PFR0_CSV3_SHIFT) 1054 #define ID_AA64PFR0_CSV3_ISOLATED (UL(0x1) << ID_AA64PFR0_CSV3_SHIFT) 1055 1056 /* ID_AA64PFR1_EL1 */ 1057 #define ID_AA64PFR1_EL1 MRS_REG(ID_AA64PFR1_EL1) 1058 #define ID_AA64PFR1_EL1_op0 0x3 1059 #define ID_AA64PFR1_EL1_op1 0x0 1060 #define ID_AA64PFR1_EL1_CRn 0x0 1061 #define ID_AA64PFR1_EL1_CRm 0x4 1062 #define ID_AA64PFR1_EL1_op2 0x1 1063 #define ID_AA64PFR1_BT_SHIFT 0 1064 #define ID_AA64PFR1_BT_MASK (UL(0xf) << ID_AA64PFR1_BT_SHIFT) 1065 #define ID_AA64PFR1_BT_VAL(x) ((x) & ID_AA64PFR1_BT_MASK) 1066 #define ID_AA64PFR1_BT_NONE (UL(0x0) << ID_AA64PFR1_BT_SHIFT) 1067 #define ID_AA64PFR1_BT_IMPL (UL(0x1) << ID_AA64PFR1_BT_SHIFT) 1068 #define ID_AA64PFR1_SSBS_SHIFT 4 1069 #define ID_AA64PFR1_SSBS_MASK (UL(0xf) << ID_AA64PFR1_SSBS_SHIFT) 1070 #define ID_AA64PFR1_SSBS_VAL(x) ((x) & ID_AA64PFR1_SSBS_MASK) 1071 #define ID_AA64PFR1_SSBS_NONE (UL(0x0) << ID_AA64PFR1_SSBS_SHIFT) 1072 #define ID_AA64PFR1_SSBS_PSTATE (UL(0x1) << ID_AA64PFR1_SSBS_SHIFT) 1073 #define ID_AA64PFR1_SSBS_PSTATE_MSR (UL(0x2) << ID_AA64PFR1_SSBS_SHIFT) 1074 #define ID_AA64PFR1_MTE_SHIFT 8 1075 #define ID_AA64PFR1_MTE_MASK (UL(0xf) << ID_AA64PFR1_MTE_SHIFT) 1076 #define ID_AA64PFR1_MTE_VAL(x) ((x) & ID_AA64PFR1_MTE_MASK) 1077 #define ID_AA64PFR1_MTE_NONE (UL(0x0) << ID_AA64PFR1_MTE_SHIFT) 1078 #define ID_AA64PFR1_MTE_IMPL_EL0 (UL(0x1) << ID_AA64PFR1_MTE_SHIFT) 1079 #define ID_AA64PFR1_MTE_IMPL (UL(0x2) << ID_AA64PFR1_MTE_SHIFT) 1080 #define ID_AA64PFR1_RAS_frac_SHIFT 12 1081 #define ID_AA64PFR1_RAS_frac_MASK (UL(0xf) << ID_AA64PFR1_RAS_frac_SHIFT) 1082 #define ID_AA64PFR1_RAS_frac_VAL(x) ((x) & ID_AA64PFR1_RAS_frac_MASK) 1083 #define ID_AA64PFR1_RAS_frac_V1 (UL(0x0) << ID_AA64PFR1_RAS_frac_SHIFT) 1084 #define ID_AA64PFR1_RAS_frac_V2 (UL(0x1) << ID_AA64PFR1_RAS_frac_SHIFT) 1085 1086 /* ID_AA64ZFR0_EL1 */ 1087 #define ID_AA64ZFR0_EL1 MRS_REG(ID_AA64ZFR0_EL1) 1088 #define ID_AA64ZFR0_EL1_REG MRS_REG_ALT_NAME(ID_AA64ZFR0_EL1) 1089 #define ID_AA64ZFR0_EL1_op0 3 1090 #define ID_AA64ZFR0_EL1_op1 0 1091 #define ID_AA64ZFR0_EL1_CRn 0 1092 #define ID_AA64ZFR0_EL1_CRm 4 1093 #define ID_AA64ZFR0_EL1_op2 4 1094 #define ID_AA64ZFR0_SVEver_SHIFT 0 1095 #define ID_AA64ZFR0_SVEver_MASK (UL(0xf) << ID_AA64ZFR0_SVEver_SHIFT) 1096 #define ID_AA64ZFR0_SVEver_VAL(x) ((x) & ID_AA64ZFR0_SVEver_MASK 1097 #define ID_AA64ZFR0_SVEver_SVE1 (UL(0x0) << ID_AA64ZFR0_SVEver_SHIFT) 1098 #define ID_AA64ZFR0_SVEver_SVE2 (UL(0x1) << ID_AA64ZFR0_SVEver_SHIFT) 1099 #define ID_AA64ZFR0_AES_SHIFT 4 1100 #define ID_AA64ZFR0_AES_MASK (UL(0xf) << ID_AA64ZFR0_AES_SHIFT) 1101 #define ID_AA64ZFR0_AES_VAL(x) ((x) & ID_AA64ZFR0_AES_MASK 1102 #define ID_AA64ZFR0_AES_NONE (UL(0x0) << ID_AA64ZFR0_AES_SHIFT) 1103 #define ID_AA64ZFR0_AES_BASE (UL(0x1) << ID_AA64ZFR0_AES_SHIFT) 1104 #define ID_AA64ZFR0_AES_PMULL (UL(0x2) << ID_AA64ZFR0_AES_SHIFT) 1105 #define ID_AA64ZFR0_BitPerm_SHIFT 16 1106 #define ID_AA64ZFR0_BitPerm_MASK (UL(0xf) << ID_AA64ZFR0_BitPerm_SHIFT) 1107 #define ID_AA64ZFR0_BitPerm_VAL(x) ((x) & ID_AA64ZFR0_BitPerm_MASK 1108 #define ID_AA64ZFR0_BitPerm_NONE (UL(0x0) << ID_AA64ZFR0_BitPerm_SHIFT) 1109 #define ID_AA64ZFR0_BitPerm_IMPL (UL(0x1) << ID_AA64ZFR0_BitPerm_SHIFT) 1110 #define ID_AA64ZFR0_BF16_SHIFT 20 1111 #define ID_AA64ZFR0_BF16_MASK (UL(0xf) << ID_AA64ZFR0_BF16_SHIFT) 1112 #define ID_AA64ZFR0_BF16_VAL(x) ((x) & ID_AA64ZFR0_BF16_MASK 1113 #define ID_AA64ZFR0_BF16_NONE (UL(0x0) << ID_AA64ZFR0_BF16_SHIFT) 1114 #define ID_AA64ZFR0_BF16_BASE (UL(0x1) << ID_AA64ZFR0_BF16_SHIFT) 1115 #define ID_AA64ZFR0_BF16_EBF (UL(0x1) << ID_AA64ZFR0_BF16_SHIFT) 1116 #define ID_AA64ZFR0_SHA3_SHIFT 32 1117 #define ID_AA64ZFR0_SHA3_MASK (UL(0xf) << ID_AA64ZFR0_SHA3_SHIFT) 1118 #define ID_AA64ZFR0_SHA3_VAL(x) ((x) & ID_AA64ZFR0_SHA3_MASK 1119 #define ID_AA64ZFR0_SHA3_NONE (UL(0x0) << ID_AA64ZFR0_SHA3_SHIFT) 1120 #define ID_AA64ZFR0_SHA3_IMPL (UL(0x1) << ID_AA64ZFR0_SHA3_SHIFT) 1121 #define ID_AA64ZFR0_SM4_SHIFT 40 1122 #define ID_AA64ZFR0_SM4_MASK (UL(0xf) << ID_AA64ZFR0_SM4_SHIFT) 1123 #define ID_AA64ZFR0_SM4_VAL(x) ((x) & ID_AA64ZFR0_SM4_MASK 1124 #define ID_AA64ZFR0_SM4_NONE (UL(0x0) << ID_AA64ZFR0_SM4_SHIFT) 1125 #define ID_AA64ZFR0_SM4_IMPL (UL(0x1) << ID_AA64ZFR0_SM4_SHIFT) 1126 #define ID_AA64ZFR0_I8MM_SHIFT 44 1127 #define ID_AA64ZFR0_I8MM_MASK (UL(0xf) << ID_AA64ZFR0_I8MM_SHIFT) 1128 #define ID_AA64ZFR0_I8MM_VAL(x) ((x) & ID_AA64ZFR0_I8MM_MASK 1129 #define ID_AA64ZFR0_I8MM_NONE (UL(0x0) << ID_AA64ZFR0_I8MM_SHIFT) 1130 #define ID_AA64ZFR0_I8MM_IMPL (UL(0x1) << ID_AA64ZFR0_I8MM_SHIFT) 1131 #define ID_AA64ZFR0_F32MM_SHIFT 52 1132 #define ID_AA64ZFR0_F32MM_MASK (UL(0xf) << ID_AA64ZFR0_F32MM_SHIFT) 1133 #define ID_AA64ZFR0_F32MM_VAL(x) ((x) & ID_AA64ZFR0_F32MM_MASK 1134 #define ID_AA64ZFR0_F32MM_NONE (UL(0x0) << ID_AA64ZFR0_F32MM_SHIFT) 1135 #define ID_AA64ZFR0_F32MM_IMPL (UL(0x1) << ID_AA64ZFR0_F32MM_SHIFT) 1136 #define ID_AA64ZFR0_F64MM_SHIFT 56 1137 #define ID_AA64ZFR0_F64MM_MASK (UL(0xf) << ID_AA64ZFR0_F64MM_SHIFT) 1138 #define ID_AA64ZFR0_F64MM_VAL(x) ((x) & ID_AA64ZFR0_F64MM_MASK 1139 #define ID_AA64ZFR0_F64MM_NONE (UL(0x0) << ID_AA64ZFR0_F64MM_SHIFT) 1140 #define ID_AA64ZFR0_F64MM_IMPL (UL(0x1) << ID_AA64ZFR0_F64MM_SHIFT) 1141 1142 /* ID_ISAR5_EL1 */ 1143 #define ID_ISAR5_EL1 MRS_REG(ID_ISAR5_EL1) 1144 #define ID_ISAR5_EL1_op0 0x3 1145 #define ID_ISAR5_EL1_op1 0x0 1146 #define ID_ISAR5_EL1_CRn 0x0 1147 #define ID_ISAR5_EL1_CRm 0x2 1148 #define ID_ISAR5_EL1_op2 0x5 1149 #define ID_ISAR5_SEVL_SHIFT 0 1150 #define ID_ISAR5_SEVL_MASK (UL(0xf) << ID_ISAR5_SEVL_SHIFT) 1151 #define ID_ISAR5_SEVL_VAL(x) ((x) & ID_ISAR5_SEVL_MASK) 1152 #define ID_ISAR5_SEVL_NOP (UL(0x0) << ID_ISAR5_SEVL_SHIFT) 1153 #define ID_ISAR5_SEVL_IMPL (UL(0x1) << ID_ISAR5_SEVL_SHIFT) 1154 #define ID_ISAR5_AES_SHIFT 4 1155 #define ID_ISAR5_AES_MASK (UL(0xf) << ID_ISAR5_AES_SHIFT) 1156 #define ID_ISAR5_AES_VAL(x) ((x) & ID_ISAR5_AES_MASK) 1157 #define ID_ISAR5_AES_NONE (UL(0x0) << ID_ISAR5_AES_SHIFT) 1158 #define ID_ISAR5_AES_BASE (UL(0x1) << ID_ISAR5_AES_SHIFT) 1159 #define ID_ISAR5_AES_VMULL (UL(0x2) << ID_ISAR5_AES_SHIFT) 1160 #define ID_ISAR5_SHA1_SHIFT 8 1161 #define ID_ISAR5_SHA1_MASK (UL(0xf) << ID_ISAR5_SHA1_SHIFT) 1162 #define ID_ISAR5_SHA1_VAL(x) ((x) & ID_ISAR5_SHA1_MASK) 1163 #define ID_ISAR5_SHA1_NONE (UL(0x0) << ID_ISAR5_SHA1_SHIFT) 1164 #define ID_ISAR5_SHA1_IMPL (UL(0x1) << ID_ISAR5_SHA1_SHIFT) 1165 #define ID_ISAR5_SHA2_SHIFT 12 1166 #define ID_ISAR5_SHA2_MASK (UL(0xf) << ID_ISAR5_SHA2_SHIFT) 1167 #define ID_ISAR5_SHA2_VAL(x) ((x) & ID_ISAR5_SHA2_MASK) 1168 #define ID_ISAR5_SHA2_NONE (UL(0x0) << ID_ISAR5_SHA2_SHIFT) 1169 #define ID_ISAR5_SHA2_IMPL (UL(0x1) << ID_ISAR5_SHA2_SHIFT) 1170 #define ID_ISAR5_CRC32_SHIFT 16 1171 #define ID_ISAR5_CRC32_MASK (UL(0xf) << ID_ISAR5_CRC32_SHIFT) 1172 #define ID_ISAR5_CRC32_VAL(x) ((x) & ID_ISAR5_CRC32_MASK) 1173 #define ID_ISAR5_CRC32_NONE (UL(0x0) << ID_ISAR5_CRC32_SHIFT) 1174 #define ID_ISAR5_CRC32_IMPL (UL(0x1) << ID_ISAR5_CRC32_SHIFT) 1175 #define ID_ISAR5_RDM_SHIFT 24 1176 #define ID_ISAR5_RDM_MASK (UL(0xf) << ID_ISAR5_RDM_SHIFT) 1177 #define ID_ISAR5_RDM_VAL(x) ((x) & ID_ISAR5_RDM_MASK) 1178 #define ID_ISAR5_RDM_NONE (UL(0x0) << ID_ISAR5_RDM_SHIFT) 1179 #define ID_ISAR5_RDM_IMPL (UL(0x1) << ID_ISAR5_RDM_SHIFT) 1180 #define ID_ISAR5_VCMA_SHIFT 28 1181 #define ID_ISAR5_VCMA_MASK (UL(0xf) << ID_ISAR5_VCMA_SHIFT) 1182 #define ID_ISAR5_VCMA_VAL(x) ((x) & ID_ISAR5_VCMA_MASK) 1183 #define ID_ISAR5_VCMA_NONE (UL(0x0) << ID_ISAR5_VCMA_SHIFT) 1184 #define ID_ISAR5_VCMA_IMPL (UL(0x1) << ID_ISAR5_VCMA_SHIFT) 1185 1186 /* MAIR_EL1 - Memory Attribute Indirection Register */ 1187 #define MAIR_ATTR_MASK(idx) (UL(0xff) << ((n)* 8)) 1188 #define MAIR_ATTR(attr, idx) ((attr) << ((idx) * 8)) 1189 #define MAIR_DEVICE_nGnRnE UL(0x00) 1190 #define MAIR_DEVICE_nGnRE UL(0x04) 1191 #define MAIR_NORMAL_NC UL(0x44) 1192 #define MAIR_NORMAL_WT UL(0xbb) 1193 #define MAIR_NORMAL_WB UL(0xff) 1194 1195 /* MDCCINT_EL1 */ 1196 #define MDCCINT_EL1 MRS_REG(MDCCINT_EL1) 1197 #define MDCCINT_EL1_op0 2 1198 #define MDCCINT_EL1_op1 0 1199 #define MDCCINT_EL1_CRn 0 1200 #define MDCCINT_EL1_CRm 2 1201 #define MDCCINT_EL1_op2 0 1202 1203 /* MDCCSR_EL0 */ 1204 #define MDCCSR_EL0 MRS_REG(MDCCSR_EL0) 1205 #define MDCCSR_EL0_op0 2 1206 #define MDCCSR_EL0_op1 3 1207 #define MDCCSR_EL0_CRn 0 1208 #define MDCCSR_EL0_CRm 1 1209 #define MDCCSR_EL0_op2 0 1210 1211 /* MDSCR_EL1 - Monitor Debug System Control Register */ 1212 #define MDSCR_EL1 MRS_REG(MDSCR_EL1) 1213 #define MDSCR_EL1_op0 2 1214 #define MDSCR_EL1_op1 0 1215 #define MDSCR_EL1_CRn 0 1216 #define MDSCR_EL1_CRm 2 1217 #define MDSCR_EL1_op2 2 1218 #define MDSCR_SS_SHIFT 0 1219 #define MDSCR_SS (UL(0x1) << MDSCR_SS_SHIFT) 1220 #define MDSCR_KDE_SHIFT 13 1221 #define MDSCR_KDE (UL(0x1) << MDSCR_KDE_SHIFT) 1222 #define MDSCR_MDE_SHIFT 15 1223 #define MDSCR_MDE (UL(0x1) << MDSCR_MDE_SHIFT) 1224 1225 /* MPIDR_EL1 - Multiprocessor Affinity Register */ 1226 #define MPIDR_EL1 MRS_REG(MPIDR_EL1) 1227 #define MPIDR_EL1_op0 3 1228 #define MPIDR_EL1_op1 0 1229 #define MPIDR_EL1_CRn 0 1230 #define MPIDR_EL1_CRm 0 1231 #define MPIDR_EL1_op2 5 1232 #define MPIDR_AFF0_SHIFT 0 1233 #define MPIDR_AFF0_MASK (UL(0xff) << MPIDR_AFF0_SHIFT) 1234 #define MPIDR_AFF0_VAL(x) ((x) & MPIDR_AFF0_MASK) 1235 #define MPIDR_AFF1_SHIFT 8 1236 #define MPIDR_AFF1_MASK (UL(0xff) << MPIDR_AFF1_SHIFT) 1237 #define MPIDR_AFF1_VAL(x) ((x) & MPIDR_AFF1_MASK) 1238 #define MPIDR_AFF2_SHIFT 16 1239 #define MPIDR_AFF2_MASK (UL(0xff) << MPIDR_AFF2_SHIFT) 1240 #define MPIDR_AFF2_VAL(x) ((x) & MPIDR_AFF2_MASK) 1241 #define MPIDR_MT_SHIFT 24 1242 #define MPIDR_MT_MASK (UL(0x1) << MPIDR_MT_SHIFT) 1243 #define MPIDR_U_SHIFT 30 1244 #define MPIDR_U_MASK (UL(0x1) << MPIDR_U_SHIFT) 1245 #define MPIDR_AFF3_SHIFT 32 1246 #define MPIDR_AFF3_MASK (UL(0xff) << MPIDR_AFF3_SHIFT) 1247 #define MPIDR_AFF3_VAL(x) ((x) & MPIDR_AFF3_MASK) 1248 1249 /* MVFR0_EL1 */ 1250 #define MVFR0_EL1 MRS_REG(MVFR0_EL1) 1251 #define MVFR0_EL1_op0 0x3 1252 #define MVFR0_EL1_op1 0x0 1253 #define MVFR0_EL1_CRn 0x0 1254 #define MVFR0_EL1_CRm 0x3 1255 #define MVFR0_EL1_op2 0x0 1256 #define MVFR0_SIMDReg_SHIFT 0 1257 #define MVFR0_SIMDReg_MASK (UL(0xf) << MVFR0_SIMDReg_SHIFT) 1258 #define MVFR0_SIMDReg_VAL(x) ((x) & MVFR0_SIMDReg_MASK) 1259 #define MVFR0_SIMDReg_NONE (UL(0x0) << MVFR0_SIMDReg_SHIFT) 1260 #define MVFR0_SIMDReg_FP (UL(0x1) << MVFR0_SIMDReg_SHIFT) 1261 #define MVFR0_SIMDReg_AdvSIMD (UL(0x2) << MVFR0_SIMDReg_SHIFT) 1262 #define MVFR0_FPSP_SHIFT 4 1263 #define MVFR0_FPSP_MASK (UL(0xf) << MVFR0_FPSP_SHIFT) 1264 #define MVFR0_FPSP_VAL(x) ((x) & MVFR0_FPSP_MASK) 1265 #define MVFR0_FPSP_NONE (UL(0x0) << MVFR0_FPSP_SHIFT) 1266 #define MVFR0_FPSP_VFP_v2 (UL(0x1) << MVFR0_FPSP_SHIFT) 1267 #define MVFR0_FPSP_VFP_v3_v4 (UL(0x2) << MVFR0_FPSP_SHIFT) 1268 #define MVFR0_FPDP_SHIFT 8 1269 #define MVFR0_FPDP_MASK (UL(0xf) << MVFR0_FPDP_SHIFT) 1270 #define MVFR0_FPDP_VAL(x) ((x) & MVFR0_FPDP_MASK) 1271 #define MVFR0_FPDP_NONE (UL(0x0) << MVFR0_FPDP_SHIFT) 1272 #define MVFR0_FPDP_VFP_v2 (UL(0x1) << MVFR0_FPDP_SHIFT) 1273 #define MVFR0_FPDP_VFP_v3_v4 (UL(0x2) << MVFR0_FPDP_SHIFT) 1274 #define MVFR0_FPTrap_SHIFT 12 1275 #define MVFR0_FPTrap_MASK (UL(0xf) << MVFR0_FPTrap_SHIFT) 1276 #define MVFR0_FPTrap_VAL(x) ((x) & MVFR0_FPTrap_MASK) 1277 #define MVFR0_FPTrap_NONE (UL(0x0) << MVFR0_FPTrap_SHIFT) 1278 #define MVFR0_FPTrap_IMPL (UL(0x1) << MVFR0_FPTrap_SHIFT) 1279 #define MVFR0_FPDivide_SHIFT 16 1280 #define MVFR0_FPDivide_MASK (UL(0xf) << MVFR0_FPDivide_SHIFT) 1281 #define MVFR0_FPDivide_VAL(x) ((x) & MVFR0_FPDivide_MASK) 1282 #define MVFR0_FPDivide_NONE (UL(0x0) << MVFR0_FPDivide_SHIFT) 1283 #define MVFR0_FPDivide_IMPL (UL(0x1) << MVFR0_FPDivide_SHIFT) 1284 #define MVFR0_FPSqrt_SHIFT 20 1285 #define MVFR0_FPSqrt_MASK (UL(0xf) << MVFR0_FPSqrt_SHIFT) 1286 #define MVFR0_FPSqrt_VAL(x) ((x) & MVFR0_FPSqrt_MASK) 1287 #define MVFR0_FPSqrt_NONE (UL(0x0) << MVFR0_FPSqrt_SHIFT) 1288 #define MVFR0_FPSqrt_IMPL (UL(0x1) << MVFR0_FPSqrt_SHIFT) 1289 #define MVFR0_FPShVec_SHIFT 24 1290 #define MVFR0_FPShVec_MASK (UL(0xf) << MVFR0_FPShVec_SHIFT) 1291 #define MVFR0_FPShVec_VAL(x) ((x) & MVFR0_FPShVec_MASK) 1292 #define MVFR0_FPShVec_NONE (UL(0x0) << MVFR0_FPShVec_SHIFT) 1293 #define MVFR0_FPShVec_IMPL (UL(0x1) << MVFR0_FPShVec_SHIFT) 1294 #define MVFR0_FPRound_SHIFT 28 1295 #define MVFR0_FPRound_MASK (UL(0xf) << MVFR0_FPRound_SHIFT) 1296 #define MVFR0_FPRound_VAL(x) ((x) & MVFR0_FPRound_MASK) 1297 #define MVFR0_FPRound_NONE (UL(0x0) << MVFR0_FPRound_SHIFT) 1298 #define MVFR0_FPRound_IMPL (UL(0x1) << MVFR0_FPRound_SHIFT) 1299 1300 /* MVFR1_EL1 */ 1301 #define MVFR1_EL1 MRS_REG(MVFR1_EL1) 1302 #define MVFR1_EL1_op0 0x3 1303 #define MVFR1_EL1_op1 0x0 1304 #define MVFR1_EL1_CRn 0x0 1305 #define MVFR1_EL1_CRm 0x3 1306 #define MVFR1_EL1_op2 0x1 1307 #define MVFR1_FPFtZ_SHIFT 0 1308 #define MVFR1_FPFtZ_MASK (UL(0xf) << MVFR1_FPFtZ_SHIFT) 1309 #define MVFR1_FPFtZ_VAL(x) ((x) & MVFR1_FPFtZ_MASK) 1310 #define MVFR1_FPFtZ_NONE (UL(0x0) << MVFR1_FPFtZ_SHIFT) 1311 #define MVFR1_FPFtZ_IMPL (UL(0x1) << MVFR1_FPFtZ_SHIFT) 1312 #define MVFR1_FPDNaN_SHIFT 4 1313 #define MVFR1_FPDNaN_MASK (UL(0xf) << MVFR1_FPDNaN_SHIFT) 1314 #define MVFR1_FPDNaN_VAL(x) ((x) & MVFR1_FPDNaN_MASK) 1315 #define MVFR1_FPDNaN_NONE (UL(0x0) << MVFR1_FPDNaN_SHIFT) 1316 #define MVFR1_FPDNaN_IMPL (UL(0x1) << MVFR1_FPDNaN_SHIFT) 1317 #define MVFR1_SIMDLS_SHIFT 8 1318 #define MVFR1_SIMDLS_MASK (UL(0xf) << MVFR1_SIMDLS_SHIFT) 1319 #define MVFR1_SIMDLS_VAL(x) ((x) & MVFR1_SIMDLS_MASK) 1320 #define MVFR1_SIMDLS_NONE (UL(0x0) << MVFR1_SIMDLS_SHIFT) 1321 #define MVFR1_SIMDLS_IMPL (UL(0x1) << MVFR1_SIMDLS_SHIFT) 1322 #define MVFR1_SIMDInt_SHIFT 12 1323 #define MVFR1_SIMDInt_MASK (UL(0xf) << MVFR1_SIMDInt_SHIFT) 1324 #define MVFR1_SIMDInt_VAL(x) ((x) & MVFR1_SIMDInt_MASK) 1325 #define MVFR1_SIMDInt_NONE (UL(0x0) << MVFR1_SIMDInt_SHIFT) 1326 #define MVFR1_SIMDInt_IMPL (UL(0x1) << MVFR1_SIMDInt_SHIFT) 1327 #define MVFR1_SIMDSP_SHIFT 16 1328 #define MVFR1_SIMDSP_MASK (UL(0xf) << MVFR1_SIMDSP_SHIFT) 1329 #define MVFR1_SIMDSP_VAL(x) ((x) & MVFR1_SIMDSP_MASK) 1330 #define MVFR1_SIMDSP_NONE (UL(0x0) << MVFR1_SIMDSP_SHIFT) 1331 #define MVFR1_SIMDSP_IMPL (UL(0x1) << MVFR1_SIMDSP_SHIFT) 1332 #define MVFR1_SIMDHP_SHIFT 20 1333 #define MVFR1_SIMDHP_MASK (UL(0xf) << MVFR1_SIMDHP_SHIFT) 1334 #define MVFR1_SIMDHP_VAL(x) ((x) & MVFR1_SIMDHP_MASK) 1335 #define MVFR1_SIMDHP_NONE (UL(0x0) << MVFR1_SIMDHP_SHIFT) 1336 #define MVFR1_SIMDHP_CONV_SP (UL(0x1) << MVFR1_SIMDHP_SHIFT) 1337 #define MVFR1_SIMDHP_ARITH (UL(0x2) << MVFR1_SIMDHP_SHIFT) 1338 #define MVFR1_FPHP_SHIFT 24 1339 #define MVFR1_FPHP_MASK (UL(0xf) << MVFR1_FPHP_SHIFT) 1340 #define MVFR1_FPHP_VAL(x) ((x) & MVFR1_FPHP_MASK) 1341 #define MVFR1_FPHP_NONE (UL(0x0) << MVFR1_FPHP_SHIFT) 1342 #define MVFR1_FPHP_CONV_SP (UL(0x1) << MVFR1_FPHP_SHIFT) 1343 #define MVFR1_FPHP_CONV_DP (UL(0x2) << MVFR1_FPHP_SHIFT) 1344 #define MVFR1_FPHP_ARITH (UL(0x3) << MVFR1_FPHP_SHIFT) 1345 #define MVFR1_SIMDFMAC_SHIFT 28 1346 #define MVFR1_SIMDFMAC_MASK (UL(0xf) << MVFR1_SIMDFMAC_SHIFT) 1347 #define MVFR1_SIMDFMAC_VAL(x) ((x) & MVFR1_SIMDFMAC_MASK) 1348 #define MVFR1_SIMDFMAC_NONE (UL(0x0) << MVFR1_SIMDFMAC_SHIFT) 1349 #define MVFR1_SIMDFMAC_IMPL (UL(0x1) << MVFR1_SIMDFMAC_SHIFT) 1350 1351 /* OSDLR_EL1 */ 1352 #define OSDLR_EL1 MRS_REG(OSDLR_EL1) 1353 #define OSDLR_EL1_op0 2 1354 #define OSDLR_EL1_op1 0 1355 #define OSDLR_EL1_CRn 1 1356 #define OSDLR_EL1_CRm 3 1357 #define OSDLR_EL1_op2 4 1358 1359 /* OSLAR_EL1 */ 1360 #define OSLAR_EL1 MRS_REG(OSLAR_EL1) 1361 #define OSLAR_EL1_op0 2 1362 #define OSLAR_EL1_op1 0 1363 #define OSLAR_EL1_CRn 1 1364 #define OSLAR_EL1_CRm 0 1365 #define OSLAR_EL1_op2 4 1366 1367 /* OSLSR_EL1 */ 1368 #define OSLSR_EL1 MRS_REG(OSLSR_EL1) 1369 #define OSLSR_EL1_op0 2 1370 #define OSLSR_EL1_op1 0 1371 #define OSLSR_EL1_CRn 1 1372 #define OSLSR_EL1_CRm 1 1373 #define OSLSR_EL1_op2 4 1374 1375 /* PAR_EL1 - Physical Address Register */ 1376 #define PAR_F_SHIFT 0 1377 #define PAR_F (0x1 << PAR_F_SHIFT) 1378 #define PAR_SUCCESS(x) (((x) & PAR_F) == 0) 1379 /* When PAR_F == 0 (success) */ 1380 #define PAR_LOW_MASK 0xfff 1381 #define PAR_SH_SHIFT 7 1382 #define PAR_SH_MASK (0x3 << PAR_SH_SHIFT) 1383 #define PAR_NS_SHIFT 9 1384 #define PAR_NS_MASK (0x3 << PAR_NS_SHIFT) 1385 #define PAR_PA_SHIFT 12 1386 #define PAR_PA_MASK 0x0000fffffffff000 1387 #define PAR_ATTR_SHIFT 56 1388 #define PAR_ATTR_MASK (0xff << PAR_ATTR_SHIFT) 1389 /* When PAR_F == 1 (aborted) */ 1390 #define PAR_FST_SHIFT 1 1391 #define PAR_FST_MASK (0x3f << PAR_FST_SHIFT) 1392 #define PAR_PTW_SHIFT 8 1393 #define PAR_PTW_MASK (0x1 << PAR_PTW_SHIFT) 1394 #define PAR_S_SHIFT 9 1395 #define PAR_S_MASK (0x1 << PAR_S_SHIFT) 1396 1397 /* PMBIDR_EL1 */ 1398 #define PMBIDR_EL1 MRS_REG(PMBIDR_EL1) 1399 #define PMBIDR_EL1_op0 0x3 1400 #define PMBIDR_EL1_op1 0x0 1401 #define PMBIDR_EL1_CRn 0x9 1402 #define PMBIDR_EL1_CRm 0xa 1403 #define PMBIDR_EL1_op2 0x7 1404 #define PMBIDR_Align_SHIFT 0 1405 #define PMBIDR_Align_MASK (UL(0xf) << PMBIDR_Align_SHIFT) 1406 #define PMBIDR_P_SHIFT 4 1407 #define PMBIDR_P (UL(0x1) << PMBIDR_P_SHIFT) 1408 #define PMBIDR_F_SHIFT 5 1409 #define PMBIDR_F (UL(0x1) << PMBIDR_F_SHIFT) 1410 1411 /* PMBLIMITR_EL1 */ 1412 #define PMBLIMITR_EL1 MRS_REG(PMBLIMITR_EL1) 1413 #define PMBLIMITR_EL1_op0 0x3 1414 #define PMBLIMITR_EL1_op1 0x0 1415 #define PMBLIMITR_EL1_CRn 0x9 1416 #define PMBLIMITR_EL1_CRm 0xa 1417 #define PMBLIMITR_EL1_op2 0x0 1418 #define PMBLIMITR_E_SHIFT 0 1419 #define PMBLIMITR_E (UL(0x1) << PMBLIMITR_E_SHIFT) 1420 #define PMBLIMITR_FM_SHIFT 1 1421 #define PMBLIMITR_FM_MASK (UL(0x3) << PMBLIMITR_FM_SHIFT) 1422 #define PMBLIMITR_PMFZ_SHIFT 5 1423 #define PMBLIMITR_PMFZ (UL(0x1) << PMBLIMITR_PMFZ_SHIFT) 1424 #define PMBLIMITR_LIMIT_SHIFT 12 1425 #define PMBLIMITR_LIMIT_MASK \ 1426 (UL(0xfffffffffffff) << PMBLIMITR_LIMIT_SHIFT) 1427 1428 /* PMBPTR_EL1 */ 1429 #define PMBPTR_EL1 MRS_REG(PMBPTR_EL1) 1430 #define PMBPTR_EL1_op0 0x3 1431 #define PMBPTR_EL1_op1 0x0 1432 #define PMBPTR_EL1_CRn 0x9 1433 #define PMBPTR_EL1_CRm 0xa 1434 #define PMBPTR_EL1_op2 0x1 1435 #define PMBPTR_PTR_SHIFT 0 1436 #define PMBPTR_PTR_MASK \ 1437 (UL(0xffffffffffffffff) << PMBPTR_PTR_SHIFT) 1438 1439 /* PMBSR_EL1 */ 1440 #define PMBSR_EL1 MRS_REG(PMBSR_EL1) 1441 #define PMBSR_EL1_op0 0x3 1442 #define PMBSR_EL1_op1 0x0 1443 #define PMBSR_EL1_CRn 0x9 1444 #define PMBSR_EL1_CRm 0xa 1445 #define PMBSR_EL1_op2 0x3 1446 #define PMBSR_MSS_SHIFT 0 1447 #define PMBSR_MSS_MASK (UL(0xffff) << PMBSR_MSS_SHIFT) 1448 #define PMBSR_COLL_SHIFT 16 1449 #define PMBSR_COLL (UL(0x1) << PMBSR_COLL_SHIFT) 1450 #define PMBSR_S_SHIFT 17 1451 #define PMBSR_S (UL(0x1) << PMBSR_S_SHIFT) 1452 #define PMBSR_EA_SHIFT 18 1453 #define PMBSR_EA (UL(0x1) << PMBSR_EA_SHIFT) 1454 #define PMBSR_DL_SHIFT 19 1455 #define PMBSR_DL (UL(0x1) << PMBSR_DL_SHIFT) 1456 #define PMBSR_EC_SHIFT 26 1457 #define PMBSR_EC_MASK (UL(0x3f) << PMBSR_EC_SHIFT) 1458 1459 /* PMCCFILTR_EL0 */ 1460 #define PMCCFILTR_EL0 MRS_REG(PMCCFILTR_EL0) 1461 #define PMCCFILTR_EL0_op0 3 1462 #define PMCCFILTR_EL0_op1 3 1463 #define PMCCFILTR_EL0_CRn 14 1464 #define PMCCFILTR_EL0_CRm 15 1465 #define PMCCFILTR_EL0_op2 7 1466 1467 /* PMCCNTR_EL0 */ 1468 #define PMCCNTR_EL0 MRS_REG(PMCCNTR_EL0) 1469 #define PMCCNTR_EL0_op0 3 1470 #define PMCCNTR_EL0_op1 3 1471 #define PMCCNTR_EL0_CRn 9 1472 #define PMCCNTR_EL0_CRm 13 1473 #define PMCCNTR_EL0_op2 0 1474 1475 /* PMCEID0_EL0 */ 1476 #define PMCEID0_EL0 MRS_REG(PMCEID0_EL0) 1477 #define PMCEID0_EL0_op0 3 1478 #define PMCEID0_EL0_op1 3 1479 #define PMCEID0_EL0_CRn 9 1480 #define PMCEID0_EL0_CRm 12 1481 #define PMCEID0_EL0_op2 6 1482 1483 /* PMCEID1_EL0 */ 1484 #define PMCEID1_EL0 MRS_REG(PMCEID1_EL0) 1485 #define PMCEID1_EL0_op0 3 1486 #define PMCEID1_EL0_op1 3 1487 #define PMCEID1_EL0_CRn 9 1488 #define PMCEID1_EL0_CRm 12 1489 #define PMCEID1_EL0_op2 7 1490 1491 /* PMCNTENCLR_EL0 */ 1492 #define PMCNTENCLR_EL0 MRS_REG(PMCNTENCLR_EL0) 1493 #define PMCNTENCLR_EL0_op0 3 1494 #define PMCNTENCLR_EL0_op1 3 1495 #define PMCNTENCLR_EL0_CRn 9 1496 #define PMCNTENCLR_EL0_CRm 12 1497 #define PMCNTENCLR_EL0_op2 2 1498 1499 /* PMCNTENSET_EL0 */ 1500 #define PMCNTENSET_EL0 MRS_REG(PMCNTENSET_EL0) 1501 #define PMCNTENSET_EL0_op0 3 1502 #define PMCNTENSET_EL0_op1 3 1503 #define PMCNTENSET_EL0_CRn 9 1504 #define PMCNTENSET_EL0_CRm 12 1505 #define PMCNTENSET_EL0_op2 1 1506 1507 /* PMCR_EL0 - Perfomance Monitoring Counters */ 1508 #define PMCR_EL0 MRS_REG(PMCR_EL0) 1509 #define PMCR_EL0_op0 3 1510 #define PMCR_EL0_op1 3 1511 #define PMCR_EL0_CRn 9 1512 #define PMCR_EL0_CRm 12 1513 #define PMCR_EL0_op2 0 1514 #define PMCR_E (1 << 0) /* Enable all counters */ 1515 #define PMCR_P (1 << 1) /* Reset all counters */ 1516 #define PMCR_C (1 << 2) /* Clock counter reset */ 1517 #define PMCR_D (1 << 3) /* CNTR counts every 64 clk cycles */ 1518 #define PMCR_X (1 << 4) /* Export to ext. monitoring (ETM) */ 1519 #define PMCR_DP (1 << 5) /* Disable CCNT if non-invasive debug*/ 1520 #define PMCR_LC (1 << 6) /* Long cycle count enable */ 1521 #define PMCR_IMP_SHIFT 24 /* Implementer code */ 1522 #define PMCR_IMP_MASK (0xff << PMCR_IMP_SHIFT) 1523 #define PMCR_IMP_ARM 0x41 1524 #define PMCR_IDCODE_SHIFT 16 /* Identification code */ 1525 #define PMCR_IDCODE_MASK (0xff << PMCR_IDCODE_SHIFT) 1526 #define PMCR_IDCODE_CORTEX_A57 0x01 1527 #define PMCR_IDCODE_CORTEX_A72 0x02 1528 #define PMCR_IDCODE_CORTEX_A53 0x03 1529 #define PMCR_IDCODE_CORTEX_A73 0x04 1530 #define PMCR_IDCODE_CORTEX_A35 0x0a 1531 #define PMCR_IDCODE_CORTEX_A76 0x0b 1532 #define PMCR_IDCODE_NEOVERSE_N1 0x0c 1533 #define PMCR_IDCODE_CORTEX_A77 0x10 1534 #define PMCR_IDCODE_CORTEX_A55 0x45 1535 #define PMCR_IDCODE_NEOVERSE_E1 0x46 1536 #define PMCR_IDCODE_CORTEX_A75 0x4a 1537 #define PMCR_N_SHIFT 11 /* Number of counters implemented */ 1538 #define PMCR_N_MASK (0x1f << PMCR_N_SHIFT) 1539 1540 /* PMEVCNTR<n>_EL0 */ 1541 #define PMEVCNTR_EL0_op0 3 1542 #define PMEVCNTR_EL0_op1 3 1543 #define PMEVCNTR_EL0_CRn 14 1544 #define PMEVCNTR_EL0_CRm 8 1545 /* 1546 * PMEVCNTRn_EL0_CRm[1:0] holds the upper 2 bits of 'n' 1547 * PMEVCNTRn_EL0_op2 holds the lower 3 bits of 'n' 1548 */ 1549 1550 /* PMEVTYPER<n>_EL0 - Performance Monitoring Event Type */ 1551 #define PMEVTYPER_EL0_op0 3 1552 #define PMEVTYPER_EL0_op1 3 1553 #define PMEVTYPER_EL0_CRn 14 1554 #define PMEVTYPER_EL0_CRm 12 1555 /* 1556 * PMEVTYPERn_EL0_CRm[1:0] holds the upper 2 bits of 'n' 1557 * PMEVTYPERn_EL0_op2 holds the lower 3 bits of 'n' 1558 */ 1559 #define PMEVTYPER_EVTCOUNT_MASK 0x000003ff /* ARMv8.0 */ 1560 #define PMEVTYPER_EVTCOUNT_8_1_MASK 0x0000ffff /* ARMv8.1+ */ 1561 #define PMEVTYPER_MT (1 << 25) /* Multithreading */ 1562 #define PMEVTYPER_M (1 << 26) /* Secure EL3 filtering */ 1563 #define PMEVTYPER_NSH (1 << 27) /* Non-secure hypervisor filtering */ 1564 #define PMEVTYPER_NSU (1 << 28) /* Non-secure user filtering */ 1565 #define PMEVTYPER_NSK (1 << 29) /* Non-secure kernel filtering */ 1566 #define PMEVTYPER_U (1 << 30) /* User filtering */ 1567 #define PMEVTYPER_P (1 << 31) /* Privileged filtering */ 1568 1569 /* PMINTENCLR_EL1 */ 1570 #define PMINTENCLR_EL1 MRS_REG(PMINTENCLR_EL1) 1571 #define PMINTENCLR_EL1_op0 3 1572 #define PMINTENCLR_EL1_op1 0 1573 #define PMINTENCLR_EL1_CRn 9 1574 #define PMINTENCLR_EL1_CRm 14 1575 #define PMINTENCLR_EL1_op2 2 1576 1577 /* PMINTENSET_EL1 */ 1578 #define PMINTENSET_EL1 MRS_REG(PMINTENSET_EL1) 1579 #define PMINTENSET_EL1_op0 3 1580 #define PMINTENSET_EL1_op1 0 1581 #define PMINTENSET_EL1_CRn 9 1582 #define PMINTENSET_EL1_CRm 14 1583 #define PMINTENSET_EL1_op2 1 1584 1585 /* PMMIR_EL1 */ 1586 #define PMMIR_EL1 MRS_REG(PMMIR_EL1) 1587 #define PMMIR_EL1_op0 3 1588 #define PMMIR_EL1_op1 0 1589 #define PMMIR_EL1_CRn 9 1590 #define PMMIR_EL1_CRm 14 1591 #define PMMIR_EL1_op2 6 1592 1593 /* PMOVSCLR_EL0 */ 1594 #define PMOVSCLR_EL0 MRS_REG(PMOVSCLR_EL0) 1595 #define PMOVSCLR_EL0_op0 3 1596 #define PMOVSCLR_EL0_op1 3 1597 #define PMOVSCLR_EL0_CRn 9 1598 #define PMOVSCLR_EL0_CRm 12 1599 #define PMOVSCLR_EL0_op2 3 1600 1601 /* PMOVSSET_EL0 */ 1602 #define PMOVSSET_EL0 MRS_REG(PMOVSSET_EL0) 1603 #define PMOVSSET_EL0_op0 3 1604 #define PMOVSSET_EL0_op1 3 1605 #define PMOVSSET_EL0_CRn 9 1606 #define PMOVSSET_EL0_CRm 14 1607 #define PMOVSSET_EL0_op2 3 1608 1609 /* PMSCR_EL1 */ 1610 #define PMSCR_EL1 MRS_REG(PMSCR_EL1) 1611 #define PMSCR_EL1_op0 0x3 1612 #define PMSCR_EL1_op1 0x0 1613 #define PMSCR_EL1_CRn 0x9 1614 #define PMSCR_EL1_CRm 0x9 1615 #define PMSCR_EL1_op2 0x0 1616 #define PMSCR_E0SPE_SHIFT 0 1617 #define PMSCR_E0SPE (UL(0x1) << PMSCR_E0SPE_SHIFT) 1618 #define PMSCR_E1SPE_SHIFT 1 1619 #define PMSCR_E1SPE (UL(0x1) << PMSCR_E1SPE_SHIFT) 1620 #define PMSCR_CX_SHIFT 3 1621 #define PMSCR_CX (UL(0x1) << PMSCR_CX_SHIFT) 1622 #define PMSCR_PA_SHIFT 4 1623 #define PMSCR_PA (UL(0x1) << PMSCR_PA_SHIFT) 1624 #define PMSCR_TS_SHIFT 5 1625 #define PMSCR_TS (UL(0x1) << PMSCR_TS_SHIFT) 1626 #define PMSCR_PCT_SHIFT 6 1627 #define PMSCR_PCT_MASK (UL(0x3) << PMSCR_PCT_SHIFT) 1628 1629 /* PMSELR_EL0 */ 1630 #define PMSELR_EL0 MRS_REG(PMSELR_EL0) 1631 #define PMSELR_EL0_op0 3 1632 #define PMSELR_EL0_op1 3 1633 #define PMSELR_EL0_CRn 9 1634 #define PMSELR_EL0_CRm 12 1635 #define PMSELR_EL0_op2 5 1636 #define PMSELR_SEL_MASK 0x1f 1637 1638 /* PMSEVFR_EL1 */ 1639 #define PMSEVFR_EL1 MRS_REG(PMSEVFR_EL1) 1640 #define PMSEVFR_EL1_op0 0x3 1641 #define PMSEVFR_EL1_op1 0x0 1642 #define PMSEVFR_EL1_CRn 0x9 1643 #define PMSEVFR_EL1_CRm 0x9 1644 #define PMSEVFR_EL1_op2 0x5 1645 1646 /* PMSFCR_EL1 */ 1647 #define PMSFCR_EL1 MRS_REG(PMSFCR_EL1) 1648 #define PMSFCR_EL1_op0 0x3 1649 #define PMSFCR_EL1_op1 0x0 1650 #define PMSFCR_EL1_CRn 0x9 1651 #define PMSFCR_EL1_CRm 0x9 1652 #define PMSFCR_EL1_op2 0x4 1653 #define PMSFCR_FE_SHIFT 0 1654 #define PMSFCR_FE (UL(0x1) << PMSFCR_FE_SHIFT) 1655 #define PMSFCR_FT_SHIFT 1 1656 #define PMSFCR_FT (UL(0x1) << PMSFCR_FT_SHIFT) 1657 #define PMSFCR_FL_SHIFT 2 1658 #define PMSFCR_FL (UL(0x1) << PMSFCR_FL_SHIFT) 1659 #define PMSFCR_FnE_SHIFT 3 1660 #define PMSFCR_FnE (UL(0x1) << PMSFCR_FnE_SHIFT) 1661 #define PMSFCR_B_SHIFT 16 1662 #define PMSFCR_B (UL(0x1) << PMSFCR_B_SHIFT) 1663 #define PMSFCR_LD_SHIFT 17 1664 #define PMSFCR_LD (UL(0x1) << PMSFCR_LD_SHIFT) 1665 #define PMSFCR_ST_SHIFT 18 1666 #define PMSFCR_ST (UL(0x1) << PMSFCR_ST_SHIFT) 1667 1668 /* PMSICR_EL1 */ 1669 #define PMSICR_EL1 MRS_REG(PMSICR_EL1) 1670 #define PMSICR_EL1_op0 0x3 1671 #define PMSICR_EL1_op1 0x0 1672 #define PMSICR_EL1_CRn 0x9 1673 #define PMSICR_EL1_CRm 0x9 1674 #define PMSICR_EL1_op2 0x2 1675 #define PMSICR_COUNT_SHIFT 0 1676 #define PMSICR_COUNT_MASK (UL(0xffffffff) << PMSICR_COUNT_SHIFT) 1677 #define PMSICR_ECOUNT_SHIFT 56 1678 #define PMSICR_ECOUNT_MASK (UL(0xff) << PMSICR_ECOUNT_SHIFT) 1679 1680 /* PMSIDR_EL1 */ 1681 #define PMSIDR_EL1 MRS_REG(PMSIDR_EL1) 1682 #define PMSIDR_EL1_op0 0x3 1683 #define PMSIDR_EL1_op1 0x0 1684 #define PMSIDR_EL1_CRn 0x9 1685 #define PMSIDR_EL1_CRm 0x9 1686 #define PMSIDR_EL1_op2 0x7 1687 #define PMSIDR_FE_SHIFT 0 1688 #define PMSIDR_FE (UL(0x1) << PMSIDR_FE_SHIFT) 1689 #define PMSIDR_FT_SHIFT 1 1690 #define PMSIDR_FT (UL(0x1) << PMSIDR_FT_SHIFT) 1691 #define PMSIDR_FL_SHIFT 2 1692 #define PMSIDR_FL (UL(0x1) << PMSIDR_FL_SHIFT) 1693 #define PMSIDR_ArchInst_SHIFT 3 1694 #define PMSIDR_ArchInst (UL(0x1) << PMSIDR_ArchInst_SHIFT) 1695 #define PMSIDR_LDS_SHIFT 4 1696 #define PMSIDR_LDS (UL(0x1) << PMSIDR_LDS_SHIFT) 1697 #define PMSIDR_ERnd_SHIFT 5 1698 #define PMSIDR_ERnd (UL(0x1) << PMSIDR_ERnd_SHIFT) 1699 #define PMSIDR_FnE_SHIFT 6 1700 #define PMSIDR_FnE (UL(0x1) << PMSIDR_FnE_SHIFT) 1701 #define PMSIDR_Interval_SHIFT 8 1702 #define PMSIDR_Interval_MASK (UL(0xf) << PMSIDR_Interval_SHIFT) 1703 #define PMSIDR_MaxSize_SHIFT 12 1704 #define PMSIDR_MaxSize_MASK (UL(0xf) << PMSIDR_MaxSize_SHIFT) 1705 #define PMSIDR_CountSize_SHIFT 16 1706 #define PMSIDR_CountSize_MASK (UL(0xf) << PMSIDR_CountSize_SHIFT) 1707 #define PMSIDR_Format_SHIFT 20 1708 #define PMSIDR_Format_MASK (UL(0xf) << PMSIDR_Format_SHIFT) 1709 #define PMSIDR_PBT_SHIFT 24 1710 #define PMSIDR_PBT (UL(0x1) << PMSIDR_PBT_SHIFT) 1711 1712 /* PMSIRR_EL1 */ 1713 #define PMSIRR_EL1 MRS_REG(PMSIRR_EL1) 1714 #define PMSIRR_EL1_op0 0x3 1715 #define PMSIRR_EL1_op1 0x0 1716 #define PMSIRR_EL1_CRn 0x9 1717 #define PMSIRR_EL1_CRm 0x9 1718 #define PMSIRR_EL1_op2 0x3 1719 #define PMSIRR_RND_SHIFT 0 1720 #define PMSIRR_RND (UL(0x1) << PMSIRR_RND_SHIFT) 1721 #define PMSIRR_INTERVAL_SHIFT 8 1722 #define PMSIRR_INTERVAL_MASK (UL(0xffffff) << PMSIRR_INTERVAL_SHIFT) 1723 1724 /* PMSLATFR_EL1 */ 1725 #define PMSLATFR_EL1 MRS_REG(PMSLATFR_EL1) 1726 #define PMSLATFR_EL1_op0 0x3 1727 #define PMSLATFR_EL1_op1 0x0 1728 #define PMSLATFR_EL1_CRn 0x9 1729 #define PMSLATFR_EL1_CRm 0x9 1730 #define PMSLATFR_EL1_op2 0x6 1731 #define PMSLATFR_MINLAT_SHIFT 0 1732 #define PMSLATFR_MINLAT_MASK (UL(0xfff) << PMSLATFR_MINLAT_SHIFT) 1733 1734 /* PMSNEVFR_EL1 */ 1735 #define PMSNEVFR_EL1 MRS_REG(PMSNEVFR_EL1) 1736 #define PMSNEVFR_EL1_op0 0x3 1737 #define PMSNEVFR_EL1_op1 0x0 1738 #define PMSNEVFR_EL1_CRn 0x9 1739 #define PMSNEVFR_EL1_CRm 0x9 1740 #define PMSNEVFR_EL1_op2 0x1 1741 1742 /* PMSWINC_EL0 */ 1743 #define PMSWINC_EL0 MRS_REG(PMSWINC_EL0) 1744 #define PMSWINC_EL0_op0 3 1745 #define PMSWINC_EL0_op1 3 1746 #define PMSWINC_EL0_CRn 9 1747 #define PMSWINC_EL0_CRm 12 1748 #define PMSWINC_EL0_op2 4 1749 1750 /* PMUSERENR_EL0 */ 1751 #define PMUSERENR_EL0 MRS_REG(PMUSERENR_EL0) 1752 #define PMUSERENR_EL0_op0 3 1753 #define PMUSERENR_EL0_op1 3 1754 #define PMUSERENR_EL0_CRn 9 1755 #define PMUSERENR_EL0_CRm 14 1756 #define PMUSERENR_EL0_op2 0 1757 1758 /* PMXEVCNTR_EL0 */ 1759 #define PMXEVCNTR_EL0 MRS_REG(PMXEVCNTR_EL0) 1760 #define PMXEVCNTR_EL0_op0 3 1761 #define PMXEVCNTR_EL0_op1 3 1762 #define PMXEVCNTR_EL0_CRn 9 1763 #define PMXEVCNTR_EL0_CRm 13 1764 #define PMXEVCNTR_EL0_op2 2 1765 1766 /* PMXEVTYPER_EL0 */ 1767 #define PMXEVTYPER_EL0 MRS_REG(PMXEVTYPER_EL0) 1768 #define PMXEVTYPER_EL0_op0 3 1769 #define PMXEVTYPER_EL0_op1 3 1770 #define PMXEVTYPER_EL0_CRn 9 1771 #define PMXEVTYPER_EL0_CRm 13 1772 #define PMXEVTYPER_EL0_op2 1 1773 1774 /* SCTLR_EL1 - System Control Register */ 1775 #define SCTLR_RES1 0x30d00800 /* Reserved ARMv8.0, write 1 */ 1776 #define SCTLR_M (UL(0x1) << 0) 1777 #define SCTLR_A (UL(0x1) << 1) 1778 #define SCTLR_C (UL(0x1) << 2) 1779 #define SCTLR_SA (UL(0x1) << 3) 1780 #define SCTLR_SA0 (UL(0x1) << 4) 1781 #define SCTLR_CP15BEN (UL(0x1) << 5) 1782 #define SCTLR_nAA (UL(0x1) << 6) 1783 #define SCTLR_ITD (UL(0x1) << 7) 1784 #define SCTLR_SED (UL(0x1) << 8) 1785 #define SCTLR_UMA (UL(0x1) << 9) 1786 #define SCTLR_EnRCTX (UL(0x1) << 10) 1787 #define SCTLR_EOS (UL(0x1) << 11) 1788 #define SCTLR_I (UL(0x1) << 12) 1789 #define SCTLR_EnDB (UL(0x1) << 13) 1790 #define SCTLR_DZE (UL(0x1) << 14) 1791 #define SCTLR_UCT (UL(0x1) << 15) 1792 #define SCTLR_nTWI (UL(0x1) << 16) 1793 /* Bit 17 is reserved */ 1794 #define SCTLR_nTWE (UL(0x1) << 18) 1795 #define SCTLR_WXN (UL(0x1) << 19) 1796 #define SCTLR_TSCXT (UL(0x1) << 20) 1797 #define SCTLR_IESB (UL(0x1) << 21) 1798 #define SCTLR_EIS (UL(0x1) << 22) 1799 #define SCTLR_SPAN (UL(0x1) << 23) 1800 #define SCTLR_E0E (UL(0x1) << 24) 1801 #define SCTLR_EE (UL(0x1) << 25) 1802 #define SCTLR_UCI (UL(0x1) << 26) 1803 #define SCTLR_EnDA (UL(0x1) << 27) 1804 #define SCTLR_nTLSMD (UL(0x1) << 28) 1805 #define SCTLR_LSMAOE (UL(0x1) << 29) 1806 #define SCTLR_EnIB (UL(0x1) << 30) 1807 #define SCTLR_EnIA (UL(0x1) << 31) 1808 /* Bits 34:32 are reserved */ 1809 #define SCTLR_BT0 (UL(0x1) << 35) 1810 #define SCTLR_BT1 (UL(0x1) << 36) 1811 #define SCTLR_ITFSB (UL(0x1) << 37) 1812 #define SCTLR_TCF0_MASK (UL(0x3) << 38) 1813 #define SCTLR_TCF_MASK (UL(0x3) << 40) 1814 #define SCTLR_ATA0 (UL(0x1) << 42) 1815 #define SCTLR_ATA (UL(0x1) << 43) 1816 #define SCTLR_DSSBS (UL(0x1) << 44) 1817 #define SCTLR_TWEDEn (UL(0x1) << 45) 1818 #define SCTLR_TWEDEL_MASK (UL(0xf) << 46) 1819 /* Bits 53:50 are reserved */ 1820 #define SCTLR_EnASR (UL(0x1) << 54) 1821 #define SCTLR_EnAS0 (UL(0x1) << 55) 1822 #define SCTLR_EnALS (UL(0x1) << 56) 1823 #define SCTLR_EPAN (UL(0x1) << 57) 1824 1825 /* SPSR_EL1 */ 1826 /* 1827 * When the exception is taken in AArch64: 1828 * M[3:2] is the exception level 1829 * M[1] is unused 1830 * M[0] is the SP select: 1831 * 0: always SP0 1832 * 1: current ELs SP 1833 */ 1834 #define PSR_M_EL0t 0x00000000UL 1835 #define PSR_M_EL1t 0x00000004UL 1836 #define PSR_M_EL1h 0x00000005UL 1837 #define PSR_M_EL2t 0x00000008UL 1838 #define PSR_M_EL2h 0x00000009UL 1839 #define PSR_M_64 0x00000000UL 1840 #define PSR_M_32 0x00000010UL 1841 #define PSR_M_MASK 0x0000000fUL 1842 1843 #define PSR_T 0x00000020UL 1844 1845 #define PSR_AARCH32 0x00000010UL 1846 #define PSR_F 0x00000040UL 1847 #define PSR_I 0x00000080UL 1848 #define PSR_A 0x00000100UL 1849 #define PSR_D 0x00000200UL 1850 #define PSR_DAIF (PSR_D | PSR_A | PSR_I | PSR_F) 1851 /* The default DAIF mask. These bits are valid in spsr_el1 and daif */ 1852 #define PSR_DAIF_DEFAULT (PSR_F) 1853 #define PSR_IL 0x00100000UL 1854 #define PSR_SS 0x00200000UL 1855 #define PSR_V 0x10000000UL 1856 #define PSR_C 0x20000000UL 1857 #define PSR_Z 0x40000000UL 1858 #define PSR_N 0x80000000UL 1859 #define PSR_FLAGS 0xf0000000UL 1860 /* PSR fields that can be set from 32-bit and 64-bit processes */ 1861 #define PSR_SETTABLE_32 PSR_FLAGS 1862 #define PSR_SETTABLE_64 (PSR_FLAGS | PSR_SS) 1863 1864 /* TCR_EL1 - Translation Control Register */ 1865 /* Bits 63:59 are reserved */ 1866 #define TCR_TCMA1_SHIFT 58 1867 #define TCR_TCMA1 (1UL << TCR_TCMA1_SHIFT) 1868 #define TCR_TCMA0_SHIFT 57 1869 #define TCR_TCMA0 (1UL << TCR_TCMA0_SHIFT) 1870 #define TCR_E0PD1_SHIFT 56 1871 #define TCR_E0PD1 (1UL << TCR_E0PD1_SHIFT) 1872 #define TCR_E0PD0_SHIFT 55 1873 #define TCR_E0PD0 (1UL << TCR_E0PD0_SHIFT) 1874 #define TCR_NFD1_SHIFT 54 1875 #define TCR_NFD1 (1UL << TCR_NFD1_SHIFT) 1876 #define TCR_NFD0_SHIFT 53 1877 #define TCR_NFD0 (1UL << TCR_NFD0_SHIFT) 1878 #define TCR_TBID1_SHIFT 52 1879 #define TCR_TBID1 (1UL << TCR_TBID1_SHIFT) 1880 #define TCR_TBID0_SHIFT 51 1881 #define TCR_TBID0 (1UL << TCR_TBID0_SHIFT) 1882 #define TCR_HWU162_SHIFT 50 1883 #define TCR_HWU162 (1UL << TCR_HWU162_SHIFT) 1884 #define TCR_HWU161_SHIFT 49 1885 #define TCR_HWU161 (1UL << TCR_HWU161_SHIFT) 1886 #define TCR_HWU160_SHIFT 48 1887 #define TCR_HWU160 (1UL << TCR_HWU160_SHIFT) 1888 #define TCR_HWU159_SHIFT 47 1889 #define TCR_HWU159 (1UL << TCR_HWU159_SHIFT) 1890 #define TCR_HWU1 \ 1891 (TCR_HWU159 | TCR_HWU160 | TCR_HWU161 | TCR_HWU162) 1892 #define TCR_HWU062_SHIFT 46 1893 #define TCR_HWU062 (1UL << TCR_HWU062_SHIFT) 1894 #define TCR_HWU061_SHIFT 45 1895 #define TCR_HWU061 (1UL << TCR_HWU061_SHIFT) 1896 #define TCR_HWU060_SHIFT 44 1897 #define TCR_HWU060 (1UL << TCR_HWU060_SHIFT) 1898 #define TCR_HWU059_SHIFT 43 1899 #define TCR_HWU059 (1UL << TCR_HWU059_SHIFT) 1900 #define TCR_HWU0 \ 1901 (TCR_HWU059 | TCR_HWU060 | TCR_HWU061 | TCR_HWU062) 1902 #define TCR_HPD1_SHIFT 42 1903 #define TCR_HPD1 (1UL << TCR_HPD1_SHIFT) 1904 #define TCR_HPD0_SHIFT 41 1905 #define TCR_HPD0 (1UL << TCR_HPD0_SHIFT) 1906 #define TCR_HD_SHIFT 40 1907 #define TCR_HD (1UL << TCR_HD_SHIFT) 1908 #define TCR_HA_SHIFT 39 1909 #define TCR_HA (1UL << TCR_HA_SHIFT) 1910 #define TCR_TBI1_SHIFT 38 1911 #define TCR_TBI1 (1UL << TCR_TBI1_SHIFT) 1912 #define TCR_TBI0_SHIFT 37 1913 #define TCR_TBI0 (1U << TCR_TBI0_SHIFT) 1914 #define TCR_ASID_SHIFT 36 1915 #define TCR_ASID_WIDTH 1 1916 #define TCR_ASID_16 (1UL << TCR_ASID_SHIFT) 1917 /* Bit 35 is reserved */ 1918 #define TCR_IPS_SHIFT 32 1919 #define TCR_IPS_WIDTH 3 1920 #define TCR_IPS_32BIT (0UL << TCR_IPS_SHIFT) 1921 #define TCR_IPS_36BIT (1UL << TCR_IPS_SHIFT) 1922 #define TCR_IPS_40BIT (2UL << TCR_IPS_SHIFT) 1923 #define TCR_IPS_42BIT (3UL << TCR_IPS_SHIFT) 1924 #define TCR_IPS_44BIT (4UL << TCR_IPS_SHIFT) 1925 #define TCR_IPS_48BIT (5UL << TCR_IPS_SHIFT) 1926 #define TCR_TG1_SHIFT 30 1927 #define TCR_TG1_16K (1UL << TCR_TG1_SHIFT) 1928 #define TCR_TG1_4K (2UL << TCR_TG1_SHIFT) 1929 #define TCR_TG1_64K (3UL << TCR_TG1_SHIFT) 1930 #define TCR_SH1_SHIFT 28 1931 #define TCR_SH1_IS (3UL << TCR_SH1_SHIFT) 1932 #define TCR_ORGN1_SHIFT 26 1933 #define TCR_ORGN1_WBWA (1UL << TCR_ORGN1_SHIFT) 1934 #define TCR_IRGN1_SHIFT 24 1935 #define TCR_IRGN1_WBWA (1UL << TCR_IRGN1_SHIFT) 1936 #define TCR_EPD1_SHIFT 23 1937 #define TCR_EPD1 (1UL << TCR_EPD1_SHIFT) 1938 #define TCR_A1_SHIFT 22 1939 #define TCR_A1 (0x1UL << TCR_A1_SHIFT) 1940 #define TCR_T1SZ_SHIFT 16 1941 #define TCR_T1SZ(x) ((x) << TCR_T1SZ_SHIFT) 1942 #define TCR_TG0_SHIFT 14 1943 #define TCR_TG0_4K (0UL << TCR_TG0_SHIFT) 1944 #define TCR_TG0_64K (1UL << TCR_TG0_SHIFT) 1945 #define TCR_TG0_16K (2UL << TCR_TG0_SHIFT) 1946 #define TCR_SH0_SHIFT 12 1947 #define TCR_SH0_IS (3UL << TCR_SH0_SHIFT) 1948 #define TCR_ORGN0_SHIFT 10 1949 #define TCR_ORGN0_WBWA (1UL << TCR_ORGN0_SHIFT) 1950 #define TCR_IRGN0_SHIFT 8 1951 #define TCR_IRGN0_WBWA (1UL << TCR_IRGN0_SHIFT) 1952 #define TCR_EPD0_SHIFT 7 1953 #define TCR_EPD0 (1UL << TCR_EPD1_SHIFT) 1954 /* Bit 6 is reserved */ 1955 #define TCR_T0SZ_SHIFT 0 1956 #define TCR_T0SZ_MASK 0x3f 1957 #define TCR_T0SZ(x) ((x) << TCR_T0SZ_SHIFT) 1958 #define TCR_TxSZ(x) (TCR_T1SZ(x) | TCR_T0SZ(x)) 1959 1960 #define TCR_CACHE_ATTRS ((TCR_IRGN0_WBWA | TCR_IRGN1_WBWA) |\ 1961 (TCR_ORGN0_WBWA | TCR_ORGN1_WBWA)) 1962 #ifdef SMP 1963 #define TCR_SMP_ATTRS (TCR_SH0_IS | TCR_SH1_IS) 1964 #else 1965 #define TCR_SMP_ATTRS 0 1966 #endif 1967 1968 /* TTBR0_EL1 & TTBR1_EL1 - Translation Table Base Register 0 & 1 */ 1969 #define TTBR_ASID_SHIFT 48 1970 #define TTBR_ASID_MASK (0xfffful << TTBR_ASID_SHIFT) 1971 #define TTBR_BADDR 0x0000fffffffffffeul 1972 #define TTBR_CnP_SHIFT 0 1973 #define TTBR_CnP (1ul << TTBR_CnP_SHIFT) 1974 1975 /* ZCR_EL1 - SVE Control Register */ 1976 #define ZCR_LEN_SHIFT 0 1977 #define ZCR_LEN_MASK (0xf << ZCR_LEN_SHIFT) 1978 #define ZCR_LEN_BYTES(x) ((((x) & ZCR_LEN_MASK) + 1) * 16) 1979 1980 #endif /* !_MACHINE_ARMREG_H_ */ 1981