1 /*- 2 * Copyright (c) 2013, 2014 Andrew Turner 3 * Copyright (c) 2015,2021 The FreeBSD Foundation 4 * 5 * Portions of this software were developed by Andrew Turner 6 * under sponsorship from the FreeBSD Foundation. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD$ 30 */ 31 32 #ifndef _MACHINE_ARMREG_H_ 33 #define _MACHINE_ARMREG_H_ 34 35 #define INSN_SIZE 4 36 37 #define MRS_MASK 0xfff00000 38 #define MRS_VALUE 0xd5300000 39 #define MRS_SPECIAL(insn) ((insn) & 0x000fffe0) 40 #define MRS_REGISTER(insn) ((insn) & 0x0000001f) 41 #define MRS_Op0_SHIFT 19 42 #define MRS_Op0_MASK 0x00080000 43 #define MRS_Op1_SHIFT 16 44 #define MRS_Op1_MASK 0x00070000 45 #define MRS_CRn_SHIFT 12 46 #define MRS_CRn_MASK 0x0000f000 47 #define MRS_CRm_SHIFT 8 48 #define MRS_CRm_MASK 0x00000f00 49 #define MRS_Op2_SHIFT 5 50 #define MRS_Op2_MASK 0x000000e0 51 #define MRS_Rt_SHIFT 0 52 #define MRS_Rt_MASK 0x0000001f 53 #define __MRS_REG(op0, op1, crn, crm, op2) \ 54 (((op0) << MRS_Op0_SHIFT) | ((op1) << MRS_Op1_SHIFT) | \ 55 ((crn) << MRS_CRn_SHIFT) | ((crm) << MRS_CRm_SHIFT) | \ 56 ((op2) << MRS_Op2_SHIFT)) 57 #define MRS_REG(reg) \ 58 __MRS_REG(reg##_op0, reg##_op1, reg##_CRn, reg##_CRm, reg##_op2) 59 60 61 62 #define READ_SPECIALREG(reg) \ 63 ({ uint64_t _val; \ 64 __asm __volatile("mrs %0, " __STRING(reg) : "=&r" (_val)); \ 65 _val; \ 66 }) 67 #define WRITE_SPECIALREG(reg, _val) \ 68 __asm __volatile("msr " __STRING(reg) ", %0" : : "r"((uint64_t)_val)) 69 70 #define UL(x) UINT64_C(x) 71 72 /* CNTHCTL_EL2 - Counter-timer Hypervisor Control register */ 73 #define CNTHCTL_EVNTI_MASK (0xf << 4) /* Bit to trigger event stream */ 74 #define CNTHCTL_EVNTDIR (1 << 3) /* Control transition trigger bit */ 75 #define CNTHCTL_EVNTEN (1 << 2) /* Enable event stream */ 76 #define CNTHCTL_EL1PCEN (1 << 1) /* Allow EL0/1 physical timer access */ 77 #define CNTHCTL_EL1PCTEN (1 << 0) /*Allow EL0/1 physical counter access*/ 78 79 /* CNTP_CTL_EL0 - Counter-timer Physical Timer Control register */ 80 #define CNTP_CTL_ENABLE (1 << 0) 81 #define CNTP_CTL_IMASK (1 << 1) 82 #define CNTP_CTL_ISTATUS (1 << 2) 83 84 /* CPACR_EL1 */ 85 #define CPACR_FPEN_MASK (0x3 << 20) 86 #define CPACR_FPEN_TRAP_ALL1 (0x0 << 20) /* Traps from EL0 and EL1 */ 87 #define CPACR_FPEN_TRAP_EL0 (0x1 << 20) /* Traps from EL0 */ 88 #define CPACR_FPEN_TRAP_ALL2 (0x2 << 20) /* Traps from EL0 and EL1 */ 89 #define CPACR_FPEN_TRAP_NONE (0x3 << 20) /* No traps */ 90 #define CPACR_TTA (0x1 << 28) 91 92 /* CTR_EL0 - Cache Type Register */ 93 #define CTR_RES1 (1 << 31) 94 #define CTR_TminLine_SHIFT 32 95 #define CTR_TminLine_MASK (UL(0x3f) << CTR_TminLine_SHIFT) 96 #define CTR_TminLine_VAL(reg) ((reg) & CTR_TminLine_MASK) 97 #define CTR_DIC_SHIFT 29 98 #define CTR_DIC_MASK (0x1 << CTR_DIC_SHIFT) 99 #define CTR_DIC_VAL(reg) ((reg) & CTR_DIC_MASK) 100 #define CTR_IDC_SHIFT 28 101 #define CTR_IDC_MASK (0x1 << CTR_IDC_SHIFT) 102 #define CTR_IDC_VAL(reg) ((reg) & CTR_IDC_MASK) 103 #define CTR_CWG_SHIFT 24 104 #define CTR_CWG_MASK (0xf << CTR_CWG_SHIFT) 105 #define CTR_CWG_VAL(reg) ((reg) & CTR_CWG_MASK) 106 #define CTR_CWG_SIZE(reg) (4 << (CTR_CWG_VAL(reg) >> CTR_CWG_SHIFT)) 107 #define CTR_ERG_SHIFT 20 108 #define CTR_ERG_MASK (0xf << CTR_ERG_SHIFT) 109 #define CTR_ERG_VAL(reg) ((reg) & CTR_ERG_MASK) 110 #define CTR_ERG_SIZE(reg) (4 << (CTR_ERG_VAL(reg) >> CTR_ERG_SHIFT)) 111 #define CTR_DLINE_SHIFT 16 112 #define CTR_DLINE_MASK (0xf << CTR_DLINE_SHIFT) 113 #define CTR_DLINE_VAL(reg) ((reg) & CTR_DLINE_MASK) 114 #define CTR_DLINE_SIZE(reg) (4 << (CTR_DLINE_VAL(reg) >> CTR_DLINE_SHIFT)) 115 #define CTR_L1IP_SHIFT 14 116 #define CTR_L1IP_MASK (0x3 << CTR_L1IP_SHIFT) 117 #define CTR_L1IP_VAL(reg) ((reg) & CTR_L1IP_MASK) 118 #define CTR_L1IP_VPIPT (0 << CTR_L1IP_SHIFT) 119 #define CTR_L1IP_AIVIVT (1 << CTR_L1IP_SHIFT) 120 #define CTR_L1IP_VIPT (2 << CTR_L1IP_SHIFT) 121 #define CTR_L1IP_PIPT (3 << CTR_L1IP_SHIFT) 122 #define CTR_ILINE_SHIFT 0 123 #define CTR_ILINE_MASK (0xf << CTR_ILINE_SHIFT) 124 #define CTR_ILINE_VAL(reg) ((reg) & CTR_ILINE_MASK) 125 #define CTR_ILINE_SIZE(reg) (4 << (CTR_ILINE_VAL(reg) >> CTR_ILINE_SHIFT)) 126 127 /* DAIFSet/DAIFClear */ 128 #define DAIF_D (1 << 3) 129 #define DAIF_A (1 << 2) 130 #define DAIF_I (1 << 1) 131 #define DAIF_F (1 << 0) 132 #define DAIF_ALL (DAIF_D | DAIF_A | DAIF_I | DAIF_F) 133 #define DAIF_INTR (DAIF_I) /* All exceptions that pass */ 134 /* through the intr framework */ 135 136 /* DCZID_EL0 - Data Cache Zero ID register */ 137 #define DCZID_DZP (1 << 4) /* DC ZVA prohibited if non-0 */ 138 #define DCZID_BS_SHIFT 0 139 #define DCZID_BS_MASK (0xf << DCZID_BS_SHIFT) 140 #define DCZID_BS_SIZE(reg) (((reg) & DCZID_BS_MASK) >> DCZID_BS_SHIFT) 141 142 /* ESR_ELx */ 143 #define ESR_ELx_ISS_MASK 0x01ffffff 144 #define ISS_INSN_FnV (0x01 << 10) 145 #define ISS_INSN_EA (0x01 << 9) 146 #define ISS_INSN_S1PTW (0x01 << 7) 147 #define ISS_INSN_IFSC_MASK (0x1f << 0) 148 149 #define ISS_MSR_DIR_SHIFT 0 150 #define ISS_MSR_DIR (0x01 << ISS_MSR_DIR_SHIFT) 151 #define ISS_MSR_Rt_SHIFT 5 152 #define ISS_MSR_Rt_MASK (0x1f << ISS_MSR_Rt_SHIFT) 153 #define ISS_MSR_Rt(x) (((x) & ISS_MSR_Rt_MASK) >> ISS_MSR_Rt_SHIFT) 154 #define ISS_MSR_CRm_SHIFT 1 155 #define ISS_MSR_CRm_MASK (0xf << ISS_MSR_CRm_SHIFT) 156 #define ISS_MSR_CRm(x) (((x) & ISS_MSR_CRm_MASK) >> ISS_MSR_CRm_SHIFT) 157 #define ISS_MSR_CRn_SHIFT 10 158 #define ISS_MSR_CRn_MASK (0xf << ISS_MSR_CRn_SHIFT) 159 #define ISS_MSR_CRn(x) (((x) & ISS_MSR_CRn_MASK) >> ISS_MSR_CRn_SHIFT) 160 #define ISS_MSR_OP1_SHIFT 14 161 #define ISS_MSR_OP1_MASK (0x7 << ISS_MSR_OP1_SHIFT) 162 #define ISS_MSR_OP1(x) (((x) & ISS_MSR_OP1_MASK) >> ISS_MSR_OP1_SHIFT) 163 #define ISS_MSR_OP2_SHIFT 17 164 #define ISS_MSR_OP2_MASK (0x7 << ISS_MSR_OP2_SHIFT) 165 #define ISS_MSR_OP2(x) (((x) & ISS_MSR_OP2_MASK) >> ISS_MSR_OP2_SHIFT) 166 #define ISS_MSR_OP0_SHIFT 20 167 #define ISS_MSR_OP0_MASK (0x3 << ISS_MSR_OP0_SHIFT) 168 #define ISS_MSR_OP0(x) (((x) & ISS_MSR_OP0_MASK) >> ISS_MSR_OP0_SHIFT) 169 #define ISS_MSR_REG_MASK \ 170 (ISS_MSR_OP0_MASK | ISS_MSR_OP2_MASK | ISS_MSR_OP1_MASK | \ 171 ISS_MSR_CRn_MASK | ISS_MSR_CRm_MASK) 172 173 #define ISS_DATA_ISV_SHIFT 24 174 #define ISS_DATA_ISV (0x01 << ISS_DATA_ISV_SHIFT) 175 #define ISS_DATA_SAS_SHIFT 22 176 #define ISS_DATA_SAS_MASK (0x03 << ISS_DATA_SAS_SHIFT) 177 #define ISS_DATA_SSE_SHIFT 21 178 #define ISS_DATA_SSE (0x01 << ISS_DATA_SSE_SHIFT) 179 #define ISS_DATA_SRT_SHIFT 16 180 #define ISS_DATA_SRT_MASK (0x1f << ISS_DATA_SRT_SHIFT) 181 #define ISS_DATA_SF (0x01 << 15) 182 #define ISS_DATA_AR (0x01 << 14) 183 #define ISS_DATA_FnV (0x01 << 10) 184 #define ISS_DATA_EA (0x01 << 9) 185 #define ISS_DATA_CM (0x01 << 8) 186 #define ISS_DATA_S1PTW (0x01 << 7) 187 #define ISS_DATA_WnR_SHIFT 6 188 #define ISS_DATA_WnR (0x01 << ISS_DATA_WnR_SHIFT) 189 #define ISS_DATA_DFSC_MASK (0x3f << 0) 190 #define ISS_DATA_DFSC_ASF_L0 (0x00 << 0) 191 #define ISS_DATA_DFSC_ASF_L1 (0x01 << 0) 192 #define ISS_DATA_DFSC_ASF_L2 (0x02 << 0) 193 #define ISS_DATA_DFSC_ASF_L3 (0x03 << 0) 194 #define ISS_DATA_DFSC_TF_L0 (0x04 << 0) 195 #define ISS_DATA_DFSC_TF_L1 (0x05 << 0) 196 #define ISS_DATA_DFSC_TF_L2 (0x06 << 0) 197 #define ISS_DATA_DFSC_TF_L3 (0x07 << 0) 198 #define ISS_DATA_DFSC_AFF_L1 (0x09 << 0) 199 #define ISS_DATA_DFSC_AFF_L2 (0x0a << 0) 200 #define ISS_DATA_DFSC_AFF_L3 (0x0b << 0) 201 #define ISS_DATA_DFSC_PF_L1 (0x0d << 0) 202 #define ISS_DATA_DFSC_PF_L2 (0x0e << 0) 203 #define ISS_DATA_DFSC_PF_L3 (0x0f << 0) 204 #define ISS_DATA_DFSC_EXT (0x10 << 0) 205 #define ISS_DATA_DFSC_EXT_L0 (0x14 << 0) 206 #define ISS_DATA_DFSC_EXT_L1 (0x15 << 0) 207 #define ISS_DATA_DFSC_EXT_L2 (0x16 << 0) 208 #define ISS_DATA_DFSC_EXT_L3 (0x17 << 0) 209 #define ISS_DATA_DFSC_ECC (0x18 << 0) 210 #define ISS_DATA_DFSC_ECC_L0 (0x1c << 0) 211 #define ISS_DATA_DFSC_ECC_L1 (0x1d << 0) 212 #define ISS_DATA_DFSC_ECC_L2 (0x1e << 0) 213 #define ISS_DATA_DFSC_ECC_L3 (0x1f << 0) 214 #define ISS_DATA_DFSC_ALIGN (0x21 << 0) 215 #define ISS_DATA_DFSC_TLB_CONFLICT (0x30 << 0) 216 #define ESR_ELx_IL (0x01 << 25) 217 #define ESR_ELx_EC_SHIFT 26 218 #define ESR_ELx_EC_MASK (0x3f << 26) 219 #define ESR_ELx_EXCEPTION(esr) (((esr) & ESR_ELx_EC_MASK) >> ESR_ELx_EC_SHIFT) 220 #define EXCP_UNKNOWN 0x00 /* Unkwn exception */ 221 #define EXCP_TRAP_WFI_WFE 0x01 /* Trapped WFI or WFE */ 222 #define EXCP_FP_SIMD 0x07 /* VFP/SIMD trap */ 223 #define EXCP_ILL_STATE 0x0e /* Illegal execution state */ 224 #define EXCP_SVC32 0x11 /* SVC trap for AArch32 */ 225 #define EXCP_SVC64 0x15 /* SVC trap for AArch64 */ 226 #define EXCP_HVC 0x16 /* HVC trap */ 227 #define EXCP_MSR 0x18 /* MSR/MRS trap */ 228 #define EXCP_INSN_ABORT_L 0x20 /* Instruction abort, from lower EL */ 229 #define EXCP_INSN_ABORT 0x21 /* Instruction abort, from same EL */ 230 #define EXCP_PC_ALIGN 0x22 /* PC alignment fault */ 231 #define EXCP_DATA_ABORT_L 0x24 /* Data abort, from lower EL */ 232 #define EXCP_DATA_ABORT 0x25 /* Data abort, from same EL */ 233 #define EXCP_SP_ALIGN 0x26 /* SP slignment fault */ 234 #define EXCP_TRAP_FP 0x2c /* Trapped FP exception */ 235 #define EXCP_SERROR 0x2f /* SError interrupt */ 236 #define EXCP_BRKPT_EL0 0x30 /* Hardware breakpoint, from same EL */ 237 #define EXCP_SOFTSTP_EL0 0x32 /* Software Step, from lower EL */ 238 #define EXCP_SOFTSTP_EL1 0x33 /* Software Step, from same EL */ 239 #define EXCP_WATCHPT_EL0 0x34 /* Watchpoint, from lower EL */ 240 #define EXCP_WATCHPT_EL1 0x35 /* Watchpoint, from same EL */ 241 #define EXCP_BRK 0x3c /* Breakpoint */ 242 243 /* ICC_CTLR_EL1 */ 244 #define ICC_CTLR_EL1_EOIMODE (1U << 1) 245 246 /* ICC_IAR1_EL1 */ 247 #define ICC_IAR1_EL1_SPUR (0x03ff) 248 249 /* ICC_IGRPEN0_EL1 */ 250 #define ICC_IGRPEN0_EL1_EN (1U << 0) 251 252 /* ICC_PMR_EL1 */ 253 #define ICC_PMR_EL1_PRIO_MASK (0xFFUL) 254 255 /* ICC_SGI1R_EL1 */ 256 #define ICC_SGI1R_EL1_TL_MASK 0xffffUL 257 #define ICC_SGI1R_EL1_AFF1_SHIFT 16 258 #define ICC_SGI1R_EL1_SGIID_SHIFT 24 259 #define ICC_SGI1R_EL1_AFF2_SHIFT 32 260 #define ICC_SGI1R_EL1_AFF3_SHIFT 48 261 #define ICC_SGI1R_EL1_SGIID_MASK 0xfUL 262 #define ICC_SGI1R_EL1_IRM (0x1UL << 40) 263 264 /* ICC_SRE_EL1 */ 265 #define ICC_SRE_EL1_SRE (1U << 0) 266 267 /* ID_AA64DFR0_EL1 */ 268 #define ID_AA64DFR0_EL1 MRS_REG(ID_AA64DFR0_EL1) 269 #define ID_AA64DFR0_EL1_op0 0x3 270 #define ID_AA64DFR0_EL1_op1 0x0 271 #define ID_AA64DFR0_EL1_CRn 0x0 272 #define ID_AA64DFR0_EL1_CRm 0x5 273 #define ID_AA64DFR0_EL1_op2 0x0 274 #define ID_AA64DFR0_DebugVer_SHIFT 0 275 #define ID_AA64DFR0_DebugVer_MASK (UL(0xf) << ID_AA64DFR0_DebugVer_SHIFT) 276 #define ID_AA64DFR0_DebugVer_VAL(x) ((x) & ID_AA64DFR0_DebugVer_MASK) 277 #define ID_AA64DFR0_DebugVer_8 (UL(0x6) << ID_AA64DFR0_DebugVer_SHIFT) 278 #define ID_AA64DFR0_DebugVer_8_VHE (UL(0x7) << ID_AA64DFR0_DebugVer_SHIFT) 279 #define ID_AA64DFR0_DebugVer_8_2 (UL(0x8) << ID_AA64DFR0_DebugVer_SHIFT) 280 #define ID_AA64DFR0_DebugVer_8_4 (UL(0x9) << ID_AA64DFR0_DebugVer_SHIFT) 281 #define ID_AA64DFR0_TraceVer_SHIFT 4 282 #define ID_AA64DFR0_TraceVer_MASK (UL(0xf) << ID_AA64DFR0_TraceVer_SHIFT) 283 #define ID_AA64DFR0_TraceVer_VAL(x) ((x) & ID_AA64DFR0_TraceVer_MASK) 284 #define ID_AA64DFR0_TraceVer_NONE (UL(0x0) << ID_AA64DFR0_TraceVer_SHIFT) 285 #define ID_AA64DFR0_TraceVer_IMPL (UL(0x1) << ID_AA64DFR0_TraceVer_SHIFT) 286 #define ID_AA64DFR0_PMUVer_SHIFT 8 287 #define ID_AA64DFR0_PMUVer_MASK (UL(0xf) << ID_AA64DFR0_PMUVer_SHIFT) 288 #define ID_AA64DFR0_PMUVer_VAL(x) ((x) & ID_AA64DFR0_PMUVer_MASK) 289 #define ID_AA64DFR0_PMUVer_NONE (UL(0x0) << ID_AA64DFR0_PMUVer_SHIFT) 290 #define ID_AA64DFR0_PMUVer_3 (UL(0x1) << ID_AA64DFR0_PMUVer_SHIFT) 291 #define ID_AA64DFR0_PMUVer_3_1 (UL(0x4) << ID_AA64DFR0_PMUVer_SHIFT) 292 #define ID_AA64DFR0_PMUVer_3_4 (UL(0x5) << ID_AA64DFR0_PMUVer_SHIFT) 293 #define ID_AA64DFR0_PMUVer_3_5 (UL(0x6) << ID_AA64DFR0_PMUVer_SHIFT) 294 #define ID_AA64DFR0_PMUVer_IMPL (UL(0xf) << ID_AA64DFR0_PMUVer_SHIFT) 295 #define ID_AA64DFR0_BRPs_SHIFT 12 296 #define ID_AA64DFR0_BRPs_MASK (UL(0xf) << ID_AA64DFR0_BRPs_SHIFT) 297 #define ID_AA64DFR0_BRPs_VAL(x) \ 298 ((((x) >> ID_AA64DFR0_BRPs_SHIFT) & 0xf) + 1) 299 #define ID_AA64DFR0_WRPs_SHIFT 20 300 #define ID_AA64DFR0_WRPs_MASK (UL(0xf) << ID_AA64DFR0_WRPs_SHIFT) 301 #define ID_AA64DFR0_WRPs_VAL(x) \ 302 ((((x) >> ID_AA64DFR0_WRPs_SHIFT) & 0xf) + 1) 303 #define ID_AA64DFR0_CTX_CMPs_SHIFT 28 304 #define ID_AA64DFR0_CTX_CMPs_MASK (UL(0xf) << ID_AA64DFR0_CTX_CMPs_SHIFT) 305 #define ID_AA64DFR0_CTX_CMPs_VAL(x) \ 306 ((((x) >> ID_AA64DFR0_CTX_CMPs_SHIFT) & 0xf) + 1) 307 #define ID_AA64DFR0_PMSVer_SHIFT 32 308 #define ID_AA64DFR0_PMSVer_MASK (UL(0xf) << ID_AA64DFR0_PMSVer_SHIFT) 309 #define ID_AA64DFR0_PMSVer_VAL(x) ((x) & ID_AA64DFR0_PMSVer_MASK) 310 #define ID_AA64DFR0_PMSVer_NONE (UL(0x0) << ID_AA64DFR0_PMSVer_SHIFT) 311 #define ID_AA64DFR0_PMSVer_SPE (UL(0x1) << ID_AA64DFR0_PMSVer_SHIFT) 312 #define ID_AA64DFR0_PMSVer_SPE_8_3 (UL(0x2) << ID_AA64DFR0_PMSVer_SHIFT) 313 #define ID_AA64DFR0_DoubleLock_SHIFT 36 314 #define ID_AA64DFR0_DoubleLock_MASK (UL(0xf) << ID_AA64DFR0_DoubleLock_SHIFT) 315 #define ID_AA64DFR0_DoubleLock_VAL(x) ((x) & ID_AA64DFR0_DoubleLock_MASK) 316 #define ID_AA64DFR0_DoubleLock_IMPL (UL(0x0) << ID_AA64DFR0_DoubleLock_SHIFT) 317 #define ID_AA64DFR0_DoubleLock_NONE (UL(0xf) << ID_AA64DFR0_DoubleLock_SHIFT) 318 #define ID_AA64DFR0_TraceFilt_SHIFT 40 319 #define ID_AA64DFR0_TraceFilt_MASK (UL(0xf) << ID_AA64DFR0_TraceFilt_SHIFT) 320 #define ID_AA64DFR0_TraceFilt_VAL(x) ((x) & ID_AA64DFR0_TraceFilt_MASK) 321 #define ID_AA64DFR0_TraceFilt_NONE (UL(0x0) << ID_AA64DFR0_TraceFilt_SHIFT) 322 #define ID_AA64DFR0_TraceFilt_8_4 (UL(0x1) << ID_AA64DFR0_TraceFilt_SHIFT) 323 324 /* ID_AA64ISAR0_EL1 */ 325 #define ID_AA64ISAR0_EL1 MRS_REG(ID_AA64ISAR0_EL1) 326 #define ID_AA64ISAR0_EL1_op0 0x3 327 #define ID_AA64ISAR0_EL1_op1 0x0 328 #define ID_AA64ISAR0_EL1_CRn 0x0 329 #define ID_AA64ISAR0_EL1_CRm 0x6 330 #define ID_AA64ISAR0_EL1_op2 0x0 331 #define ID_AA64ISAR0_AES_SHIFT 4 332 #define ID_AA64ISAR0_AES_MASK (UL(0xf) << ID_AA64ISAR0_AES_SHIFT) 333 #define ID_AA64ISAR0_AES_VAL(x) ((x) & ID_AA64ISAR0_AES_MASK) 334 #define ID_AA64ISAR0_AES_NONE (UL(0x0) << ID_AA64ISAR0_AES_SHIFT) 335 #define ID_AA64ISAR0_AES_BASE (UL(0x1) << ID_AA64ISAR0_AES_SHIFT) 336 #define ID_AA64ISAR0_AES_PMULL (UL(0x2) << ID_AA64ISAR0_AES_SHIFT) 337 #define ID_AA64ISAR0_SHA1_SHIFT 8 338 #define ID_AA64ISAR0_SHA1_MASK (UL(0xf) << ID_AA64ISAR0_SHA1_SHIFT) 339 #define ID_AA64ISAR0_SHA1_VAL(x) ((x) & ID_AA64ISAR0_SHA1_MASK) 340 #define ID_AA64ISAR0_SHA1_NONE (UL(0x0) << ID_AA64ISAR0_SHA1_SHIFT) 341 #define ID_AA64ISAR0_SHA1_BASE (UL(0x1) << ID_AA64ISAR0_SHA1_SHIFT) 342 #define ID_AA64ISAR0_SHA2_SHIFT 12 343 #define ID_AA64ISAR0_SHA2_MASK (UL(0xf) << ID_AA64ISAR0_SHA2_SHIFT) 344 #define ID_AA64ISAR0_SHA2_VAL(x) ((x) & ID_AA64ISAR0_SHA2_MASK) 345 #define ID_AA64ISAR0_SHA2_NONE (UL(0x0) << ID_AA64ISAR0_SHA2_SHIFT) 346 #define ID_AA64ISAR0_SHA2_BASE (UL(0x1) << ID_AA64ISAR0_SHA2_SHIFT) 347 #define ID_AA64ISAR0_SHA2_512 (UL(0x2) << ID_AA64ISAR0_SHA2_SHIFT) 348 #define ID_AA64ISAR0_CRC32_SHIFT 16 349 #define ID_AA64ISAR0_CRC32_MASK (UL(0xf) << ID_AA64ISAR0_CRC32_SHIFT) 350 #define ID_AA64ISAR0_CRC32_VAL(x) ((x) & ID_AA64ISAR0_CRC32_MASK) 351 #define ID_AA64ISAR0_CRC32_NONE (UL(0x0) << ID_AA64ISAR0_CRC32_SHIFT) 352 #define ID_AA64ISAR0_CRC32_BASE (UL(0x1) << ID_AA64ISAR0_CRC32_SHIFT) 353 #define ID_AA64ISAR0_Atomic_SHIFT 20 354 #define ID_AA64ISAR0_Atomic_MASK (UL(0xf) << ID_AA64ISAR0_Atomic_SHIFT) 355 #define ID_AA64ISAR0_Atomic_VAL(x) ((x) & ID_AA64ISAR0_Atomic_MASK) 356 #define ID_AA64ISAR0_Atomic_NONE (UL(0x0) << ID_AA64ISAR0_Atomic_SHIFT) 357 #define ID_AA64ISAR0_Atomic_IMPL (UL(0x2) << ID_AA64ISAR0_Atomic_SHIFT) 358 #define ID_AA64ISAR0_RDM_SHIFT 28 359 #define ID_AA64ISAR0_RDM_MASK (UL(0xf) << ID_AA64ISAR0_RDM_SHIFT) 360 #define ID_AA64ISAR0_RDM_VAL(x) ((x) & ID_AA64ISAR0_RDM_MASK) 361 #define ID_AA64ISAR0_RDM_NONE (UL(0x0) << ID_AA64ISAR0_RDM_SHIFT) 362 #define ID_AA64ISAR0_RDM_IMPL (UL(0x1) << ID_AA64ISAR0_RDM_SHIFT) 363 #define ID_AA64ISAR0_SHA3_SHIFT 32 364 #define ID_AA64ISAR0_SHA3_MASK (UL(0xf) << ID_AA64ISAR0_SHA3_SHIFT) 365 #define ID_AA64ISAR0_SHA3_VAL(x) ((x) & ID_AA64ISAR0_SHA3_MASK) 366 #define ID_AA64ISAR0_SHA3_NONE (UL(0x0) << ID_AA64ISAR0_SHA3_SHIFT) 367 #define ID_AA64ISAR0_SHA3_IMPL (UL(0x1) << ID_AA64ISAR0_SHA3_SHIFT) 368 #define ID_AA64ISAR0_SM3_SHIFT 36 369 #define ID_AA64ISAR0_SM3_MASK (UL(0xf) << ID_AA64ISAR0_SM3_SHIFT) 370 #define ID_AA64ISAR0_SM3_VAL(x) ((x) & ID_AA64ISAR0_SM3_MASK) 371 #define ID_AA64ISAR0_SM3_NONE (UL(0x0) << ID_AA64ISAR0_SM3_SHIFT) 372 #define ID_AA64ISAR0_SM3_IMPL (UL(0x1) << ID_AA64ISAR0_SM3_SHIFT) 373 #define ID_AA64ISAR0_SM4_SHIFT 40 374 #define ID_AA64ISAR0_SM4_MASK (UL(0xf) << ID_AA64ISAR0_SM4_SHIFT) 375 #define ID_AA64ISAR0_SM4_VAL(x) ((x) & ID_AA64ISAR0_SM4_MASK) 376 #define ID_AA64ISAR0_SM4_NONE (UL(0x0) << ID_AA64ISAR0_SM4_SHIFT) 377 #define ID_AA64ISAR0_SM4_IMPL (UL(0x1) << ID_AA64ISAR0_SM4_SHIFT) 378 #define ID_AA64ISAR0_DP_SHIFT 44 379 #define ID_AA64ISAR0_DP_MASK (UL(0xf) << ID_AA64ISAR0_DP_SHIFT) 380 #define ID_AA64ISAR0_DP_VAL(x) ((x) & ID_AA64ISAR0_DP_MASK) 381 #define ID_AA64ISAR0_DP_NONE (UL(0x0) << ID_AA64ISAR0_DP_SHIFT) 382 #define ID_AA64ISAR0_DP_IMPL (UL(0x1) << ID_AA64ISAR0_DP_SHIFT) 383 #define ID_AA64ISAR0_FHM_SHIFT 48 384 #define ID_AA64ISAR0_FHM_MASK (UL(0xf) << ID_AA64ISAR0_FHM_SHIFT) 385 #define ID_AA64ISAR0_FHM_VAL(x) ((x) & ID_AA64ISAR0_FHM_MASK) 386 #define ID_AA64ISAR0_FHM_NONE (UL(0x0) << ID_AA64ISAR0_FHM_SHIFT) 387 #define ID_AA64ISAR0_FHM_IMPL (UL(0x1) << ID_AA64ISAR0_FHM_SHIFT) 388 #define ID_AA64ISAR0_TS_SHIFT 52 389 #define ID_AA64ISAR0_TS_MASK (UL(0xf) << ID_AA64ISAR0_TS_SHIFT) 390 #define ID_AA64ISAR0_TS_VAL(x) ((x) & ID_AA64ISAR0_TS_MASK) 391 #define ID_AA64ISAR0_TS_NONE (UL(0x0) << ID_AA64ISAR0_TS_SHIFT) 392 #define ID_AA64ISAR0_TS_CondM_8_4 (UL(0x1) << ID_AA64ISAR0_TS_SHIFT) 393 #define ID_AA64ISAR0_TS_CondM_8_5 (UL(0x2) << ID_AA64ISAR0_TS_SHIFT) 394 #define ID_AA64ISAR0_TLB_SHIFT 56 395 #define ID_AA64ISAR0_TLB_MASK (UL(0xf) << ID_AA64ISAR0_TLB_SHIFT) 396 #define ID_AA64ISAR0_TLB_VAL(x) ((x) & ID_AA64ISAR0_TLB_MASK) 397 #define ID_AA64ISAR0_TLB_NONE (UL(0x0) << ID_AA64ISAR0_TLB_SHIFT) 398 #define ID_AA64ISAR0_TLB_TLBIOS (UL(0x1) << ID_AA64ISAR0_TLB_SHIFT) 399 #define ID_AA64ISAR0_TLB_TLBIOSR (UL(0x2) << ID_AA64ISAR0_TLB_SHIFT) 400 #define ID_AA64ISAR0_RNDR_SHIFT 60 401 #define ID_AA64ISAR0_RNDR_MASK (UL(0xf) << ID_AA64ISAR0_RNDR_SHIFT) 402 #define ID_AA64ISAR0_RNDR_VAL(x) ((x) & ID_AA64ISAR0_RNDR_MASK) 403 #define ID_AA64ISAR0_RNDR_NONE (UL(0x0) << ID_AA64ISAR0_RNDR_SHIFT) 404 #define ID_AA64ISAR0_RNDR_IMPL (UL(0x1) << ID_AA64ISAR0_RNDR_SHIFT) 405 406 /* ID_AA64ISAR1_EL1 */ 407 #define ID_AA64ISAR1_EL1 MRS_REG(ID_AA64ISAR1_EL1) 408 #define ID_AA64ISAR1_EL1_op0 0x3 409 #define ID_AA64ISAR1_EL1_op1 0x0 410 #define ID_AA64ISAR1_EL1_CRn 0x0 411 #define ID_AA64ISAR1_EL1_CRm 0x6 412 #define ID_AA64ISAR1_EL1_op2 0x1 413 #define ID_AA64ISAR1_DPB_SHIFT 0 414 #define ID_AA64ISAR1_DPB_MASK (UL(0xf) << ID_AA64ISAR1_DPB_SHIFT) 415 #define ID_AA64ISAR1_DPB_VAL(x) ((x) & ID_AA64ISAR1_DPB_MASK) 416 #define ID_AA64ISAR1_DPB_NONE (UL(0x0) << ID_AA64ISAR1_DPB_SHIFT) 417 #define ID_AA64ISAR1_DPB_DCCVAP (UL(0x1) << ID_AA64ISAR1_DPB_SHIFT) 418 #define ID_AA64ISAR1_DPB_DCCVADP (UL(0x2) << ID_AA64ISAR1_DPB_SHIFT) 419 #define ID_AA64ISAR1_APA_SHIFT 4 420 #define ID_AA64ISAR1_APA_MASK (UL(0xf) << ID_AA64ISAR1_APA_SHIFT) 421 #define ID_AA64ISAR1_APA_VAL(x) ((x) & ID_AA64ISAR1_APA_MASK) 422 #define ID_AA64ISAR1_APA_NONE (UL(0x0) << ID_AA64ISAR1_APA_SHIFT) 423 #define ID_AA64ISAR1_APA_PAC (UL(0x1) << ID_AA64ISAR1_APA_SHIFT) 424 #define ID_AA64ISAR1_APA_EPAC (UL(0x2) << ID_AA64ISAR1_APA_SHIFT) 425 #define ID_AA64ISAR1_API_SHIFT 8 426 #define ID_AA64ISAR1_API_MASK (UL(0xf) << ID_AA64ISAR1_API_SHIFT) 427 #define ID_AA64ISAR1_API_VAL(x) ((x) & ID_AA64ISAR1_API_MASK) 428 #define ID_AA64ISAR1_API_NONE (UL(0x0) << ID_AA64ISAR1_API_SHIFT) 429 #define ID_AA64ISAR1_API_PAC (UL(0x1) << ID_AA64ISAR1_API_SHIFT) 430 #define ID_AA64ISAR1_API_EPAC (UL(0x2) << ID_AA64ISAR1_API_SHIFT) 431 #define ID_AA64ISAR1_JSCVT_SHIFT 12 432 #define ID_AA64ISAR1_JSCVT_MASK (UL(0xf) << ID_AA64ISAR1_JSCVT_SHIFT) 433 #define ID_AA64ISAR1_JSCVT_VAL(x) ((x) & ID_AA64ISAR1_JSCVT_MASK) 434 #define ID_AA64ISAR1_JSCVT_NONE (UL(0x0) << ID_AA64ISAR1_JSCVT_SHIFT) 435 #define ID_AA64ISAR1_JSCVT_IMPL (UL(0x1) << ID_AA64ISAR1_JSCVT_SHIFT) 436 #define ID_AA64ISAR1_FCMA_SHIFT 16 437 #define ID_AA64ISAR1_FCMA_MASK (UL(0xf) << ID_AA64ISAR1_FCMA_SHIFT) 438 #define ID_AA64ISAR1_FCMA_VAL(x) ((x) & ID_AA64ISAR1_FCMA_MASK) 439 #define ID_AA64ISAR1_FCMA_NONE (UL(0x0) << ID_AA64ISAR1_FCMA_SHIFT) 440 #define ID_AA64ISAR1_FCMA_IMPL (UL(0x1) << ID_AA64ISAR1_FCMA_SHIFT) 441 #define ID_AA64ISAR1_LRCPC_SHIFT 20 442 #define ID_AA64ISAR1_LRCPC_MASK (UL(0xf) << ID_AA64ISAR1_LRCPC_SHIFT) 443 #define ID_AA64ISAR1_LRCPC_VAL(x) ((x) & ID_AA64ISAR1_LRCPC_MASK) 444 #define ID_AA64ISAR1_LRCPC_NONE (UL(0x0) << ID_AA64ISAR1_LRCPC_SHIFT) 445 #define ID_AA64ISAR1_LRCPC_RCPC_8_3 (UL(0x1) << ID_AA64ISAR1_LRCPC_SHIFT) 446 #define ID_AA64ISAR1_LRCPC_RCPC_8_4 (UL(0x2) << ID_AA64ISAR1_LRCPC_SHIFT) 447 #define ID_AA64ISAR1_GPA_SHIFT 24 448 #define ID_AA64ISAR1_GPA_MASK (UL(0xf) << ID_AA64ISAR1_GPA_SHIFT) 449 #define ID_AA64ISAR1_GPA_VAL(x) ((x) & ID_AA64ISAR1_GPA_MASK) 450 #define ID_AA64ISAR1_GPA_NONE (UL(0x0) << ID_AA64ISAR1_GPA_SHIFT) 451 #define ID_AA64ISAR1_GPA_IMPL (UL(0x1) << ID_AA64ISAR1_GPA_SHIFT) 452 #define ID_AA64ISAR1_GPI_SHIFT 28 453 #define ID_AA64ISAR1_GPI_MASK (UL(0xf) << ID_AA64ISAR1_GPI_SHIFT) 454 #define ID_AA64ISAR1_GPI_VAL(x) ((x) & ID_AA64ISAR1_GPI_MASK) 455 #define ID_AA64ISAR1_GPI_NONE (UL(0x0) << ID_AA64ISAR1_GPI_SHIFT) 456 #define ID_AA64ISAR1_GPI_IMPL (UL(0x1) << ID_AA64ISAR1_GPI_SHIFT) 457 #define ID_AA64ISAR1_FRINTTS_SHIFT 32 458 #define ID_AA64ISAR1_FRINTTS_MASK (UL(0xf) << ID_AA64ISAR1_FRINTTS_SHIFT) 459 #define ID_AA64ISAR1_FRINTTS_VAL(x) ((x) & ID_AA64ISAR1_FRINTTS_MASK) 460 #define ID_AA64ISAR1_FRINTTS_NONE (UL(0x0) << ID_AA64ISAR1_FRINTTS_SHIFT) 461 #define ID_AA64ISAR1_FRINTTS_IMPL (UL(0x1) << ID_AA64ISAR1_FRINTTS_SHIFT) 462 #define ID_AA64ISAR1_SB_SHIFT 36 463 #define ID_AA64ISAR1_SB_MASK (UL(0xf) << ID_AA64ISAR1_SB_SHIFT) 464 #define ID_AA64ISAR1_SB_VAL(x) ((x) & ID_AA64ISAR1_SB_MASK) 465 #define ID_AA64ISAR1_SB_NONE (UL(0x0) << ID_AA64ISAR1_SB_SHIFT) 466 #define ID_AA64ISAR1_SB_IMPL (UL(0x1) << ID_AA64ISAR1_SB_SHIFT) 467 #define ID_AA64ISAR1_SPECRES_SHIFT 40 468 #define ID_AA64ISAR1_SPECRES_MASK (UL(0xf) << ID_AA64ISAR1_SPECRES_SHIFT) 469 #define ID_AA64ISAR1_SPECRES_VAL(x) ((x) & ID_AA64ISAR1_SPECRES_MASK) 470 #define ID_AA64ISAR1_SPECRES_NONE (UL(0x0) << ID_AA64ISAR1_SPECRES_SHIFT) 471 #define ID_AA64ISAR1_SPECRES_IMPL (UL(0x1) << ID_AA64ISAR1_SPECRES_SHIFT) 472 #define ID_AA64ISAR1_BF16_SHIFT 44 473 #define ID_AA64ISAR1_BF16_MASK (UL(0xf) << ID_AA64ISAR1_BF16_SHIFT) 474 #define ID_AA64ISAR1_BF16_VAL(x) ((x) & ID_AA64ISAR1_BF16_MASK) 475 #define ID_AA64ISAR1_BF16_NONE (UL(0x0) << ID_AA64ISAR1_BF16_SHIFT) 476 #define ID_AA64ISAR1_BF16_IMPL (UL(0x1) << ID_AA64ISAR1_BF16_SHIFT) 477 #define ID_AA64ISAR1_DGH_SHIFT 48 478 #define ID_AA64ISAR1_DGH_MASK (UL(0xf) << ID_AA64ISAR1_DGH_SHIFT) 479 #define ID_AA64ISAR1_DGH_VAL(x) ((x) & ID_AA64ISAR1_DGH_MASK) 480 #define ID_AA64ISAR1_DGH_NONE (UL(0x0) << ID_AA64ISAR1_DGH_SHIFT) 481 #define ID_AA64ISAR1_DGH_IMPL (UL(0x1) << ID_AA64ISAR1_DGH_SHIFT) 482 #define ID_AA64ISAR1_I8MM_SHIFT 52 483 #define ID_AA64ISAR1_I8MM_MASK (UL(0xf) << ID_AA64ISAR1_I8MM_SHIFT) 484 #define ID_AA64ISAR1_I8MM_VAL(x) ((x) & ID_AA64ISAR1_I8MM_MASK) 485 #define ID_AA64ISAR1_I8MM_NONE (UL(0x0) << ID_AA64ISAR1_I8MM_SHIFT) 486 #define ID_AA64ISAR1_I8MM_IMPL (UL(0x1) << ID_AA64ISAR1_I8MM_SHIFT) 487 488 /* ID_AA64MMFR0_EL1 */ 489 #define ID_AA64MMFR0_EL1 MRS_REG(ID_AA64MMFR0_EL1) 490 #define ID_AA64MMFR0_EL1_op0 0x3 491 #define ID_AA64MMFR0_EL1_op1 0x0 492 #define ID_AA64MMFR0_EL1_CRn 0x0 493 #define ID_AA64MMFR0_EL1_CRm 0x7 494 #define ID_AA64MMFR0_EL1_op2 0x0 495 #define ID_AA64MMFR0_PARange_SHIFT 0 496 #define ID_AA64MMFR0_PARange_MASK (UL(0xf) << ID_AA64MMFR0_PARange_SHIFT) 497 #define ID_AA64MMFR0_PARange_VAL(x) ((x) & ID_AA64MMFR0_PARange_MASK) 498 #define ID_AA64MMFR0_PARange_4G (UL(0x0) << ID_AA64MMFR0_PARange_SHIFT) 499 #define ID_AA64MMFR0_PARange_64G (UL(0x1) << ID_AA64MMFR0_PARange_SHIFT) 500 #define ID_AA64MMFR0_PARange_1T (UL(0x2) << ID_AA64MMFR0_PARange_SHIFT) 501 #define ID_AA64MMFR0_PARange_4T (UL(0x3) << ID_AA64MMFR0_PARange_SHIFT) 502 #define ID_AA64MMFR0_PARange_16T (UL(0x4) << ID_AA64MMFR0_PARange_SHIFT) 503 #define ID_AA64MMFR0_PARange_256T (UL(0x5) << ID_AA64MMFR0_PARange_SHIFT) 504 #define ID_AA64MMFR0_PARange_4P (UL(0x6) << ID_AA64MMFR0_PARange_SHIFT) 505 #define ID_AA64MMFR0_ASIDBits_SHIFT 4 506 #define ID_AA64MMFR0_ASIDBits_MASK (UL(0xf) << ID_AA64MMFR0_ASIDBits_SHIFT) 507 #define ID_AA64MMFR0_ASIDBits_VAL(x) ((x) & ID_AA64MMFR0_ASIDBits_MASK) 508 #define ID_AA64MMFR0_ASIDBits_8 (UL(0x0) << ID_AA64MMFR0_ASIDBits_SHIFT) 509 #define ID_AA64MMFR0_ASIDBits_16 (UL(0x2) << ID_AA64MMFR0_ASIDBits_SHIFT) 510 #define ID_AA64MMFR0_BigEnd_SHIFT 8 511 #define ID_AA64MMFR0_BigEnd_MASK (UL(0xf) << ID_AA64MMFR0_BigEnd_SHIFT) 512 #define ID_AA64MMFR0_BigEnd_VAL(x) ((x) & ID_AA64MMFR0_BigEnd_MASK) 513 #define ID_AA64MMFR0_BigEnd_FIXED (UL(0x0) << ID_AA64MMFR0_BigEnd_SHIFT) 514 #define ID_AA64MMFR0_BigEnd_MIXED (UL(0x1) << ID_AA64MMFR0_BigEnd_SHIFT) 515 #define ID_AA64MMFR0_SNSMem_SHIFT 12 516 #define ID_AA64MMFR0_SNSMem_MASK (UL(0xf) << ID_AA64MMFR0_SNSMem_SHIFT) 517 #define ID_AA64MMFR0_SNSMem_VAL(x) ((x) & ID_AA64MMFR0_SNSMem_MASK) 518 #define ID_AA64MMFR0_SNSMem_NONE (UL(0x0) << ID_AA64MMFR0_SNSMem_SHIFT) 519 #define ID_AA64MMFR0_SNSMem_DISTINCT (UL(0x1) << ID_AA64MMFR0_SNSMem_SHIFT) 520 #define ID_AA64MMFR0_BigEndEL0_SHIFT 16 521 #define ID_AA64MMFR0_BigEndEL0_MASK (UL(0xf) << ID_AA64MMFR0_BigEndEL0_SHIFT) 522 #define ID_AA64MMFR0_BigEndEL0_VAL(x) ((x) & ID_AA64MMFR0_BigEndEL0_MASK) 523 #define ID_AA64MMFR0_BigEndEL0_FIXED (UL(0x0) << ID_AA64MMFR0_BigEndEL0_SHIFT) 524 #define ID_AA64MMFR0_BigEndEL0_MIXED (UL(0x1) << ID_AA64MMFR0_BigEndEL0_SHIFT) 525 #define ID_AA64MMFR0_TGran16_SHIFT 20 526 #define ID_AA64MMFR0_TGran16_MASK (UL(0xf) << ID_AA64MMFR0_TGran16_SHIFT) 527 #define ID_AA64MMFR0_TGran16_VAL(x) ((x) & ID_AA64MMFR0_TGran16_MASK) 528 #define ID_AA64MMFR0_TGran16_NONE (UL(0x0) << ID_AA64MMFR0_TGran16_SHIFT) 529 #define ID_AA64MMFR0_TGran16_IMPL (UL(0x1) << ID_AA64MMFR0_TGran16_SHIFT) 530 #define ID_AA64MMFR0_TGran64_SHIFT 24 531 #define ID_AA64MMFR0_TGran64_MASK (UL(0xf) << ID_AA64MMFR0_TGran64_SHIFT) 532 #define ID_AA64MMFR0_TGran64_VAL(x) ((x) & ID_AA64MMFR0_TGran64_MASK) 533 #define ID_AA64MMFR0_TGran64_IMPL (UL(0x0) << ID_AA64MMFR0_TGran64_SHIFT) 534 #define ID_AA64MMFR0_TGran64_NONE (UL(0xf) << ID_AA64MMFR0_TGran64_SHIFT) 535 #define ID_AA64MMFR0_TGran4_SHIFT 28 536 #define ID_AA64MMFR0_TGran4_MASK (UL(0xf) << ID_AA64MMFR0_TGran4_SHIFT) 537 #define ID_AA64MMFR0_TGran4_VAL(x) ((x) & ID_AA64MMFR0_TGran4_MASK) 538 #define ID_AA64MMFR0_TGran4_IMPL (UL(0x0) << ID_AA64MMFR0_TGran4_SHIFT) 539 #define ID_AA64MMFR0_TGran4_NONE (UL(0xf) << ID_AA64MMFR0_TGran4_SHIFT) 540 #define ID_AA64MMFR0_TGran16_2_SHIFT 32 541 #define ID_AA64MMFR0_TGran16_2_MASK (UL(0xf) << ID_AA64MMFR0_TGran16_2_SHIFT) 542 #define ID_AA64MMFR0_TGran16_2_VAL(x) ((x) & ID_AA64MMFR0_TGran16_2_MASK) 543 #define ID_AA64MMFR0_TGran16_2_TGran16 (UL(0x0) << ID_AA64MMFR0_TGran16_2_SHIFT) 544 #define ID_AA64MMFR0_TGran16_2_NONE (UL(0x1) << ID_AA64MMFR0_TGran16_2_SHIFT) 545 #define ID_AA64MMFR0_TGran16_2_IMPL (UL(0x2) << ID_AA64MMFR0_TGran16_2_SHIFT) 546 #define ID_AA64MMFR0_TGran64_2_SHIFT 36 547 #define ID_AA64MMFR0_TGran64_2_MASK (UL(0xf) << ID_AA64MMFR0_TGran64_2_SHIFT) 548 #define ID_AA64MMFR0_TGran64_2_VAL(x) ((x) & ID_AA64MMFR0_TGran64_2_MASK) 549 #define ID_AA64MMFR0_TGran64_2_TGran64 (UL(0x0) << ID_AA64MMFR0_TGran64_2_SHIFT) 550 #define ID_AA64MMFR0_TGran64_2_NONE (UL(0x1) << ID_AA64MMFR0_TGran64_2_SHIFT) 551 #define ID_AA64MMFR0_TGran64_2_IMPL (UL(0x2) << ID_AA64MMFR0_TGran64_2_SHIFT) 552 #define ID_AA64MMFR0_TGran4_2_SHIFT 40 553 #define ID_AA64MMFR0_TGran4_2_MASK (UL(0xf) << ID_AA64MMFR0_TGran4_2_SHIFT) 554 #define ID_AA64MMFR0_TGran4_2_VAL(x) ((x) & ID_AA64MMFR0_TGran4_2_MASK) 555 #define ID_AA64MMFR0_TGran4_2_TGran4 (UL(0x0) << ID_AA64MMFR0_TGran4_2_SHIFT) 556 #define ID_AA64MMFR0_TGran4_2_NONE (UL(0x1) << ID_AA64MMFR0_TGran4_2_SHIFT) 557 #define ID_AA64MMFR0_TGran4_2_IMPL (UL(0x2) << ID_AA64MMFR0_TGran4_2_SHIFT) 558 #define ID_AA64MMFR0_ExS_SHIFT 44 559 #define ID_AA64MMFR0_ExS_MASK (UL(0xf) << ID_AA64MMFR0_ExS_SHIFT) 560 #define ID_AA64MMFR0_ExS_VAL(x) ((x) & ID_AA64MMFR0_ExS_MASK) 561 #define ID_AA64MMFR0_ExS_ALL (UL(0x0) << ID_AA64MMFR0_ExS_SHIFT) 562 #define ID_AA64MMFR0_ExS_IMPL (UL(0x1) << ID_AA64MMFR0_ExS_SHIFT) 563 564 /* ID_AA64MMFR1_EL1 */ 565 #define ID_AA64MMFR1_EL1 MRS_REG(ID_AA64MMFR1_EL1) 566 #define ID_AA64MMFR1_EL1_op0 0x3 567 #define ID_AA64MMFR1_EL1_op1 0x0 568 #define ID_AA64MMFR1_EL1_CRn 0x0 569 #define ID_AA64MMFR1_EL1_CRm 0x7 570 #define ID_AA64MMFR1_EL1_op2 0x1 571 #define ID_AA64MMFR1_HAFDBS_SHIFT 0 572 #define ID_AA64MMFR1_HAFDBS_MASK (UL(0xf) << ID_AA64MMFR1_HAFDBS_SHIFT) 573 #define ID_AA64MMFR1_HAFDBS_VAL(x) ((x) & ID_AA64MMFR1_HAFDBS_MASK) 574 #define ID_AA64MMFR1_HAFDBS_NONE (UL(0x0) << ID_AA64MMFR1_HAFDBS_SHIFT) 575 #define ID_AA64MMFR1_HAFDBS_AF (UL(0x1) << ID_AA64MMFR1_HAFDBS_SHIFT) 576 #define ID_AA64MMFR1_HAFDBS_AF_DBS (UL(0x2) << ID_AA64MMFR1_HAFDBS_SHIFT) 577 #define ID_AA64MMFR1_VMIDBits_SHIFT 4 578 #define ID_AA64MMFR1_VMIDBits_MASK (UL(0xf) << ID_AA64MMFR1_VMIDBits_SHIFT) 579 #define ID_AA64MMFR1_VMIDBits_VAL(x) ((x) & ID_AA64MMFR1_VMIDBits_MASK) 580 #define ID_AA64MMFR1_VMIDBits_8 (UL(0x0) << ID_AA64MMFR1_VMIDBits_SHIFT) 581 #define ID_AA64MMFR1_VMIDBits_16 (UL(0x2) << ID_AA64MMFR1_VMIDBits_SHIFT) 582 #define ID_AA64MMFR1_VH_SHIFT 8 583 #define ID_AA64MMFR1_VH_MASK (UL(0xf) << ID_AA64MMFR1_VH_SHIFT) 584 #define ID_AA64MMFR1_VH_VAL(x) ((x) & ID_AA64MMFR1_VH_MASK) 585 #define ID_AA64MMFR1_VH_NONE (UL(0x0) << ID_AA64MMFR1_VH_SHIFT) 586 #define ID_AA64MMFR1_VH_IMPL (UL(0x1) << ID_AA64MMFR1_VH_SHIFT) 587 #define ID_AA64MMFR1_HPDS_SHIFT 12 588 #define ID_AA64MMFR1_HPDS_MASK (UL(0xf) << ID_AA64MMFR1_HPDS_SHIFT) 589 #define ID_AA64MMFR1_HPDS_VAL(x) ((x) & ID_AA64MMFR1_HPDS_MASK) 590 #define ID_AA64MMFR1_HPDS_NONE (UL(0x0) << ID_AA64MMFR1_HPDS_SHIFT) 591 #define ID_AA64MMFR1_HPDS_HPD (UL(0x1) << ID_AA64MMFR1_HPDS_SHIFT) 592 #define ID_AA64MMFR1_HPDS_TTPBHA (UL(0x2) << ID_AA64MMFR1_HPDS_SHIFT) 593 #define ID_AA64MMFR1_LO_SHIFT 16 594 #define ID_AA64MMFR1_LO_MASK (UL(0xf) << ID_AA64MMFR1_LO_SHIFT) 595 #define ID_AA64MMFR1_LO_VAL(x) ((x) & ID_AA64MMFR1_LO_MASK) 596 #define ID_AA64MMFR1_LO_NONE (UL(0x0) << ID_AA64MMFR1_LO_SHIFT) 597 #define ID_AA64MMFR1_LO_IMPL (UL(0x1) << ID_AA64MMFR1_LO_SHIFT) 598 #define ID_AA64MMFR1_PAN_SHIFT 20 599 #define ID_AA64MMFR1_PAN_MASK (UL(0xf) << ID_AA64MMFR1_PAN_SHIFT) 600 #define ID_AA64MMFR1_PAN_VAL(x) ((x) & ID_AA64MMFR1_PAN_MASK) 601 #define ID_AA64MMFR1_PAN_NONE (UL(0x0) << ID_AA64MMFR1_PAN_SHIFT) 602 #define ID_AA64MMFR1_PAN_IMPL (UL(0x1) << ID_AA64MMFR1_PAN_SHIFT) 603 #define ID_AA64MMFR1_PAN_ATS1E1 (UL(0x2) << ID_AA64MMFR1_PAN_SHIFT) 604 #define ID_AA64MMFR1_SpecSEI_SHIFT 24 605 #define ID_AA64MMFR1_SpecSEI_MASK (UL(0xf) << ID_AA64MMFR1_SpecSEI_SHIFT) 606 #define ID_AA64MMFR1_SpecSEI_VAL(x) ((x) & ID_AA64MMFR1_SpecSEI_MASK) 607 #define ID_AA64MMFR1_SpecSEI_NONE (UL(0x0) << ID_AA64MMFR1_SpecSEI_SHIFT) 608 #define ID_AA64MMFR1_SpecSEI_IMPL (UL(0x1) << ID_AA64MMFR1_SpecSEI_SHIFT) 609 #define ID_AA64MMFR1_XNX_SHIFT 28 610 #define ID_AA64MMFR1_XNX_MASK (UL(0xf) << ID_AA64MMFR1_XNX_SHIFT) 611 #define ID_AA64MMFR1_XNX_VAL(x) ((x) & ID_AA64MMFR1_XNX_MASK) 612 #define ID_AA64MMFR1_XNX_NONE (UL(0x0) << ID_AA64MMFR1_XNX_SHIFT) 613 #define ID_AA64MMFR1_XNX_IMPL (UL(0x1) << ID_AA64MMFR1_XNX_SHIFT) 614 615 /* ID_AA64MMFR2_EL1 */ 616 #define ID_AA64MMFR2_EL1 MRS_REG(ID_AA64MMFR2_EL1) 617 #define ID_AA64MMFR2_EL1_op0 0x3 618 #define ID_AA64MMFR2_EL1_op1 0x0 619 #define ID_AA64MMFR2_EL1_CRn 0x0 620 #define ID_AA64MMFR2_EL1_CRm 0x7 621 #define ID_AA64MMFR2_EL1_op2 0x2 622 #define ID_AA64MMFR2_CnP_SHIFT 0 623 #define ID_AA64MMFR2_CnP_MASK (UL(0xf) << ID_AA64MMFR2_CnP_SHIFT) 624 #define ID_AA64MMFR2_CnP_VAL(x) ((x) & ID_AA64MMFR2_CnP_MASK) 625 #define ID_AA64MMFR2_CnP_NONE (UL(0x0) << ID_AA64MMFR2_CnP_SHIFT) 626 #define ID_AA64MMFR2_CnP_IMPL (UL(0x1) << ID_AA64MMFR2_CnP_SHIFT) 627 #define ID_AA64MMFR2_UAO_SHIFT 4 628 #define ID_AA64MMFR2_UAO_MASK (UL(0xf) << ID_AA64MMFR2_UAO_SHIFT) 629 #define ID_AA64MMFR2_UAO_VAL(x) ((x) & ID_AA64MMFR2_UAO_MASK) 630 #define ID_AA64MMFR2_UAO_NONE (UL(0x0) << ID_AA64MMFR2_UAO_SHIFT) 631 #define ID_AA64MMFR2_UAO_IMPL (UL(0x1) << ID_AA64MMFR2_UAO_SHIFT) 632 #define ID_AA64MMFR2_LSM_SHIFT 8 633 #define ID_AA64MMFR2_LSM_MASK (UL(0xf) << ID_AA64MMFR2_LSM_SHIFT) 634 #define ID_AA64MMFR2_LSM_VAL(x) ((x) & ID_AA64MMFR2_LSM_MASK) 635 #define ID_AA64MMFR2_LSM_NONE (UL(0x0) << ID_AA64MMFR2_LSM_SHIFT) 636 #define ID_AA64MMFR2_LSM_IMPL (UL(0x1) << ID_AA64MMFR2_LSM_SHIFT) 637 #define ID_AA64MMFR2_IESB_SHIFT 12 638 #define ID_AA64MMFR2_IESB_MASK (UL(0xf) << ID_AA64MMFR2_IESB_SHIFT) 639 #define ID_AA64MMFR2_IESB_VAL(x) ((x) & ID_AA64MMFR2_IESB_MASK) 640 #define ID_AA64MMFR2_IESB_NONE (UL(0x0) << ID_AA64MMFR2_IESB_SHIFT) 641 #define ID_AA64MMFR2_IESB_IMPL (UL(0x1) << ID_AA64MMFR2_IESB_SHIFT) 642 #define ID_AA64MMFR2_VARange_SHIFT 16 643 #define ID_AA64MMFR2_VARange_MASK (UL(0xf) << ID_AA64MMFR2_VARange_SHIFT) 644 #define ID_AA64MMFR2_VARange_VAL(x) ((x) & ID_AA64MMFR2_VARange_MASK) 645 #define ID_AA64MMFR2_VARange_48 (UL(0x0) << ID_AA64MMFR2_VARange_SHIFT) 646 #define ID_AA64MMFR2_VARange_52 (UL(0x1) << ID_AA64MMFR2_VARange_SHIFT) 647 #define ID_AA64MMFR2_CCIDX_SHIFT 20 648 #define ID_AA64MMFR2_CCIDX_MASK (UL(0xf) << ID_AA64MMFR2_CCIDX_SHIFT) 649 #define ID_AA64MMFR2_CCIDX_VAL(x) ((x) & ID_AA64MMFR2_CCIDX_MASK) 650 #define ID_AA64MMFR2_CCIDX_32 (UL(0x0) << ID_AA64MMFR2_CCIDX_SHIFT) 651 #define ID_AA64MMFR2_CCIDX_64 (UL(0x1) << ID_AA64MMFR2_CCIDX_SHIFT) 652 #define ID_AA64MMFR2_NV_SHIFT 24 653 #define ID_AA64MMFR2_NV_MASK (UL(0xf) << ID_AA64MMFR2_NV_SHIFT) 654 #define ID_AA64MMFR2_NV_VAL(x) ((x) & ID_AA64MMFR2_NV_MASK) 655 #define ID_AA64MMFR2_NV_NONE (UL(0x0) << ID_AA64MMFR2_NV_SHIFT) 656 #define ID_AA64MMFR2_NV_8_3 (UL(0x1) << ID_AA64MMFR2_NV_SHIFT) 657 #define ID_AA64MMFR2_NV_8_4 (UL(0x2) << ID_AA64MMFR2_NV_SHIFT) 658 #define ID_AA64MMFR2_ST_SHIFT 28 659 #define ID_AA64MMFR2_ST_MASK (UL(0xf) << ID_AA64MMFR2_ST_SHIFT) 660 #define ID_AA64MMFR2_ST_VAL(x) ((x) & ID_AA64MMFR2_ST_MASK) 661 #define ID_AA64MMFR2_ST_NONE (UL(0x0) << ID_AA64MMFR2_ST_SHIFT) 662 #define ID_AA64MMFR2_ST_IMPL (UL(0x1) << ID_AA64MMFR2_ST_SHIFT) 663 #define ID_AA64MMFR2_AT_SHIFT 32 664 #define ID_AA64MMFR2_AT_MASK (UL(0xf) << ID_AA64MMFR2_AT_SHIFT) 665 #define ID_AA64MMFR2_AT_VAL(x) ((x) & ID_AA64MMFR2_AT_MASK) 666 #define ID_AA64MMFR2_AT_NONE (UL(0x0) << ID_AA64MMFR2_AT_SHIFT) 667 #define ID_AA64MMFR2_AT_IMPL (UL(0x1) << ID_AA64MMFR2_AT_SHIFT) 668 #define ID_AA64MMFR2_IDS_SHIFT 36 669 #define ID_AA64MMFR2_IDS_MASK (UL(0xf) << ID_AA64MMFR2_IDS_SHIFT) 670 #define ID_AA64MMFR2_IDS_VAL(x) ((x) & ID_AA64MMFR2_IDS_MASK) 671 #define ID_AA64MMFR2_IDS_NONE (UL(0x0) << ID_AA64MMFR2_IDS_SHIFT) 672 #define ID_AA64MMFR2_IDS_IMPL (UL(0x1) << ID_AA64MMFR2_IDS_SHIFT) 673 #define ID_AA64MMFR2_FWB_SHIFT 40 674 #define ID_AA64MMFR2_FWB_MASK (UL(0xf) << ID_AA64MMFR2_FWB_SHIFT) 675 #define ID_AA64MMFR2_FWB_VAL(x) ((x) & ID_AA64MMFR2_FWB_MASK) 676 #define ID_AA64MMFR2_FWB_NONE (UL(0x0) << ID_AA64MMFR2_FWB_SHIFT) 677 #define ID_AA64MMFR2_FWB_IMPL (UL(0x1) << ID_AA64MMFR2_FWB_SHIFT) 678 #define ID_AA64MMFR2_TTL_SHIFT 48 679 #define ID_AA64MMFR2_TTL_MASK (UL(0xf) << ID_AA64MMFR2_TTL_SHIFT) 680 #define ID_AA64MMFR2_TTL_VAL(x) ((x) & ID_AA64MMFR2_TTL_MASK) 681 #define ID_AA64MMFR2_TTL_NONE (UL(0x0) << ID_AA64MMFR2_TTL_SHIFT) 682 #define ID_AA64MMFR2_TTL_IMPL (UL(0x1) << ID_AA64MMFR2_TTL_SHIFT) 683 #define ID_AA64MMFR2_BBM_SHIFT 52 684 #define ID_AA64MMFR2_BBM_MASK (UL(0xf) << ID_AA64MMFR2_BBM_SHIFT) 685 #define ID_AA64MMFR2_BBM_VAL(x) ((x) & ID_AA64MMFR2_BBM_MASK) 686 #define ID_AA64MMFR2_BBM_LEVEL0 (UL(0x0) << ID_AA64MMFR2_BBM_SHIFT) 687 #define ID_AA64MMFR2_BBM_LEVEL1 (UL(0x1) << ID_AA64MMFR2_BBM_SHIFT) 688 #define ID_AA64MMFR2_BBM_LEVEL2 (UL(0x2) << ID_AA64MMFR2_BBM_SHIFT) 689 #define ID_AA64MMFR2_EVT_SHIFT 56 690 #define ID_AA64MMFR2_EVT_MASK (UL(0xf) << ID_AA64MMFR2_EVT_SHIFT) 691 #define ID_AA64MMFR2_EVT_VAL(x) ((x) & ID_AA64MMFR2_EVT_MASK) 692 #define ID_AA64MMFR2_EVT_NONE (UL(0x0) << ID_AA64MMFR2_EVT_SHIFT) 693 #define ID_AA64MMFR2_EVT_8_2 (UL(0x1) << ID_AA64MMFR2_EVT_SHIFT) 694 #define ID_AA64MMFR2_EVT_8_5 (UL(0x2) << ID_AA64MMFR2_EVT_SHIFT) 695 #define ID_AA64MMFR2_E0PD_SHIFT 60 696 #define ID_AA64MMFR2_E0PD_MASK (UL(0xf) << ID_AA64MMFR2_E0PD_SHIFT) 697 #define ID_AA64MMFR2_E0PD_VAL(x) ((x) & ID_AA64MMFR2_E0PD_MASK) 698 #define ID_AA64MMFR2_E0PD_NONE (UL(0x0) << ID_AA64MMFR2_E0PD_SHIFT) 699 #define ID_AA64MMFR2_E0PD_IMPL (UL(0x1) << ID_AA64MMFR2_E0PD_SHIFT) 700 701 /* ID_AA64PFR0_EL1 */ 702 #define ID_AA64PFR0_EL1 MRS_REG(ID_AA64PFR0_EL1) 703 #define ID_AA64PFR0_EL1_op0 0x3 704 #define ID_AA64PFR0_EL1_op1 0x0 705 #define ID_AA64PFR0_EL1_CRn 0x0 706 #define ID_AA64PFR0_EL1_CRm 0x4 707 #define ID_AA64PFR0_EL1_op2 0x0 708 #define ID_AA64PFR0_EL0_SHIFT 0 709 #define ID_AA64PFR0_EL0_MASK (UL(0xf) << ID_AA64PFR0_EL0_SHIFT) 710 #define ID_AA64PFR0_EL0_VAL(x) ((x) & ID_AA64PFR0_EL0_MASK) 711 #define ID_AA64PFR0_EL0_64 (UL(0x1) << ID_AA64PFR0_EL0_SHIFT) 712 #define ID_AA64PFR0_EL0_64_32 (UL(0x2) << ID_AA64PFR0_EL0_SHIFT) 713 #define ID_AA64PFR0_EL1_SHIFT 4 714 #define ID_AA64PFR0_EL1_MASK (UL(0xf) << ID_AA64PFR0_EL1_SHIFT) 715 #define ID_AA64PFR0_EL1_VAL(x) ((x) & ID_AA64PFR0_EL1_MASK) 716 #define ID_AA64PFR0_EL1_64 (UL(0x1) << ID_AA64PFR0_EL1_SHIFT) 717 #define ID_AA64PFR0_EL1_64_32 (UL(0x2) << ID_AA64PFR0_EL1_SHIFT) 718 #define ID_AA64PFR0_EL2_SHIFT 8 719 #define ID_AA64PFR0_EL2_MASK (UL(0xf) << ID_AA64PFR0_EL2_SHIFT) 720 #define ID_AA64PFR0_EL2_VAL(x) ((x) & ID_AA64PFR0_EL2_MASK) 721 #define ID_AA64PFR0_EL2_NONE (UL(0x0) << ID_AA64PFR0_EL2_SHIFT) 722 #define ID_AA64PFR0_EL2_64 (UL(0x1) << ID_AA64PFR0_EL2_SHIFT) 723 #define ID_AA64PFR0_EL2_64_32 (UL(0x2) << ID_AA64PFR0_EL2_SHIFT) 724 #define ID_AA64PFR0_EL3_SHIFT 12 725 #define ID_AA64PFR0_EL3_MASK (UL(0xf) << ID_AA64PFR0_EL3_SHIFT) 726 #define ID_AA64PFR0_EL3_VAL(x) ((x) & ID_AA64PFR0_EL3_MASK) 727 #define ID_AA64PFR0_EL3_NONE (UL(0x0) << ID_AA64PFR0_EL3_SHIFT) 728 #define ID_AA64PFR0_EL3_64 (UL(0x1) << ID_AA64PFR0_EL3_SHIFT) 729 #define ID_AA64PFR0_EL3_64_32 (UL(0x2) << ID_AA64PFR0_EL3_SHIFT) 730 #define ID_AA64PFR0_FP_SHIFT 16 731 #define ID_AA64PFR0_FP_MASK (UL(0xf) << ID_AA64PFR0_FP_SHIFT) 732 #define ID_AA64PFR0_FP_VAL(x) ((x) & ID_AA64PFR0_FP_MASK) 733 #define ID_AA64PFR0_FP_IMPL (UL(0x0) << ID_AA64PFR0_FP_SHIFT) 734 #define ID_AA64PFR0_FP_HP (UL(0x1) << ID_AA64PFR0_FP_SHIFT) 735 #define ID_AA64PFR0_FP_NONE (UL(0xf) << ID_AA64PFR0_FP_SHIFT) 736 #define ID_AA64PFR0_AdvSIMD_SHIFT 20 737 #define ID_AA64PFR0_AdvSIMD_MASK (UL(0xf) << ID_AA64PFR0_AdvSIMD_SHIFT) 738 #define ID_AA64PFR0_AdvSIMD_VAL(x) ((x) & ID_AA64PFR0_AdvSIMD_MASK) 739 #define ID_AA64PFR0_AdvSIMD_IMPL (UL(0x0) << ID_AA64PFR0_AdvSIMD_SHIFT) 740 #define ID_AA64PFR0_AdvSIMD_HP (UL(0x1) << ID_AA64PFR0_AdvSIMD_SHIFT) 741 #define ID_AA64PFR0_AdvSIMD_NONE (UL(0xf) << ID_AA64PFR0_AdvSIMD_SHIFT) 742 #define ID_AA64PFR0_GIC_BITS 0x4 /* Number of bits in GIC field */ 743 #define ID_AA64PFR0_GIC_SHIFT 24 744 #define ID_AA64PFR0_GIC_MASK (UL(0xf) << ID_AA64PFR0_GIC_SHIFT) 745 #define ID_AA64PFR0_GIC_VAL(x) ((x) & ID_AA64PFR0_GIC_MASK) 746 #define ID_AA64PFR0_GIC_CPUIF_NONE (UL(0x0) << ID_AA64PFR0_GIC_SHIFT) 747 #define ID_AA64PFR0_GIC_CPUIF_EN (UL(0x1) << ID_AA64PFR0_GIC_SHIFT) 748 #define ID_AA64PFR0_RAS_SHIFT 28 749 #define ID_AA64PFR0_RAS_MASK (UL(0xf) << ID_AA64PFR0_RAS_SHIFT) 750 #define ID_AA64PFR0_RAS_VAL(x) ((x) & ID_AA64PFR0_RAS_MASK) 751 #define ID_AA64PFR0_RAS_NONE (UL(0x0) << ID_AA64PFR0_RAS_SHIFT) 752 #define ID_AA64PFR0_RAS_IMPL (UL(0x1) << ID_AA64PFR0_RAS_SHIFT) 753 #define ID_AA64PFR0_RAS_8_4 (UL(0x2) << ID_AA64PFR0_RAS_SHIFT) 754 #define ID_AA64PFR0_SVE_SHIFT 32 755 #define ID_AA64PFR0_SVE_MASK (UL(0xf) << ID_AA64PFR0_SVE_SHIFT) 756 #define ID_AA64PFR0_SVE_VAL(x) ((x) & ID_AA64PFR0_SVE_MASK) 757 #define ID_AA64PFR0_SVE_NONE (UL(0x0) << ID_AA64PFR0_SVE_SHIFT) 758 #define ID_AA64PFR0_SVE_IMPL (UL(0x1) << ID_AA64PFR0_SVE_SHIFT) 759 #define ID_AA64PFR0_SEL2_SHIFT 36 760 #define ID_AA64PFR0_SEL2_MASK (UL(0xf) << ID_AA64PFR0_SEL2_SHIFT) 761 #define ID_AA64PFR0_SEL2_VAL(x) ((x) & ID_AA64PFR0_SEL2_MASK) 762 #define ID_AA64PFR0_SEL2_NONE (UL(0x0) << ID_AA64PFR0_SEL2_SHIFT) 763 #define ID_AA64PFR0_SEL2_IMPL (UL(0x1) << ID_AA64PFR0_SEL2_SHIFT) 764 #define ID_AA64PFR0_MPAM_SHIFT 40 765 #define ID_AA64PFR0_MPAM_MASK (UL(0xf) << ID_AA64PFR0_MPAM_SHIFT) 766 #define ID_AA64PFR0_MPAM_VAL(x) ((x) & ID_AA64PFR0_MPAM_MASK) 767 #define ID_AA64PFR0_MPAM_NONE (UL(0x0) << ID_AA64PFR0_MPAM_SHIFT) 768 #define ID_AA64PFR0_MPAM_IMPL (UL(0x1) << ID_AA64PFR0_MPAM_SHIFT) 769 #define ID_AA64PFR0_AMU_SHIFT 44 770 #define ID_AA64PFR0_AMU_MASK (UL(0xf) << ID_AA64PFR0_AMU_SHIFT) 771 #define ID_AA64PFR0_AMU_VAL(x) ((x) & ID_AA64PFR0_AMU_MASK) 772 #define ID_AA64PFR0_AMU_NONE (UL(0x0) << ID_AA64PFR0_AMU_SHIFT) 773 #define ID_AA64PFR0_AMU_V1 (UL(0x1) << ID_AA64PFR0_AMU_SHIFT) 774 #define ID_AA64PFR0_DIT_SHIFT 48 775 #define ID_AA64PFR0_DIT_MASK (UL(0xf) << ID_AA64PFR0_DIT_SHIFT) 776 #define ID_AA64PFR0_DIT_VAL(x) ((x) & ID_AA64PFR0_DIT_MASK) 777 #define ID_AA64PFR0_DIT_NONE (UL(0x0) << ID_AA64PFR0_DIT_SHIFT) 778 #define ID_AA64PFR0_DIT_PSTATE (UL(0x1) << ID_AA64PFR0_DIT_SHIFT) 779 #define ID_AA64PFR0_CSV2_SHIFT 56 780 #define ID_AA64PFR0_CSV2_MASK (UL(0xf) << ID_AA64PFR0_CSV2_SHIFT) 781 #define ID_AA64PFR0_CSV2_VAL(x) ((x) & ID_AA64PFR0_CSV2_MASK) 782 #define ID_AA64PFR0_CSV2_NONE (UL(0x0) << ID_AA64PFR0_CSV2_SHIFT) 783 #define ID_AA64PFR0_CSV2_ISOLATED (UL(0x1) << ID_AA64PFR0_CSV2_SHIFT) 784 #define ID_AA64PFR0_CSV2_SCXTNUM (UL(0x2) << ID_AA64PFR0_CSV2_SHIFT) 785 #define ID_AA64PFR0_CSV3_SHIFT 60 786 #define ID_AA64PFR0_CSV3_MASK (UL(0xf) << ID_AA64PFR0_CSV3_SHIFT) 787 #define ID_AA64PFR0_CSV3_VAL(x) ((x) & ID_AA64PFR0_CSV3_MASK) 788 #define ID_AA64PFR0_CSV3_NONE (UL(0x0) << ID_AA64PFR0_CSV3_SHIFT) 789 #define ID_AA64PFR0_CSV3_ISOLATED (UL(0x1) << ID_AA64PFR0_CSV3_SHIFT) 790 791 /* ID_AA64PFR1_EL1 */ 792 #define ID_AA64PFR1_EL1 MRS_REG(ID_AA64PFR1_EL1) 793 #define ID_AA64PFR1_EL1_op0 0x3 794 #define ID_AA64PFR1_EL1_op1 0x0 795 #define ID_AA64PFR1_EL1_CRn 0x0 796 #define ID_AA64PFR1_EL1_CRm 0x4 797 #define ID_AA64PFR1_EL1_op2 0x1 798 #define ID_AA64PFR1_BT_SHIFT 0 799 #define ID_AA64PFR1_BT_MASK (UL(0xf) << ID_AA64PFR1_BT_SHIFT) 800 #define ID_AA64PFR1_BT_VAL(x) ((x) & ID_AA64PFR1_BT_MASK) 801 #define ID_AA64PFR1_BT_NONE (UL(0x0) << ID_AA64PFR1_BT_SHIFT) 802 #define ID_AA64PFR1_BT_IMPL (UL(0x1) << ID_AA64PFR1_BT_SHIFT) 803 #define ID_AA64PFR1_SSBS_SHIFT 4 804 #define ID_AA64PFR1_SSBS_MASK (UL(0xf) << ID_AA64PFR1_SSBS_SHIFT) 805 #define ID_AA64PFR1_SSBS_VAL(x) ((x) & ID_AA64PFR1_SSBS_MASK) 806 #define ID_AA64PFR1_SSBS_NONE (UL(0x0) << ID_AA64PFR1_SSBS_SHIFT) 807 #define ID_AA64PFR1_SSBS_PSTATE (UL(0x1) << ID_AA64PFR1_SSBS_SHIFT) 808 #define ID_AA64PFR1_SSBS_PSTATE_MSR (UL(0x2) << ID_AA64PFR1_SSBS_SHIFT) 809 #define ID_AA64PFR1_MTE_SHIFT 8 810 #define ID_AA64PFR1_MTE_MASK (UL(0xf) << ID_AA64PFR1_MTE_SHIFT) 811 #define ID_AA64PFR1_MTE_VAL(x) ((x) & ID_AA64PFR1_MTE_MASK) 812 #define ID_AA64PFR1_MTE_NONE (UL(0x0) << ID_AA64PFR1_MTE_SHIFT) 813 #define ID_AA64PFR1_MTE_IMPL_EL0 (UL(0x1) << ID_AA64PFR1_MTE_SHIFT) 814 #define ID_AA64PFR1_MTE_IMPL (UL(0x2) << ID_AA64PFR1_MTE_SHIFT) 815 #define ID_AA64PFR1_RAS_frac_SHIFT 12 816 #define ID_AA64PFR1_RAS_frac_MASK (UL(0xf) << ID_AA64PFR1_RAS_frac_SHIFT) 817 #define ID_AA64PFR1_RAS_frac_VAL(x) ((x) & ID_AA64PFR1_RAS_frac_MASK) 818 #define ID_AA64PFR1_RAS_frac_V1 (UL(0x0) << ID_AA64PFR1_RAS_frac_SHIFT) 819 #define ID_AA64PFR1_RAS_frac_V2 (UL(0x1) << ID_AA64PFR1_RAS_frac_SHIFT) 820 821 /* ID_ISAR5_EL1 */ 822 #define ID_ISAR5_EL1 MRS_REG(ID_ISAR5_EL1) 823 #define ID_ISAR5_EL1_op0 0x3 824 #define ID_ISAR5_EL1_op1 0x0 825 #define ID_ISAR5_EL1_CRn 0x0 826 #define ID_ISAR5_EL1_CRm 0x2 827 #define ID_ISAR5_EL1_op2 0x5 828 #define ID_ISAR5_SEVL_SHIFT 0 829 #define ID_ISAR5_SEVL_MASK (UL(0xf) << ID_ISAR5_SEVL_SHIFT) 830 #define ID_ISAR5_SEVL_VAL(x) ((x) & ID_ISAR5_SEVL_MASK) 831 #define ID_ISAR5_SEVL_NOP (UL(0x0) << ID_ISAR5_SEVL_SHIFT) 832 #define ID_ISAR5_SEVL_IMPL (UL(0x1) << ID_ISAR5_SEVL_SHIFT) 833 #define ID_ISAR5_AES_SHIFT 4 834 #define ID_ISAR5_AES_MASK (UL(0xf) << ID_ISAR5_AES_SHIFT) 835 #define ID_ISAR5_AES_VAL(x) ((x) & ID_ISAR5_AES_MASK) 836 #define ID_ISAR5_AES_NONE (UL(0x0) << ID_ISAR5_AES_SHIFT) 837 #define ID_ISAR5_AES_BASE (UL(0x1) << ID_ISAR5_AES_SHIFT) 838 #define ID_ISAR5_AES_VMULL (UL(0x2) << ID_ISAR5_AES_SHIFT) 839 #define ID_ISAR5_SHA1_SHIFT 8 840 #define ID_ISAR5_SHA1_MASK (UL(0xf) << ID_ISAR5_SHA1_SHIFT) 841 #define ID_ISAR5_SHA1_VAL(x) ((x) & ID_ISAR5_SHA1_MASK) 842 #define ID_ISAR5_SHA1_NONE (UL(0x0) << ID_ISAR5_SHA1_SHIFT) 843 #define ID_ISAR5_SHA1_IMPL (UL(0x1) << ID_ISAR5_SHA1_SHIFT) 844 #define ID_ISAR5_SHA2_SHIFT 12 845 #define ID_ISAR5_SHA2_MASK (UL(0xf) << ID_ISAR5_SHA2_SHIFT) 846 #define ID_ISAR5_SHA2_VAL(x) ((x) & ID_ISAR5_SHA2_MASK) 847 #define ID_ISAR5_SHA2_NONE (UL(0x0) << ID_ISAR5_SHA2_SHIFT) 848 #define ID_ISAR5_SHA2_IMPL (UL(0x1) << ID_ISAR5_SHA2_SHIFT) 849 #define ID_ISAR5_CRC32_SHIFT 16 850 #define ID_ISAR5_CRC32_MASK (UL(0xf) << ID_ISAR5_CRC32_SHIFT) 851 #define ID_ISAR5_CRC32_VAL(x) ((x) & ID_ISAR5_CRC32_MASK) 852 #define ID_ISAR5_CRC32_NONE (UL(0x0) << ID_ISAR5_CRC32_SHIFT) 853 #define ID_ISAR5_CRC32_IMPL (UL(0x1) << ID_ISAR5_CRC32_SHIFT) 854 #define ID_ISAR5_RDM_SHIFT 24 855 #define ID_ISAR5_RDM_MASK (UL(0xf) << ID_ISAR5_RDM_SHIFT) 856 #define ID_ISAR5_RDM_VAL(x) ((x) & ID_ISAR5_RDM_MASK) 857 #define ID_ISAR5_RDM_NONE (UL(0x0) << ID_ISAR5_RDM_SHIFT) 858 #define ID_ISAR5_RDM_IMPL (UL(0x1) << ID_ISAR5_RDM_SHIFT) 859 #define ID_ISAR5_VCMA_SHIFT 28 860 #define ID_ISAR5_VCMA_MASK (UL(0xf) << ID_ISAR5_VCMA_SHIFT) 861 #define ID_ISAR5_VCMA_VAL(x) ((x) & ID_ISAR5_VCMA_MASK) 862 #define ID_ISAR5_VCMA_NONE (UL(0x0) << ID_ISAR5_VCMA_SHIFT) 863 #define ID_ISAR5_VCMA_IMPL (UL(0x1) << ID_ISAR5_VCMA_SHIFT) 864 865 /* MAIR_EL1 - Memory Attribute Indirection Register */ 866 #define MAIR_ATTR_MASK(idx) (0xff << ((n)* 8)) 867 #define MAIR_ATTR(attr, idx) ((attr) << ((idx) * 8)) 868 #define MAIR_DEVICE_nGnRnE 0x00 869 #define MAIR_DEVICE_nGnRE 0x04 870 #define MAIR_NORMAL_NC 0x44 871 #define MAIR_NORMAL_WT 0xbb 872 #define MAIR_NORMAL_WB 0xff 873 874 /* MVFR0_EL1 */ 875 #define MVFR0_EL1 MRS_REG(MVFR0_EL1) 876 #define MVFR0_EL1_op0 0x3 877 #define MVFR0_EL1_op1 0x0 878 #define MVFR0_EL1_CRn 0x0 879 #define MVFR0_EL1_CRm 0x3 880 #define MVFR0_EL1_op2 0x0 881 #define MVFR0_SIMDReg_SHIFT 0 882 #define MVFR0_SIMDReg_MASK (UL(0xf) << MVFR0_SIMDReg_SHIFT) 883 #define MVFR0_SIMDReg_VAL(x) ((x) & MVFR0_SIMDReg_MASK) 884 #define MVFR0_SIMDReg_NONE (UL(0x0) << MVFR0_SIMDReg_SHIFT) 885 #define MVFR0_SIMDReg_FP (UL(0x1) << MVFR0_SIMDReg_SHIFT) 886 #define MVFR0_SIMDReg_AdvSIMD (UL(0x2) << MVFR0_SIMDReg_SHIFT) 887 #define MVFR0_FPSP_SHIFT 4 888 #define MVFR0_FPSP_MASK (UL(0xf) << MVFR0_FPSP_SHIFT) 889 #define MVFR0_FPSP_VAL(x) ((x) & MVFR0_FPSP_MASK) 890 #define MVFR0_FPSP_NONE (UL(0x0) << MVFR0_FPSP_SHIFT) 891 #define MVFR0_FPSP_VFP_v2 (UL(0x1) << MVFR0_FPSP_SHIFT) 892 #define MVFR0_FPSP_VFP_v3_v4 (UL(0x2) << MVFR0_FPSP_SHIFT) 893 #define MVFR0_FPDP_SHIFT 8 894 #define MVFR0_FPDP_MASK (UL(0xf) << MVFR0_FPDP_SHIFT) 895 #define MVFR0_FPDP_VAL(x) ((x) & MVFR0_FPDP_MASK) 896 #define MVFR0_FPDP_NONE (UL(0x0) << MVFR0_FPDP_SHIFT) 897 #define MVFR0_FPDP_VFP_v2 (UL(0x1) << MVFR0_FPDP_SHIFT) 898 #define MVFR0_FPDP_VFP_v3_v4 (UL(0x2) << MVFR0_FPDP_SHIFT) 899 #define MVFR0_FPTrap_SHIFT 12 900 #define MVFR0_FPTrap_MASK (UL(0xf) << MVFR0_FPTrap_SHIFT) 901 #define MVFR0_FPTrap_VAL(x) ((x) & MVFR0_FPTrap_MASK) 902 #define MVFR0_FPTrap_NONE (UL(0x0) << MVFR0_FPTrap_SHIFT) 903 #define MVFR0_FPTrap_IMPL (UL(0x1) << MVFR0_FPTrap_SHIFT) 904 #define MVFR0_FPDivide_SHIFT 16 905 #define MVFR0_FPDivide_MASK (UL(0xf) << MVFR0_FPDivide_SHIFT) 906 #define MVFR0_FPDivide_VAL(x) ((x) & MVFR0_FPDivide_MASK) 907 #define MVFR0_FPDivide_NONE (UL(0x0) << MVFR0_FPDivide_SHIFT) 908 #define MVFR0_FPDivide_IMPL (UL(0x1) << MVFR0_FPDivide_SHIFT) 909 #define MVFR0_FPSqrt_SHIFT 20 910 #define MVFR0_FPSqrt_MASK (UL(0xf) << MVFR0_FPSqrt_SHIFT) 911 #define MVFR0_FPSqrt_VAL(x) ((x) & MVFR0_FPSqrt_MASK) 912 #define MVFR0_FPSqrt_NONE (UL(0x0) << MVFR0_FPSqrt_SHIFT) 913 #define MVFR0_FPSqrt_IMPL (UL(0x1) << MVFR0_FPSqrt_SHIFT) 914 #define MVFR0_FPShVec_SHIFT 24 915 #define MVFR0_FPShVec_MASK (UL(0xf) << MVFR0_FPShVec_SHIFT) 916 #define MVFR0_FPShVec_VAL(x) ((x) & MVFR0_FPShVec_MASK) 917 #define MVFR0_FPShVec_NONE (UL(0x0) << MVFR0_FPShVec_SHIFT) 918 #define MVFR0_FPShVec_IMPL (UL(0x1) << MVFR0_FPShVec_SHIFT) 919 #define MVFR0_FPRound_SHIFT 28 920 #define MVFR0_FPRound_MASK (UL(0xf) << MVFR0_FPRound_SHIFT) 921 #define MVFR0_FPRound_VAL(x) ((x) & MVFR0_FPRound_MASK) 922 #define MVFR0_FPRound_NONE (UL(0x0) << MVFR0_FPRound_SHIFT) 923 #define MVFR0_FPRound_IMPL (UL(0x1) << MVFR0_FPRound_SHIFT) 924 925 /* MVFR1_EL1 */ 926 #define MVFR1_EL1 MRS_REG(MVFR1_EL1) 927 #define MVFR1_EL1_op0 0x3 928 #define MVFR1_EL1_op1 0x0 929 #define MVFR1_EL1_CRn 0x0 930 #define MVFR1_EL1_CRm 0x3 931 #define MVFR1_EL1_op2 0x1 932 #define MVFR1_FPFtZ_SHIFT 0 933 #define MVFR1_FPFtZ_MASK (UL(0xf) << MVFR1_FPFtZ_SHIFT) 934 #define MVFR1_FPFtZ_VAL(x) ((x) & MVFR1_FPFtZ_MASK) 935 #define MVFR1_FPFtZ_NONE (UL(0x0) << MVFR1_FPFtZ_SHIFT) 936 #define MVFR1_FPFtZ_IMPL (UL(0x1) << MVFR1_FPFtZ_SHIFT) 937 #define MVFR1_FPDNaN_SHIFT 4 938 #define MVFR1_FPDNaN_MASK (UL(0xf) << MVFR1_FPDNaN_SHIFT) 939 #define MVFR1_FPDNaN_VAL(x) ((x) & MVFR1_FPDNaN_MASK) 940 #define MVFR1_FPDNaN_NONE (UL(0x0) << MVFR1_FPDNaN_SHIFT) 941 #define MVFR1_FPDNaN_IMPL (UL(0x1) << MVFR1_FPDNaN_SHIFT) 942 #define MVFR1_SIMDLS_SHIFT 8 943 #define MVFR1_SIMDLS_MASK (UL(0xf) << MVFR1_SIMDLS_SHIFT) 944 #define MVFR1_SIMDLS_VAL(x) ((x) & MVFR1_SIMDLS_MASK) 945 #define MVFR1_SIMDLS_NONE (UL(0x0) << MVFR1_SIMDLS_SHIFT) 946 #define MVFR1_SIMDLS_IMPL (UL(0x1) << MVFR1_SIMDLS_SHIFT) 947 #define MVFR1_SIMDInt_SHIFT 12 948 #define MVFR1_SIMDInt_MASK (UL(0xf) << MVFR1_SIMDInt_SHIFT) 949 #define MVFR1_SIMDInt_VAL(x) ((x) & MVFR1_SIMDInt_MASK) 950 #define MVFR1_SIMDInt_NONE (UL(0x0) << MVFR1_SIMDInt_SHIFT) 951 #define MVFR1_SIMDInt_IMPL (UL(0x1) << MVFR1_SIMDInt_SHIFT) 952 #define MVFR1_SIMDSP_SHIFT 16 953 #define MVFR1_SIMDSP_MASK (UL(0xf) << MVFR1_SIMDSP_SHIFT) 954 #define MVFR1_SIMDSP_VAL(x) ((x) & MVFR1_SIMDSP_MASK) 955 #define MVFR1_SIMDSP_NONE (UL(0x0) << MVFR1_SIMDSP_SHIFT) 956 #define MVFR1_SIMDSP_IMPL (UL(0x1) << MVFR1_SIMDSP_SHIFT) 957 #define MVFR1_SIMDHP_SHIFT 20 958 #define MVFR1_SIMDHP_MASK (UL(0xf) << MVFR1_SIMDHP_SHIFT) 959 #define MVFR1_SIMDHP_VAL(x) ((x) & MVFR1_SIMDHP_MASK) 960 #define MVFR1_SIMDHP_NONE (UL(0x0) << MVFR1_SIMDHP_SHIFT) 961 #define MVFR1_SIMDHP_CONV_SP (UL(0x1) << MVFR1_SIMDHP_SHIFT) 962 #define MVFR1_SIMDHP_ARITH (UL(0x2) << MVFR1_SIMDHP_SHIFT) 963 #define MVFR1_FPHP_SHIFT 24 964 #define MVFR1_FPHP_MASK (UL(0xf) << MVFR1_FPHP_SHIFT) 965 #define MVFR1_FPHP_VAL(x) ((x) & MVFR1_FPHP_MASK) 966 #define MVFR1_FPHP_NONE (UL(0x0) << MVFR1_FPHP_SHIFT) 967 #define MVFR1_FPHP_CONV_SP (UL(0x1) << MVFR1_FPHP_SHIFT) 968 #define MVFR1_FPHP_CONV_DP (UL(0x2) << MVFR1_FPHP_SHIFT) 969 #define MVFR1_FPHP_ARITH (UL(0x3) << MVFR1_FPHP_SHIFT) 970 #define MVFR1_SIMDFMAC_SHIFT 28 971 #define MVFR1_SIMDFMAC_MASK (UL(0xf) << MVFR1_SIMDFMAC_SHIFT) 972 #define MVFR1_SIMDFMAC_VAL(x) ((x) & MVFR1_SIMDFMAC_MASK) 973 #define MVFR1_SIMDFMAC_NONE (UL(0x0) << MVFR1_SIMDFMAC_SHIFT) 974 #define MVFR1_SIMDFMAC_IMPL (UL(0x1) << MVFR1_SIMDFMAC_SHIFT) 975 976 /* PAR_EL1 - Physical Address Register */ 977 #define PAR_F_SHIFT 0 978 #define PAR_F (0x1 << PAR_F_SHIFT) 979 #define PAR_SUCCESS(x) (((x) & PAR_F) == 0) 980 /* When PAR_F == 0 (success) */ 981 #define PAR_LOW_MASK 0xfff 982 #define PAR_SH_SHIFT 7 983 #define PAR_SH_MASK (0x3 << PAR_SH_SHIFT) 984 #define PAR_NS_SHIFT 9 985 #define PAR_NS_MASK (0x3 << PAR_NS_SHIFT) 986 #define PAR_PA_SHIFT 12 987 #define PAR_PA_MASK 0x0000fffffffff000 988 #define PAR_ATTR_SHIFT 56 989 #define PAR_ATTR_MASK (0xff << PAR_ATTR_SHIFT) 990 /* When PAR_F == 1 (aborted) */ 991 #define PAR_FST_SHIFT 1 992 #define PAR_FST_MASK (0x3f << PAR_FST_SHIFT) 993 #define PAR_PTW_SHIFT 8 994 #define PAR_PTW_MASK (0x1 << PAR_PTW_SHIFT) 995 #define PAR_S_SHIFT 9 996 #define PAR_S_MASK (0x1 << PAR_S_SHIFT) 997 998 /* SCTLR_EL1 - System Control Register */ 999 #define SCTLR_RES1 0x30d00800 /* Reserved ARMv8.0, write 1 */ 1000 #define SCTLR_M (UL(0x1) << 0) 1001 #define SCTLR_A (UL(0x1) << 1) 1002 #define SCTLR_C (UL(0x1) << 2) 1003 #define SCTLR_SA (UL(0x1) << 3) 1004 #define SCTLR_SA0 (UL(0x1) << 4) 1005 #define SCTLR_CP15BEN (UL(0x1) << 5) 1006 #define SCTLR_nAA (UL(0x1) << 6) 1007 #define SCTLR_ITD (UL(0x1) << 7) 1008 #define SCTLR_SED (UL(0x1) << 8) 1009 #define SCTLR_UMA (UL(0x1) << 9) 1010 #define SCTLR_EnRCTX (UL(0x1) << 10) 1011 #define SCTLR_EOS (UL(0x1) << 11) 1012 #define SCTLR_I (UL(0x1) << 12) 1013 #define SCTLR_EnDB (UL(0x1) << 13) 1014 #define SCTLR_DZE (UL(0x1) << 14) 1015 #define SCTLR_UCT (UL(0x1) << 15) 1016 #define SCTLR_nTWI (UL(0x1) << 16) 1017 /* Bit 17 is reserved */ 1018 #define SCTLR_nTWE (UL(0x1) << 18) 1019 #define SCTLR_WXN (UL(0x1) << 19) 1020 #define SCTLR_TSCXT (UL(0x1) << 20) 1021 #define SCTLR_IESB (UL(0x1) << 21) 1022 #define SCTLR_EIS (UL(0x1) << 22) 1023 #define SCTLR_SPAN (UL(0x1) << 23) 1024 #define SCTLR_E0E (UL(0x1) << 24) 1025 #define SCTLR_EE (UL(0x1) << 25) 1026 #define SCTLR_UCI (UL(0x1) << 26) 1027 #define SCTLR_EnDA (UL(0x1) << 27) 1028 #define SCTLR_nTLSMD (UL(0x1) << 28) 1029 #define SCTLR_LSMAOE (UL(0x1) << 29) 1030 #define SCTLR_EnIB (UL(0x1) << 30) 1031 #define SCTLR_EnIA (UL(0x1) << 31) 1032 /* Bits 34:32 are reserved */ 1033 #define SCTLR_BT0 (UL(0x1) << 35) 1034 #define SCTLR_BT1 (UL(0x1) << 36) 1035 #define SCTLR_ITFSB (UL(0x1) << 37) 1036 #define SCTLR_TCF0_MASK (UL(0x3) << 38) 1037 #define SCTLR_TCF_MASK (UL(0x3) << 40) 1038 #define SCTLR_ATA0 (UL(0x1) << 42) 1039 #define SCTLR_ATA (UL(0x1) << 43) 1040 #define SCTLR_DSSBS (UL(0x1) << 44) 1041 #define SCTLR_TWEDEn (UL(0x1) << 45) 1042 #define SCTLR_TWEDEL_MASK (UL(0xf) << 46) 1043 /* Bits 53:50 are reserved */ 1044 #define SCTLR_EnASR (UL(0x1) << 54) 1045 #define SCTLR_EnAS0 (UL(0x1) << 55) 1046 #define SCTLR_EnALS (UL(0x1) << 56) 1047 #define SCTLR_EPAN (UL(0x1) << 57) 1048 1049 /* SPSR_EL1 */ 1050 /* 1051 * When the exception is taken in AArch64: 1052 * M[3:2] is the exception level 1053 * M[1] is unused 1054 * M[0] is the SP select: 1055 * 0: always SP0 1056 * 1: current ELs SP 1057 */ 1058 #define PSR_M_EL0t 0x00000000 1059 #define PSR_M_EL1t 0x00000004 1060 #define PSR_M_EL1h 0x00000005 1061 #define PSR_M_EL2t 0x00000008 1062 #define PSR_M_EL2h 0x00000009 1063 #define PSR_M_64 0x00000000 1064 #define PSR_M_32 0x00000010 1065 #define PSR_M_MASK 0x0000000f 1066 1067 #define PSR_T 0x00000020 1068 1069 #define PSR_AARCH32 0x00000010 1070 #define PSR_F 0x00000040 1071 #define PSR_I 0x00000080 1072 #define PSR_A 0x00000100 1073 #define PSR_D 0x00000200 1074 #define PSR_DAIF (PSR_D | PSR_A | PSR_I | PSR_F) 1075 /* The default DAIF mask. These bits are valid in spsr_el1 and daif */ 1076 #define PSR_DAIF_DEFAULT (PSR_F) 1077 #define PSR_IL 0x00100000 1078 #define PSR_SS 0x00200000 1079 #define PSR_V 0x10000000 1080 #define PSR_C 0x20000000 1081 #define PSR_Z 0x40000000 1082 #define PSR_N 0x80000000 1083 #define PSR_FLAGS 0xf0000000 1084 1085 /* TCR_EL1 - Translation Control Register */ 1086 /* Bits 63:59 are reserved */ 1087 #define TCR_TCMA1_SHIFT 58 1088 #define TCR_TCMA1 (1UL << TCR_TCMA1_SHIFT) 1089 #define TCR_TCMA0_SHIFT 57 1090 #define TCR_TCMA0 (1UL << TCR_TCMA0_SHIFT) 1091 #define TCR_E0PD1_SHIFT 56 1092 #define TCR_E0PD1 (1UL << TCR_E0PD1_SHIFT) 1093 #define TCR_E0PD0_SHIFT 55 1094 #define TCR_E0PD0 (1UL << TCR_E0PD0_SHIFT) 1095 #define TCR_NFD1_SHIFT 54 1096 #define TCR_NFD1 (1UL << TCR_NFD1_SHIFT) 1097 #define TCR_NFD0_SHIFT 53 1098 #define TCR_NFD0 (1UL << TCR_NFD0_SHIFT) 1099 #define TCR_TBID1_SHIFT 52 1100 #define TCR_TBID1 (1UL << TCR_TBID1_SHIFT) 1101 #define TCR_TBID0_SHIFT 51 1102 #define TCR_TBID0 (1UL << TCR_TBID0_SHIFT) 1103 #define TCR_HWU162_SHIFT 50 1104 #define TCR_HWU162 (1UL << TCR_HWU162_SHIFT) 1105 #define TCR_HWU161_SHIFT 49 1106 #define TCR_HWU161 (1UL << TCR_HWU161_SHIFT) 1107 #define TCR_HWU160_SHIFT 48 1108 #define TCR_HWU160 (1UL << TCR_HWU160_SHIFT) 1109 #define TCR_HWU159_SHIFT 47 1110 #define TCR_HWU159 (1UL << TCR_HWU159_SHIFT) 1111 #define TCR_HWU1 \ 1112 (TCR_HWU159 | TCR_HWU160 | TCR_HWU161 | TCR_HWU162) 1113 #define TCR_HWU062_SHIFT 46 1114 #define TCR_HWU062 (1UL << TCR_HWU062_SHIFT) 1115 #define TCR_HWU061_SHIFT 45 1116 #define TCR_HWU061 (1UL << TCR_HWU061_SHIFT) 1117 #define TCR_HWU060_SHIFT 44 1118 #define TCR_HWU060 (1UL << TCR_HWU060_SHIFT) 1119 #define TCR_HWU059_SHIFT 43 1120 #define TCR_HWU059 (1UL << TCR_HWU059_SHIFT) 1121 #define TCR_HWU0 \ 1122 (TCR_HWU059 | TCR_HWU060 | TCR_HWU061 | TCR_HWU062) 1123 #define TCR_HPD1_SHIFT 42 1124 #define TCR_HPD1 (1UL << TCR_HPD1_SHIFT) 1125 #define TCR_HPD0_SHIFT 41 1126 #define TCR_HPD0 (1UL << TCR_HPD0_SHIFT) 1127 #define TCR_HD_SHIFT 40 1128 #define TCR_HD (1UL << TCR_HD_SHIFT) 1129 #define TCR_HA_SHIFT 39 1130 #define TCR_HA (1UL << TCR_HA_SHIFT) 1131 #define TCR_TBI1_SHIFT 38 1132 #define TCR_TBI1 (1UL << TCR_TBI1_SHIFT) 1133 #define TCR_TBI0_SHIFT 37 1134 #define TCR_TBI0 (1U << TCR_TBI0_SHIFT) 1135 #define TCR_ASID_SHIFT 36 1136 #define TCR_ASID_WIDTH 1 1137 #define TCR_ASID_16 (1UL << TCR_ASID_SHIFT) 1138 /* Bit 35 is reserved */ 1139 #define TCR_IPS_SHIFT 32 1140 #define TCR_IPS_WIDTH 3 1141 #define TCR_IPS_32BIT (0UL << TCR_IPS_SHIFT) 1142 #define TCR_IPS_36BIT (1UL << TCR_IPS_SHIFT) 1143 #define TCR_IPS_40BIT (2UL << TCR_IPS_SHIFT) 1144 #define TCR_IPS_42BIT (3UL << TCR_IPS_SHIFT) 1145 #define TCR_IPS_44BIT (4UL << TCR_IPS_SHIFT) 1146 #define TCR_IPS_48BIT (5UL << TCR_IPS_SHIFT) 1147 #define TCR_TG1_SHIFT 30 1148 #define TCR_TG1_16K (1UL << TCR_TG1_SHIFT) 1149 #define TCR_TG1_4K (2UL << TCR_TG1_SHIFT) 1150 #define TCR_TG1_64K (3UL << TCR_TG1_SHIFT) 1151 #define TCR_SH1_SHIFT 28 1152 #define TCR_SH1_IS (3UL << TCR_SH1_SHIFT) 1153 #define TCR_ORGN1_SHIFT 26 1154 #define TCR_ORGN1_WBWA (1UL << TCR_ORGN1_SHIFT) 1155 #define TCR_IRGN1_SHIFT 24 1156 #define TCR_IRGN1_WBWA (1UL << TCR_IRGN1_SHIFT) 1157 #define TCR_EPD1_SHIFT 23 1158 #define TCR_EPD1 (1UL << TCR_EPD1_SHIFT) 1159 #define TCR_A1_SHIFT 22 1160 #define TCR_A1 (0x1UL << TCR_A1_SHIFT) 1161 #define TCR_T1SZ_SHIFT 16 1162 #define TCR_T1SZ(x) ((x) << TCR_T1SZ_SHIFT) 1163 #define TCR_TG0_SHIFT 14 1164 #define TCR_TG0_16K (1UL << TCR_TG0_SHIFT) 1165 #define TCR_TG0_4K (2UL << TCR_TG0_SHIFT) 1166 #define TCR_TG0_64K (3UL << TCR_TG0_SHIFT) 1167 #define TCR_SH0_SHIFT 12 1168 #define TCR_SH0_IS (3UL << TCR_SH0_SHIFT) 1169 #define TCR_ORGN0_SHIFT 10 1170 #define TCR_ORGN0_WBWA (1UL << TCR_ORGN0_SHIFT) 1171 #define TCR_IRGN0_SHIFT 8 1172 #define TCR_IRGN0_WBWA (1UL << TCR_IRGN0_SHIFT) 1173 #define TCR_EPD0_SHIFT 7 1174 #define TCR_EPD0 (1UL << TCR_EPD1_SHIFT) 1175 /* Bit 6 is reserved */ 1176 #define TCR_T0SZ_SHIFT 0 1177 #define TCR_T0SZ_MASK 0x3f 1178 #define TCR_T0SZ(x) ((x) << TCR_T0SZ_SHIFT) 1179 #define TCR_TxSZ(x) (TCR_T1SZ(x) | TCR_T0SZ(x)) 1180 1181 #define TCR_CACHE_ATTRS ((TCR_IRGN0_WBWA | TCR_IRGN1_WBWA) |\ 1182 (TCR_ORGN0_WBWA | TCR_ORGN1_WBWA)) 1183 #ifdef SMP 1184 #define TCR_SMP_ATTRS (TCR_SH0_IS | TCR_SH1_IS) 1185 #else 1186 #define TCR_SMP_ATTRS 0 1187 #endif 1188 1189 /* Saved Program Status Register */ 1190 #define DBG_SPSR_SS (0x1 << 21) 1191 1192 /* Monitor Debug System Control Register */ 1193 #define DBG_MDSCR_SS (0x1 << 0) 1194 #define DBG_MDSCR_KDE (0x1 << 13) 1195 #define DBG_MDSCR_MDE (0x1 << 15) 1196 1197 /* Debug Breakpoint Control Registers */ 1198 #define DBG_BCR_EN 0x1 1199 #define DBG_BCR_PMC_SHIFT 1 1200 #define DBG_BCR_PMC (0x3 << DBG_BCR_PMC_SHIFT) 1201 #define DBG_BCR_PMC_EL1 (0x1 << DBG_BCR_PMC_SHIFT) 1202 #define DBG_BCR_PMC_EL0 (0x2 << DBG_BCR_PMC_SHIFT) 1203 #define DBG_BCR_BAS_SHIFT 5 1204 #define DBG_BCR_BAS (0xf << DBG_BCR_BAS_SHIFT) 1205 #define DBG_BCR_HMC_SHIFT 13 1206 #define DBG_BCR_HMC (0x1 << DBG_BCR_HMC_SHIFT) 1207 #define DBG_BCR_SSC_SHIFT 14 1208 #define DBG_BCR_SSC (0x3 << DBG_BCR_SSC_SHIFT) 1209 #define DBG_BCR_LBN_SHIFT 16 1210 #define DBG_BCR_LBN (0xf << DBG_BCR_LBN_SHIFT) 1211 #define DBG_BCR_BT_SHIFT 20 1212 #define DBG_BCR_BT (0xf << DBG_BCR_BT_SHIFT) 1213 1214 /* Debug Watchpoint Control Registers */ 1215 #define DBG_WCR_EN 0x1 1216 #define DBG_WCR_PAC_SHIFT 1 1217 #define DBG_WCR_PAC (0x3 << DBG_WCR_PAC_SHIFT) 1218 #define DBG_WCR_PAC_EL1 (0x1 << DBG_WCR_PAC_SHIFT) 1219 #define DBG_WCR_PAC_EL0 (0x2 << DBG_WCR_PAC_SHIFT) 1220 #define DBG_WCR_LSC_SHIFT 3 1221 #define DBG_WCR_LSC (0x3 << DBG_WCR_LSC_SHIFT) 1222 #define DBG_WCR_BAS_SHIFT 5 1223 #define DBG_WCR_BAS (0xff << DBG_WCR_BAS_SHIFT) 1224 #define DBG_WCR_BAS_MASK DBG_WCR_BAS 1225 #define DBG_WCR_HMC_SHIFT 13 1226 #define DBG_WCR_HMC (0x1 << DBG_WCR_HMC_SHIFT) 1227 #define DBG_WCR_SSC_SHIFT 14 1228 #define DBG_WCR_SSC (0x3 << DBG_WCR_SSC_SHIFT) 1229 #define DBG_WCR_LBN_SHIFT 16 1230 #define DBG_WCR_LBN (0xf << DBG_WCR_LBN_SHIFT) 1231 #define DBG_WCR_WT_SHIFT 20 1232 #define DBG_WCR_WT (0x1 << DBG_WCR_WT_SHIFT) 1233 #define DBG_WCR_MASK_SHIFT 24 1234 #define DBG_WCR_MASK (0x1f << DBG_WCR_MASK_SHIFT) 1235 1236 /* Perfomance Monitoring Counters */ 1237 #define PMCR_E (1 << 0) /* Enable all counters */ 1238 #define PMCR_P (1 << 1) /* Reset all counters */ 1239 #define PMCR_C (1 << 2) /* Clock counter reset */ 1240 #define PMCR_D (1 << 3) /* CNTR counts every 64 clk cycles */ 1241 #define PMCR_X (1 << 4) /* Export to ext. monitoring (ETM) */ 1242 #define PMCR_DP (1 << 5) /* Disable CCNT if non-invasive debug*/ 1243 #define PMCR_LC (1 << 6) /* Long cycle count enable */ 1244 #define PMCR_IMP_SHIFT 24 /* Implementer code */ 1245 #define PMCR_IMP_MASK (0xff << PMCR_IMP_SHIFT) 1246 #define PMCR_IMP_ARM 0x41 1247 #define PMCR_IDCODE_SHIFT 16 /* Identification code */ 1248 #define PMCR_IDCODE_MASK (0xff << PMCR_IDCODE_SHIFT) 1249 #define PMCR_IDCODE_CORTEX_A57 0x01 1250 #define PMCR_IDCODE_CORTEX_A72 0x02 1251 #define PMCR_IDCODE_CORTEX_A53 0x03 1252 #define PMCR_IDCODE_CORTEX_A73 0x04 1253 #define PMCR_IDCODE_CORTEX_A35 0x0a 1254 #define PMCR_IDCODE_CORTEX_A76 0x0b 1255 #define PMCR_IDCODE_NEOVERSE_N1 0x0c 1256 #define PMCR_IDCODE_CORTEX_A77 0x10 1257 #define PMCR_IDCODE_CORTEX_A55 0x45 1258 #define PMCR_IDCODE_NEOVERSE_E1 0x46 1259 #define PMCR_IDCODE_CORTEX_A75 0x4a 1260 #define PMCR_N_SHIFT 11 /* Number of counters implemented */ 1261 #define PMCR_N_MASK (0x1f << PMCR_N_SHIFT) 1262 1263 #endif /* !_MACHINE_ARMREG_H_ */ 1264