xref: /freebsd/sys/arm64/include/armreg.h (revision 924226fba12cc9a228c73b956e1b7fa24c60b055)
1 /*-
2  * Copyright (c) 2013, 2014 Andrew Turner
3  * Copyright (c) 2015,2021 The FreeBSD Foundation
4  *
5  * Portions of this software were developed by Andrew Turner
6  * under sponsorship from the FreeBSD Foundation.
7  *
8  * Redistribution and use in source and binary forms, with or without
9  * modification, are permitted provided that the following conditions
10  * are met:
11  * 1. Redistributions of source code must retain the above copyright
12  *    notice, this list of conditions and the following disclaimer.
13  * 2. Redistributions in binary form must reproduce the above copyright
14  *    notice, this list of conditions and the following disclaimer in the
15  *    documentation and/or other materials provided with the distribution.
16  *
17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27  * SUCH DAMAGE.
28  *
29  * $FreeBSD$
30  */
31 
32 #ifndef _MACHINE_ARMREG_H_
33 #define	_MACHINE_ARMREG_H_
34 
35 #define	INSN_SIZE		4
36 
37 #define	MRS_MASK			0xfff00000
38 #define	MRS_VALUE			0xd5300000
39 #define	MRS_SPECIAL(insn)		((insn) & 0x000fffe0)
40 #define	MRS_REGISTER(insn)		((insn) & 0x0000001f)
41 #define	 MRS_Op0_SHIFT			19
42 #define	 MRS_Op0_MASK			0x00080000
43 #define	 MRS_Op1_SHIFT			16
44 #define	 MRS_Op1_MASK			0x00070000
45 #define	 MRS_CRn_SHIFT			12
46 #define	 MRS_CRn_MASK			0x0000f000
47 #define	 MRS_CRm_SHIFT			8
48 #define	 MRS_CRm_MASK			0x00000f00
49 #define	 MRS_Op2_SHIFT			5
50 #define	 MRS_Op2_MASK			0x000000e0
51 #define	 MRS_Rt_SHIFT			0
52 #define	 MRS_Rt_MASK			0x0000001f
53 #define	__MRS_REG(op0, op1, crn, crm, op2)				\
54     (((op0) << MRS_Op0_SHIFT) | ((op1) << MRS_Op1_SHIFT) |		\
55      ((crn) << MRS_CRn_SHIFT) | ((crm) << MRS_CRm_SHIFT) |		\
56      ((op2) << MRS_Op2_SHIFT))
57 #define	MRS_REG(reg)							\
58     __MRS_REG(reg##_op0, reg##_op1, reg##_CRn, reg##_CRm, reg##_op2)
59 
60 
61 
62 #define	READ_SPECIALREG(reg)						\
63 ({	uint64_t _val;							\
64 	__asm __volatile("mrs	%0, " __STRING(reg) : "=&r" (_val));	\
65 	_val;								\
66 })
67 #define	WRITE_SPECIALREG(reg, _val)					\
68 	__asm __volatile("msr	" __STRING(reg) ", %0" : : "r"((uint64_t)_val))
69 
70 #define	UL(x)	UINT64_C(x)
71 
72 /* CCSIDR_EL1 - Cache Size ID Register */
73 #define	CCSIDR_NumSets_MASK	0x0FFFE000
74 #define	CCSIDR_NumSets64_MASK	0x00FFFFFF00000000
75 #define	CCSIDR_NumSets_SHIFT	13
76 #define	CCSIDR_NumSets64_SHIFT	32
77 #define	CCSIDR_Assoc_MASK	0x00001FF8
78 #define	CCSIDR_Assoc64_MASK	0x0000000000FFFFF8
79 #define	CCSIDR_Assoc_SHIFT	3
80 #define	CCSIDR_Assoc64_SHIFT	3
81 #define	CCSIDR_LineSize_MASK	0x7
82 #define	CCSIDR_NSETS(idr)						\
83 	(((idr) & CCSIDR_NumSets_MASK) >> CCSIDR_NumSets_SHIFT)
84 #define	CCSIDR_ASSOC(idr)						\
85 	(((idr) & CCSIDR_Assoc_MASK) >> CCSIDR_Assoc_SHIFT)
86 #define	CCSIDR_NSETS_64(idr)						\
87 	(((idr) & CCSIDR_NumSets64_MASK) >> CCSIDR_NumSets64_SHIFT)
88 #define	CCSIDR_ASSOC_64(idr)						\
89 	(((idr) & CCSIDR_Assoc64_MASK) >> CCSIDR_Assoc64_SHIFT)
90 
91 /* CLIDR_EL1 - Cache level ID register */
92 #define	CLIDR_CTYPE_MASK	0x7	/* Cache type mask bits */
93 #define	CLIDR_CTYPE_IO		0x1	/* Instruction only */
94 #define	CLIDR_CTYPE_DO		0x2	/* Data only */
95 #define	CLIDR_CTYPE_ID		0x3	/* Split instruction and data */
96 #define	CLIDR_CTYPE_UNIFIED	0x4	/* Unified */
97 
98 /* CNTHCTL_EL2 - Counter-timer Hypervisor Control register */
99 #define	CNTHCTL_EVNTI_MASK	(0xf << 4) /* Bit to trigger event stream */
100 #define	CNTHCTL_EVNTDIR		(1 << 3) /* Control transition trigger bit */
101 #define	CNTHCTL_EVNTEN		(1 << 2) /* Enable event stream */
102 #define	CNTHCTL_EL1PCEN		(1 << 1) /* Allow EL0/1 physical timer access */
103 #define	CNTHCTL_EL1PCTEN	(1 << 0) /*Allow EL0/1 physical counter access*/
104 
105 /* CNTP_CTL_EL0 - Counter-timer Physical Timer Control register */
106 #define	CNTP_CTL_EL0		MRS_REG(CNTP_CTL_EL0)
107 #define	CNTP_CTL_EL0_op0	3
108 #define	CNTP_CTL_EL0_op1	3
109 #define	CNTP_CTL_EL0_CRn	14
110 #define	CNTP_CTL_EL0_CRm	2
111 #define	CNTP_CTL_EL0_op2	1
112 #define	CNTP_CTL_ENABLE		(1 << 0)
113 #define	CNTP_CTL_IMASK		(1 << 1)
114 #define	CNTP_CTL_ISTATUS	(1 << 2)
115 
116 /* CNTP_CVAL_EL0 - Counter-timer Physical Timer CompareValue register */
117 #define	CNTP_CVAL_EL0		MRS_REG(CNTP_CVAL_EL0)
118 #define	CNTP_CVAL_EL0_op0	3
119 #define	CNTP_CVAL_EL0_op1	3
120 #define	CNTP_CVAL_EL0_CRn	14
121 #define	CNTP_CVAL_EL0_CRm	2
122 #define	CNTP_CVAL_EL0_op2	2
123 
124 /* CNTP_TVAL_EL0 - Counter-timer Physical Timer TimerValue register */
125 #define	CNTP_TVAL_EL0		MRS_REG(CNTP_TVAL_EL0)
126 #define	CNTP_TVAL_EL0_op0	3
127 #define	CNTP_TVAL_EL0_op1	3
128 #define	CNTP_TVAL_EL0_CRn	14
129 #define	CNTP_TVAL_EL0_CRm	2
130 #define	CNTP_TVAL_EL0_op2	0
131 
132 /* CNTPCT_EL0 - Counter-timer Physical Count register */
133 #define	CNTPCT_EL0		MRS_REG(CNTPCT_EL0)
134 #define	CNTPCT_EL0_op0		3
135 #define	CNTPCT_EL0_op1		3
136 #define	CNTPCT_EL0_CRn		14
137 #define	CNTPCT_EL0_CRm		0
138 #define	CNTPCT_EL0_op2		1
139 
140 /* CPACR_EL1 */
141 #define	CPACR_ZEN_MASK		(0x3 << 16)
142 #define	 CPACR_ZEN_TRAP_ALL1	(0x0 << 16) /* Traps from EL0 and EL1 */
143 #define	 CPACR_ZEN_TRAP_EL0	(0x1 << 16) /* Traps from EL0 */
144 #define	 CPACR_ZEN_TRAP_ALL2	(0x2 << 16) /* Traps from EL0 and EL1 */
145 #define	 CPACR_ZEN_TRAP_NONE	(0x3 << 16) /* No traps */
146 #define	CPACR_FPEN_MASK		(0x3 << 20)
147 #define	 CPACR_FPEN_TRAP_ALL1	(0x0 << 20) /* Traps from EL0 and EL1 */
148 #define	 CPACR_FPEN_TRAP_EL0	(0x1 << 20) /* Traps from EL0 */
149 #define	 CPACR_FPEN_TRAP_ALL2	(0x2 << 20) /* Traps from EL0 and EL1 */
150 #define	 CPACR_FPEN_TRAP_NONE	(0x3 << 20) /* No traps */
151 #define	CPACR_TTA		(0x1 << 28)
152 
153 /* CSSELR_EL1 - Cache size selection register */
154 #define	CSSELR_Level(i)		(i << 1)
155 #define	CSSELR_InD		0x00000001
156 
157 /* CTR_EL0 - Cache Type Register */
158 #define	CTR_RES1		(1 << 31)
159 #define	CTR_TminLine_SHIFT	32
160 #define	CTR_TminLine_MASK	(UL(0x3f) << CTR_TminLine_SHIFT)
161 #define	CTR_TminLine_VAL(reg)	((reg) & CTR_TminLine_MASK)
162 #define	CTR_DIC_SHIFT		29
163 #define	CTR_DIC_MASK		(0x1 << CTR_DIC_SHIFT)
164 #define	CTR_DIC_VAL(reg)	((reg) & CTR_DIC_MASK)
165 #define	CTR_IDC_SHIFT		28
166 #define	CTR_IDC_MASK		(0x1 << CTR_IDC_SHIFT)
167 #define	CTR_IDC_VAL(reg)	((reg) & CTR_IDC_MASK)
168 #define	CTR_CWG_SHIFT		24
169 #define	CTR_CWG_MASK		(0xf << CTR_CWG_SHIFT)
170 #define	CTR_CWG_VAL(reg)	((reg) & CTR_CWG_MASK)
171 #define	CTR_CWG_SIZE(reg)	(4 << (CTR_CWG_VAL(reg) >> CTR_CWG_SHIFT))
172 #define	CTR_ERG_SHIFT		20
173 #define	CTR_ERG_MASK		(0xf << CTR_ERG_SHIFT)
174 #define	CTR_ERG_VAL(reg)	((reg) & CTR_ERG_MASK)
175 #define	CTR_ERG_SIZE(reg)	(4 << (CTR_ERG_VAL(reg) >> CTR_ERG_SHIFT))
176 #define	CTR_DLINE_SHIFT		16
177 #define	CTR_DLINE_MASK		(0xf << CTR_DLINE_SHIFT)
178 #define	CTR_DLINE_VAL(reg)	((reg) & CTR_DLINE_MASK)
179 #define	CTR_DLINE_SIZE(reg)	(4 << (CTR_DLINE_VAL(reg) >> CTR_DLINE_SHIFT))
180 #define	CTR_L1IP_SHIFT		14
181 #define	CTR_L1IP_MASK		(0x3 << CTR_L1IP_SHIFT)
182 #define	CTR_L1IP_VAL(reg)	((reg) & CTR_L1IP_MASK)
183 #define	 CTR_L1IP_VPIPT		(0 << CTR_L1IP_SHIFT)
184 #define	 CTR_L1IP_AIVIVT	(1 << CTR_L1IP_SHIFT)
185 #define	 CTR_L1IP_VIPT		(2 << CTR_L1IP_SHIFT)
186 #define	 CTR_L1IP_PIPT		(3 << CTR_L1IP_SHIFT)
187 #define	CTR_ILINE_SHIFT		0
188 #define	CTR_ILINE_MASK		(0xf << CTR_ILINE_SHIFT)
189 #define	CTR_ILINE_VAL(reg)	((reg) & CTR_ILINE_MASK)
190 #define	CTR_ILINE_SIZE(reg)	(4 << (CTR_ILINE_VAL(reg) >> CTR_ILINE_SHIFT))
191 
192 /* DAIFSet/DAIFClear */
193 #define	DAIF_D			(1 << 3)
194 #define	DAIF_A			(1 << 2)
195 #define	DAIF_I			(1 << 1)
196 #define	DAIF_F			(1 << 0)
197 #define	DAIF_ALL		(DAIF_D | DAIF_A | DAIF_I | DAIF_F)
198 #define	DAIF_INTR		(DAIF_I)	/* All exceptions that pass */
199 						/* through the intr framework */
200 
201 /* DBGBCR<n>_EL1 - Debug Breakpoint Control Registers */
202 #define	DBGBCR_EL1_op0		2
203 #define	DBGBCR_EL1_op1		0
204 #define	DBGBCR_EL1_CRn		0
205 /* DBGBCR_EL1_CRm indicates which watchpoint this register is for */
206 #define	DBGBCR_EL1_op2		5
207 #define	DBGBCR_EN		0x1
208 #define	DBGBCR_PMC_SHIFT	1
209 #define	DBGBCR_PMC		(0x3 << DBGBCR_PMC_SHIFT)
210 #define	 DBGBCR_PMC_EL1		(0x1 << DBGBCR_PMC_SHIFT)
211 #define	 DBGBCR_PMC_EL0		(0x2 << DBGBCR_PMC_SHIFT)
212 #define	DBGBCR_BAS_SHIFT	5
213 #define	DBGBCR_BAS		(0xf << DBGBCR_BAS_SHIFT)
214 #define	DBGBCR_HMC_SHIFT	13
215 #define	DBGBCR_HMC		(0x1 << DBGBCR_HMC_SHIFT)
216 #define	DBGBCR_SSC_SHIFT	14
217 #define	DBGBCR_SSC		(0x3 << DBGBCR_SSC_SHIFT)
218 #define	DBGBCR_LBN_SHIFT	16
219 #define	DBGBCR_LBN		(0xf << DBGBCR_LBN_SHIFT)
220 #define	DBGBCR_BT_SHIFT		20
221 #define	DBGBCR_BT		(0xf << DBGBCR_BT_SHIFT)
222 
223 /* DBGBVR<n>_EL1 - Debug Breakpoint Value Registers */
224 #define	DBGBVR_EL1_op0		2
225 #define	DBGBVR_EL1_op1		0
226 #define	DBGBVR_EL1_CRn		0
227 /* DBGBVR_EL1_CRm indicates which watchpoint this register is for */
228 #define	DBGBVR_EL1_op2		4
229 
230 /* DBGWCR<n>_EL1 - Debug Watchpoint Control Registers */
231 #define	DBGWCR_EL1_op0		2
232 #define	DBGWCR_EL1_op1		0
233 #define	DBGWCR_EL1_CRn		0
234 /* DBGWCR_EL1_CRm indicates which watchpoint this register is for */
235 #define	DBGWCR_EL1_op2		7
236 #define	DBGWCR_EN		0x1
237 #define	DBGWCR_PAC_SHIFT	1
238 #define	DBGWCR_PAC		(0x3 << DBGWCR_PAC_SHIFT)
239 #define	 DBGWCR_PAC_EL1		(0x1 << DBGWCR_PAC_SHIFT)
240 #define	 DBGWCR_PAC_EL0		(0x2 << DBGWCR_PAC_SHIFT)
241 #define	DBGWCR_LSC_SHIFT	3
242 #define	DBGWCR_LSC		(0x3 << DBGWCR_LSC_SHIFT)
243 #define	DBGWCR_BAS_SHIFT	5
244 #define	DBGWCR_BAS		(0xff << DBGWCR_BAS_SHIFT)
245 #define	DBGWCR_HMC_SHIFT	13
246 #define	DBGWCR_HMC		(0x1 << DBGWCR_HMC_SHIFT)
247 #define	DBGWCR_SSC_SHIFT	14
248 #define	DBGWCR_SSC		(0x3 << DBGWCR_SSC_SHIFT)
249 #define	DBGWCR_LBN_SHIFT	16
250 #define	DBGWCR_LBN		(0xf << DBGWCR_LBN_SHIFT)
251 #define	DBGWCR_WT_SHIFT		20
252 #define	DBGWCR_WT		(0x1 << DBGWCR_WT_SHIFT)
253 #define	DBGWCR_MASK_SHIFT	24
254 #define	DBGWCR_MASK		(0x1f << DBGWCR_MASK_SHIFT)
255 
256 /* DBGWVR<n>_EL1 - Debug Watchpoint Value Registers */
257 #define	DBGWVR_EL1_op0		2
258 #define	DBGWVR_EL1_op1		0
259 #define	DBGWVR_EL1_CRn		0
260 /* DBGWVR_EL1_CRm indicates which watchpoint this register is for */
261 #define	DBGWVR_EL1_op2		6
262 
263 /* DCZID_EL0 - Data Cache Zero ID register */
264 #define DCZID_DZP		(1 << 4) /* DC ZVA prohibited if non-0 */
265 #define DCZID_BS_SHIFT		0
266 #define DCZID_BS_MASK		(0xf << DCZID_BS_SHIFT)
267 #define	DCZID_BS_SIZE(reg)	(((reg) & DCZID_BS_MASK) >> DCZID_BS_SHIFT)
268 
269 /* DBGAUTHSTATUS_EL1 */
270 #define	DBGAUTHSTATUS_EL1		MRS_REG(DBGAUTHSTATUS_EL1)
271 #define	DBGAUTHSTATUS_EL1_op0		2
272 #define	DBGAUTHSTATUS_EL1_op1		0
273 #define	DBGAUTHSTATUS_EL1_CRn		7
274 #define	DBGAUTHSTATUS_EL1_CRm		14
275 #define	DBGAUTHSTATUS_EL1_op2		6
276 
277 /* DBGCLAIMCLR_EL1 */
278 #define	DBGCLAIMCLR_EL1			MRS_REG(DBGCLAIMCLR_EL1)
279 #define	DBGCLAIMCLR_EL1_op0		2
280 #define	DBGCLAIMCLR_EL1_op1		0
281 #define	DBGCLAIMCLR_EL1_CRn		7
282 #define	DBGCLAIMCLR_EL1_CRm		9
283 #define	DBGCLAIMCLR_EL1_op2		6
284 
285 /* DBGCLAIMSET_EL1 */
286 #define	DBGCLAIMSET_EL1			MRS_REG(DBGCLAIMSET_EL1)
287 #define	DBGCLAIMSET_EL1_op0		2
288 #define	DBGCLAIMSET_EL1_op1		0
289 #define	DBGCLAIMSET_EL1_CRn		7
290 #define	DBGCLAIMSET_EL1_CRm		8
291 #define	DBGCLAIMSET_EL1_op2		6
292 
293 /* DBGPRCR_EL1 */
294 #define	DBGPRCR_EL1			MRS_REG(DBGPRCR_EL1)
295 #define	DBGPRCR_EL1_op0			2
296 #define	DBGPRCR_EL1_op1			0
297 #define	DBGPRCR_EL1_CRn			1
298 #define	DBGPRCR_EL1_CRm			4
299 #define	DBGPRCR_EL1_op2			4
300 
301 /* ESR_ELx */
302 #define	ESR_ELx_ISS_MASK	0x01ffffff
303 #define	 ISS_FP_TFV_SHIFT	23
304 #define	 ISS_FP_TFV		(0x01 << ISS_FP_TFV_SHIFT)
305 #define	 ISS_FP_IOF		0x01
306 #define	 ISS_FP_DZF		0x02
307 #define	 ISS_FP_OFF		0x04
308 #define	 ISS_FP_UFF		0x08
309 #define	 ISS_FP_IXF		0x10
310 #define	 ISS_FP_IDF		0x80
311 #define	 ISS_INSN_FnV		(0x01 << 10)
312 #define	 ISS_INSN_EA		(0x01 << 9)
313 #define	 ISS_INSN_S1PTW		(0x01 << 7)
314 #define	 ISS_INSN_IFSC_MASK	(0x1f << 0)
315 
316 #define	 ISS_MSR_DIR_SHIFT	0
317 #define	 ISS_MSR_DIR		(0x01 << ISS_MSR_DIR_SHIFT)
318 #define	 ISS_MSR_Rt_SHIFT	5
319 #define	 ISS_MSR_Rt_MASK	(0x1f << ISS_MSR_Rt_SHIFT)
320 #define	 ISS_MSR_Rt(x)		(((x) & ISS_MSR_Rt_MASK) >> ISS_MSR_Rt_SHIFT)
321 #define	 ISS_MSR_CRm_SHIFT	1
322 #define	 ISS_MSR_CRm_MASK	(0xf << ISS_MSR_CRm_SHIFT)
323 #define	 ISS_MSR_CRm(x)		(((x) & ISS_MSR_CRm_MASK) >> ISS_MSR_CRm_SHIFT)
324 #define	 ISS_MSR_CRn_SHIFT	10
325 #define	 ISS_MSR_CRn_MASK	(0xf << ISS_MSR_CRn_SHIFT)
326 #define	 ISS_MSR_CRn(x)		(((x) & ISS_MSR_CRn_MASK) >> ISS_MSR_CRn_SHIFT)
327 #define	 ISS_MSR_OP1_SHIFT	14
328 #define	 ISS_MSR_OP1_MASK	(0x7 << ISS_MSR_OP1_SHIFT)
329 #define	 ISS_MSR_OP1(x)		(((x) & ISS_MSR_OP1_MASK) >> ISS_MSR_OP1_SHIFT)
330 #define	 ISS_MSR_OP2_SHIFT	17
331 #define	 ISS_MSR_OP2_MASK	(0x7 << ISS_MSR_OP2_SHIFT)
332 #define	 ISS_MSR_OP2(x)		(((x) & ISS_MSR_OP2_MASK) >> ISS_MSR_OP2_SHIFT)
333 #define	 ISS_MSR_OP0_SHIFT	20
334 #define	 ISS_MSR_OP0_MASK	(0x3 << ISS_MSR_OP0_SHIFT)
335 #define	 ISS_MSR_OP0(x)		(((x) & ISS_MSR_OP0_MASK) >> ISS_MSR_OP0_SHIFT)
336 #define	 ISS_MSR_REG_MASK	\
337     (ISS_MSR_OP0_MASK | ISS_MSR_OP2_MASK | ISS_MSR_OP1_MASK | 	\
338      ISS_MSR_CRn_MASK | ISS_MSR_CRm_MASK)
339 
340 #define	 ISS_DATA_ISV_SHIFT	24
341 #define	 ISS_DATA_ISV		(0x01 << ISS_DATA_ISV_SHIFT)
342 #define	 ISS_DATA_SAS_SHIFT	22
343 #define	 ISS_DATA_SAS_MASK	(0x03 << ISS_DATA_SAS_SHIFT)
344 #define	 ISS_DATA_SSE_SHIFT	21
345 #define	 ISS_DATA_SSE		(0x01 << ISS_DATA_SSE_SHIFT)
346 #define	 ISS_DATA_SRT_SHIFT	16
347 #define	 ISS_DATA_SRT_MASK	(0x1f << ISS_DATA_SRT_SHIFT)
348 #define	 ISS_DATA_SF		(0x01 << 15)
349 #define	 ISS_DATA_AR		(0x01 << 14)
350 #define	 ISS_DATA_FnV		(0x01 << 10)
351 #define	 ISS_DATA_EA		(0x01 << 9)
352 #define	 ISS_DATA_CM		(0x01 << 8)
353 #define	 ISS_DATA_S1PTW		(0x01 << 7)
354 #define	 ISS_DATA_WnR_SHIFT	6
355 #define	 ISS_DATA_WnR		(0x01 << ISS_DATA_WnR_SHIFT)
356 #define	 ISS_DATA_DFSC_MASK	(0x3f << 0)
357 #define	 ISS_DATA_DFSC_ASF_L0	(0x00 << 0)
358 #define	 ISS_DATA_DFSC_ASF_L1	(0x01 << 0)
359 #define	 ISS_DATA_DFSC_ASF_L2	(0x02 << 0)
360 #define	 ISS_DATA_DFSC_ASF_L3	(0x03 << 0)
361 #define	 ISS_DATA_DFSC_TF_L0	(0x04 << 0)
362 #define	 ISS_DATA_DFSC_TF_L1	(0x05 << 0)
363 #define	 ISS_DATA_DFSC_TF_L2	(0x06 << 0)
364 #define	 ISS_DATA_DFSC_TF_L3	(0x07 << 0)
365 #define	 ISS_DATA_DFSC_AFF_L1	(0x09 << 0)
366 #define	 ISS_DATA_DFSC_AFF_L2	(0x0a << 0)
367 #define	 ISS_DATA_DFSC_AFF_L3	(0x0b << 0)
368 #define	 ISS_DATA_DFSC_PF_L1	(0x0d << 0)
369 #define	 ISS_DATA_DFSC_PF_L2	(0x0e << 0)
370 #define	 ISS_DATA_DFSC_PF_L3	(0x0f << 0)
371 #define	 ISS_DATA_DFSC_EXT	(0x10 << 0)
372 #define	 ISS_DATA_DFSC_EXT_L0	(0x14 << 0)
373 #define	 ISS_DATA_DFSC_EXT_L1	(0x15 << 0)
374 #define	 ISS_DATA_DFSC_EXT_L2	(0x16 << 0)
375 #define	 ISS_DATA_DFSC_EXT_L3	(0x17 << 0)
376 #define	 ISS_DATA_DFSC_ECC	(0x18 << 0)
377 #define	 ISS_DATA_DFSC_ECC_L0	(0x1c << 0)
378 #define	 ISS_DATA_DFSC_ECC_L1	(0x1d << 0)
379 #define	 ISS_DATA_DFSC_ECC_L2	(0x1e << 0)
380 #define	 ISS_DATA_DFSC_ECC_L3	(0x1f << 0)
381 #define	 ISS_DATA_DFSC_ALIGN	(0x21 << 0)
382 #define	 ISS_DATA_DFSC_TLB_CONFLICT (0x30 << 0)
383 #define	ESR_ELx_IL		(0x01 << 25)
384 #define	ESR_ELx_EC_SHIFT	26
385 #define	ESR_ELx_EC_MASK		(0x3f << 26)
386 #define	ESR_ELx_EXCEPTION(esr)	(((esr) & ESR_ELx_EC_MASK) >> ESR_ELx_EC_SHIFT)
387 #define	 EXCP_UNKNOWN		0x00	/* Unkwn exception */
388 #define	 EXCP_TRAP_WFI_WFE	0x01	/* Trapped WFI or WFE */
389 #define	 EXCP_FP_SIMD		0x07	/* VFP/SIMD trap */
390 #define	 EXCP_ILL_STATE		0x0e	/* Illegal execution state */
391 #define	 EXCP_SVC32		0x11	/* SVC trap for AArch32 */
392 #define	 EXCP_SVC64		0x15	/* SVC trap for AArch64 */
393 #define	 EXCP_HVC		0x16	/* HVC trap */
394 #define	 EXCP_MSR		0x18	/* MSR/MRS trap */
395 #define	 EXCP_SVE		0x19	/* SVE trap */
396 #define	 EXCP_FPAC		0x1c	/* Faulting PAC trap */
397 #define	 EXCP_INSN_ABORT_L	0x20	/* Instruction abort, from lower EL */
398 #define	 EXCP_INSN_ABORT	0x21	/* Instruction abort, from same EL */
399 #define	 EXCP_PC_ALIGN		0x22	/* PC alignment fault */
400 #define	 EXCP_DATA_ABORT_L	0x24	/* Data abort, from lower EL */
401 #define	 EXCP_DATA_ABORT	0x25	/* Data abort, from same EL */
402 #define	 EXCP_SP_ALIGN		0x26	/* SP slignment fault */
403 #define	 EXCP_TRAP_FP		0x2c	/* Trapped FP exception */
404 #define	 EXCP_SERROR		0x2f	/* SError interrupt */
405 #define	 EXCP_BRKPT_EL0		0x30	/* Hardware breakpoint, from same EL */
406 #define	 EXCP_SOFTSTP_EL0	0x32	/* Software Step, from lower EL */
407 #define	 EXCP_SOFTSTP_EL1	0x33	/* Software Step, from same EL */
408 #define	 EXCP_WATCHPT_EL0	0x34	/* Watchpoint, from lower EL */
409 #define	 EXCP_WATCHPT_EL1	0x35	/* Watchpoint, from same EL */
410 #define	 EXCP_BRKPT_32		0x38    /* 32bits breakpoint */
411 #define	 EXCP_BRK		0x3c	/* Breakpoint */
412 
413 /* ICC_CTLR_EL1 */
414 #define	ICC_CTLR_EL1_EOIMODE	(1U << 1)
415 
416 /* ICC_IAR1_EL1 */
417 #define	ICC_IAR1_EL1_SPUR	(0x03ff)
418 
419 /* ICC_IGRPEN0_EL1 */
420 #define	ICC_IGRPEN0_EL1_EN	(1U << 0)
421 
422 /* ICC_PMR_EL1 */
423 #define	ICC_PMR_EL1_PRIO_MASK	(0xFFUL)
424 
425 /* ICC_SGI1R_EL1 */
426 #define	ICC_SGI1R_EL1			MRS_REG(ICC_SGI1R_EL1)
427 #define	ICC_SGI1R_EL1_op0		3
428 #define	ICC_SGI1R_EL1_op1		0
429 #define	ICC_SGI1R_EL1_CRn		12
430 #define	ICC_SGI1R_EL1_CRm		11
431 #define	ICC_SGI1R_EL1_op2		5
432 #define	ICC_SGI1R_EL1_TL_MASK		0xffffUL
433 #define	ICC_SGI1R_EL1_AFF1_SHIFT	16
434 #define	ICC_SGI1R_EL1_SGIID_SHIFT	24
435 #define	ICC_SGI1R_EL1_AFF2_SHIFT	32
436 #define	ICC_SGI1R_EL1_AFF3_SHIFT	48
437 #define	ICC_SGI1R_EL1_SGIID_MASK	0xfUL
438 #define	ICC_SGI1R_EL1_IRM		(0x1UL << 40)
439 
440 /* ICC_SRE_EL1 */
441 #define	ICC_SRE_EL1_SRE		(1U << 0)
442 
443 /* ID_AA64DFR0_EL1 */
444 #define	ID_AA64DFR0_EL1			MRS_REG(ID_AA64DFR0_EL1)
445 #define	ID_AA64DFR0_EL1_op0		0x3
446 #define	ID_AA64DFR0_EL1_op1		0x0
447 #define	ID_AA64DFR0_EL1_CRn		0x0
448 #define	ID_AA64DFR0_EL1_CRm		0x5
449 #define	ID_AA64DFR0_EL1_op2		0x0
450 #define	ID_AA64DFR0_DebugVer_SHIFT	0
451 #define	ID_AA64DFR0_DebugVer_MASK	(UL(0xf) << ID_AA64DFR0_DebugVer_SHIFT)
452 #define	ID_AA64DFR0_DebugVer_VAL(x)	((x) & ID_AA64DFR0_DebugVer_MASK)
453 #define	 ID_AA64DFR0_DebugVer_8		(UL(0x6) << ID_AA64DFR0_DebugVer_SHIFT)
454 #define	 ID_AA64DFR0_DebugVer_8_VHE	(UL(0x7) << ID_AA64DFR0_DebugVer_SHIFT)
455 #define	 ID_AA64DFR0_DebugVer_8_2	(UL(0x8) << ID_AA64DFR0_DebugVer_SHIFT)
456 #define	 ID_AA64DFR0_DebugVer_8_4	(UL(0x9) << ID_AA64DFR0_DebugVer_SHIFT)
457 #define	ID_AA64DFR0_TraceVer_SHIFT	4
458 #define	ID_AA64DFR0_TraceVer_MASK	(UL(0xf) << ID_AA64DFR0_TraceVer_SHIFT)
459 #define	ID_AA64DFR0_TraceVer_VAL(x)	((x) & ID_AA64DFR0_TraceVer_MASK)
460 #define	 ID_AA64DFR0_TraceVer_NONE	(UL(0x0) << ID_AA64DFR0_TraceVer_SHIFT)
461 #define	 ID_AA64DFR0_TraceVer_IMPL	(UL(0x1) << ID_AA64DFR0_TraceVer_SHIFT)
462 #define	ID_AA64DFR0_PMUVer_SHIFT	8
463 #define	ID_AA64DFR0_PMUVer_MASK		(UL(0xf) << ID_AA64DFR0_PMUVer_SHIFT)
464 #define	ID_AA64DFR0_PMUVer_VAL(x)	((x) & ID_AA64DFR0_PMUVer_MASK)
465 #define	 ID_AA64DFR0_PMUVer_NONE	(UL(0x0) << ID_AA64DFR0_PMUVer_SHIFT)
466 #define	 ID_AA64DFR0_PMUVer_3		(UL(0x1) << ID_AA64DFR0_PMUVer_SHIFT)
467 #define	 ID_AA64DFR0_PMUVer_3_1		(UL(0x4) << ID_AA64DFR0_PMUVer_SHIFT)
468 #define	 ID_AA64DFR0_PMUVer_3_4		(UL(0x5) << ID_AA64DFR0_PMUVer_SHIFT)
469 #define	 ID_AA64DFR0_PMUVer_3_5		(UL(0x6) << ID_AA64DFR0_PMUVer_SHIFT)
470 #define	 ID_AA64DFR0_PMUVer_IMPL	(UL(0xf) << ID_AA64DFR0_PMUVer_SHIFT)
471 #define	ID_AA64DFR0_BRPs_SHIFT		12
472 #define	ID_AA64DFR0_BRPs_MASK		(UL(0xf) << ID_AA64DFR0_BRPs_SHIFT)
473 #define	ID_AA64DFR0_BRPs_VAL(x)	\
474     ((((x) >> ID_AA64DFR0_BRPs_SHIFT) & 0xf) + 1)
475 #define	ID_AA64DFR0_WRPs_SHIFT		20
476 #define	ID_AA64DFR0_WRPs_MASK		(UL(0xf) << ID_AA64DFR0_WRPs_SHIFT)
477 #define	ID_AA64DFR0_WRPs_VAL(x)	\
478     ((((x) >> ID_AA64DFR0_WRPs_SHIFT) & 0xf) + 1)
479 #define	ID_AA64DFR0_CTX_CMPs_SHIFT	28
480 #define	ID_AA64DFR0_CTX_CMPs_MASK	(UL(0xf) << ID_AA64DFR0_CTX_CMPs_SHIFT)
481 #define	ID_AA64DFR0_CTX_CMPs_VAL(x)	\
482     ((((x) >> ID_AA64DFR0_CTX_CMPs_SHIFT) & 0xf) + 1)
483 #define	ID_AA64DFR0_PMSVer_SHIFT	32
484 #define	ID_AA64DFR0_PMSVer_MASK		(UL(0xf) << ID_AA64DFR0_PMSVer_SHIFT)
485 #define	ID_AA64DFR0_PMSVer_VAL(x)	((x) & ID_AA64DFR0_PMSVer_MASK)
486 #define	 ID_AA64DFR0_PMSVer_NONE	(UL(0x0) << ID_AA64DFR0_PMSVer_SHIFT)
487 #define	 ID_AA64DFR0_PMSVer_SPE		(UL(0x1) << ID_AA64DFR0_PMSVer_SHIFT)
488 #define	 ID_AA64DFR0_PMSVer_SPE_8_3	(UL(0x2) << ID_AA64DFR0_PMSVer_SHIFT)
489 #define	ID_AA64DFR0_DoubleLock_SHIFT	36
490 #define	ID_AA64DFR0_DoubleLock_MASK	(UL(0xf) << ID_AA64DFR0_DoubleLock_SHIFT)
491 #define	ID_AA64DFR0_DoubleLock_VAL(x)	((x) & ID_AA64DFR0_DoubleLock_MASK)
492 #define	 ID_AA64DFR0_DoubleLock_IMPL	(UL(0x0) << ID_AA64DFR0_DoubleLock_SHIFT)
493 #define	 ID_AA64DFR0_DoubleLock_NONE	(UL(0xf) << ID_AA64DFR0_DoubleLock_SHIFT)
494 #define	ID_AA64DFR0_TraceFilt_SHIFT	40
495 #define	ID_AA64DFR0_TraceFilt_MASK	(UL(0xf) << ID_AA64DFR0_TraceFilt_SHIFT)
496 #define	ID_AA64DFR0_TraceFilt_VAL(x)	((x) & ID_AA64DFR0_TraceFilt_MASK)
497 #define	 ID_AA64DFR0_TraceFilt_NONE	(UL(0x0) << ID_AA64DFR0_TraceFilt_SHIFT)
498 #define	 ID_AA64DFR0_TraceFilt_8_4	(UL(0x1) << ID_AA64DFR0_TraceFilt_SHIFT)
499 
500 /* ID_AA64ISAR0_EL1 */
501 #define	ID_AA64ISAR0_EL1		MRS_REG(ID_AA64ISAR0_EL1)
502 #define	ID_AA64ISAR0_EL1_op0		0x3
503 #define	ID_AA64ISAR0_EL1_op1		0x0
504 #define	ID_AA64ISAR0_EL1_CRn		0x0
505 #define	ID_AA64ISAR0_EL1_CRm		0x6
506 #define	ID_AA64ISAR0_EL1_op2		0x0
507 #define	ID_AA64ISAR0_AES_SHIFT		4
508 #define	ID_AA64ISAR0_AES_MASK		(UL(0xf) << ID_AA64ISAR0_AES_SHIFT)
509 #define	ID_AA64ISAR0_AES_VAL(x)		((x) & ID_AA64ISAR0_AES_MASK)
510 #define	 ID_AA64ISAR0_AES_NONE		(UL(0x0) << ID_AA64ISAR0_AES_SHIFT)
511 #define	 ID_AA64ISAR0_AES_BASE		(UL(0x1) << ID_AA64ISAR0_AES_SHIFT)
512 #define	 ID_AA64ISAR0_AES_PMULL		(UL(0x2) << ID_AA64ISAR0_AES_SHIFT)
513 #define	ID_AA64ISAR0_SHA1_SHIFT		8
514 #define	ID_AA64ISAR0_SHA1_MASK		(UL(0xf) << ID_AA64ISAR0_SHA1_SHIFT)
515 #define	ID_AA64ISAR0_SHA1_VAL(x)	((x) & ID_AA64ISAR0_SHA1_MASK)
516 #define	 ID_AA64ISAR0_SHA1_NONE		(UL(0x0) << ID_AA64ISAR0_SHA1_SHIFT)
517 #define	 ID_AA64ISAR0_SHA1_BASE		(UL(0x1) << ID_AA64ISAR0_SHA1_SHIFT)
518 #define	ID_AA64ISAR0_SHA2_SHIFT		12
519 #define	ID_AA64ISAR0_SHA2_MASK		(UL(0xf) << ID_AA64ISAR0_SHA2_SHIFT)
520 #define	ID_AA64ISAR0_SHA2_VAL(x)	((x) & ID_AA64ISAR0_SHA2_MASK)
521 #define	 ID_AA64ISAR0_SHA2_NONE		(UL(0x0) << ID_AA64ISAR0_SHA2_SHIFT)
522 #define	 ID_AA64ISAR0_SHA2_BASE		(UL(0x1) << ID_AA64ISAR0_SHA2_SHIFT)
523 #define	 ID_AA64ISAR0_SHA2_512		(UL(0x2) << ID_AA64ISAR0_SHA2_SHIFT)
524 #define	ID_AA64ISAR0_CRC32_SHIFT	16
525 #define	ID_AA64ISAR0_CRC32_MASK		(UL(0xf) << ID_AA64ISAR0_CRC32_SHIFT)
526 #define	ID_AA64ISAR0_CRC32_VAL(x)	((x) & ID_AA64ISAR0_CRC32_MASK)
527 #define	 ID_AA64ISAR0_CRC32_NONE	(UL(0x0) << ID_AA64ISAR0_CRC32_SHIFT)
528 #define	 ID_AA64ISAR0_CRC32_BASE	(UL(0x1) << ID_AA64ISAR0_CRC32_SHIFT)
529 #define	ID_AA64ISAR0_Atomic_SHIFT	20
530 #define	ID_AA64ISAR0_Atomic_MASK	(UL(0xf) << ID_AA64ISAR0_Atomic_SHIFT)
531 #define	ID_AA64ISAR0_Atomic_VAL(x)	((x) & ID_AA64ISAR0_Atomic_MASK)
532 #define	 ID_AA64ISAR0_Atomic_NONE	(UL(0x0) << ID_AA64ISAR0_Atomic_SHIFT)
533 #define	 ID_AA64ISAR0_Atomic_IMPL	(UL(0x2) << ID_AA64ISAR0_Atomic_SHIFT)
534 #define	ID_AA64ISAR0_RDM_SHIFT		28
535 #define	ID_AA64ISAR0_RDM_MASK		(UL(0xf) << ID_AA64ISAR0_RDM_SHIFT)
536 #define	ID_AA64ISAR0_RDM_VAL(x)		((x) & ID_AA64ISAR0_RDM_MASK)
537 #define	 ID_AA64ISAR0_RDM_NONE		(UL(0x0) << ID_AA64ISAR0_RDM_SHIFT)
538 #define	 ID_AA64ISAR0_RDM_IMPL		(UL(0x1) << ID_AA64ISAR0_RDM_SHIFT)
539 #define	ID_AA64ISAR0_SHA3_SHIFT		32
540 #define	ID_AA64ISAR0_SHA3_MASK		(UL(0xf) << ID_AA64ISAR0_SHA3_SHIFT)
541 #define	ID_AA64ISAR0_SHA3_VAL(x)	((x) & ID_AA64ISAR0_SHA3_MASK)
542 #define	 ID_AA64ISAR0_SHA3_NONE		(UL(0x0) << ID_AA64ISAR0_SHA3_SHIFT)
543 #define	 ID_AA64ISAR0_SHA3_IMPL		(UL(0x1) << ID_AA64ISAR0_SHA3_SHIFT)
544 #define	ID_AA64ISAR0_SM3_SHIFT		36
545 #define	ID_AA64ISAR0_SM3_MASK		(UL(0xf) << ID_AA64ISAR0_SM3_SHIFT)
546 #define	ID_AA64ISAR0_SM3_VAL(x)		((x) & ID_AA64ISAR0_SM3_MASK)
547 #define	 ID_AA64ISAR0_SM3_NONE		(UL(0x0) << ID_AA64ISAR0_SM3_SHIFT)
548 #define	 ID_AA64ISAR0_SM3_IMPL		(UL(0x1) << ID_AA64ISAR0_SM3_SHIFT)
549 #define	ID_AA64ISAR0_SM4_SHIFT		40
550 #define	ID_AA64ISAR0_SM4_MASK		(UL(0xf) << ID_AA64ISAR0_SM4_SHIFT)
551 #define	ID_AA64ISAR0_SM4_VAL(x)		((x) & ID_AA64ISAR0_SM4_MASK)
552 #define	 ID_AA64ISAR0_SM4_NONE		(UL(0x0) << ID_AA64ISAR0_SM4_SHIFT)
553 #define	 ID_AA64ISAR0_SM4_IMPL		(UL(0x1) << ID_AA64ISAR0_SM4_SHIFT)
554 #define	ID_AA64ISAR0_DP_SHIFT		44
555 #define	ID_AA64ISAR0_DP_MASK		(UL(0xf) << ID_AA64ISAR0_DP_SHIFT)
556 #define	ID_AA64ISAR0_DP_VAL(x)		((x) & ID_AA64ISAR0_DP_MASK)
557 #define	 ID_AA64ISAR0_DP_NONE		(UL(0x0) << ID_AA64ISAR0_DP_SHIFT)
558 #define	 ID_AA64ISAR0_DP_IMPL		(UL(0x1) << ID_AA64ISAR0_DP_SHIFT)
559 #define	ID_AA64ISAR0_FHM_SHIFT		48
560 #define	ID_AA64ISAR0_FHM_MASK		(UL(0xf) << ID_AA64ISAR0_FHM_SHIFT)
561 #define	ID_AA64ISAR0_FHM_VAL(x)		((x) & ID_AA64ISAR0_FHM_MASK)
562 #define	 ID_AA64ISAR0_FHM_NONE		(UL(0x0) << ID_AA64ISAR0_FHM_SHIFT)
563 #define	 ID_AA64ISAR0_FHM_IMPL		(UL(0x1) << ID_AA64ISAR0_FHM_SHIFT)
564 #define	ID_AA64ISAR0_TS_SHIFT		52
565 #define	ID_AA64ISAR0_TS_MASK		(UL(0xf) << ID_AA64ISAR0_TS_SHIFT)
566 #define	ID_AA64ISAR0_TS_VAL(x)		((x) & ID_AA64ISAR0_TS_MASK)
567 #define	 ID_AA64ISAR0_TS_NONE		(UL(0x0) << ID_AA64ISAR0_TS_SHIFT)
568 #define	 ID_AA64ISAR0_TS_CondM_8_4	(UL(0x1) << ID_AA64ISAR0_TS_SHIFT)
569 #define	 ID_AA64ISAR0_TS_CondM_8_5	(UL(0x2) << ID_AA64ISAR0_TS_SHIFT)
570 #define	ID_AA64ISAR0_TLB_SHIFT		56
571 #define	ID_AA64ISAR0_TLB_MASK		(UL(0xf) << ID_AA64ISAR0_TLB_SHIFT)
572 #define	ID_AA64ISAR0_TLB_VAL(x)		((x) & ID_AA64ISAR0_TLB_MASK)
573 #define	 ID_AA64ISAR0_TLB_NONE		(UL(0x0) << ID_AA64ISAR0_TLB_SHIFT)
574 #define	 ID_AA64ISAR0_TLB_TLBIOS	(UL(0x1) << ID_AA64ISAR0_TLB_SHIFT)
575 #define	 ID_AA64ISAR0_TLB_TLBIOSR	(UL(0x2) << ID_AA64ISAR0_TLB_SHIFT)
576 #define	ID_AA64ISAR0_RNDR_SHIFT		60
577 #define	ID_AA64ISAR0_RNDR_MASK		(UL(0xf) << ID_AA64ISAR0_RNDR_SHIFT)
578 #define	ID_AA64ISAR0_RNDR_VAL(x)	((x) & ID_AA64ISAR0_RNDR_MASK)
579 #define	 ID_AA64ISAR0_RNDR_NONE		(UL(0x0) << ID_AA64ISAR0_RNDR_SHIFT)
580 #define	 ID_AA64ISAR0_RNDR_IMPL		(UL(0x1) << ID_AA64ISAR0_RNDR_SHIFT)
581 
582 /* ID_AA64ISAR1_EL1 */
583 #define	ID_AA64ISAR1_EL1		MRS_REG(ID_AA64ISAR1_EL1)
584 #define	ID_AA64ISAR1_EL1_op0		0x3
585 #define	ID_AA64ISAR1_EL1_op1		0x0
586 #define	ID_AA64ISAR1_EL1_CRn		0x0
587 #define	ID_AA64ISAR1_EL1_CRm		0x6
588 #define	ID_AA64ISAR1_EL1_op2		0x1
589 #define	ID_AA64ISAR1_DPB_SHIFT		0
590 #define	ID_AA64ISAR1_DPB_MASK		(UL(0xf) << ID_AA64ISAR1_DPB_SHIFT)
591 #define	ID_AA64ISAR1_DPB_VAL(x)		((x) & ID_AA64ISAR1_DPB_MASK)
592 #define	 ID_AA64ISAR1_DPB_NONE		(UL(0x0) << ID_AA64ISAR1_DPB_SHIFT)
593 #define	 ID_AA64ISAR1_DPB_DCCVAP	(UL(0x1) << ID_AA64ISAR1_DPB_SHIFT)
594 #define	 ID_AA64ISAR1_DPB_DCCVADP	(UL(0x2) << ID_AA64ISAR1_DPB_SHIFT)
595 #define	ID_AA64ISAR1_APA_SHIFT		4
596 #define	ID_AA64ISAR1_APA_MASK		(UL(0xf) << ID_AA64ISAR1_APA_SHIFT)
597 #define	ID_AA64ISAR1_APA_VAL(x)		((x) & ID_AA64ISAR1_APA_MASK)
598 #define	 ID_AA64ISAR1_APA_NONE		(UL(0x0) << ID_AA64ISAR1_APA_SHIFT)
599 #define	 ID_AA64ISAR1_APA_PAC		(UL(0x1) << ID_AA64ISAR1_APA_SHIFT)
600 #define	 ID_AA64ISAR1_APA_EPAC		(UL(0x2) << ID_AA64ISAR1_APA_SHIFT)
601 #define	 ID_AA64ISAR1_APA_EPAC2		(UL(0x3) << ID_AA64ISAR1_APA_SHIFT)
602 #define	 ID_AA64ISAR1_APA_FPAC		(UL(0x4) << ID_AA64ISAR1_APA_SHIFT)
603 #define	 ID_AA64ISAR1_APA_FPAC_COMBINED	(UL(0x5) << ID_AA64ISAR1_APA_SHIFT)
604 #define	ID_AA64ISAR1_API_SHIFT		8
605 #define	ID_AA64ISAR1_API_MASK		(UL(0xf) << ID_AA64ISAR1_API_SHIFT)
606 #define	ID_AA64ISAR1_API_VAL(x)		((x) & ID_AA64ISAR1_API_MASK)
607 #define	 ID_AA64ISAR1_API_NONE		(UL(0x0) << ID_AA64ISAR1_API_SHIFT)
608 #define	 ID_AA64ISAR1_API_PAC		(UL(0x1) << ID_AA64ISAR1_API_SHIFT)
609 #define	 ID_AA64ISAR1_API_EPAC		(UL(0x2) << ID_AA64ISAR1_API_SHIFT)
610 #define	 ID_AA64ISAR1_API_EPAC2		(UL(0x3) << ID_AA64ISAR1_API_SHIFT)
611 #define	 ID_AA64ISAR1_API_FPAC		(UL(0x4) << ID_AA64ISAR1_API_SHIFT)
612 #define	 ID_AA64ISAR1_API_FPAC_COMBINED	(UL(0x5) << ID_AA64ISAR1_API_SHIFT)
613 #define	ID_AA64ISAR1_JSCVT_SHIFT	12
614 #define	ID_AA64ISAR1_JSCVT_MASK		(UL(0xf) << ID_AA64ISAR1_JSCVT_SHIFT)
615 #define	ID_AA64ISAR1_JSCVT_VAL(x)	((x) & ID_AA64ISAR1_JSCVT_MASK)
616 #define	 ID_AA64ISAR1_JSCVT_NONE	(UL(0x0) << ID_AA64ISAR1_JSCVT_SHIFT)
617 #define	 ID_AA64ISAR1_JSCVT_IMPL	(UL(0x1) << ID_AA64ISAR1_JSCVT_SHIFT)
618 #define	ID_AA64ISAR1_FCMA_SHIFT		16
619 #define	ID_AA64ISAR1_FCMA_MASK		(UL(0xf) << ID_AA64ISAR1_FCMA_SHIFT)
620 #define	ID_AA64ISAR1_FCMA_VAL(x)	((x) & ID_AA64ISAR1_FCMA_MASK)
621 #define	 ID_AA64ISAR1_FCMA_NONE		(UL(0x0) << ID_AA64ISAR1_FCMA_SHIFT)
622 #define	 ID_AA64ISAR1_FCMA_IMPL		(UL(0x1) << ID_AA64ISAR1_FCMA_SHIFT)
623 #define	ID_AA64ISAR1_LRCPC_SHIFT	20
624 #define	ID_AA64ISAR1_LRCPC_MASK		(UL(0xf) << ID_AA64ISAR1_LRCPC_SHIFT)
625 #define	ID_AA64ISAR1_LRCPC_VAL(x)	((x) & ID_AA64ISAR1_LRCPC_MASK)
626 #define	 ID_AA64ISAR1_LRCPC_NONE	(UL(0x0) << ID_AA64ISAR1_LRCPC_SHIFT)
627 #define	 ID_AA64ISAR1_LRCPC_RCPC_8_3	(UL(0x1) << ID_AA64ISAR1_LRCPC_SHIFT)
628 #define	 ID_AA64ISAR1_LRCPC_RCPC_8_4	(UL(0x2) << ID_AA64ISAR1_LRCPC_SHIFT)
629 #define	ID_AA64ISAR1_GPA_SHIFT		24
630 #define	ID_AA64ISAR1_GPA_MASK		(UL(0xf) << ID_AA64ISAR1_GPA_SHIFT)
631 #define	ID_AA64ISAR1_GPA_VAL(x)		((x) & ID_AA64ISAR1_GPA_MASK)
632 #define	 ID_AA64ISAR1_GPA_NONE		(UL(0x0) << ID_AA64ISAR1_GPA_SHIFT)
633 #define	 ID_AA64ISAR1_GPA_IMPL		(UL(0x1) << ID_AA64ISAR1_GPA_SHIFT)
634 #define	ID_AA64ISAR1_GPI_SHIFT		28
635 #define	ID_AA64ISAR1_GPI_MASK		(UL(0xf) << ID_AA64ISAR1_GPI_SHIFT)
636 #define	ID_AA64ISAR1_GPI_VAL(x)		((x) & ID_AA64ISAR1_GPI_MASK)
637 #define	 ID_AA64ISAR1_GPI_NONE		(UL(0x0) << ID_AA64ISAR1_GPI_SHIFT)
638 #define	 ID_AA64ISAR1_GPI_IMPL		(UL(0x1) << ID_AA64ISAR1_GPI_SHIFT)
639 #define	ID_AA64ISAR1_FRINTTS_SHIFT	32
640 #define	ID_AA64ISAR1_FRINTTS_MASK	(UL(0xf) << ID_AA64ISAR1_FRINTTS_SHIFT)
641 #define	ID_AA64ISAR1_FRINTTS_VAL(x)	((x) & ID_AA64ISAR1_FRINTTS_MASK)
642 #define	 ID_AA64ISAR1_FRINTTS_NONE	(UL(0x0) << ID_AA64ISAR1_FRINTTS_SHIFT)
643 #define	 ID_AA64ISAR1_FRINTTS_IMPL	(UL(0x1) << ID_AA64ISAR1_FRINTTS_SHIFT)
644 #define	ID_AA64ISAR1_SB_SHIFT		36
645 #define	ID_AA64ISAR1_SB_MASK		(UL(0xf) << ID_AA64ISAR1_SB_SHIFT)
646 #define	ID_AA64ISAR1_SB_VAL(x)		((x) & ID_AA64ISAR1_SB_MASK)
647 #define	 ID_AA64ISAR1_SB_NONE		(UL(0x0) << ID_AA64ISAR1_SB_SHIFT)
648 #define	 ID_AA64ISAR1_SB_IMPL		(UL(0x1) << ID_AA64ISAR1_SB_SHIFT)
649 #define	ID_AA64ISAR1_SPECRES_SHIFT	40
650 #define	ID_AA64ISAR1_SPECRES_MASK	(UL(0xf) << ID_AA64ISAR1_SPECRES_SHIFT)
651 #define	ID_AA64ISAR1_SPECRES_VAL(x)	((x) & ID_AA64ISAR1_SPECRES_MASK)
652 #define	 ID_AA64ISAR1_SPECRES_NONE	(UL(0x0) << ID_AA64ISAR1_SPECRES_SHIFT)
653 #define	 ID_AA64ISAR1_SPECRES_IMPL	(UL(0x1) << ID_AA64ISAR1_SPECRES_SHIFT)
654 #define	ID_AA64ISAR1_BF16_SHIFT		44
655 #define	ID_AA64ISAR1_BF16_MASK		(UL(0xf) << ID_AA64ISAR1_BF16_SHIFT)
656 #define	ID_AA64ISAR1_BF16_VAL(x)	((x) & ID_AA64ISAR1_BF16_MASK)
657 #define	 ID_AA64ISAR1_BF16_NONE		(UL(0x0) << ID_AA64ISAR1_BF16_SHIFT)
658 #define	 ID_AA64ISAR1_BF16_IMPL		(UL(0x1) << ID_AA64ISAR1_BF16_SHIFT)
659 #define	ID_AA64ISAR1_DGH_SHIFT		48
660 #define	ID_AA64ISAR1_DGH_MASK		(UL(0xf) << ID_AA64ISAR1_DGH_SHIFT)
661 #define	ID_AA64ISAR1_DGH_VAL(x)		((x) & ID_AA64ISAR1_DGH_MASK)
662 #define	 ID_AA64ISAR1_DGH_NONE		(UL(0x0) << ID_AA64ISAR1_DGH_SHIFT)
663 #define	 ID_AA64ISAR1_DGH_IMPL		(UL(0x1) << ID_AA64ISAR1_DGH_SHIFT)
664 #define	ID_AA64ISAR1_I8MM_SHIFT		52
665 #define	ID_AA64ISAR1_I8MM_MASK		(UL(0xf) << ID_AA64ISAR1_I8MM_SHIFT)
666 #define	ID_AA64ISAR1_I8MM_VAL(x)	((x) & ID_AA64ISAR1_I8MM_MASK)
667 #define	 ID_AA64ISAR1_I8MM_NONE		(UL(0x0) << ID_AA64ISAR1_I8MM_SHIFT)
668 #define	 ID_AA64ISAR1_I8MM_IMPL		(UL(0x1) << ID_AA64ISAR1_I8MM_SHIFT)
669 
670 /* ID_AA64MMFR0_EL1 */
671 #define	ID_AA64MMFR0_EL1		MRS_REG(ID_AA64MMFR0_EL1)
672 #define	ID_AA64MMFR0_EL1_op0		0x3
673 #define	ID_AA64MMFR0_EL1_op1		0x0
674 #define	ID_AA64MMFR0_EL1_CRn		0x0
675 #define	ID_AA64MMFR0_EL1_CRm		0x7
676 #define	ID_AA64MMFR0_EL1_op2		0x0
677 #define	ID_AA64MMFR0_PARange_SHIFT	0
678 #define	ID_AA64MMFR0_PARange_MASK	(UL(0xf) << ID_AA64MMFR0_PARange_SHIFT)
679 #define	ID_AA64MMFR0_PARange_VAL(x)	((x) & ID_AA64MMFR0_PARange_MASK)
680 #define	 ID_AA64MMFR0_PARange_4G	(UL(0x0) << ID_AA64MMFR0_PARange_SHIFT)
681 #define	 ID_AA64MMFR0_PARange_64G	(UL(0x1) << ID_AA64MMFR0_PARange_SHIFT)
682 #define	 ID_AA64MMFR0_PARange_1T	(UL(0x2) << ID_AA64MMFR0_PARange_SHIFT)
683 #define	 ID_AA64MMFR0_PARange_4T	(UL(0x3) << ID_AA64MMFR0_PARange_SHIFT)
684 #define	 ID_AA64MMFR0_PARange_16T	(UL(0x4) << ID_AA64MMFR0_PARange_SHIFT)
685 #define	 ID_AA64MMFR0_PARange_256T	(UL(0x5) << ID_AA64MMFR0_PARange_SHIFT)
686 #define	 ID_AA64MMFR0_PARange_4P	(UL(0x6) << ID_AA64MMFR0_PARange_SHIFT)
687 #define	ID_AA64MMFR0_ASIDBits_SHIFT	4
688 #define	ID_AA64MMFR0_ASIDBits_MASK	(UL(0xf) << ID_AA64MMFR0_ASIDBits_SHIFT)
689 #define	ID_AA64MMFR0_ASIDBits_VAL(x)	((x) & ID_AA64MMFR0_ASIDBits_MASK)
690 #define	 ID_AA64MMFR0_ASIDBits_8	(UL(0x0) << ID_AA64MMFR0_ASIDBits_SHIFT)
691 #define	 ID_AA64MMFR0_ASIDBits_16	(UL(0x2) << ID_AA64MMFR0_ASIDBits_SHIFT)
692 #define	ID_AA64MMFR0_BigEnd_SHIFT	8
693 #define	ID_AA64MMFR0_BigEnd_MASK	(UL(0xf) << ID_AA64MMFR0_BigEnd_SHIFT)
694 #define	ID_AA64MMFR0_BigEnd_VAL(x)	((x) & ID_AA64MMFR0_BigEnd_MASK)
695 #define	 ID_AA64MMFR0_BigEnd_FIXED	(UL(0x0) << ID_AA64MMFR0_BigEnd_SHIFT)
696 #define	 ID_AA64MMFR0_BigEnd_MIXED	(UL(0x1) << ID_AA64MMFR0_BigEnd_SHIFT)
697 #define	ID_AA64MMFR0_SNSMem_SHIFT	12
698 #define	ID_AA64MMFR0_SNSMem_MASK	(UL(0xf) << ID_AA64MMFR0_SNSMem_SHIFT)
699 #define	ID_AA64MMFR0_SNSMem_VAL(x)	((x) & ID_AA64MMFR0_SNSMem_MASK)
700 #define	 ID_AA64MMFR0_SNSMem_NONE	(UL(0x0) << ID_AA64MMFR0_SNSMem_SHIFT)
701 #define	 ID_AA64MMFR0_SNSMem_DISTINCT	(UL(0x1) << ID_AA64MMFR0_SNSMem_SHIFT)
702 #define	ID_AA64MMFR0_BigEndEL0_SHIFT	16
703 #define	ID_AA64MMFR0_BigEndEL0_MASK	(UL(0xf) << ID_AA64MMFR0_BigEndEL0_SHIFT)
704 #define	ID_AA64MMFR0_BigEndEL0_VAL(x)	((x) & ID_AA64MMFR0_BigEndEL0_MASK)
705 #define	 ID_AA64MMFR0_BigEndEL0_FIXED	(UL(0x0) << ID_AA64MMFR0_BigEndEL0_SHIFT)
706 #define	 ID_AA64MMFR0_BigEndEL0_MIXED	(UL(0x1) << ID_AA64MMFR0_BigEndEL0_SHIFT)
707 #define	ID_AA64MMFR0_TGran16_SHIFT	20
708 #define	ID_AA64MMFR0_TGran16_MASK	(UL(0xf) << ID_AA64MMFR0_TGran16_SHIFT)
709 #define	ID_AA64MMFR0_TGran16_VAL(x)	((x) & ID_AA64MMFR0_TGran16_MASK)
710 #define	 ID_AA64MMFR0_TGran16_NONE	(UL(0x0) << ID_AA64MMFR0_TGran16_SHIFT)
711 #define	 ID_AA64MMFR0_TGran16_IMPL	(UL(0x1) << ID_AA64MMFR0_TGran16_SHIFT)
712 #define	ID_AA64MMFR0_TGran64_SHIFT	24
713 #define	ID_AA64MMFR0_TGran64_MASK	(UL(0xf) << ID_AA64MMFR0_TGran64_SHIFT)
714 #define	ID_AA64MMFR0_TGran64_VAL(x)	((x) & ID_AA64MMFR0_TGran64_MASK)
715 #define	 ID_AA64MMFR0_TGran64_IMPL	(UL(0x0) << ID_AA64MMFR0_TGran64_SHIFT)
716 #define	 ID_AA64MMFR0_TGran64_NONE	(UL(0xf) << ID_AA64MMFR0_TGran64_SHIFT)
717 #define	ID_AA64MMFR0_TGran4_SHIFT	28
718 #define	ID_AA64MMFR0_TGran4_MASK	(UL(0xf) << ID_AA64MMFR0_TGran4_SHIFT)
719 #define	ID_AA64MMFR0_TGran4_VAL(x)	((x) & ID_AA64MMFR0_TGran4_MASK)
720 #define	 ID_AA64MMFR0_TGran4_IMPL	(UL(0x0) << ID_AA64MMFR0_TGran4_SHIFT)
721 #define	 ID_AA64MMFR0_TGran4_NONE	(UL(0xf) << ID_AA64MMFR0_TGran4_SHIFT)
722 #define	ID_AA64MMFR0_TGran16_2_SHIFT	32
723 #define	ID_AA64MMFR0_TGran16_2_MASK	(UL(0xf) << ID_AA64MMFR0_TGran16_2_SHIFT)
724 #define	ID_AA64MMFR0_TGran16_2_VAL(x)	((x) & ID_AA64MMFR0_TGran16_2_MASK)
725 #define	 ID_AA64MMFR0_TGran16_2_TGran16	(UL(0x0) << ID_AA64MMFR0_TGran16_2_SHIFT)
726 #define	 ID_AA64MMFR0_TGran16_2_NONE	(UL(0x1) << ID_AA64MMFR0_TGran16_2_SHIFT)
727 #define	 ID_AA64MMFR0_TGran16_2_IMPL	(UL(0x2) << ID_AA64MMFR0_TGran16_2_SHIFT)
728 #define	ID_AA64MMFR0_TGran64_2_SHIFT	36
729 #define	ID_AA64MMFR0_TGran64_2_MASK	(UL(0xf) << ID_AA64MMFR0_TGran64_2_SHIFT)
730 #define	ID_AA64MMFR0_TGran64_2_VAL(x)	((x) & ID_AA64MMFR0_TGran64_2_MASK)
731 #define	 ID_AA64MMFR0_TGran64_2_TGran64	(UL(0x0) << ID_AA64MMFR0_TGran64_2_SHIFT)
732 #define	 ID_AA64MMFR0_TGran64_2_NONE	(UL(0x1) << ID_AA64MMFR0_TGran64_2_SHIFT)
733 #define	 ID_AA64MMFR0_TGran64_2_IMPL	(UL(0x2) << ID_AA64MMFR0_TGran64_2_SHIFT)
734 #define	ID_AA64MMFR0_TGran4_2_SHIFT	40
735 #define	ID_AA64MMFR0_TGran4_2_MASK	(UL(0xf) << ID_AA64MMFR0_TGran4_2_SHIFT)
736 #define	ID_AA64MMFR0_TGran4_2_VAL(x)	((x) & ID_AA64MMFR0_TGran4_2_MASK)
737 #define	 ID_AA64MMFR0_TGran4_2_TGran4	(UL(0x0) << ID_AA64MMFR0_TGran4_2_SHIFT)
738 #define	 ID_AA64MMFR0_TGran4_2_NONE	(UL(0x1) << ID_AA64MMFR0_TGran4_2_SHIFT)
739 #define	 ID_AA64MMFR0_TGran4_2_IMPL	(UL(0x2) << ID_AA64MMFR0_TGran4_2_SHIFT)
740 #define	ID_AA64MMFR0_ExS_SHIFT		44
741 #define	ID_AA64MMFR0_ExS_MASK		(UL(0xf) << ID_AA64MMFR0_ExS_SHIFT)
742 #define	ID_AA64MMFR0_ExS_VAL(x)		((x) & ID_AA64MMFR0_ExS_MASK)
743 #define	 ID_AA64MMFR0_ExS_ALL		(UL(0x0) << ID_AA64MMFR0_ExS_SHIFT)
744 #define	 ID_AA64MMFR0_ExS_IMPL		(UL(0x1) << ID_AA64MMFR0_ExS_SHIFT)
745 
746 /* ID_AA64MMFR1_EL1 */
747 #define	ID_AA64MMFR1_EL1		MRS_REG(ID_AA64MMFR1_EL1)
748 #define	ID_AA64MMFR1_EL1_op0		0x3
749 #define	ID_AA64MMFR1_EL1_op1		0x0
750 #define	ID_AA64MMFR1_EL1_CRn		0x0
751 #define	ID_AA64MMFR1_EL1_CRm		0x7
752 #define	ID_AA64MMFR1_EL1_op2		0x1
753 #define	ID_AA64MMFR1_HAFDBS_SHIFT	0
754 #define	ID_AA64MMFR1_HAFDBS_MASK	(UL(0xf) << ID_AA64MMFR1_HAFDBS_SHIFT)
755 #define	ID_AA64MMFR1_HAFDBS_VAL(x)	((x) & ID_AA64MMFR1_HAFDBS_MASK)
756 #define	 ID_AA64MMFR1_HAFDBS_NONE	(UL(0x0) << ID_AA64MMFR1_HAFDBS_SHIFT)
757 #define	 ID_AA64MMFR1_HAFDBS_AF		(UL(0x1) << ID_AA64MMFR1_HAFDBS_SHIFT)
758 #define	 ID_AA64MMFR1_HAFDBS_AF_DBS	(UL(0x2) << ID_AA64MMFR1_HAFDBS_SHIFT)
759 #define	ID_AA64MMFR1_VMIDBits_SHIFT	4
760 #define	ID_AA64MMFR1_VMIDBits_MASK	(UL(0xf) << ID_AA64MMFR1_VMIDBits_SHIFT)
761 #define	ID_AA64MMFR1_VMIDBits_VAL(x)	((x) & ID_AA64MMFR1_VMIDBits_MASK)
762 #define	 ID_AA64MMFR1_VMIDBits_8	(UL(0x0) << ID_AA64MMFR1_VMIDBits_SHIFT)
763 #define	 ID_AA64MMFR1_VMIDBits_16	(UL(0x2) << ID_AA64MMFR1_VMIDBits_SHIFT)
764 #define	ID_AA64MMFR1_VH_SHIFT		8
765 #define	ID_AA64MMFR1_VH_MASK		(UL(0xf) << ID_AA64MMFR1_VH_SHIFT)
766 #define	ID_AA64MMFR1_VH_VAL(x)		((x) & ID_AA64MMFR1_VH_MASK)
767 #define	 ID_AA64MMFR1_VH_NONE		(UL(0x0) << ID_AA64MMFR1_VH_SHIFT)
768 #define	 ID_AA64MMFR1_VH_IMPL		(UL(0x1) << ID_AA64MMFR1_VH_SHIFT)
769 #define	ID_AA64MMFR1_HPDS_SHIFT		12
770 #define	ID_AA64MMFR1_HPDS_MASK		(UL(0xf) << ID_AA64MMFR1_HPDS_SHIFT)
771 #define	ID_AA64MMFR1_HPDS_VAL(x)	((x) & ID_AA64MMFR1_HPDS_MASK)
772 #define	 ID_AA64MMFR1_HPDS_NONE		(UL(0x0) << ID_AA64MMFR1_HPDS_SHIFT)
773 #define	 ID_AA64MMFR1_HPDS_HPD		(UL(0x1) << ID_AA64MMFR1_HPDS_SHIFT)
774 #define	 ID_AA64MMFR1_HPDS_TTPBHA	(UL(0x2) << ID_AA64MMFR1_HPDS_SHIFT)
775 #define	ID_AA64MMFR1_LO_SHIFT		16
776 #define	ID_AA64MMFR1_LO_MASK		(UL(0xf) << ID_AA64MMFR1_LO_SHIFT)
777 #define	ID_AA64MMFR1_LO_VAL(x)		((x) & ID_AA64MMFR1_LO_MASK)
778 #define	 ID_AA64MMFR1_LO_NONE		(UL(0x0) << ID_AA64MMFR1_LO_SHIFT)
779 #define	 ID_AA64MMFR1_LO_IMPL		(UL(0x1) << ID_AA64MMFR1_LO_SHIFT)
780 #define	ID_AA64MMFR1_PAN_SHIFT		20
781 #define	ID_AA64MMFR1_PAN_MASK		(UL(0xf) << ID_AA64MMFR1_PAN_SHIFT)
782 #define	ID_AA64MMFR1_PAN_VAL(x)		((x) & ID_AA64MMFR1_PAN_MASK)
783 #define	 ID_AA64MMFR1_PAN_NONE		(UL(0x0) << ID_AA64MMFR1_PAN_SHIFT)
784 #define	 ID_AA64MMFR1_PAN_IMPL		(UL(0x1) << ID_AA64MMFR1_PAN_SHIFT)
785 #define	 ID_AA64MMFR1_PAN_ATS1E1	(UL(0x2) << ID_AA64MMFR1_PAN_SHIFT)
786 #define	ID_AA64MMFR1_SpecSEI_SHIFT	24
787 #define	ID_AA64MMFR1_SpecSEI_MASK	(UL(0xf) << ID_AA64MMFR1_SpecSEI_SHIFT)
788 #define	ID_AA64MMFR1_SpecSEI_VAL(x)	((x) & ID_AA64MMFR1_SpecSEI_MASK)
789 #define	 ID_AA64MMFR1_SpecSEI_NONE	(UL(0x0) << ID_AA64MMFR1_SpecSEI_SHIFT)
790 #define	 ID_AA64MMFR1_SpecSEI_IMPL	(UL(0x1) << ID_AA64MMFR1_SpecSEI_SHIFT)
791 #define	ID_AA64MMFR1_XNX_SHIFT		28
792 #define	ID_AA64MMFR1_XNX_MASK		(UL(0xf) << ID_AA64MMFR1_XNX_SHIFT)
793 #define	ID_AA64MMFR1_XNX_VAL(x)		((x) & ID_AA64MMFR1_XNX_MASK)
794 #define	 ID_AA64MMFR1_XNX_NONE		(UL(0x0) << ID_AA64MMFR1_XNX_SHIFT)
795 #define	 ID_AA64MMFR1_XNX_IMPL		(UL(0x1) << ID_AA64MMFR1_XNX_SHIFT)
796 
797 /* ID_AA64MMFR2_EL1 */
798 #define	ID_AA64MMFR2_EL1		MRS_REG(ID_AA64MMFR2_EL1)
799 #define	ID_AA64MMFR2_EL1_op0		0x3
800 #define	ID_AA64MMFR2_EL1_op1		0x0
801 #define	ID_AA64MMFR2_EL1_CRn		0x0
802 #define	ID_AA64MMFR2_EL1_CRm		0x7
803 #define	ID_AA64MMFR2_EL1_op2		0x2
804 #define	ID_AA64MMFR2_CnP_SHIFT		0
805 #define	ID_AA64MMFR2_CnP_MASK		(UL(0xf) << ID_AA64MMFR2_CnP_SHIFT)
806 #define	ID_AA64MMFR2_CnP_VAL(x)		((x) & ID_AA64MMFR2_CnP_MASK)
807 #define	 ID_AA64MMFR2_CnP_NONE		(UL(0x0) << ID_AA64MMFR2_CnP_SHIFT)
808 #define	 ID_AA64MMFR2_CnP_IMPL		(UL(0x1) << ID_AA64MMFR2_CnP_SHIFT)
809 #define	ID_AA64MMFR2_UAO_SHIFT		4
810 #define	ID_AA64MMFR2_UAO_MASK		(UL(0xf) << ID_AA64MMFR2_UAO_SHIFT)
811 #define	ID_AA64MMFR2_UAO_VAL(x)		((x) & ID_AA64MMFR2_UAO_MASK)
812 #define	 ID_AA64MMFR2_UAO_NONE		(UL(0x0) << ID_AA64MMFR2_UAO_SHIFT)
813 #define	 ID_AA64MMFR2_UAO_IMPL		(UL(0x1) << ID_AA64MMFR2_UAO_SHIFT)
814 #define	ID_AA64MMFR2_LSM_SHIFT		8
815 #define	ID_AA64MMFR2_LSM_MASK		(UL(0xf) << ID_AA64MMFR2_LSM_SHIFT)
816 #define	ID_AA64MMFR2_LSM_VAL(x)		((x) & ID_AA64MMFR2_LSM_MASK)
817 #define	 ID_AA64MMFR2_LSM_NONE		(UL(0x0) << ID_AA64MMFR2_LSM_SHIFT)
818 #define	 ID_AA64MMFR2_LSM_IMPL		(UL(0x1) << ID_AA64MMFR2_LSM_SHIFT)
819 #define	ID_AA64MMFR2_IESB_SHIFT		12
820 #define	ID_AA64MMFR2_IESB_MASK		(UL(0xf) << ID_AA64MMFR2_IESB_SHIFT)
821 #define	ID_AA64MMFR2_IESB_VAL(x)	((x) & ID_AA64MMFR2_IESB_MASK)
822 #define	 ID_AA64MMFR2_IESB_NONE		(UL(0x0) << ID_AA64MMFR2_IESB_SHIFT)
823 #define	 ID_AA64MMFR2_IESB_IMPL		(UL(0x1) << ID_AA64MMFR2_IESB_SHIFT)
824 #define	ID_AA64MMFR2_VARange_SHIFT	16
825 #define	ID_AA64MMFR2_VARange_MASK	(UL(0xf) << ID_AA64MMFR2_VARange_SHIFT)
826 #define	ID_AA64MMFR2_VARange_VAL(x)	((x) & ID_AA64MMFR2_VARange_MASK)
827 #define	 ID_AA64MMFR2_VARange_48	(UL(0x0) << ID_AA64MMFR2_VARange_SHIFT)
828 #define	 ID_AA64MMFR2_VARange_52	(UL(0x1) << ID_AA64MMFR2_VARange_SHIFT)
829 #define	ID_AA64MMFR2_CCIDX_SHIFT	20
830 #define	ID_AA64MMFR2_CCIDX_MASK		(UL(0xf) << ID_AA64MMFR2_CCIDX_SHIFT)
831 #define	ID_AA64MMFR2_CCIDX_VAL(x)	((x) & ID_AA64MMFR2_CCIDX_MASK)
832 #define	 ID_AA64MMFR2_CCIDX_32		(UL(0x0) << ID_AA64MMFR2_CCIDX_SHIFT)
833 #define	 ID_AA64MMFR2_CCIDX_64		(UL(0x1) << ID_AA64MMFR2_CCIDX_SHIFT)
834 #define	ID_AA64MMFR2_NV_SHIFT		24
835 #define	ID_AA64MMFR2_NV_MASK		(UL(0xf) << ID_AA64MMFR2_NV_SHIFT)
836 #define	ID_AA64MMFR2_NV_VAL(x)		((x) & ID_AA64MMFR2_NV_MASK)
837 #define	 ID_AA64MMFR2_NV_NONE		(UL(0x0) << ID_AA64MMFR2_NV_SHIFT)
838 #define	 ID_AA64MMFR2_NV_8_3		(UL(0x1) << ID_AA64MMFR2_NV_SHIFT)
839 #define	 ID_AA64MMFR2_NV_8_4		(UL(0x2) << ID_AA64MMFR2_NV_SHIFT)
840 #define	ID_AA64MMFR2_ST_SHIFT		28
841 #define	ID_AA64MMFR2_ST_MASK		(UL(0xf) << ID_AA64MMFR2_ST_SHIFT)
842 #define	ID_AA64MMFR2_ST_VAL(x)		((x) & ID_AA64MMFR2_ST_MASK)
843 #define	 ID_AA64MMFR2_ST_NONE		(UL(0x0) << ID_AA64MMFR2_ST_SHIFT)
844 #define	 ID_AA64MMFR2_ST_IMPL		(UL(0x1) << ID_AA64MMFR2_ST_SHIFT)
845 #define	ID_AA64MMFR2_AT_SHIFT		32
846 #define	ID_AA64MMFR2_AT_MASK		(UL(0xf) << ID_AA64MMFR2_AT_SHIFT)
847 #define	ID_AA64MMFR2_AT_VAL(x)		((x) & ID_AA64MMFR2_AT_MASK)
848 #define	 ID_AA64MMFR2_AT_NONE		(UL(0x0) << ID_AA64MMFR2_AT_SHIFT)
849 #define	 ID_AA64MMFR2_AT_IMPL		(UL(0x1) << ID_AA64MMFR2_AT_SHIFT)
850 #define	ID_AA64MMFR2_IDS_SHIFT		36
851 #define	ID_AA64MMFR2_IDS_MASK		(UL(0xf) << ID_AA64MMFR2_IDS_SHIFT)
852 #define	ID_AA64MMFR2_IDS_VAL(x)		((x) & ID_AA64MMFR2_IDS_MASK)
853 #define	 ID_AA64MMFR2_IDS_NONE		(UL(0x0) << ID_AA64MMFR2_IDS_SHIFT)
854 #define	 ID_AA64MMFR2_IDS_IMPL		(UL(0x1) << ID_AA64MMFR2_IDS_SHIFT)
855 #define	ID_AA64MMFR2_FWB_SHIFT		40
856 #define	ID_AA64MMFR2_FWB_MASK		(UL(0xf) << ID_AA64MMFR2_FWB_SHIFT)
857 #define	ID_AA64MMFR2_FWB_VAL(x)		((x) & ID_AA64MMFR2_FWB_MASK)
858 #define	 ID_AA64MMFR2_FWB_NONE		(UL(0x0) << ID_AA64MMFR2_FWB_SHIFT)
859 #define	 ID_AA64MMFR2_FWB_IMPL		(UL(0x1) << ID_AA64MMFR2_FWB_SHIFT)
860 #define	ID_AA64MMFR2_TTL_SHIFT		48
861 #define	ID_AA64MMFR2_TTL_MASK		(UL(0xf) << ID_AA64MMFR2_TTL_SHIFT)
862 #define	ID_AA64MMFR2_TTL_VAL(x)		((x) & ID_AA64MMFR2_TTL_MASK)
863 #define	 ID_AA64MMFR2_TTL_NONE		(UL(0x0) << ID_AA64MMFR2_TTL_SHIFT)
864 #define	 ID_AA64MMFR2_TTL_IMPL		(UL(0x1) << ID_AA64MMFR2_TTL_SHIFT)
865 #define	ID_AA64MMFR2_BBM_SHIFT		52
866 #define	ID_AA64MMFR2_BBM_MASK		(UL(0xf) << ID_AA64MMFR2_BBM_SHIFT)
867 #define	ID_AA64MMFR2_BBM_VAL(x)		((x) & ID_AA64MMFR2_BBM_MASK)
868 #define	 ID_AA64MMFR2_BBM_LEVEL0	(UL(0x0) << ID_AA64MMFR2_BBM_SHIFT)
869 #define	 ID_AA64MMFR2_BBM_LEVEL1	(UL(0x1) << ID_AA64MMFR2_BBM_SHIFT)
870 #define	 ID_AA64MMFR2_BBM_LEVEL2	(UL(0x2) << ID_AA64MMFR2_BBM_SHIFT)
871 #define	ID_AA64MMFR2_EVT_SHIFT		56
872 #define	ID_AA64MMFR2_EVT_MASK		(UL(0xf) << ID_AA64MMFR2_EVT_SHIFT)
873 #define	ID_AA64MMFR2_EVT_VAL(x)		((x) & ID_AA64MMFR2_EVT_MASK)
874 #define	 ID_AA64MMFR2_EVT_NONE		(UL(0x0) << ID_AA64MMFR2_EVT_SHIFT)
875 #define	 ID_AA64MMFR2_EVT_8_2		(UL(0x1) << ID_AA64MMFR2_EVT_SHIFT)
876 #define	 ID_AA64MMFR2_EVT_8_5		(UL(0x2) << ID_AA64MMFR2_EVT_SHIFT)
877 #define	ID_AA64MMFR2_E0PD_SHIFT		60
878 #define	ID_AA64MMFR2_E0PD_MASK		(UL(0xf) << ID_AA64MMFR2_E0PD_SHIFT)
879 #define	ID_AA64MMFR2_E0PD_VAL(x)	((x) & ID_AA64MMFR2_E0PD_MASK)
880 #define	 ID_AA64MMFR2_E0PD_NONE		(UL(0x0) << ID_AA64MMFR2_E0PD_SHIFT)
881 #define	 ID_AA64MMFR2_E0PD_IMPL		(UL(0x1) << ID_AA64MMFR2_E0PD_SHIFT)
882 
883 /* ID_AA64PFR0_EL1 */
884 #define	ID_AA64PFR0_EL1			MRS_REG(ID_AA64PFR0_EL1)
885 #define	ID_AA64PFR0_EL1_op0		0x3
886 #define	ID_AA64PFR0_EL1_op1		0x0
887 #define	ID_AA64PFR0_EL1_CRn		0x0
888 #define	ID_AA64PFR0_EL1_CRm		0x4
889 #define	ID_AA64PFR0_EL1_op2		0x0
890 #define	ID_AA64PFR0_EL0_SHIFT		0
891 #define	ID_AA64PFR0_EL0_MASK		(UL(0xf) << ID_AA64PFR0_EL0_SHIFT)
892 #define	ID_AA64PFR0_EL0_VAL(x)		((x) & ID_AA64PFR0_EL0_MASK)
893 #define	 ID_AA64PFR0_EL0_64		(UL(0x1) << ID_AA64PFR0_EL0_SHIFT)
894 #define	 ID_AA64PFR0_EL0_64_32		(UL(0x2) << ID_AA64PFR0_EL0_SHIFT)
895 #define	ID_AA64PFR0_EL1_SHIFT		4
896 #define	ID_AA64PFR0_EL1_MASK		(UL(0xf) << ID_AA64PFR0_EL1_SHIFT)
897 #define	ID_AA64PFR0_EL1_VAL(x)		((x) & ID_AA64PFR0_EL1_MASK)
898 #define	 ID_AA64PFR0_EL1_64		(UL(0x1) << ID_AA64PFR0_EL1_SHIFT)
899 #define	 ID_AA64PFR0_EL1_64_32		(UL(0x2) << ID_AA64PFR0_EL1_SHIFT)
900 #define	ID_AA64PFR0_EL2_SHIFT		8
901 #define	ID_AA64PFR0_EL2_MASK		(UL(0xf) << ID_AA64PFR0_EL2_SHIFT)
902 #define	ID_AA64PFR0_EL2_VAL(x)		((x) & ID_AA64PFR0_EL2_MASK)
903 #define	 ID_AA64PFR0_EL2_NONE		(UL(0x0) << ID_AA64PFR0_EL2_SHIFT)
904 #define	 ID_AA64PFR0_EL2_64		(UL(0x1) << ID_AA64PFR0_EL2_SHIFT)
905 #define	 ID_AA64PFR0_EL2_64_32		(UL(0x2) << ID_AA64PFR0_EL2_SHIFT)
906 #define	ID_AA64PFR0_EL3_SHIFT		12
907 #define	ID_AA64PFR0_EL3_MASK		(UL(0xf) << ID_AA64PFR0_EL3_SHIFT)
908 #define	ID_AA64PFR0_EL3_VAL(x)		((x) & ID_AA64PFR0_EL3_MASK)
909 #define	 ID_AA64PFR0_EL3_NONE		(UL(0x0) << ID_AA64PFR0_EL3_SHIFT)
910 #define	 ID_AA64PFR0_EL3_64		(UL(0x1) << ID_AA64PFR0_EL3_SHIFT)
911 #define	 ID_AA64PFR0_EL3_64_32		(UL(0x2) << ID_AA64PFR0_EL3_SHIFT)
912 #define	ID_AA64PFR0_FP_SHIFT		16
913 #define	ID_AA64PFR0_FP_MASK		(UL(0xf) << ID_AA64PFR0_FP_SHIFT)
914 #define	ID_AA64PFR0_FP_VAL(x)		((x) & ID_AA64PFR0_FP_MASK)
915 #define	 ID_AA64PFR0_FP_IMPL		(UL(0x0) << ID_AA64PFR0_FP_SHIFT)
916 #define	 ID_AA64PFR0_FP_HP		(UL(0x1) << ID_AA64PFR0_FP_SHIFT)
917 #define	 ID_AA64PFR0_FP_NONE		(UL(0xf) << ID_AA64PFR0_FP_SHIFT)
918 #define	ID_AA64PFR0_AdvSIMD_SHIFT	20
919 #define	ID_AA64PFR0_AdvSIMD_MASK	(UL(0xf) << ID_AA64PFR0_AdvSIMD_SHIFT)
920 #define	ID_AA64PFR0_AdvSIMD_VAL(x)	((x) & ID_AA64PFR0_AdvSIMD_MASK)
921 #define	 ID_AA64PFR0_AdvSIMD_IMPL	(UL(0x0) << ID_AA64PFR0_AdvSIMD_SHIFT)
922 #define	 ID_AA64PFR0_AdvSIMD_HP		(UL(0x1) << ID_AA64PFR0_AdvSIMD_SHIFT)
923 #define	 ID_AA64PFR0_AdvSIMD_NONE	(UL(0xf) << ID_AA64PFR0_AdvSIMD_SHIFT)
924 #define	ID_AA64PFR0_GIC_BITS		0x4 /* Number of bits in GIC field */
925 #define	ID_AA64PFR0_GIC_SHIFT		24
926 #define	ID_AA64PFR0_GIC_MASK		(UL(0xf) << ID_AA64PFR0_GIC_SHIFT)
927 #define	ID_AA64PFR0_GIC_VAL(x)		((x) & ID_AA64PFR0_GIC_MASK)
928 #define	 ID_AA64PFR0_GIC_CPUIF_NONE	(UL(0x0) << ID_AA64PFR0_GIC_SHIFT)
929 #define	 ID_AA64PFR0_GIC_CPUIF_EN	(UL(0x1) << ID_AA64PFR0_GIC_SHIFT)
930 #define	 ID_AA64PFR0_GIC_CPUIF_4_1	(UL(0x3) << ID_AA64PFR0_GIC_SHIFT)
931 #define	ID_AA64PFR0_RAS_SHIFT		28
932 #define	ID_AA64PFR0_RAS_MASK		(UL(0xf) << ID_AA64PFR0_RAS_SHIFT)
933 #define	ID_AA64PFR0_RAS_VAL(x)		((x) & ID_AA64PFR0_RAS_MASK)
934 #define	 ID_AA64PFR0_RAS_NONE		(UL(0x0) << ID_AA64PFR0_RAS_SHIFT)
935 #define	 ID_AA64PFR0_RAS_IMPL		(UL(0x1) << ID_AA64PFR0_RAS_SHIFT)
936 #define	 ID_AA64PFR0_RAS_8_4		(UL(0x2) << ID_AA64PFR0_RAS_SHIFT)
937 #define	ID_AA64PFR0_SVE_SHIFT		32
938 #define	ID_AA64PFR0_SVE_MASK		(UL(0xf) << ID_AA64PFR0_SVE_SHIFT)
939 #define	ID_AA64PFR0_SVE_VAL(x)		((x) & ID_AA64PFR0_SVE_MASK)
940 #define	 ID_AA64PFR0_SVE_NONE		(UL(0x0) << ID_AA64PFR0_SVE_SHIFT)
941 #define	 ID_AA64PFR0_SVE_IMPL		(UL(0x1) << ID_AA64PFR0_SVE_SHIFT)
942 #define	ID_AA64PFR0_SEL2_SHIFT		36
943 #define	ID_AA64PFR0_SEL2_MASK		(UL(0xf) << ID_AA64PFR0_SEL2_SHIFT)
944 #define	ID_AA64PFR0_SEL2_VAL(x)		((x) & ID_AA64PFR0_SEL2_MASK)
945 #define	 ID_AA64PFR0_SEL2_NONE		(UL(0x0) << ID_AA64PFR0_SEL2_SHIFT)
946 #define	 ID_AA64PFR0_SEL2_IMPL		(UL(0x1) << ID_AA64PFR0_SEL2_SHIFT)
947 #define	ID_AA64PFR0_MPAM_SHIFT		40
948 #define	ID_AA64PFR0_MPAM_MASK		(UL(0xf) << ID_AA64PFR0_MPAM_SHIFT)
949 #define	ID_AA64PFR0_MPAM_VAL(x)		((x) & ID_AA64PFR0_MPAM_MASK)
950 #define	 ID_AA64PFR0_MPAM_NONE		(UL(0x0) << ID_AA64PFR0_MPAM_SHIFT)
951 #define	 ID_AA64PFR0_MPAM_IMPL		(UL(0x1) << ID_AA64PFR0_MPAM_SHIFT)
952 #define	ID_AA64PFR0_AMU_SHIFT		44
953 #define	ID_AA64PFR0_AMU_MASK		(UL(0xf) << ID_AA64PFR0_AMU_SHIFT)
954 #define	ID_AA64PFR0_AMU_VAL(x)		((x) & ID_AA64PFR0_AMU_MASK)
955 #define	 ID_AA64PFR0_AMU_NONE		(UL(0x0) << ID_AA64PFR0_AMU_SHIFT)
956 #define	 ID_AA64PFR0_AMU_V1		(UL(0x1) << ID_AA64PFR0_AMU_SHIFT)
957 #define	ID_AA64PFR0_DIT_SHIFT		48
958 #define	ID_AA64PFR0_DIT_MASK		(UL(0xf) << ID_AA64PFR0_DIT_SHIFT)
959 #define	ID_AA64PFR0_DIT_VAL(x)		((x) & ID_AA64PFR0_DIT_MASK)
960 #define	 ID_AA64PFR0_DIT_NONE		(UL(0x0) << ID_AA64PFR0_DIT_SHIFT)
961 #define	 ID_AA64PFR0_DIT_PSTATE		(UL(0x1) << ID_AA64PFR0_DIT_SHIFT)
962 #define	ID_AA64PFR0_CSV2_SHIFT		56
963 #define	ID_AA64PFR0_CSV2_MASK		(UL(0xf) << ID_AA64PFR0_CSV2_SHIFT)
964 #define	ID_AA64PFR0_CSV2_VAL(x)		((x) & ID_AA64PFR0_CSV2_MASK)
965 #define	 ID_AA64PFR0_CSV2_NONE		(UL(0x0) << ID_AA64PFR0_CSV2_SHIFT)
966 #define	 ID_AA64PFR0_CSV2_ISOLATED	(UL(0x1) << ID_AA64PFR0_CSV2_SHIFT)
967 #define	 ID_AA64PFR0_CSV2_SCXTNUM	(UL(0x2) << ID_AA64PFR0_CSV2_SHIFT)
968 #define	ID_AA64PFR0_CSV3_SHIFT		60
969 #define	ID_AA64PFR0_CSV3_MASK		(UL(0xf) << ID_AA64PFR0_CSV3_SHIFT)
970 #define	ID_AA64PFR0_CSV3_VAL(x)		((x) & ID_AA64PFR0_CSV3_MASK)
971 #define	 ID_AA64PFR0_CSV3_NONE		(UL(0x0) << ID_AA64PFR0_CSV3_SHIFT)
972 #define	 ID_AA64PFR0_CSV3_ISOLATED	(UL(0x1) << ID_AA64PFR0_CSV3_SHIFT)
973 
974 /* ID_AA64PFR1_EL1 */
975 #define	ID_AA64PFR1_EL1			MRS_REG(ID_AA64PFR1_EL1)
976 #define	ID_AA64PFR1_EL1_op0		0x3
977 #define	ID_AA64PFR1_EL1_op1		0x0
978 #define	ID_AA64PFR1_EL1_CRn		0x0
979 #define	ID_AA64PFR1_EL1_CRm		0x4
980 #define	ID_AA64PFR1_EL1_op2		0x1
981 #define	ID_AA64PFR1_BT_SHIFT		0
982 #define	ID_AA64PFR1_BT_MASK		(UL(0xf) << ID_AA64PFR1_BT_SHIFT)
983 #define	ID_AA64PFR1_BT_VAL(x)		((x) & ID_AA64PFR1_BT_MASK)
984 #define	 ID_AA64PFR1_BT_NONE		(UL(0x0) << ID_AA64PFR1_BT_SHIFT)
985 #define	 ID_AA64PFR1_BT_IMPL		(UL(0x1) << ID_AA64PFR1_BT_SHIFT)
986 #define	ID_AA64PFR1_SSBS_SHIFT		4
987 #define	ID_AA64PFR1_SSBS_MASK		(UL(0xf) << ID_AA64PFR1_SSBS_SHIFT)
988 #define	ID_AA64PFR1_SSBS_VAL(x)		((x) & ID_AA64PFR1_SSBS_MASK)
989 #define	 ID_AA64PFR1_SSBS_NONE		(UL(0x0) << ID_AA64PFR1_SSBS_SHIFT)
990 #define	 ID_AA64PFR1_SSBS_PSTATE	(UL(0x1) << ID_AA64PFR1_SSBS_SHIFT)
991 #define	 ID_AA64PFR1_SSBS_PSTATE_MSR	(UL(0x2) << ID_AA64PFR1_SSBS_SHIFT)
992 #define	ID_AA64PFR1_MTE_SHIFT		8
993 #define	ID_AA64PFR1_MTE_MASK		(UL(0xf) << ID_AA64PFR1_MTE_SHIFT)
994 #define	ID_AA64PFR1_MTE_VAL(x)		((x) & ID_AA64PFR1_MTE_MASK)
995 #define	 ID_AA64PFR1_MTE_NONE		(UL(0x0) << ID_AA64PFR1_MTE_SHIFT)
996 #define	 ID_AA64PFR1_MTE_IMPL_EL0	(UL(0x1) << ID_AA64PFR1_MTE_SHIFT)
997 #define	 ID_AA64PFR1_MTE_IMPL		(UL(0x2) << ID_AA64PFR1_MTE_SHIFT)
998 #define	ID_AA64PFR1_RAS_frac_SHIFT	12
999 #define	ID_AA64PFR1_RAS_frac_MASK	(UL(0xf) << ID_AA64PFR1_RAS_frac_SHIFT)
1000 #define	ID_AA64PFR1_RAS_frac_VAL(x)	((x) & ID_AA64PFR1_RAS_frac_MASK)
1001 #define	 ID_AA64PFR1_RAS_frac_V1	(UL(0x0) << ID_AA64PFR1_RAS_frac_SHIFT)
1002 #define	 ID_AA64PFR1_RAS_frac_V2	(UL(0x1) << ID_AA64PFR1_RAS_frac_SHIFT)
1003 
1004 /* ID_ISAR5_EL1 */
1005 #define	ID_ISAR5_EL1			MRS_REG(ID_ISAR5_EL1)
1006 #define	ID_ISAR5_EL1_op0		0x3
1007 #define	ID_ISAR5_EL1_op1		0x0
1008 #define	ID_ISAR5_EL1_CRn		0x0
1009 #define	ID_ISAR5_EL1_CRm		0x2
1010 #define	ID_ISAR5_EL1_op2		0x5
1011 #define	ID_ISAR5_SEVL_SHIFT		0
1012 #define	ID_ISAR5_SEVL_MASK		(UL(0xf) << ID_ISAR5_SEVL_SHIFT)
1013 #define	ID_ISAR5_SEVL_VAL(x)		((x) & ID_ISAR5_SEVL_MASK)
1014 #define	 ID_ISAR5_SEVL_NOP		(UL(0x0) << ID_ISAR5_SEVL_SHIFT)
1015 #define	 ID_ISAR5_SEVL_IMPL		(UL(0x1) << ID_ISAR5_SEVL_SHIFT)
1016 #define	ID_ISAR5_AES_SHIFT		4
1017 #define	ID_ISAR5_AES_MASK		(UL(0xf) << ID_ISAR5_AES_SHIFT)
1018 #define	ID_ISAR5_AES_VAL(x)		((x) & ID_ISAR5_AES_MASK)
1019 #define	 ID_ISAR5_AES_NONE		(UL(0x0) << ID_ISAR5_AES_SHIFT)
1020 #define	 ID_ISAR5_AES_BASE		(UL(0x1) << ID_ISAR5_AES_SHIFT)
1021 #define	 ID_ISAR5_AES_VMULL		(UL(0x2) << ID_ISAR5_AES_SHIFT)
1022 #define	ID_ISAR5_SHA1_SHIFT		8
1023 #define	ID_ISAR5_SHA1_MASK		(UL(0xf) << ID_ISAR5_SHA1_SHIFT)
1024 #define	ID_ISAR5_SHA1_VAL(x)		((x) & ID_ISAR5_SHA1_MASK)
1025 #define	 ID_ISAR5_SHA1_NONE		(UL(0x0) << ID_ISAR5_SHA1_SHIFT)
1026 #define	 ID_ISAR5_SHA1_IMPL		(UL(0x1) << ID_ISAR5_SHA1_SHIFT)
1027 #define	ID_ISAR5_SHA2_SHIFT		12
1028 #define	ID_ISAR5_SHA2_MASK		(UL(0xf) << ID_ISAR5_SHA2_SHIFT)
1029 #define	ID_ISAR5_SHA2_VAL(x)		((x) & ID_ISAR5_SHA2_MASK)
1030 #define	 ID_ISAR5_SHA2_NONE		(UL(0x0) << ID_ISAR5_SHA2_SHIFT)
1031 #define	 ID_ISAR5_SHA2_IMPL		(UL(0x1) << ID_ISAR5_SHA2_SHIFT)
1032 #define	ID_ISAR5_CRC32_SHIFT		16
1033 #define	ID_ISAR5_CRC32_MASK		(UL(0xf) << ID_ISAR5_CRC32_SHIFT)
1034 #define	ID_ISAR5_CRC32_VAL(x)		((x) & ID_ISAR5_CRC32_MASK)
1035 #define	 ID_ISAR5_CRC32_NONE		(UL(0x0) << ID_ISAR5_CRC32_SHIFT)
1036 #define	 ID_ISAR5_CRC32_IMPL		(UL(0x1) << ID_ISAR5_CRC32_SHIFT)
1037 #define	ID_ISAR5_RDM_SHIFT		24
1038 #define	ID_ISAR5_RDM_MASK		(UL(0xf) << ID_ISAR5_RDM_SHIFT)
1039 #define	ID_ISAR5_RDM_VAL(x)		((x) & ID_ISAR5_RDM_MASK)
1040 #define	 ID_ISAR5_RDM_NONE		(UL(0x0) << ID_ISAR5_RDM_SHIFT)
1041 #define	 ID_ISAR5_RDM_IMPL		(UL(0x1) << ID_ISAR5_RDM_SHIFT)
1042 #define	ID_ISAR5_VCMA_SHIFT		28
1043 #define	ID_ISAR5_VCMA_MASK		(UL(0xf) << ID_ISAR5_VCMA_SHIFT)
1044 #define	ID_ISAR5_VCMA_VAL(x)		((x) & ID_ISAR5_VCMA_MASK)
1045 #define	 ID_ISAR5_VCMA_NONE		(UL(0x0) << ID_ISAR5_VCMA_SHIFT)
1046 #define	 ID_ISAR5_VCMA_IMPL		(UL(0x1) << ID_ISAR5_VCMA_SHIFT)
1047 
1048 /* MAIR_EL1 - Memory Attribute Indirection Register */
1049 #define	MAIR_ATTR_MASK(idx)	(0xff << ((n)* 8))
1050 #define	MAIR_ATTR(attr, idx) ((attr) << ((idx) * 8))
1051 #define	 MAIR_DEVICE_nGnRnE	0x00
1052 #define	 MAIR_DEVICE_nGnRE	0x04
1053 #define	 MAIR_NORMAL_NC		0x44
1054 #define	 MAIR_NORMAL_WT		0xbb
1055 #define	 MAIR_NORMAL_WB		0xff
1056 
1057 /* MDCCINT_EL1 */
1058 #define	MDCCINT_EL1			MRS_REG(MDCCINT_EL1)
1059 #define	MDCCINT_EL1_op0			2
1060 #define	MDCCINT_EL1_op1			0
1061 #define	MDCCINT_EL1_CRn			0
1062 #define	MDCCINT_EL1_CRm			2
1063 #define	MDCCINT_EL1_op2			0
1064 
1065 /* MDCCSR_EL0 */
1066 #define	MDCCSR_EL0			MRS_REG(MDCCSR_EL0)
1067 #define	MDCCSR_EL0_op0			2
1068 #define	MDCCSR_EL0_op1			3
1069 #define	MDCCSR_EL0_CRn			0
1070 #define	MDCCSR_EL0_CRm			1
1071 #define	MDCCSR_EL0_op2			0
1072 
1073 /* MDSCR_EL1 - Monitor Debug System Control Register */
1074 #define	MDSCR_EL1			MRS_REG(MDSCR_EL1)
1075 #define	MDSCR_EL1_op0			2
1076 #define	MDSCR_EL1_op1			0
1077 #define	MDSCR_EL1_CRn			0
1078 #define	MDSCR_EL1_CRm			2
1079 #define	MDSCR_EL1_op2			2
1080 #define	MDSCR_SS_SHIFT			0
1081 #define	MDSCR_SS			(UL(0x1) << MDSCR_SS_SHIFT)
1082 #define	MDSCR_KDE_SHIFT			13
1083 #define	MDSCR_KDE			(UL(0x1) << MDSCR_KDE_SHIFT)
1084 #define	MDSCR_MDE_SHIFT			15
1085 #define	MDSCR_MDE			(UL(0x1) << MDSCR_MDE_SHIFT)
1086 
1087 /* MVFR0_EL1 */
1088 #define	MVFR0_EL1			MRS_REG(MVFR0_EL1)
1089 #define	MVFR0_EL1_op0			0x3
1090 #define	MVFR0_EL1_op1			0x0
1091 #define	MVFR0_EL1_CRn			0x0
1092 #define	MVFR0_EL1_CRm			0x3
1093 #define	MVFR0_EL1_op2			0x0
1094 #define	MVFR0_SIMDReg_SHIFT		0
1095 #define	MVFR0_SIMDReg_MASK		(UL(0xf) << MVFR0_SIMDReg_SHIFT)
1096 #define	MVFR0_SIMDReg_VAL(x)		((x) & MVFR0_SIMDReg_MASK)
1097 #define	 MVFR0_SIMDReg_NONE		(UL(0x0) << MVFR0_SIMDReg_SHIFT)
1098 #define	 MVFR0_SIMDReg_FP		(UL(0x1) << MVFR0_SIMDReg_SHIFT)
1099 #define	 MVFR0_SIMDReg_AdvSIMD		(UL(0x2) << MVFR0_SIMDReg_SHIFT)
1100 #define	MVFR0_FPSP_SHIFT		4
1101 #define	MVFR0_FPSP_MASK			(UL(0xf) << MVFR0_FPSP_SHIFT)
1102 #define	MVFR0_FPSP_VAL(x)		((x) & MVFR0_FPSP_MASK)
1103 #define	 MVFR0_FPSP_NONE		(UL(0x0) << MVFR0_FPSP_SHIFT)
1104 #define	 MVFR0_FPSP_VFP_v2		(UL(0x1) << MVFR0_FPSP_SHIFT)
1105 #define	 MVFR0_FPSP_VFP_v3_v4		(UL(0x2) << MVFR0_FPSP_SHIFT)
1106 #define	MVFR0_FPDP_SHIFT		8
1107 #define	MVFR0_FPDP_MASK			(UL(0xf) << MVFR0_FPDP_SHIFT)
1108 #define	MVFR0_FPDP_VAL(x)		((x) & MVFR0_FPDP_MASK)
1109 #define	 MVFR0_FPDP_NONE		(UL(0x0) << MVFR0_FPDP_SHIFT)
1110 #define	 MVFR0_FPDP_VFP_v2		(UL(0x1) << MVFR0_FPDP_SHIFT)
1111 #define	 MVFR0_FPDP_VFP_v3_v4		(UL(0x2) << MVFR0_FPDP_SHIFT)
1112 #define	MVFR0_FPTrap_SHIFT		12
1113 #define	MVFR0_FPTrap_MASK		(UL(0xf) << MVFR0_FPTrap_SHIFT)
1114 #define	MVFR0_FPTrap_VAL(x)		((x) & MVFR0_FPTrap_MASK)
1115 #define	 MVFR0_FPTrap_NONE		(UL(0x0) << MVFR0_FPTrap_SHIFT)
1116 #define	 MVFR0_FPTrap_IMPL		(UL(0x1) << MVFR0_FPTrap_SHIFT)
1117 #define	MVFR0_FPDivide_SHIFT		16
1118 #define	MVFR0_FPDivide_MASK		(UL(0xf) << MVFR0_FPDivide_SHIFT)
1119 #define	MVFR0_FPDivide_VAL(x)		((x) & MVFR0_FPDivide_MASK)
1120 #define	 MVFR0_FPDivide_NONE		(UL(0x0) << MVFR0_FPDivide_SHIFT)
1121 #define	 MVFR0_FPDivide_IMPL		(UL(0x1) << MVFR0_FPDivide_SHIFT)
1122 #define	MVFR0_FPSqrt_SHIFT		20
1123 #define	MVFR0_FPSqrt_MASK		(UL(0xf) << MVFR0_FPSqrt_SHIFT)
1124 #define	MVFR0_FPSqrt_VAL(x)		((x) & MVFR0_FPSqrt_MASK)
1125 #define	 MVFR0_FPSqrt_NONE		(UL(0x0) << MVFR0_FPSqrt_SHIFT)
1126 #define	 MVFR0_FPSqrt_IMPL		(UL(0x1) << MVFR0_FPSqrt_SHIFT)
1127 #define	MVFR0_FPShVec_SHIFT		24
1128 #define	MVFR0_FPShVec_MASK		(UL(0xf) << MVFR0_FPShVec_SHIFT)
1129 #define	MVFR0_FPShVec_VAL(x)		((x) & MVFR0_FPShVec_MASK)
1130 #define	 MVFR0_FPShVec_NONE		(UL(0x0) << MVFR0_FPShVec_SHIFT)
1131 #define	 MVFR0_FPShVec_IMPL		(UL(0x1) << MVFR0_FPShVec_SHIFT)
1132 #define	MVFR0_FPRound_SHIFT		28
1133 #define	MVFR0_FPRound_MASK		(UL(0xf) << MVFR0_FPRound_SHIFT)
1134 #define	MVFR0_FPRound_VAL(x)		((x) & MVFR0_FPRound_MASK)
1135 #define	 MVFR0_FPRound_NONE		(UL(0x0) << MVFR0_FPRound_SHIFT)
1136 #define	 MVFR0_FPRound_IMPL		(UL(0x1) << MVFR0_FPRound_SHIFT)
1137 
1138 /* MVFR1_EL1 */
1139 #define	MVFR1_EL1			MRS_REG(MVFR1_EL1)
1140 #define	MVFR1_EL1_op0			0x3
1141 #define	MVFR1_EL1_op1			0x0
1142 #define	MVFR1_EL1_CRn			0x0
1143 #define	MVFR1_EL1_CRm			0x3
1144 #define	MVFR1_EL1_op2			0x1
1145 #define	MVFR1_FPFtZ_SHIFT		0
1146 #define	MVFR1_FPFtZ_MASK		(UL(0xf) << MVFR1_FPFtZ_SHIFT)
1147 #define	MVFR1_FPFtZ_VAL(x)		((x) & MVFR1_FPFtZ_MASK)
1148 #define	 MVFR1_FPFtZ_NONE		(UL(0x0) << MVFR1_FPFtZ_SHIFT)
1149 #define	 MVFR1_FPFtZ_IMPL		(UL(0x1) << MVFR1_FPFtZ_SHIFT)
1150 #define	MVFR1_FPDNaN_SHIFT		4
1151 #define	MVFR1_FPDNaN_MASK		(UL(0xf) << MVFR1_FPDNaN_SHIFT)
1152 #define	MVFR1_FPDNaN_VAL(x)		((x) & MVFR1_FPDNaN_MASK)
1153 #define	 MVFR1_FPDNaN_NONE		(UL(0x0) << MVFR1_FPDNaN_SHIFT)
1154 #define	 MVFR1_FPDNaN_IMPL		(UL(0x1) << MVFR1_FPDNaN_SHIFT)
1155 #define	MVFR1_SIMDLS_SHIFT		8
1156 #define	MVFR1_SIMDLS_MASK		(UL(0xf) << MVFR1_SIMDLS_SHIFT)
1157 #define	MVFR1_SIMDLS_VAL(x)		((x) & MVFR1_SIMDLS_MASK)
1158 #define	 MVFR1_SIMDLS_NONE		(UL(0x0) << MVFR1_SIMDLS_SHIFT)
1159 #define	 MVFR1_SIMDLS_IMPL		(UL(0x1) << MVFR1_SIMDLS_SHIFT)
1160 #define	MVFR1_SIMDInt_SHIFT		12
1161 #define	MVFR1_SIMDInt_MASK		(UL(0xf) << MVFR1_SIMDInt_SHIFT)
1162 #define	MVFR1_SIMDInt_VAL(x)		((x) & MVFR1_SIMDInt_MASK)
1163 #define	 MVFR1_SIMDInt_NONE		(UL(0x0) << MVFR1_SIMDInt_SHIFT)
1164 #define	 MVFR1_SIMDInt_IMPL		(UL(0x1) << MVFR1_SIMDInt_SHIFT)
1165 #define	MVFR1_SIMDSP_SHIFT		16
1166 #define	MVFR1_SIMDSP_MASK		(UL(0xf) << MVFR1_SIMDSP_SHIFT)
1167 #define	MVFR1_SIMDSP_VAL(x)		((x) & MVFR1_SIMDSP_MASK)
1168 #define	 MVFR1_SIMDSP_NONE		(UL(0x0) << MVFR1_SIMDSP_SHIFT)
1169 #define	 MVFR1_SIMDSP_IMPL		(UL(0x1) << MVFR1_SIMDSP_SHIFT)
1170 #define	MVFR1_SIMDHP_SHIFT		20
1171 #define	MVFR1_SIMDHP_MASK		(UL(0xf) << MVFR1_SIMDHP_SHIFT)
1172 #define	MVFR1_SIMDHP_VAL(x)		((x) & MVFR1_SIMDHP_MASK)
1173 #define	 MVFR1_SIMDHP_NONE		(UL(0x0) << MVFR1_SIMDHP_SHIFT)
1174 #define	 MVFR1_SIMDHP_CONV_SP		(UL(0x1) << MVFR1_SIMDHP_SHIFT)
1175 #define	 MVFR1_SIMDHP_ARITH		(UL(0x2) << MVFR1_SIMDHP_SHIFT)
1176 #define	MVFR1_FPHP_SHIFT		24
1177 #define	MVFR1_FPHP_MASK			(UL(0xf) << MVFR1_FPHP_SHIFT)
1178 #define	MVFR1_FPHP_VAL(x)		((x) & MVFR1_FPHP_MASK)
1179 #define	 MVFR1_FPHP_NONE		(UL(0x0) << MVFR1_FPHP_SHIFT)
1180 #define	 MVFR1_FPHP_CONV_SP		(UL(0x1) << MVFR1_FPHP_SHIFT)
1181 #define	 MVFR1_FPHP_CONV_DP		(UL(0x2) << MVFR1_FPHP_SHIFT)
1182 #define	 MVFR1_FPHP_ARITH		(UL(0x3) << MVFR1_FPHP_SHIFT)
1183 #define	MVFR1_SIMDFMAC_SHIFT		28
1184 #define	MVFR1_SIMDFMAC_MASK		(UL(0xf) << MVFR1_SIMDFMAC_SHIFT)
1185 #define	MVFR1_SIMDFMAC_VAL(x)		((x) & MVFR1_SIMDFMAC_MASK)
1186 #define	 MVFR1_SIMDFMAC_NONE		(UL(0x0) << MVFR1_SIMDFMAC_SHIFT)
1187 #define	 MVFR1_SIMDFMAC_IMPL		(UL(0x1) << MVFR1_SIMDFMAC_SHIFT)
1188 
1189 /* OSDLR_EL1 */
1190 #define	OSDLR_EL1			MRS_REG(OSDLR_EL1)
1191 #define	OSDLR_EL1_op0			2
1192 #define	OSDLR_EL1_op1			0
1193 #define	OSDLR_EL1_CRn			1
1194 #define	OSDLR_EL1_CRm			3
1195 #define	OSDLR_EL1_op2			4
1196 
1197 /* OSLAR_EL1 */
1198 #define	OSLAR_EL1			MRS_REG(OSLAR_EL1)
1199 #define	OSLAR_EL1_op0			2
1200 #define	OSLAR_EL1_op1			0
1201 #define	OSLAR_EL1_CRn			1
1202 #define	OSLAR_EL1_CRm			0
1203 #define	OSLAR_EL1_op2			4
1204 
1205 /* OSLSR_EL1 */
1206 #define	OSLSR_EL1			MRS_REG(OSLSR_EL1)
1207 #define	OSLSR_EL1_op0			2
1208 #define	OSLSR_EL1_op1			0
1209 #define	OSLSR_EL1_CRn			1
1210 #define	OSLSR_EL1_CRm			1
1211 #define	OSLSR_EL1_op2			4
1212 
1213 /* PAR_EL1 - Physical Address Register */
1214 #define	PAR_F_SHIFT		0
1215 #define	PAR_F			(0x1 << PAR_F_SHIFT)
1216 #define	PAR_SUCCESS(x)		(((x) & PAR_F) == 0)
1217 /* When PAR_F == 0 (success) */
1218 #define	PAR_LOW_MASK		0xfff
1219 #define	PAR_SH_SHIFT		7
1220 #define	PAR_SH_MASK		(0x3 << PAR_SH_SHIFT)
1221 #define	PAR_NS_SHIFT		9
1222 #define	PAR_NS_MASK		(0x3 << PAR_NS_SHIFT)
1223 #define	PAR_PA_SHIFT		12
1224 #define	PAR_PA_MASK		0x0000fffffffff000
1225 #define	PAR_ATTR_SHIFT		56
1226 #define	PAR_ATTR_MASK		(0xff << PAR_ATTR_SHIFT)
1227 /* When PAR_F == 1 (aborted) */
1228 #define	PAR_FST_SHIFT		1
1229 #define	PAR_FST_MASK		(0x3f << PAR_FST_SHIFT)
1230 #define	PAR_PTW_SHIFT		8
1231 #define	PAR_PTW_MASK		(0x1 << PAR_PTW_SHIFT)
1232 #define	PAR_S_SHIFT		9
1233 #define	PAR_S_MASK		(0x1 << PAR_S_SHIFT)
1234 
1235 /* PMBIDR_EL1 */
1236 #define	PMBIDR_EL1			MRS_REG(PMBIDR_EL1)
1237 #define	PMBIDR_EL1_op0			0x3
1238 #define	PMBIDR_EL1_op1			0x0
1239 #define	PMBIDR_EL1_CRn			0x9
1240 #define	PMBIDR_EL1_CRm			0xa
1241 #define	PMBIDR_EL1_op2			0x7
1242 #define	PMBIDR_Align_SHIFT		0
1243 #define	PMBIDR_Align_MASK		(UL(0xf) << PMBIDR_Align_SHIFT)
1244 #define	PMBIDR_P_SHIFT			4
1245 #define	PMBIDR_P			(UL(0x1) << PMBIDR_P_SHIFT)
1246 #define	PMBIDR_F_SHIFT			5
1247 #define	PMBIDR_F			(UL(0x1) << PMBIDR_F_SHIFT)
1248 
1249 /* PMBLIMITR_EL1 */
1250 #define	PMBLIMITR_EL1			MRS_REG(PMBLIMITR_EL1)
1251 #define	PMBLIMITR_EL1_op0		0x3
1252 #define	PMBLIMITR_EL1_op1		0x0
1253 #define	PMBLIMITR_EL1_CRn		0x9
1254 #define	PMBLIMITR_EL1_CRm		0xa
1255 #define	PMBLIMITR_EL1_op2		0x0
1256 #define	PMBLIMITR_E_SHIFT		0
1257 #define	PMBLIMITR_E			(UL(0x1) << PMBLIMITR_E_SHIFT)
1258 #define	PMBLIMITR_FM_SHIFT		1
1259 #define	PMBLIMITR_FM_MASK		(UL(0x3) << PMBLIMITR_FM_SHIFT)
1260 #define	PMBLIMITR_PMFZ_SHIFT		5
1261 #define	PMBLIMITR_PMFZ			(UL(0x1) << PMBLIMITR_PMFZ_SHIFT)
1262 #define	PMBLIMITR_LIMIT_SHIFT		12
1263 #define	PMBLIMITR_LIMIT_MASK		\
1264     (UL(0xfffffffffffff) << PMBLIMITR_LIMIT_SHIFT)
1265 
1266 /* PMBPTR_EL1 */
1267 #define	PMBPTR_EL1			MRS_REG(PMBPTR_EL1)
1268 #define	PMBPTR_EL1_op0			0x3
1269 #define	PMBPTR_EL1_op1			0x0
1270 #define	PMBPTR_EL1_CRn			0x9
1271 #define	PMBPTR_EL1_CRm			0xa
1272 #define	PMBPTR_EL1_op2			0x1
1273 #define	PMBPTR_PTR_SHIFT		0
1274 #define	PMBPTR_PTR_MASK			\
1275     (UL(0xffffffffffffffff) << PMBPTR_PTR_SHIFT)
1276 
1277 /* PMBSR_EL1 */
1278 #define	PMBSR_EL1			MRS_REG(PMBSR_EL1)
1279 #define	PMBSR_EL1_op0			0x3
1280 #define	PMBSR_EL1_op1			0x0
1281 #define	PMBSR_EL1_CRn			0x9
1282 #define	PMBSR_EL1_CRm			0xa
1283 #define	PMBSR_EL1_op2			0x3
1284 #define	PMBSR_MSS_SHIFT			0
1285 #define	PMBSR_MSS_MASK			(UL(0xffff) << PMBSR_MSS_SHIFT)
1286 #define	PMBSR_COLL_SHIFT		16
1287 #define	PMBSR_COLL			(UL(0x1) << PMBSR_COLL_SHIFT)
1288 #define	PMBSR_S_SHIFT			17
1289 #define	PMBSR_S				(UL(0x1) << PMBSR_S_SHIFT)
1290 #define	PMBSR_EA_SHIFT			18
1291 #define	PMBSR_EA			(UL(0x1) << PMBSR_EA_SHIFT)
1292 #define	PMBSR_DL_SHIFT			19
1293 #define	PMBSR_DL			(UL(0x1) << PMBSR_DL_SHIFT)
1294 #define	PMBSR_EC_SHIFT			26
1295 #define	PMBSR_EC_MASK			(UL(0x3f) << PMBSR_EC_SHIFT)
1296 
1297 /* PMCCFILTR_EL0 */
1298 #define	PMCCFILTR_EL0			MRS_REG(PMCCFILTR_EL0)
1299 #define	PMCCFILTR_EL0_op0		3
1300 #define	PMCCFILTR_EL0_op1		3
1301 #define	PMCCFILTR_EL0_CRn		14
1302 #define	PMCCFILTR_EL0_CRm		15
1303 #define	PMCCFILTR_EL0_op2		7
1304 
1305 /* PMCCNTR_EL0 */
1306 #define	PMCCNTR_EL0			MRS_REG(PMCCNTR_EL0)
1307 #define	PMCCNTR_EL0_op0			3
1308 #define	PMCCNTR_EL0_op1			3
1309 #define	PMCCNTR_EL0_CRn			9
1310 #define	PMCCNTR_EL0_CRm			13
1311 #define	PMCCNTR_EL0_op2			0
1312 
1313 /* PMCEID0_EL0 */
1314 #define	PMCEID0_EL0			MRS_REG(PMCEID0_EL0)
1315 #define	PMCEID0_EL0_op0			3
1316 #define	PMCEID0_EL0_op1			3
1317 #define	PMCEID0_EL0_CRn			9
1318 #define	PMCEID0_EL0_CRm			12
1319 #define	PMCEID0_EL0_op2			6
1320 
1321 /* PMCEID1_EL0 */
1322 #define	PMCEID1_EL0			MRS_REG(PMCEID1_EL0)
1323 #define	PMCEID1_EL0_op0			3
1324 #define	PMCEID1_EL0_op1			3
1325 #define	PMCEID1_EL0_CRn			9
1326 #define	PMCEID1_EL0_CRm			12
1327 #define	PMCEID1_EL0_op2			7
1328 
1329 /* PMCNTENCLR_EL0 */
1330 #define	PMCNTENCLR_EL0			MRS_REG(PMCNTENCLR_EL0)
1331 #define	PMCNTENCLR_EL0_op0		3
1332 #define	PMCNTENCLR_EL0_op1		3
1333 #define	PMCNTENCLR_EL0_CRn		9
1334 #define	PMCNTENCLR_EL0_CRm		12
1335 #define	PMCNTENCLR_EL0_op2		2
1336 
1337 /* PMCNTENSET_EL0 */
1338 #define	PMCNTENSET_EL0			MRS_REG(PMCNTENSET_EL0)
1339 #define	PMCNTENSET_EL0_op0		3
1340 #define	PMCNTENSET_EL0_op1		3
1341 #define	PMCNTENSET_EL0_CRn		9
1342 #define	PMCNTENSET_EL0_CRm		12
1343 #define	PMCNTENSET_EL0_op2		1
1344 
1345 /* PMCR_EL0 - Perfomance Monitoring Counters */
1346 #define	PMCR_EL0			MRS_REG(PMCR_EL0)
1347 #define	PMCR_EL0_op0			3
1348 #define	PMCR_EL0_op1			3
1349 #define	PMCR_EL0_CRn			9
1350 #define	PMCR_EL0_CRm			12
1351 #define	PMCR_EL0_op2			0
1352 #define	PMCR_E				(1 << 0) /* Enable all counters */
1353 #define	PMCR_P				(1 << 1) /* Reset all counters */
1354 #define	PMCR_C				(1 << 2) /* Clock counter reset */
1355 #define	PMCR_D				(1 << 3) /* CNTR counts every 64 clk cycles */
1356 #define	PMCR_X				(1 << 4) /* Export to ext. monitoring (ETM) */
1357 #define	PMCR_DP				(1 << 5) /* Disable CCNT if non-invasive debug*/
1358 #define	PMCR_LC				(1 << 6) /* Long cycle count enable */
1359 #define	PMCR_IMP_SHIFT			24	/* Implementer code */
1360 #define	PMCR_IMP_MASK			(0xff << PMCR_IMP_SHIFT)
1361 #define	 PMCR_IMP_ARM			0x41
1362 #define	PMCR_IDCODE_SHIFT		16	/* Identification code */
1363 #define	PMCR_IDCODE_MASK		(0xff << PMCR_IDCODE_SHIFT)
1364 #define	 PMCR_IDCODE_CORTEX_A57		0x01
1365 #define	 PMCR_IDCODE_CORTEX_A72		0x02
1366 #define	 PMCR_IDCODE_CORTEX_A53		0x03
1367 #define	 PMCR_IDCODE_CORTEX_A73		0x04
1368 #define	 PMCR_IDCODE_CORTEX_A35		0x0a
1369 #define	 PMCR_IDCODE_CORTEX_A76		0x0b
1370 #define	 PMCR_IDCODE_NEOVERSE_N1	0x0c
1371 #define	 PMCR_IDCODE_CORTEX_A77		0x10
1372 #define	 PMCR_IDCODE_CORTEX_A55		0x45
1373 #define	 PMCR_IDCODE_NEOVERSE_E1	0x46
1374 #define	 PMCR_IDCODE_CORTEX_A75		0x4a
1375 #define	PMCR_N_SHIFT			11  /* Number of counters implemented */
1376 #define	PMCR_N_MASK			(0x1f << PMCR_N_SHIFT)
1377 
1378 /* PMEVCNTR<n>_EL0 */
1379 #define	PMEVCNTR_EL0_op0		3
1380 #define	PMEVCNTR_EL0_op1		3
1381 #define	PMEVCNTR_EL0_CRn		14
1382 #define	PMEVCNTR_EL0_CRm		8
1383 /*
1384  * PMEVCNTRn_EL0_CRm[1:0] holds the upper 2 bits of 'n'
1385  * PMEVCNTRn_EL0_op2 holds the lower 3 bits of 'n'
1386  */
1387 
1388 /* PMEVTYPER<n>_EL0 - Performance Monitoring Event Type */
1389 #define	PMEVTYPER_EL0_op0		3
1390 #define	PMEVTYPER_EL0_op1		3
1391 #define	PMEVTYPER_EL0_CRn		14
1392 #define	PMEVTYPER_EL0_CRm		12
1393 /*
1394  * PMEVTYPERn_EL0_CRm[1:0] holds the upper 2 bits of 'n'
1395  * PMEVTYPERn_EL0_op2 holds the lower 3 bits of 'n'
1396  */
1397 #define	PMEVTYPER_EVTCOUNT_MASK		0x000003ff /* ARMv8.0 */
1398 #define	PMEVTYPER_EVTCOUNT_8_1_MASK	0x0000ffff /* ARMv8.1+ */
1399 #define	PMEVTYPER_MT			(1 << 25) /* Multithreading */
1400 #define	PMEVTYPER_M			(1 << 26) /* Secure EL3 filtering */
1401 #define	PMEVTYPER_NSH			(1 << 27) /* Non-secure hypervisor filtering */
1402 #define	PMEVTYPER_NSU			(1 << 28) /* Non-secure user filtering */
1403 #define	PMEVTYPER_NSK			(1 << 29) /* Non-secure kernel filtering */
1404 #define	PMEVTYPER_U			(1 << 30) /* User filtering */
1405 #define	PMEVTYPER_P			(1 << 31) /* Privileged filtering */
1406 
1407 /* PMINTENCLR_EL1 */
1408 #define	PMINTENCLR_EL1			MRS_REG(PMINTENCLR_EL1)
1409 #define	PMINTENCLR_EL1_op0		3
1410 #define	PMINTENCLR_EL1_op1		0
1411 #define	PMINTENCLR_EL1_CRn		9
1412 #define	PMINTENCLR_EL1_CRm		14
1413 #define	PMINTENCLR_EL1_op2		2
1414 
1415 /* PMINTENSET_EL1 */
1416 #define	PMINTENSET_EL1			MRS_REG(PMINTENSET_EL1)
1417 #define	PMINTENSET_EL1_op0		3
1418 #define	PMINTENSET_EL1_op1		0
1419 #define	PMINTENSET_EL1_CRn		9
1420 #define	PMINTENSET_EL1_CRm		14
1421 #define	PMINTENSET_EL1_op2		1
1422 
1423 /* PMMIR_EL1 */
1424 #define	PMMIR_EL1			MRS_REG(PMMIR_EL1)
1425 #define	PMMIR_EL1_op0			3
1426 #define	PMMIR_EL1_op1			0
1427 #define	PMMIR_EL1_CRn			9
1428 #define	PMMIR_EL1_CRm			14
1429 #define	PMMIR_EL1_op2			6
1430 
1431 /* PMOVSCLR_EL0 */
1432 #define	PMOVSCLR_EL0			MRS_REG(PMOVSCLR_EL0)
1433 #define	PMOVSCLR_EL0_op0		3
1434 #define	PMOVSCLR_EL0_op1		3
1435 #define	PMOVSCLR_EL0_CRn		9
1436 #define	PMOVSCLR_EL0_CRm		12
1437 #define	PMOVSCLR_EL0_op2		3
1438 
1439 /* PMOVSSET_EL0 */
1440 #define	PMOVSSET_EL0			MRS_REG(PMOVSSET_EL0)
1441 #define	PMOVSSET_EL0_op0		3
1442 #define	PMOVSSET_EL0_op1		3
1443 #define	PMOVSSET_EL0_CRn		9
1444 #define	PMOVSSET_EL0_CRm		14
1445 #define	PMOVSSET_EL0_op2		3
1446 
1447 /* PMSCR_EL1 */
1448 #define	PMSCR_EL1			MRS_REG(PMSCR_EL1)
1449 #define	PMSCR_EL1_op0			0x3
1450 #define	PMSCR_EL1_op1			0x0
1451 #define	PMSCR_EL1_CRn			0x9
1452 #define	PMSCR_EL1_CRm			0x9
1453 #define	PMSCR_EL1_op2			0x0
1454 #define	PMSCR_E0SPE_SHIFT		0
1455 #define	PMSCR_E0SPE			(UL(0x1) << PMSCR_E0SPE_SHIFT)
1456 #define	PMSCR_E1SPE_SHIFT		1
1457 #define	PMSCR_E1SPE			(UL(0x1) << PMSCR_E1SPE_SHIFT)
1458 #define	PMSCR_CX_SHIFT			3
1459 #define	PMSCR_CX			(UL(0x1) << PMSCR_CX_SHIFT)
1460 #define	PMSCR_PA_SHIFT			4
1461 #define	PMSCR_PA			(UL(0x1) << PMSCR_PA_SHIFT)
1462 #define	PMSCR_TS_SHIFT			5
1463 #define	PMSCR_TS			(UL(0x1) << PMSCR_TS_SHIFT)
1464 #define	PMSCR_PCT_SHIFT			6
1465 #define	PMSCR_PCT_MASK			(UL(0x3) << PMSCR_PCT_SHIFT)
1466 
1467 /* PMSELR_EL0 */
1468 #define	PMSELR_EL0			MRS_REG(PMSELR_EL0)
1469 #define	PMSELR_EL0_op0			3
1470 #define	PMSELR_EL0_op1			3
1471 #define	PMSELR_EL0_CRn			9
1472 #define	PMSELR_EL0_CRm			12
1473 #define	PMSELR_EL0_op2			5
1474 #define	PMSELR_SEL_MASK			0x1f
1475 
1476 /* PMSEVFR_EL1 */
1477 #define	PMSEVFR_EL1			MRS_REG(PMSEVFR_EL1)
1478 #define	PMSEVFR_EL1_op0			0x3
1479 #define	PMSEVFR_EL1_op1			0x0
1480 #define	PMSEVFR_EL1_CRn			0x9
1481 #define	PMSEVFR_EL1_CRm			0x9
1482 #define	PMSEVFR_EL1_op2			0x5
1483 
1484 /* PMSFCR_EL1 */
1485 #define	PMSFCR_EL1			MRS_REG(PMSFCR_EL1)
1486 #define	PMSFCR_EL1_op0			0x3
1487 #define	PMSFCR_EL1_op1			0x0
1488 #define	PMSFCR_EL1_CRn			0x9
1489 #define	PMSFCR_EL1_CRm			0x9
1490 #define	PMSFCR_EL1_op2			0x4
1491 #define	PMSFCR_FE_SHIFT			0
1492 #define	PMSFCR_FE			(UL(0x1) << PMSFCR_FE_SHIFT)
1493 #define	PMSFCR_FT_SHIFT			1
1494 #define	PMSFCR_FT			(UL(0x1) << PMSFCR_FT_SHIFT)
1495 #define	PMSFCR_FL_SHIFT			2
1496 #define	PMSFCR_FL			(UL(0x1) << PMSFCR_FL_SHIFT)
1497 #define	PMSFCR_FnE_SHIFT		3
1498 #define	PMSFCR_FnE			(UL(0x1) << PMSFCR_FnE_SHIFT)
1499 #define	PMSFCR_B_SHIFT			16
1500 #define	PMSFCR_B			(UL(0x1) << PMSFCR_B_SHIFT)
1501 #define	PMSFCR_LD_SHIFT			17
1502 #define	PMSFCR_LD			(UL(0x1) << PMSFCR_LD_SHIFT)
1503 #define	PMSFCR_ST_SHIFT			18
1504 #define	PMSFCR_ST			(UL(0x1) << PMSFCR_ST_SHIFT)
1505 
1506 /* PMSICR_EL1 */
1507 #define	PMSICR_EL1			MRS_REG(PMSICR_EL1)
1508 #define	PMSICR_EL1_op0			0x3
1509 #define	PMSICR_EL1_op1			0x0
1510 #define	PMSICR_EL1_CRn			0x9
1511 #define	PMSICR_EL1_CRm			0x9
1512 #define	PMSICR_EL1_op2			0x2
1513 #define	PMSICR_COUNT_SHIFT		0
1514 #define	PMSICR_COUNT_MASK		(UL(0xffffffff) << PMSICR_COUNT_SHIFT)
1515 #define	PMSICR_ECOUNT_SHIFT		56
1516 #define	PMSICR_ECOUNT_MASK		(UL(0xff) << PMSICR_ECOUNT_SHIFT)
1517 
1518 /* PMSIDR_EL1 */
1519 #define	PMSIDR_EL1			MRS_REG(PMSIDR_EL1)
1520 #define	PMSIDR_EL1_op0			0x3
1521 #define	PMSIDR_EL1_op1			0x0
1522 #define	PMSIDR_EL1_CRn			0x9
1523 #define	PMSIDR_EL1_CRm			0x9
1524 #define	PMSIDR_EL1_op2			0x7
1525 #define	PMSIDR_FE_SHIFT			0
1526 #define	PMSIDR_FE			(UL(0x1) << PMSIDR_FE_SHIFT)
1527 #define	PMSIDR_FT_SHIFT			1
1528 #define	PMSIDR_FT			(UL(0x1) << PMSIDR_FT_SHIFT)
1529 #define	PMSIDR_FL_SHIFT			2
1530 #define	PMSIDR_FL			(UL(0x1) << PMSIDR_FL_SHIFT)
1531 #define	PMSIDR_ArchInst_SHIFT		3
1532 #define	PMSIDR_ArchInst			(UL(0x1) << PMSIDR_ArchInst_SHIFT)
1533 #define	PMSIDR_LDS_SHIFT		4
1534 #define	PMSIDR_LDS			(UL(0x1) << PMSIDR_LDS_SHIFT)
1535 #define	PMSIDR_ERnd_SHIFT		5
1536 #define	PMSIDR_ERnd			(UL(0x1) << PMSIDR_ERnd_SHIFT)
1537 #define	PMSIDR_FnE_SHIFT		6
1538 #define	PMSIDR_FnE			(UL(0x1) << PMSIDR_FnE_SHIFT)
1539 #define	PMSIDR_Interval_SHIFT		8
1540 #define	PMSIDR_Interval_MASK		(UL(0xf) << PMSIDR_Interval_SHIFT)
1541 #define	PMSIDR_MaxSize_SHIFT		12
1542 #define	PMSIDR_MaxSize_MASK		(UL(0xf) << PMSIDR_MaxSize_SHIFT)
1543 #define	PMSIDR_CountSize_SHIFT		16
1544 #define	PMSIDR_CountSize_MASK		(UL(0xf) << PMSIDR_CountSize_SHIFT)
1545 #define	PMSIDR_Format_SHIFT		20
1546 #define	PMSIDR_Format_MASK		(UL(0xf) << PMSIDR_Format_SHIFT)
1547 #define	PMSIDR_PBT_SHIFT		24
1548 #define	PMSIDR_PBT			(UL(0x1) << PMSIDR_PBT_SHIFT)
1549 
1550 /* PMSIRR_EL1 */
1551 #define	PMSIRR_EL1			MRS_REG(PMSIRR_EL1)
1552 #define	PMSIRR_EL1_op0			0x3
1553 #define	PMSIRR_EL1_op1			0x0
1554 #define	PMSIRR_EL1_CRn			0x9
1555 #define	PMSIRR_EL1_CRm			0x9
1556 #define	PMSIRR_EL1_op2			0x3
1557 #define	PMSIRR_RND_SHIFT		0
1558 #define	PMSIRR_RND			(UL(0x1) << PMSIRR_RND_SHIFT)
1559 #define	PMSIRR_INTERVAL_SHIFT		8
1560 #define	PMSIRR_INTERVAL_MASK		(UL(0xffffff) << PMSIRR_INTERVAL_SHIFT)
1561 
1562 /* PMSLATFR_EL1 */
1563 #define	PMSLATFR_EL1			MRS_REG(PMSLATFR_EL1)
1564 #define	PMSLATFR_EL1_op0		0x3
1565 #define	PMSLATFR_EL1_op1		0x0
1566 #define	PMSLATFR_EL1_CRn		0x9
1567 #define	PMSLATFR_EL1_CRm		0x9
1568 #define	PMSLATFR_EL1_op2		0x6
1569 #define	PMSLATFR_MINLAT_SHIFT		0
1570 #define	PMSLATFR_MINLAT_MASK		(UL(0xfff) << PMSLATFR_MINLAT_SHIFT)
1571 
1572 /* PMSNEVFR_EL1 */
1573 #define	PMSNEVFR_EL1			MRS_REG(PMSNEVFR_EL1)
1574 #define	PMSNEVFR_EL1_op0		0x3
1575 #define	PMSNEVFR_EL1_op1		0x0
1576 #define	PMSNEVFR_EL1_CRn		0x9
1577 #define	PMSNEVFR_EL1_CRm		0x9
1578 #define	PMSNEVFR_EL1_op2		0x1
1579 
1580 /* PMSWINC_EL0 */
1581 #define	PMSWINC_EL0			MRS_REG(PMSWINC_EL0)
1582 #define	PMSWINC_EL0_op0			3
1583 #define	PMSWINC_EL0_op1			3
1584 #define	PMSWINC_EL0_CRn			9
1585 #define	PMSWINC_EL0_CRm			12
1586 #define	PMSWINC_EL0_op2			4
1587 
1588 /* PMUSERENR_EL0 */
1589 #define	PMUSERENR_EL0			MRS_REG(PMUSERENR_EL0)
1590 #define	PMUSERENR_EL0_op0		3
1591 #define	PMUSERENR_EL0_op1		3
1592 #define	PMUSERENR_EL0_CRn		9
1593 #define	PMUSERENR_EL0_CRm		14
1594 #define	PMUSERENR_EL0_op2		0
1595 
1596 /* PMXEVCNTR_EL0 */
1597 #define	PMXEVCNTR_EL0			MRS_REG(PMXEVCNTR_EL0)
1598 #define	PMXEVCNTR_EL0_op0		3
1599 #define	PMXEVCNTR_EL0_op1		3
1600 #define	PMXEVCNTR_EL0_CRn		9
1601 #define	PMXEVCNTR_EL0_CRm		13
1602 #define	PMXEVCNTR_EL0_op2		2
1603 
1604 /* PMXEVTYPER_EL0 */
1605 #define	PMXEVTYPER_EL0			MRS_REG(PMXEVTYPER_EL0)
1606 #define	PMXEVTYPER_EL0_op0		3
1607 #define	PMXEVTYPER_EL0_op1		3
1608 #define	PMXEVTYPER_EL0_CRn		9
1609 #define	PMXEVTYPER_EL0_CRm		13
1610 #define	PMXEVTYPER_EL0_op2		1
1611 
1612 /* SCTLR_EL1 - System Control Register */
1613 #define	SCTLR_RES1	0x30d00800	/* Reserved ARMv8.0, write 1 */
1614 #define	SCTLR_M				(UL(0x1) << 0)
1615 #define	SCTLR_A				(UL(0x1) << 1)
1616 #define	SCTLR_C				(UL(0x1) << 2)
1617 #define	SCTLR_SA			(UL(0x1) << 3)
1618 #define	SCTLR_SA0			(UL(0x1) << 4)
1619 #define	SCTLR_CP15BEN			(UL(0x1) << 5)
1620 #define	SCTLR_nAA			(UL(0x1) << 6)
1621 #define	SCTLR_ITD			(UL(0x1) << 7)
1622 #define	SCTLR_SED			(UL(0x1) << 8)
1623 #define	SCTLR_UMA			(UL(0x1) << 9)
1624 #define	SCTLR_EnRCTX			(UL(0x1) << 10)
1625 #define	SCTLR_EOS			(UL(0x1) << 11)
1626 #define	SCTLR_I				(UL(0x1) << 12)
1627 #define	SCTLR_EnDB			(UL(0x1) << 13)
1628 #define	SCTLR_DZE			(UL(0x1) << 14)
1629 #define	SCTLR_UCT			(UL(0x1) << 15)
1630 #define	SCTLR_nTWI			(UL(0x1) << 16)
1631 /* Bit 17 is reserved */
1632 #define	SCTLR_nTWE			(UL(0x1) << 18)
1633 #define	SCTLR_WXN			(UL(0x1) << 19)
1634 #define	SCTLR_TSCXT			(UL(0x1) << 20)
1635 #define	SCTLR_IESB			(UL(0x1) << 21)
1636 #define	SCTLR_EIS			(UL(0x1) << 22)
1637 #define	SCTLR_SPAN			(UL(0x1) << 23)
1638 #define	SCTLR_E0E			(UL(0x1) << 24)
1639 #define	SCTLR_EE			(UL(0x1) << 25)
1640 #define	SCTLR_UCI			(UL(0x1) << 26)
1641 #define	SCTLR_EnDA			(UL(0x1) << 27)
1642 #define	SCTLR_nTLSMD			(UL(0x1) << 28)
1643 #define	SCTLR_LSMAOE			(UL(0x1) << 29)
1644 #define	SCTLR_EnIB			(UL(0x1) << 30)
1645 #define	SCTLR_EnIA			(UL(0x1) << 31)
1646 /* Bits 34:32 are reserved */
1647 #define	SCTLR_BT0			(UL(0x1) << 35)
1648 #define	SCTLR_BT1			(UL(0x1) << 36)
1649 #define	SCTLR_ITFSB			(UL(0x1) << 37)
1650 #define	SCTLR_TCF0_MASK			(UL(0x3) << 38)
1651 #define	SCTLR_TCF_MASK			(UL(0x3) << 40)
1652 #define	SCTLR_ATA0			(UL(0x1) << 42)
1653 #define	SCTLR_ATA			(UL(0x1) << 43)
1654 #define	SCTLR_DSSBS			(UL(0x1) << 44)
1655 #define	SCTLR_TWEDEn			(UL(0x1) << 45)
1656 #define	SCTLR_TWEDEL_MASK		(UL(0xf) << 46)
1657 /* Bits 53:50 are reserved */
1658 #define	SCTLR_EnASR			(UL(0x1) << 54)
1659 #define	SCTLR_EnAS0			(UL(0x1) << 55)
1660 #define	SCTLR_EnALS			(UL(0x1) << 56)
1661 #define	SCTLR_EPAN			(UL(0x1) << 57)
1662 
1663 /* SPSR_EL1 */
1664 /*
1665  * When the exception is taken in AArch64:
1666  * M[3:2] is the exception level
1667  * M[1]   is unused
1668  * M[0]   is the SP select:
1669  *         0: always SP0
1670  *         1: current ELs SP
1671  */
1672 #define	PSR_M_EL0t	0x00000000
1673 #define	PSR_M_EL1t	0x00000004
1674 #define	PSR_M_EL1h	0x00000005
1675 #define	PSR_M_EL2t	0x00000008
1676 #define	PSR_M_EL2h	0x00000009
1677 #define	PSR_M_64	0x00000000
1678 #define	PSR_M_32	0x00000010
1679 #define	PSR_M_MASK	0x0000000f
1680 
1681 #define	PSR_T		0x00000020
1682 
1683 #define	PSR_AARCH32	0x00000010
1684 #define	PSR_F		0x00000040
1685 #define	PSR_I		0x00000080
1686 #define	PSR_A		0x00000100
1687 #define	PSR_D		0x00000200
1688 #define	PSR_DAIF	(PSR_D | PSR_A | PSR_I | PSR_F)
1689 /* The default DAIF mask. These bits are valid in spsr_el1 and daif */
1690 #define	PSR_DAIF_DEFAULT (PSR_F)
1691 #define	PSR_IL		0x00100000
1692 #define	PSR_SS		0x00200000
1693 #define	PSR_V		0x10000000
1694 #define	PSR_C		0x20000000
1695 #define	PSR_Z		0x40000000
1696 #define	PSR_N		0x80000000
1697 #define	PSR_FLAGS	0xf0000000
1698 /* PSR fields that can be set from 32-bit and 64-bit processes */
1699 #define	PSR_SETTABLE_32	PSR_FLAGS
1700 #define	PSR_SETTABLE_64	(PSR_FLAGS | PSR_SS)
1701 
1702 /* TCR_EL1 - Translation Control Register */
1703 /* Bits 63:59 are reserved */
1704 #define	TCR_TCMA1_SHIFT		58
1705 #define	TCR_TCMA1		(1UL << TCR_TCMA1_SHIFT)
1706 #define	TCR_TCMA0_SHIFT		57
1707 #define	TCR_TCMA0		(1UL << TCR_TCMA0_SHIFT)
1708 #define	TCR_E0PD1_SHIFT		56
1709 #define	TCR_E0PD1		(1UL << TCR_E0PD1_SHIFT)
1710 #define	TCR_E0PD0_SHIFT		55
1711 #define	TCR_E0PD0		(1UL << TCR_E0PD0_SHIFT)
1712 #define	TCR_NFD1_SHIFT		54
1713 #define	TCR_NFD1		(1UL << TCR_NFD1_SHIFT)
1714 #define	TCR_NFD0_SHIFT		53
1715 #define	TCR_NFD0		(1UL << TCR_NFD0_SHIFT)
1716 #define	TCR_TBID1_SHIFT		52
1717 #define	TCR_TBID1		(1UL << TCR_TBID1_SHIFT)
1718 #define	TCR_TBID0_SHIFT		51
1719 #define	TCR_TBID0		(1UL << TCR_TBID0_SHIFT)
1720 #define	TCR_HWU162_SHIFT	50
1721 #define	TCR_HWU162		(1UL << TCR_HWU162_SHIFT)
1722 #define	TCR_HWU161_SHIFT	49
1723 #define	TCR_HWU161		(1UL << TCR_HWU161_SHIFT)
1724 #define	TCR_HWU160_SHIFT	48
1725 #define	TCR_HWU160		(1UL << TCR_HWU160_SHIFT)
1726 #define	TCR_HWU159_SHIFT	47
1727 #define	TCR_HWU159		(1UL << TCR_HWU159_SHIFT)
1728 #define	TCR_HWU1		\
1729     (TCR_HWU159 | TCR_HWU160 | TCR_HWU161 | TCR_HWU162)
1730 #define	TCR_HWU062_SHIFT	46
1731 #define	TCR_HWU062		(1UL << TCR_HWU062_SHIFT)
1732 #define	TCR_HWU061_SHIFT	45
1733 #define	TCR_HWU061		(1UL << TCR_HWU061_SHIFT)
1734 #define	TCR_HWU060_SHIFT	44
1735 #define	TCR_HWU060		(1UL << TCR_HWU060_SHIFT)
1736 #define	TCR_HWU059_SHIFT	43
1737 #define	TCR_HWU059		(1UL << TCR_HWU059_SHIFT)
1738 #define	TCR_HWU0		\
1739     (TCR_HWU059 | TCR_HWU060 | TCR_HWU061 | TCR_HWU062)
1740 #define	TCR_HPD1_SHIFT		42
1741 #define	TCR_HPD1		(1UL << TCR_HPD1_SHIFT)
1742 #define	TCR_HPD0_SHIFT		41
1743 #define	TCR_HPD0		(1UL << TCR_HPD0_SHIFT)
1744 #define	TCR_HD_SHIFT		40
1745 #define	TCR_HD			(1UL << TCR_HD_SHIFT)
1746 #define	TCR_HA_SHIFT		39
1747 #define	TCR_HA			(1UL << TCR_HA_SHIFT)
1748 #define	TCR_TBI1_SHIFT		38
1749 #define	TCR_TBI1		(1UL << TCR_TBI1_SHIFT)
1750 #define	TCR_TBI0_SHIFT		37
1751 #define	TCR_TBI0		(1U << TCR_TBI0_SHIFT)
1752 #define	TCR_ASID_SHIFT		36
1753 #define	TCR_ASID_WIDTH		1
1754 #define	TCR_ASID_16		(1UL << TCR_ASID_SHIFT)
1755 /* Bit 35 is reserved */
1756 #define	TCR_IPS_SHIFT		32
1757 #define	TCR_IPS_WIDTH		3
1758 #define	TCR_IPS_32BIT		(0UL << TCR_IPS_SHIFT)
1759 #define	TCR_IPS_36BIT		(1UL << TCR_IPS_SHIFT)
1760 #define	TCR_IPS_40BIT		(2UL << TCR_IPS_SHIFT)
1761 #define	TCR_IPS_42BIT		(3UL << TCR_IPS_SHIFT)
1762 #define	TCR_IPS_44BIT		(4UL << TCR_IPS_SHIFT)
1763 #define	TCR_IPS_48BIT		(5UL << TCR_IPS_SHIFT)
1764 #define	TCR_TG1_SHIFT		30
1765 #define	TCR_TG1_16K		(1UL << TCR_TG1_SHIFT)
1766 #define	TCR_TG1_4K		(2UL << TCR_TG1_SHIFT)
1767 #define	TCR_TG1_64K		(3UL << TCR_TG1_SHIFT)
1768 #define	TCR_SH1_SHIFT		28
1769 #define	TCR_SH1_IS		(3UL << TCR_SH1_SHIFT)
1770 #define	TCR_ORGN1_SHIFT		26
1771 #define	TCR_ORGN1_WBWA		(1UL << TCR_ORGN1_SHIFT)
1772 #define	TCR_IRGN1_SHIFT		24
1773 #define	TCR_IRGN1_WBWA		(1UL << TCR_IRGN1_SHIFT)
1774 #define	TCR_EPD1_SHIFT		23
1775 #define	TCR_EPD1		(1UL << TCR_EPD1_SHIFT)
1776 #define	TCR_A1_SHIFT		22
1777 #define	TCR_A1			(0x1UL << TCR_A1_SHIFT)
1778 #define	TCR_T1SZ_SHIFT		16
1779 #define	TCR_T1SZ(x)		((x) << TCR_T1SZ_SHIFT)
1780 #define	TCR_TG0_SHIFT		14
1781 #define	TCR_TG0_4K		(0UL << TCR_TG0_SHIFT)
1782 #define	TCR_TG0_64K		(1UL << TCR_TG0_SHIFT)
1783 #define	TCR_TG0_16K		(2UL << TCR_TG0_SHIFT)
1784 #define	TCR_SH0_SHIFT		12
1785 #define	TCR_SH0_IS		(3UL << TCR_SH0_SHIFT)
1786 #define	TCR_ORGN0_SHIFT		10
1787 #define	TCR_ORGN0_WBWA		(1UL << TCR_ORGN0_SHIFT)
1788 #define	TCR_IRGN0_SHIFT		8
1789 #define	TCR_IRGN0_WBWA		(1UL << TCR_IRGN0_SHIFT)
1790 #define	TCR_EPD0_SHIFT		7
1791 #define	TCR_EPD0		(1UL << TCR_EPD1_SHIFT)
1792 /* Bit 6 is reserved */
1793 #define	TCR_T0SZ_SHIFT		0
1794 #define	TCR_T0SZ_MASK		0x3f
1795 #define	TCR_T0SZ(x)		((x) << TCR_T0SZ_SHIFT)
1796 #define	TCR_TxSZ(x)		(TCR_T1SZ(x) | TCR_T0SZ(x))
1797 
1798 #define	TCR_CACHE_ATTRS	((TCR_IRGN0_WBWA | TCR_IRGN1_WBWA) |\
1799 				(TCR_ORGN0_WBWA | TCR_ORGN1_WBWA))
1800 #ifdef SMP
1801 #define	TCR_SMP_ATTRS	(TCR_SH0_IS | TCR_SH1_IS)
1802 #else
1803 #define	TCR_SMP_ATTRS	0
1804 #endif
1805 
1806 /* TTBR0_EL1 & TTBR1_EL1 - Translation Table Base Register 0 & 1 */
1807 #define	TTBR_ASID_SHIFT		48
1808 #define	TTBR_ASID_MASK		(0xfffful << TTBR_ASID_SHIFT)
1809 #define	TTBR_BADDR		0x0000fffffffffffeul
1810 #define	TTBR_CnP_SHIFT		0
1811 #define	TTBR_CnP		(1ul << TTBR_CnP_SHIFT)
1812 
1813 /* ZCR_EL1 - SVE Control Register */
1814 #define	ZCR_LEN_SHIFT		0
1815 #define	ZCR_LEN_MASK		(0xf << ZCR_LEN_SHIFT)
1816 #define	ZCR_LEN_BYTES(x)	((((x) & ZCR_LEN_MASK) + 1) * 16)
1817 
1818 #endif /* !_MACHINE_ARMREG_H_ */
1819