1 /*- 2 * Copyright (c) 2013, 2014 Andrew Turner 3 * Copyright (c) 2015 The FreeBSD Foundation 4 * All rights reserved. 5 * 6 * This software was developed by Andrew Turner under 7 * sponsorship from the FreeBSD Foundation. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * $FreeBSD$ 31 */ 32 33 #ifndef _MACHINE_ARMREG_H_ 34 #define _MACHINE_ARMREG_H_ 35 36 #define INSN_SIZE 4 37 38 #define MRS_MASK 0xfff00000 39 #define MRS_VALUE 0xd5300000 40 #define MRS_SPECIAL(insn) ((insn) & 0x000fffe0) 41 #define MRS_REGISTER(insn) ((insn) & 0x0000001f) 42 #define MRS_Op0_SHIFT 19 43 #define MRS_Op0_MASK 0x00080000 44 #define MRS_Op1_SHIFT 16 45 #define MRS_Op1_MASK 0x00070000 46 #define MRS_CRn_SHIFT 12 47 #define MRS_CRn_MASK 0x0000f000 48 #define MRS_CRm_SHIFT 8 49 #define MRS_CRm_MASK 0x00000f00 50 #define MRS_Op2_SHIFT 5 51 #define MRS_Op2_MASK 0x000000e0 52 #define MRS_Rt_SHIFT 0 53 #define MRS_Rt_MASK 0x0000001f 54 #define MRS_REG(op0, op1, crn, crm, op2) \ 55 (((op0) << MRS_Op0_SHIFT) | ((op1) << MRS_Op1_SHIFT) | \ 56 ((crn) << MRS_CRn_SHIFT) | ((crm) << MRS_CRm_SHIFT) | \ 57 ((op2) << MRS_Op2_SHIFT)) 58 59 #define READ_SPECIALREG(reg) \ 60 ({ uint64_t _val; \ 61 __asm __volatile("mrs %0, " __STRING(reg) : "=&r" (_val)); \ 62 _val; \ 63 }) 64 #define WRITE_SPECIALREG(reg, _val) \ 65 __asm __volatile("msr " __STRING(reg) ", %0" : : "r"((uint64_t)_val)) 66 67 #define UL(x) UINT64_C(x) 68 69 /* CNTHCTL_EL2 - Counter-timer Hypervisor Control register */ 70 #define CNTHCTL_EVNTI_MASK (0xf << 4) /* Bit to trigger event stream */ 71 #define CNTHCTL_EVNTDIR (1 << 3) /* Control transition trigger bit */ 72 #define CNTHCTL_EVNTEN (1 << 2) /* Enable event stream */ 73 #define CNTHCTL_EL1PCEN (1 << 1) /* Allow EL0/1 physical timer access */ 74 #define CNTHCTL_EL1PCTEN (1 << 0) /*Allow EL0/1 physical counter access*/ 75 76 /* CPACR_EL1 */ 77 #define CPACR_FPEN_MASK (0x3 << 20) 78 #define CPACR_FPEN_TRAP_ALL1 (0x0 << 20) /* Traps from EL0 and EL1 */ 79 #define CPACR_FPEN_TRAP_EL0 (0x1 << 20) /* Traps from EL0 */ 80 #define CPACR_FPEN_TRAP_ALL2 (0x2 << 20) /* Traps from EL0 and EL1 */ 81 #define CPACR_FPEN_TRAP_NONE (0x3 << 20) /* No traps */ 82 #define CPACR_TTA (0x1 << 28) 83 84 /* CTR_EL0 - Cache Type Register */ 85 #define CTR_RES1 (1 << 31) 86 #define CTR_TminLine_SHIFT 32 87 #define CTR_TminLine_MASK (UL(0x3f) << CTR_TminLine_SHIFT) 88 #define CTR_TminLine_VAL(reg) ((reg) & CTR_TminLine_MASK) 89 #define CTR_DIC_SHIFT 29 90 #define CTR_DIC_MASK (0x1 << CTR_DIC_SHIFT) 91 #define CTR_DIC_VAL(reg) ((reg) & CTR_DIC_MASK) 92 #define CTR_IDC_SHIFT 28 93 #define CTR_IDC_MASK (0x1 << CTR_IDC_SHIFT) 94 #define CTR_IDC_VAL(reg) ((reg) & CTR_IDC_MASK) 95 #define CTR_CWG_SHIFT 24 96 #define CTR_CWG_MASK (0xf << CTR_CWG_SHIFT) 97 #define CTR_CWG_VAL(reg) ((reg) & CTR_CWG_MASK) 98 #define CTR_CWG_SIZE(reg) (4 << (CTR_CWG_VAL(reg) >> CTR_CWG_SHIFT)) 99 #define CTR_ERG_SHIFT 20 100 #define CTR_ERG_MASK (0xf << CTR_ERG_SHIFT) 101 #define CTR_ERG_VAL(reg) ((reg) & CTR_ERG_MASK) 102 #define CTR_ERG_SIZE(reg) (4 << (CTR_ERG_VAL(reg) >> CTR_ERG_SHIFT)) 103 #define CTR_DLINE_SHIFT 16 104 #define CTR_DLINE_MASK (0xf << CTR_DLINE_SHIFT) 105 #define CTR_DLINE_VAL(reg) ((reg) & CTR_DLINE_MASK) 106 #define CTR_DLINE_SIZE(reg) (4 << (CTR_DLINE_VAL(reg) >> CTR_DLINE_SHIFT)) 107 #define CTR_L1IP_SHIFT 14 108 #define CTR_L1IP_MASK (0x3 << CTR_L1IP_SHIFT) 109 #define CTR_L1IP_VAL(reg) ((reg) & CTR_L1IP_MASK) 110 #define CTR_L1IP_VPIPT (0 << CTR_L1IP_SHIFT) 111 #define CTR_L1IP_AIVIVT (1 << CTR_L1IP_SHIFT) 112 #define CTR_L1IP_VIPT (2 << CTR_L1IP_SHIFT) 113 #define CTR_L1IP_PIPT (3 << CTR_L1IP_SHIFT) 114 #define CTR_ILINE_SHIFT 0 115 #define CTR_ILINE_MASK (0xf << CTR_ILINE_SHIFT) 116 #define CTR_ILINE_VAL(reg) ((reg) & CTR_ILINE_MASK) 117 #define CTR_ILINE_SIZE(reg) (4 << (CTR_ILINE_VAL(reg) >> CTR_ILINE_SHIFT)) 118 119 /* DAIF - Interrupt Mask Bits */ 120 #define DAIF_D_MASKED (1 << 9) 121 #define DAIF_A_MASKED (1 << 8) 122 #define DAIF_I_MASKED (1 << 7) 123 #define DAIF_F_MASKED (1 << 6) 124 125 /* DCZID_EL0 - Data Cache Zero ID register */ 126 #define DCZID_DZP (1 << 4) /* DC ZVA prohibited if non-0 */ 127 #define DCZID_BS_SHIFT 0 128 #define DCZID_BS_MASK (0xf << DCZID_BS_SHIFT) 129 #define DCZID_BS_SIZE(reg) (((reg) & DCZID_BS_MASK) >> DCZID_BS_SHIFT) 130 131 /* ESR_ELx */ 132 #define ESR_ELx_ISS_MASK 0x00ffffff 133 #define ISS_INSN_FnV (0x01 << 10) 134 #define ISS_INSN_EA (0x01 << 9) 135 #define ISS_INSN_S1PTW (0x01 << 7) 136 #define ISS_INSN_IFSC_MASK (0x1f << 0) 137 #define ISS_DATA_ISV (0x01 << 24) 138 #define ISS_DATA_SAS_MASK (0x03 << 22) 139 #define ISS_DATA_SSE (0x01 << 21) 140 #define ISS_DATA_SRT_MASK (0x1f << 16) 141 #define ISS_DATA_SF (0x01 << 15) 142 #define ISS_DATA_AR (0x01 << 14) 143 #define ISS_DATA_FnV (0x01 << 10) 144 #define ISS_DATA_EA (0x01 << 9) 145 #define ISS_DATA_CM (0x01 << 8) 146 #define ISS_DATA_S1PTW (0x01 << 7) 147 #define ISS_DATA_WnR (0x01 << 6) 148 #define ISS_DATA_DFSC_MASK (0x3f << 0) 149 #define ISS_DATA_DFSC_ASF_L0 (0x00 << 0) 150 #define ISS_DATA_DFSC_ASF_L1 (0x01 << 0) 151 #define ISS_DATA_DFSC_ASF_L2 (0x02 << 0) 152 #define ISS_DATA_DFSC_ASF_L3 (0x03 << 0) 153 #define ISS_DATA_DFSC_TF_L0 (0x04 << 0) 154 #define ISS_DATA_DFSC_TF_L1 (0x05 << 0) 155 #define ISS_DATA_DFSC_TF_L2 (0x06 << 0) 156 #define ISS_DATA_DFSC_TF_L3 (0x07 << 0) 157 #define ISS_DATA_DFSC_AFF_L1 (0x09 << 0) 158 #define ISS_DATA_DFSC_AFF_L2 (0x0a << 0) 159 #define ISS_DATA_DFSC_AFF_L3 (0x0b << 0) 160 #define ISS_DATA_DFSC_PF_L1 (0x0d << 0) 161 #define ISS_DATA_DFSC_PF_L2 (0x0e << 0) 162 #define ISS_DATA_DFSC_PF_L3 (0x0f << 0) 163 #define ISS_DATA_DFSC_EXT (0x10 << 0) 164 #define ISS_DATA_DFSC_EXT_L0 (0x14 << 0) 165 #define ISS_DATA_DFSC_EXT_L1 (0x15 << 0) 166 #define ISS_DATA_DFSC_EXT_L2 (0x16 << 0) 167 #define ISS_DATA_DFSC_EXT_L3 (0x17 << 0) 168 #define ISS_DATA_DFSC_ECC (0x18 << 0) 169 #define ISS_DATA_DFSC_ECC_L0 (0x1c << 0) 170 #define ISS_DATA_DFSC_ECC_L1 (0x1d << 0) 171 #define ISS_DATA_DFSC_ECC_L2 (0x1e << 0) 172 #define ISS_DATA_DFSC_ECC_L3 (0x1f << 0) 173 #define ISS_DATA_DFSC_ALIGN (0x21 << 0) 174 #define ISS_DATA_DFSC_TLB_CONFLICT (0x30 << 0) 175 #define ESR_ELx_IL (0x01 << 25) 176 #define ESR_ELx_EC_SHIFT 26 177 #define ESR_ELx_EC_MASK (0x3f << 26) 178 #define ESR_ELx_EXCEPTION(esr) (((esr) & ESR_ELx_EC_MASK) >> ESR_ELx_EC_SHIFT) 179 #define EXCP_UNKNOWN 0x00 /* Unkwn exception */ 180 #define EXCP_FP_SIMD 0x07 /* VFP/SIMD trap */ 181 #define EXCP_ILL_STATE 0x0e /* Illegal execution state */ 182 #define EXCP_SVC32 0x11 /* SVC trap for AArch32 */ 183 #define EXCP_SVC64 0x15 /* SVC trap for AArch64 */ 184 #define EXCP_MSR 0x18 /* MSR/MRS trap */ 185 #define EXCP_INSN_ABORT_L 0x20 /* Instruction abort, from lower EL */ 186 #define EXCP_INSN_ABORT 0x21 /* Instruction abort, from same EL */ 187 #define EXCP_PC_ALIGN 0x22 /* PC alignment fault */ 188 #define EXCP_DATA_ABORT_L 0x24 /* Data abort, from lower EL */ 189 #define EXCP_DATA_ABORT 0x25 /* Data abort, from same EL */ 190 #define EXCP_SP_ALIGN 0x26 /* SP slignment fault */ 191 #define EXCP_TRAP_FP 0x2c /* Trapped FP exception */ 192 #define EXCP_SERROR 0x2f /* SError interrupt */ 193 #define EXCP_BRKPT_EL0 0x30 /* Hardware breakpoint, from same EL */ 194 #define EXCP_SOFTSTP_EL0 0x32 /* Software Step, from lower EL */ 195 #define EXCP_SOFTSTP_EL1 0x33 /* Software Step, from same EL */ 196 #define EXCP_WATCHPT_EL1 0x35 /* Watchpoint, from same EL */ 197 #define EXCP_BRK 0x3c /* Breakpoint */ 198 199 /* ICC_CTLR_EL1 */ 200 #define ICC_CTLR_EL1_EOIMODE (1U << 1) 201 202 /* ICC_IAR1_EL1 */ 203 #define ICC_IAR1_EL1_SPUR (0x03ff) 204 205 /* ICC_IGRPEN0_EL1 */ 206 #define ICC_IGRPEN0_EL1_EN (1U << 0) 207 208 /* ICC_PMR_EL1 */ 209 #define ICC_PMR_EL1_PRIO_MASK (0xFFUL) 210 211 /* ICC_SGI1R_EL1 */ 212 #define ICC_SGI1R_EL1_TL_MASK 0xffffUL 213 #define ICC_SGI1R_EL1_AFF1_SHIFT 16 214 #define ICC_SGI1R_EL1_SGIID_SHIFT 24 215 #define ICC_SGI1R_EL1_AFF2_SHIFT 32 216 #define ICC_SGI1R_EL1_AFF3_SHIFT 48 217 #define ICC_SGI1R_EL1_SGIID_MASK 0xfUL 218 #define ICC_SGI1R_EL1_IRM (0x1UL << 40) 219 220 /* ICC_SRE_EL1 */ 221 #define ICC_SRE_EL1_SRE (1U << 0) 222 223 /* ICC_SRE_EL2 */ 224 #define ICC_SRE_EL2_SRE (1U << 0) 225 #define ICC_SRE_EL2_EN (1U << 3) 226 227 /* ID_AA64DFR0_EL1 */ 228 #define ID_AA64DFR0_EL1 MRS_REG(3, 0, 0, 5, 0) 229 #define ID_AA64DFR0_DebugVer_SHIFT 0 230 #define ID_AA64DFR0_DebugVer_MASK (UL(0xf) << ID_AA64DFR0_DebugVer_SHIFT) 231 #define ID_AA64DFR0_DebugVer_VAL(x) ((x) & ID_AA64DFR0_DebugVer_MASK) 232 #define ID_AA64DFR0_DebugVer_8 (UL(0x6) << ID_AA64DFR0_DebugVer_SHIFT) 233 #define ID_AA64DFR0_DebugVer_8_VHE (UL(0x7) << ID_AA64DFR0_DebugVer_SHIFT) 234 #define ID_AA64DFR0_DebugVer_8_2 (UL(0x8) << ID_AA64DFR0_DebugVer_SHIFT) 235 #define ID_AA64DFR0_TraceVer_SHIFT 4 236 #define ID_AA64DFR0_TraceVer_MASK (UL(0xf) << ID_AA64DFR0_TraceVer_SHIFT) 237 #define ID_AA64DFR0_TraceVer_VAL(x) ((x) & ID_AA64DFR0_TraceVer_MASK) 238 #define ID_AA64DFR0_TraceVer_NONE (UL(0x0) << ID_AA64DFR0_TraceVer_SHIFT) 239 #define ID_AA64DFR0_TraceVer_IMPL (UL(0x1) << ID_AA64DFR0_TraceVer_SHIFT) 240 #define ID_AA64DFR0_PMUVer_SHIFT 8 241 #define ID_AA64DFR0_PMUVer_MASK (UL(0xf) << ID_AA64DFR0_PMUVer_SHIFT) 242 #define ID_AA64DFR0_PMUVer_VAL(x) ((x) & ID_AA64DFR0_PMUVer_MASK) 243 #define ID_AA64DFR0_PMUVer_NONE (UL(0x0) << ID_AA64DFR0_PMUVer_SHIFT) 244 #define ID_AA64DFR0_PMUVer_3 (UL(0x1) << ID_AA64DFR0_PMUVer_SHIFT) 245 #define ID_AA64DFR0_PMUVer_3_1 (UL(0x4) << ID_AA64DFR0_PMUVer_SHIFT) 246 #define ID_AA64DFR0_PMUVer_IMPL (UL(0xf) << ID_AA64DFR0_PMUVer_SHIFT) 247 #define ID_AA64DFR0_BRPs_SHIFT 12 248 #define ID_AA64DFR0_BRPs_MASK (UL(0xf) << ID_AA64DFR0_BRPs_SHIFT) 249 #define ID_AA64DFR0_BRPs_VAL(x) \ 250 ((((x) >> ID_AA64DFR0_BRPs_SHIFT) & 0xf) + 1) 251 #define ID_AA64DFR0_WRPs_SHIFT 20 252 #define ID_AA64DFR0_WRPs_MASK (UL(0xf) << ID_AA64DFR0_WRPs_SHIFT) 253 #define ID_AA64DFR0_WRPs_VAL(x) \ 254 ((((x) >> ID_AA64DFR0_WRPs_SHIFT) & 0xf) + 1) 255 #define ID_AA64DFR0_CTX_CMPs_SHIFT 28 256 #define ID_AA64DFR0_CTX_CMPs_MASK (UL(0xf) << ID_AA64DFR0_CTX_CMPs_SHIFT) 257 #define ID_AA64DFR0_CTX_CMPs_VAL(x) \ 258 ((((x) >> ID_AA64DFR0_CTX_CMPs_SHIFT) & 0xf) + 1) 259 #define ID_AA64DFR0_PMSVer_SHIFT 32 260 #define ID_AA64DFR0_PMSVer_MASK (UL(0xf) << ID_AA64DFR0_PMSVer_SHIFT) 261 #define ID_AA64DFR0_PMSVer_VAL(x) ((x) & ID_AA64DFR0_PMSVer_MASK) 262 #define ID_AA64DFR0_PMSVer_NONE (UL(0x0) << ID_AA64DFR0_PMSVer_SHIFT) 263 #define ID_AA64DFR0_PMSVer_V1 (UL(0x1) << ID_AA64DFR0_PMSVer_SHIFT) 264 265 /* ID_AA64ISAR0_EL1 */ 266 #define ID_AA64ISAR0_EL1 MRS_REG(3, 0, 0, 6, 0) 267 #define ID_AA64ISAR0_AES_SHIFT 4 268 #define ID_AA64ISAR0_AES_MASK (UL(0xf) << ID_AA64ISAR0_AES_SHIFT) 269 #define ID_AA64ISAR0_AES_VAL(x) ((x) & ID_AA64ISAR0_AES_MASK) 270 #define ID_AA64ISAR0_AES_NONE (UL(0x0) << ID_AA64ISAR0_AES_SHIFT) 271 #define ID_AA64ISAR0_AES_BASE (UL(0x1) << ID_AA64ISAR0_AES_SHIFT) 272 #define ID_AA64ISAR0_AES_PMULL (UL(0x2) << ID_AA64ISAR0_AES_SHIFT) 273 #define ID_AA64ISAR0_SHA1_SHIFT 8 274 #define ID_AA64ISAR0_SHA1_MASK (UL(0xf) << ID_AA64ISAR0_SHA1_SHIFT) 275 #define ID_AA64ISAR0_SHA1_VAL(x) ((x) & ID_AA64ISAR0_SHA1_MASK) 276 #define ID_AA64ISAR0_SHA1_NONE (UL(0x0) << ID_AA64ISAR0_SHA1_SHIFT) 277 #define ID_AA64ISAR0_SHA1_BASE (UL(0x1) << ID_AA64ISAR0_SHA1_SHIFT) 278 #define ID_AA64ISAR0_SHA2_SHIFT 12 279 #define ID_AA64ISAR0_SHA2_MASK (UL(0xf) << ID_AA64ISAR0_SHA2_SHIFT) 280 #define ID_AA64ISAR0_SHA2_VAL(x) ((x) & ID_AA64ISAR0_SHA2_MASK) 281 #define ID_AA64ISAR0_SHA2_NONE (UL(0x0) << ID_AA64ISAR0_SHA2_SHIFT) 282 #define ID_AA64ISAR0_SHA2_BASE (UL(0x1) << ID_AA64ISAR0_SHA2_SHIFT) 283 #define ID_AA64ISAR0_SHA2_512 (UL(0x2) << ID_AA64ISAR0_SHA2_SHIFT) 284 #define ID_AA64ISAR0_CRC32_SHIFT 16 285 #define ID_AA64ISAR0_CRC32_MASK (UL(0xf) << ID_AA64ISAR0_CRC32_SHIFT) 286 #define ID_AA64ISAR0_CRC32_VAL(x) ((x) & ID_AA64ISAR0_CRC32_MASK) 287 #define ID_AA64ISAR0_CRC32_NONE (UL(0x0) << ID_AA64ISAR0_CRC32_SHIFT) 288 #define ID_AA64ISAR0_CRC32_BASE (UL(0x1) << ID_AA64ISAR0_CRC32_SHIFT) 289 #define ID_AA64ISAR0_Atomic_SHIFT 20 290 #define ID_AA64ISAR0_Atomic_MASK (UL(0xf) << ID_AA64ISAR0_Atomic_SHIFT) 291 #define ID_AA64ISAR0_Atomic_VAL(x) ((x) & ID_AA64ISAR0_Atomic_MASK) 292 #define ID_AA64ISAR0_Atomic_NONE (UL(0x0) << ID_AA64ISAR0_Atomic_SHIFT) 293 #define ID_AA64ISAR0_Atomic_IMPL (UL(0x2) << ID_AA64ISAR0_Atomic_SHIFT) 294 #define ID_AA64ISAR0_RDM_SHIFT 28 295 #define ID_AA64ISAR0_RDM_MASK (UL(0xf) << ID_AA64ISAR0_RDM_SHIFT) 296 #define ID_AA64ISAR0_RDM_VAL(x) ((x) & ID_AA64ISAR0_RDM_MASK) 297 #define ID_AA64ISAR0_RDM_NONE (UL(0x0) << ID_AA64ISAR0_RDM_SHIFT) 298 #define ID_AA64ISAR0_RDM_IMPL (UL(0x1) << ID_AA64ISAR0_RDM_SHIFT) 299 #define ID_AA64ISAR0_SHA3_SHIFT 32 300 #define ID_AA64ISAR0_SHA3_MASK (UL(0xf) << ID_AA64ISAR0_SHA3_SHIFT) 301 #define ID_AA64ISAR0_SHA3_VAL(x) ((x) & ID_AA64ISAR0_SHA3_MASK) 302 #define ID_AA64ISAR0_SHA3_NONE (UL(0x0) << ID_AA64ISAR0_SHA3_SHIFT) 303 #define ID_AA64ISAR0_SHA3_IMPL (UL(0x1) << ID_AA64ISAR0_SHA3_SHIFT) 304 #define ID_AA64ISAR0_SM3_SHIFT 36 305 #define ID_AA64ISAR0_SM3_MASK (UL(0xf) << ID_AA64ISAR0_SM3_SHIFT) 306 #define ID_AA64ISAR0_SM3_VAL(x) ((x) & ID_AA64ISAR0_SM3_MASK) 307 #define ID_AA64ISAR0_SM3_NONE (UL(0x0) << ID_AA64ISAR0_SM3_SHIFT) 308 #define ID_AA64ISAR0_SM3_IMPL (UL(0x1) << ID_AA64ISAR0_SM3_SHIFT) 309 #define ID_AA64ISAR0_SM4_SHIFT 40 310 #define ID_AA64ISAR0_SM4_MASK (UL(0xf) << ID_AA64ISAR0_SM4_SHIFT) 311 #define ID_AA64ISAR0_SM4_VAL(x) ((x) & ID_AA64ISAR0_SM4_MASK) 312 #define ID_AA64ISAR0_SM4_NONE (UL(0x0) << ID_AA64ISAR0_SM4_SHIFT) 313 #define ID_AA64ISAR0_SM4_IMPL (UL(0x1) << ID_AA64ISAR0_SM4_SHIFT) 314 #define ID_AA64ISAR0_DP_SHIFT 44 315 #define ID_AA64ISAR0_DP_MASK (UL(0xf) << ID_AA64ISAR0_DP_SHIFT) 316 #define ID_AA64ISAR0_DP_VAL(x) ((x) & ID_AA64ISAR0_DP_MASK) 317 #define ID_AA64ISAR0_DP_NONE (UL(0x0) << ID_AA64ISAR0_DP_SHIFT) 318 #define ID_AA64ISAR0_DP_IMPL (UL(0x1) << ID_AA64ISAR0_DP_SHIFT) 319 320 /* ID_AA64ISAR1_EL1 */ 321 #define ID_AA64ISAR1_EL1 MRS_REG(3, 0, 0, 6, 1) 322 #define ID_AA64ISAR1_DPB_SHIFT 0 323 #define ID_AA64ISAR1_DPB_MASK (UL(0xf) << ID_AA64ISAR1_DPB_SHIFT) 324 #define ID_AA64ISAR1_DPB_VAL(x) ((x) & ID_AA64ISAR1_DPB_MASK) 325 #define ID_AA64ISAR1_DPB_NONE (UL(0x0) << ID_AA64ISAR1_DPB_SHIFT) 326 #define ID_AA64ISAR1_DPB_IMPL (UL(0x1) << ID_AA64ISAR1_DPB_SHIFT) 327 #define ID_AA64ISAR1_APA_SHIFT 4 328 #define ID_AA64ISAR1_APA_MASK (UL(0xf) << ID_AA64ISAR1_APA_SHIFT) 329 #define ID_AA64ISAR1_APA_VAL(x) ((x) & ID_AA64ISAR1_APA_MASK) 330 #define ID_AA64ISAR1_APA_NONE (UL(0x0) << ID_AA64ISAR1_APA_SHIFT) 331 #define ID_AA64ISAR1_APA_IMPL (UL(0x1) << ID_AA64ISAR1_APA_SHIFT) 332 #define ID_AA64ISAR1_API_SHIFT 8 333 #define ID_AA64ISAR1_API_MASK (UL(0xf) << ID_AA64ISAR1_API_SHIFT) 334 #define ID_AA64ISAR1_API_VAL(x) ((x) & ID_AA64ISAR1_API_MASK) 335 #define ID_AA64ISAR1_API_NONE (UL(0x0) << ID_AA64ISAR1_API_SHIFT) 336 #define ID_AA64ISAR1_API_IMPL (UL(0x1) << ID_AA64ISAR1_API_SHIFT) 337 #define ID_AA64ISAR1_JSCVT_SHIFT 12 338 #define ID_AA64ISAR1_JSCVT_MASK (UL(0xf) << ID_AA64ISAR1_JSCVT_SHIFT) 339 #define ID_AA64ISAR1_JSCVT_VAL(x) ((x) & ID_AA64ISAR1_JSCVT_MASK) 340 #define ID_AA64ISAR1_JSCVT_NONE (UL(0x0) << ID_AA64ISAR1_JSCVT_SHIFT) 341 #define ID_AA64ISAR1_JSCVT_IMPL (UL(0x1) << ID_AA64ISAR1_JSCVT_SHIFT) 342 #define ID_AA64ISAR1_FCMA_SHIFT 16 343 #define ID_AA64ISAR1_FCMA_MASK (UL(0xf) << ID_AA64ISAR1_FCMA_SHIFT) 344 #define ID_AA64ISAR1_FCMA_VAL(x) ((x) & ID_AA64ISAR1_FCMA_MASK) 345 #define ID_AA64ISAR1_FCMA_NONE (UL(0x0) << ID_AA64ISAR1_FCMA_SHIFT) 346 #define ID_AA64ISAR1_FCMA_IMPL (UL(0x1) << ID_AA64ISAR1_FCMA_SHIFT) 347 #define ID_AA64ISAR1_LRCPC_SHIFT 20 348 #define ID_AA64ISAR1_LRCPC_MASK (UL(0xf) << ID_AA64ISAR1_LRCPC_SHIFT) 349 #define ID_AA64ISAR1_LRCPC_VAL(x) ((x) & ID_AA64ISAR1_LRCPC_MASK) 350 #define ID_AA64ISAR1_LRCPC_NONE (UL(0x0) << ID_AA64ISAR1_LRCPC_SHIFT) 351 #define ID_AA64ISAR1_LRCPC_IMPL (UL(0x1) << ID_AA64ISAR1_LRCPC_SHIFT) 352 #define ID_AA64ISAR1_GPA_SHIFT 24 353 #define ID_AA64ISAR1_GPA_MASK (UL(0xf) << ID_AA64ISAR1_GPA_SHIFT) 354 #define ID_AA64ISAR1_GPA_VAL(x) ((x) & ID_AA64ISAR1_GPA_MASK) 355 #define ID_AA64ISAR1_GPA_NONE (UL(0x0) << ID_AA64ISAR1_GPA_SHIFT) 356 #define ID_AA64ISAR1_GPA_IMPL (UL(0x1) << ID_AA64ISAR1_GPA_SHIFT) 357 #define ID_AA64ISAR1_GPI_SHIFT 28 358 #define ID_AA64ISAR1_GPI_MASK (UL(0xf) << ID_AA64ISAR1_GPI_SHIFT) 359 #define ID_AA64ISAR1_GPI_VAL(x) ((x) & ID_AA64ISAR1_GPI_MASK) 360 #define ID_AA64ISAR1_GPI_NONE (UL(0x0) << ID_AA64ISAR1_GPI_SHIFT) 361 #define ID_AA64ISAR1_GPI_IMPL (UL(0x1) << ID_AA64ISAR1_GPI_SHIFT) 362 363 /* ID_AA64MMFR0_EL1 */ 364 #define ID_AA64MMFR0_EL1 MRS_REG(3, 0, 0, 7, 0) 365 #define ID_AA64MMFR0_PARange_SHIFT 0 366 #define ID_AA64MMFR0_PARange_MASK (UL(0xf) << ID_AA64MMFR0_PARange_SHIFT) 367 #define ID_AA64MMFR0_PARange_VAL(x) ((x) & ID_AA64MMFR0_PARange_MASK) 368 #define ID_AA64MMFR0_PARange_4G (UL(0x0) << ID_AA64MMFR0_PARange_SHIFT) 369 #define ID_AA64MMFR0_PARange_64G (UL(0x1) << ID_AA64MMFR0_PARange_SHIFT) 370 #define ID_AA64MMFR0_PARange_1T (UL(0x2) << ID_AA64MMFR0_PARange_SHIFT) 371 #define ID_AA64MMFR0_PARange_4T (UL(0x3) << ID_AA64MMFR0_PARange_SHIFT) 372 #define ID_AA64MMFR0_PARange_16T (UL(0x4) << ID_AA64MMFR0_PARange_SHIFT) 373 #define ID_AA64MMFR0_PARange_256T (UL(0x5) << ID_AA64MMFR0_PARange_SHIFT) 374 #define ID_AA64MMFR0_PARange_4P (UL(0x6) << ID_AA64MMFR0_PARange_SHIFT) 375 #define ID_AA64MMFR0_ASIDBits_SHIFT 4 376 #define ID_AA64MMFR0_ASIDBits_MASK (UL(0xf) << ID_AA64MMFR0_ASIDBits_SHIFT) 377 #define ID_AA64MMFR0_ASIDBits_VAL(x) ((x) & ID_AA64MMFR0_ASIDBits_MASK) 378 #define ID_AA64MMFR0_ASIDBits_8 (UL(0x0) << ID_AA64MMFR0_ASIDBits_SHIFT) 379 #define ID_AA64MMFR0_ASIDBits_16 (UL(0x2) << ID_AA64MMFR0_ASIDBits_SHIFT) 380 #define ID_AA64MMFR0_BigEnd_SHIFT 8 381 #define ID_AA64MMFR0_BigEnd_MASK (UL(0xf) << ID_AA64MMFR0_BigEnd_SHIFT) 382 #define ID_AA64MMFR0_BigEnd_VAL(x) ((x) & ID_AA64MMFR0_BigEnd_MASK) 383 #define ID_AA64MMFR0_BigEnd_FIXED (UL(0x0) << ID_AA64MMFR0_BigEnd_SHIFT) 384 #define ID_AA64MMFR0_BigEnd_MIXED (UL(0x1) << ID_AA64MMFR0_BigEnd_SHIFT) 385 #define ID_AA64MMFR0_SNSMem_SHIFT 12 386 #define ID_AA64MMFR0_SNSMem_MASK (UL(0xf) << ID_AA64MMFR0_SNSMem_SHIFT) 387 #define ID_AA64MMFR0_SNSMem_VAL(x) ((x) & ID_AA64MMFR0_SNSMem_MASK) 388 #define ID_AA64MMFR0_SNSMem_NONE (UL(0x0) << ID_AA64MMFR0_SNSMem_SHIFT) 389 #define ID_AA64MMFR0_SNSMem_DISTINCT (UL(0x1) << ID_AA64MMFR0_SNSMem_SHIFT) 390 #define ID_AA64MMFR0_BigEndEL0_SHIFT 16 391 #define ID_AA64MMFR0_BigEndEL0_MASK (UL(0xf) << ID_AA64MMFR0_BigEndEL0_SHIFT) 392 #define ID_AA64MMFR0_BigEndEL0_VAL(x) ((x) & ID_AA64MMFR0_BigEndEL0_MASK) 393 #define ID_AA64MMFR0_BigEndEL0_FIXED (UL(0x0) << ID_AA64MMFR0_BigEndEL0_SHIFT) 394 #define ID_AA64MMFR0_BigEndEL0_MIXED (UL(0x1) << ID_AA64MMFR0_BigEndEL0_SHIFT) 395 #define ID_AA64MMFR0_TGran16_SHIFT 20 396 #define ID_AA64MMFR0_TGran16_MASK (UL(0xf) << ID_AA64MMFR0_TGran16_SHIFT) 397 #define ID_AA64MMFR0_TGran16_VAL(x) ((x) & ID_AA64MMFR0_TGran16_MASK) 398 #define ID_AA64MMFR0_TGran16_NONE (UL(0x0) << ID_AA64MMFR0_TGran16_SHIFT) 399 #define ID_AA64MMFR0_TGran16_IMPL (UL(0x1) << ID_AA64MMFR0_TGran16_SHIFT) 400 #define ID_AA64MMFR0_TGran64_SHIFT 24 401 #define ID_AA64MMFR0_TGran64_MASK (UL(0xf) << ID_AA64MMFR0_TGran64_SHIFT) 402 #define ID_AA64MMFR0_TGran64_VAL(x) ((x) & ID_AA64MMFR0_TGran64_MASK) 403 #define ID_AA64MMFR0_TGran64_IMPL (UL(0x0) << ID_AA64MMFR0_TGran64_SHIFT) 404 #define ID_AA64MMFR0_TGran64_NONE (UL(0xf) << ID_AA64MMFR0_TGran64_SHIFT) 405 #define ID_AA64MMFR0_TGran4_SHIFT 28 406 #define ID_AA64MMFR0_TGran4_MASK (UL(0xf) << ID_AA64MMFR0_TGran4_SHIFT) 407 #define ID_AA64MMFR0_TGran4_VAL(x) ((x) & ID_AA64MMFR0_TGran4_MASK) 408 #define ID_AA64MMFR0_TGran4_IMPL (UL(0x0) << ID_AA64MMFR0_TGran4_SHIFT) 409 #define ID_AA64MMFR0_TGran4_NONE (UL(0xf) << ID_AA64MMFR0_TGran4_SHIFT) 410 411 /* ID_AA64MMFR1_EL1 */ 412 #define ID_AA64MMFR1_EL1 MRS_REG(3, 0, 0, 7, 1) 413 #define ID_AA64MMFR1_HAFDBS_SHIFT 0 414 #define ID_AA64MMFR1_HAFDBS_MASK (UL(0xf) << ID_AA64MMFR1_HAFDBS_SHIFT) 415 #define ID_AA64MMFR1_HAFDBS_VAL(x) ((x) & ID_AA64MMFR1_HAFDBS_MASK) 416 #define ID_AA64MMFR1_HAFDBS_NONE (UL(0x0) << ID_AA64MMFR1_HAFDBS_SHIFT) 417 #define ID_AA64MMFR1_HAFDBS_AF (UL(0x1) << ID_AA64MMFR1_HAFDBS_SHIFT) 418 #define ID_AA64MMFR1_HAFDBS_AF_DBS (UL(0x2) << ID_AA64MMFR1_HAFDBS_SHIFT) 419 #define ID_AA64MMFR1_VMIDBits_SHIFT 4 420 #define ID_AA64MMFR1_VMIDBits_MASK (UL(0xf) << ID_AA64MMFR1_VMIDBits_SHIFT) 421 #define ID_AA64MMFR1_VMIDBits_VAL(x) ((x) & ID_AA64MMFR1_VMIDBits_MASK) 422 #define ID_AA64MMFR1_VMIDBits_8 (UL(0x0) << ID_AA64MMFR1_VMIDBits_SHIFT) 423 #define ID_AA64MMFR1_VMIDBits_16 (UL(0x2) << ID_AA64MMFR1_VMIDBits_SHIFT) 424 #define ID_AA64MMFR1_VH_SHIFT 8 425 #define ID_AA64MMFR1_VH_MASK (UL(0xf) << ID_AA64MMFR1_VH_SHIFT) 426 #define ID_AA64MMFR1_VH_VAL(x) ((x) & ID_AA64MMFR1_VH_MASK) 427 #define ID_AA64MMFR1_VH_NONE (UL(0x0) << ID_AA64MMFR1_VH_SHIFT) 428 #define ID_AA64MMFR1_VH_IMPL (UL(0x1) << ID_AA64MMFR1_VH_SHIFT) 429 #define ID_AA64MMFR1_HPDS_SHIFT 12 430 #define ID_AA64MMFR1_HPDS_MASK (UL(0xf) << ID_AA64MMFR1_HPDS_SHIFT) 431 #define ID_AA64MMFR1_HPDS_VAL(x) ((x) & ID_AA64MMFR1_HPDS_MASK) 432 #define ID_AA64MMFR1_HPDS_NONE (UL(0x0) << ID_AA64MMFR1_HPDS_SHIFT) 433 #define ID_AA64MMFR1_HPDS_HPD (UL(0x1) << ID_AA64MMFR1_HPDS_SHIFT) 434 #define ID_AA64MMFR1_HPDS_TTPBHA (UL(0x2) << ID_AA64MMFR1_HPDS_SHIFT) 435 #define ID_AA64MMFR1_LO_SHIFT 16 436 #define ID_AA64MMFR1_LO_MASK (UL(0xf) << ID_AA64MMFR1_LO_SHIFT) 437 #define ID_AA64MMFR1_LO_VAL(x) ((x) & ID_AA64MMFR1_LO_MASK) 438 #define ID_AA64MMFR1_LO_NONE (UL(0x0) << ID_AA64MMFR1_LO_SHIFT) 439 #define ID_AA64MMFR1_LO_IMPL (UL(0x1) << ID_AA64MMFR1_LO_SHIFT) 440 #define ID_AA64MMFR1_PAN_SHIFT 20 441 #define ID_AA64MMFR1_PAN_MASK (UL(0xf) << ID_AA64MMFR1_PAN_SHIFT) 442 #define ID_AA64MMFR1_PAN_VAL(x) ((x) & ID_AA64MMFR1_PAN_MASK) 443 #define ID_AA64MMFR1_PAN_NONE (UL(0x0) << ID_AA64MMFR1_PAN_SHIFT) 444 #define ID_AA64MMFR1_PAN_IMPL (UL(0x1) << ID_AA64MMFR1_PAN_SHIFT) 445 #define ID_AA64MMFR1_PAN_ATS1E1 (UL(0x2) << ID_AA64MMFR1_PAN_SHIFT) 446 #define ID_AA64MMFR1_SpecSEI_SHIFT 24 447 #define ID_AA64MMFR1_SpecSEI_MASK (UL(0xf) << ID_AA64MMFR1_SpecSEI_SHIFT) 448 #define ID_AA64MMFR1_SpecSEI_VAL(x) ((x) & ID_AA64MMFR1_SpecSEI_MASK) 449 #define ID_AA64MMFR1_SpecSEI_NONE (UL(0x0) << ID_AA64MMFR1_SpecSEI_SHIFT) 450 #define ID_AA64MMFR1_SpecSEI_IMPL (UL(0x1) << ID_AA64MMFR1_SpecSEI_SHIFT) 451 #define ID_AA64MMFR1_XNX_SHIFT 28 452 #define ID_AA64MMFR1_XNX_MASK (UL(0xf) << ID_AA64MMFR1_XNX_SHIFT) 453 #define ID_AA64MMFR1_XNX_VAL(x) ((x) & ID_AA64MMFR1_XNX_MASK) 454 #define ID_AA64MMFR1_XNX_NONE (UL(0x0) << ID_AA64MMFR1_XNX_SHIFT) 455 #define ID_AA64MMFR1_XNX_IMPL (UL(0x1) << ID_AA64MMFR1_XNX_SHIFT) 456 457 /* ID_AA64MMFR2_EL1 */ 458 #define ID_AA64MMFR2_EL1 MRS_REG(3, 0, 0, 7, 2) 459 #define ID_AA64MMFR2_CnP_SHIFT 0 460 #define ID_AA64MMFR2_CnP_MASK (UL(0xf) << ID_AA64MMFR2_CnP_SHIFT) 461 #define ID_AA64MMFR2_CnP_VAL(x) ((x) & ID_AA64MMFR2_CnP_MASK) 462 #define ID_AA64MMFR2_CnP_NONE (UL(0x0) << ID_AA64MMFR2_CnP_SHIFT) 463 #define ID_AA64MMFR2_CnP_IMPL (UL(0x1) << ID_AA64MMFR2_CnP_SHIFT) 464 #define ID_AA64MMFR2_UAO_SHIFT 4 465 #define ID_AA64MMFR2_UAO_MASK (UL(0xf) << ID_AA64MMFR2_UAO_SHIFT) 466 #define ID_AA64MMFR2_UAO_VAL(x) ((x) & ID_AA64MMFR2_UAO_MASK) 467 #define ID_AA64MMFR2_UAO_NONE (UL(0x0) << ID_AA64MMFR2_UAO_SHIFT) 468 #define ID_AA64MMFR2_UAO_IMPL (UL(0x1) << ID_AA64MMFR2_UAO_SHIFT) 469 #define ID_AA64MMFR2_LSM_SHIFT 8 470 #define ID_AA64MMFR2_LSM_MASK (UL(0xf) << ID_AA64MMFR2_LSM_SHIFT) 471 #define ID_AA64MMFR2_LSM_VAL(x) ((x) & ID_AA64MMFR2_LSM_MASK) 472 #define ID_AA64MMFR2_LSM_NONE (UL(0x0) << ID_AA64MMFR2_LSM_SHIFT) 473 #define ID_AA64MMFR2_LSM_IMPL (UL(0x1) << ID_AA64MMFR2_LSM_SHIFT) 474 #define ID_AA64MMFR2_IESB_SHIFT 12 475 #define ID_AA64MMFR2_IESB_MASK (UL(0xf) << ID_AA64MMFR2_IESB_SHIFT) 476 #define ID_AA64MMFR2_IESB_VAL(x) ((x) & ID_AA64MMFR2_IESB_MASK) 477 #define ID_AA64MMFR2_IESB_NONE (UL(0x0) << ID_AA64MMFR2_IESB_SHIFT) 478 #define ID_AA64MMFR2_IESB_IMPL (UL(0x1) << ID_AA64MMFR2_IESB_SHIFT) 479 #define ID_AA64MMFR2_VARange_SHIFT 16 480 #define ID_AA64MMFR2_VARange_MASK (UL(0xf) << ID_AA64MMFR2_VARange_SHIFT) 481 #define ID_AA64MMFR2_VARange_VAL(x) ((x) & ID_AA64MMFR2_VARange_MASK) 482 #define ID_AA64MMFR2_VARange_48 (UL(0x0) << ID_AA64MMFR2_VARange_SHIFT) 483 #define ID_AA64MMFR2_VARange_52 (UL(0x1) << ID_AA64MMFR2_VARange_SHIFT) 484 #define ID_AA64MMFR2_CCIDX_SHIFT 20 485 #define ID_AA64MMFR2_CCIDX_MASK (UL(0xf) << ID_AA64MMFR2_CCIDX_SHIFT) 486 #define ID_AA64MMFR2_CCIDX_VAL(x) ((x) & ID_AA64MMFR2_CCIDX_MASK) 487 #define ID_AA64MMFR2_CCIDX_32 (UL(0x0) << ID_AA64MMFR2_CCIDX_SHIFT) 488 #define ID_AA64MMFR2_CCIDX_64 (UL(0x1) << ID_AA64MMFR2_CCIDX_SHIFT) 489 #define ID_AA64MMFR2_NV_SHIFT 24 490 #define ID_AA64MMFR2_NV_MASK (UL(0xf) << ID_AA64MMFR2_NV_SHIFT) 491 #define ID_AA64MMFR2_NV_VAL(x) ((x) & ID_AA64MMFR2_NV_MASK) 492 #define ID_AA64MMFR2_NV_NONE (UL(0x0) << ID_AA64MMFR2_NV_SHIFT) 493 #define ID_AA64MMFR2_NV_IMPL (UL(0x1) << ID_AA64MMFR2_NV_SHIFT) 494 495 /* ID_AA64PFR0_EL1 */ 496 #define ID_AA64PFR0_EL1 MRS_REG(3, 0, 0, 4, 0) 497 #define ID_AA64PFR0_EL0_SHIFT 0 498 #define ID_AA64PFR0_EL0_MASK (UL(0xf) << ID_AA64PFR0_EL0_SHIFT) 499 #define ID_AA64PFR0_EL0_VAL(x) ((x) & ID_AA64PFR0_EL0_MASK) 500 #define ID_AA64PFR0_EL0_64 (UL(0x1) << ID_AA64PFR0_EL0_SHIFT) 501 #define ID_AA64PFR0_EL0_64_32 (UL(0x2) << ID_AA64PFR0_EL0_SHIFT) 502 #define ID_AA64PFR0_EL1_SHIFT 4 503 #define ID_AA64PFR0_EL1_MASK (UL(0xf) << ID_AA64PFR0_EL1_SHIFT) 504 #define ID_AA64PFR0_EL1_VAL(x) ((x) & ID_AA64PFR0_EL1_MASK) 505 #define ID_AA64PFR0_EL1_64 (UL(0x1) << ID_AA64PFR0_EL1_SHIFT) 506 #define ID_AA64PFR0_EL1_64_32 (UL(0x2) << ID_AA64PFR0_EL1_SHIFT) 507 #define ID_AA64PFR0_EL2_SHIFT 8 508 #define ID_AA64PFR0_EL2_MASK (UL(0xf) << ID_AA64PFR0_EL2_SHIFT) 509 #define ID_AA64PFR0_EL2_VAL(x) ((x) & ID_AA64PFR0_EL2_MASK) 510 #define ID_AA64PFR0_EL2_NONE (UL(0x0) << ID_AA64PFR0_EL2_SHIFT) 511 #define ID_AA64PFR0_EL2_64 (UL(0x1) << ID_AA64PFR0_EL2_SHIFT) 512 #define ID_AA64PFR0_EL2_64_32 (UL(0x2) << ID_AA64PFR0_EL2_SHIFT) 513 #define ID_AA64PFR0_EL3_SHIFT 12 514 #define ID_AA64PFR0_EL3_MASK (UL(0xf) << ID_AA64PFR0_EL3_SHIFT) 515 #define ID_AA64PFR0_EL3_VAL(x) ((x) & ID_AA64PFR0_EL3_MASK) 516 #define ID_AA64PFR0_EL3_NONE (UL(0x0) << ID_AA64PFR0_EL3_SHIFT) 517 #define ID_AA64PFR0_EL3_64 (UL(0x1) << ID_AA64PFR0_EL3_SHIFT) 518 #define ID_AA64PFR0_EL3_64_32 (UL(0x2) << ID_AA64PFR0_EL3_SHIFT) 519 #define ID_AA64PFR0_FP_SHIFT 16 520 #define ID_AA64PFR0_FP_MASK (UL(0xf) << ID_AA64PFR0_FP_SHIFT) 521 #define ID_AA64PFR0_FP_VAL(x) ((x) & ID_AA64PFR0_FP_MASK) 522 #define ID_AA64PFR0_FP_IMPL (UL(0x0) << ID_AA64PFR0_FP_SHIFT) 523 #define ID_AA64PFR0_FP_HP (UL(0x1) << ID_AA64PFR0_FP_SHIFT) 524 #define ID_AA64PFR0_FP_NONE (UL(0xf) << ID_AA64PFR0_FP_SHIFT) 525 #define ID_AA64PFR0_AdvSIMD_SHIFT 20 526 #define ID_AA64PFR0_AdvSIMD_MASK (UL(0xf) << ID_AA64PFR0_AdvSIMD_SHIFT) 527 #define ID_AA64PFR0_AdvSIMD_VAL(x) ((x) & ID_AA64PFR0_AdvSIMD_MASK) 528 #define ID_AA64PFR0_AdvSIMD_IMPL (UL(0x0) << ID_AA64PFR0_AdvSIMD_SHIFT) 529 #define ID_AA64PFR0_AdvSIMD_HP (UL(0x1) << ID_AA64PFR0_AdvSIMD_SHIFT) 530 #define ID_AA64PFR0_AdvSIMD_NONE (UL(0xf) << ID_AA64PFR0_AdvSIMD_SHIFT) 531 #define ID_AA64PFR0_GIC_BITS 0x4 /* Number of bits in GIC field */ 532 #define ID_AA64PFR0_GIC_SHIFT 24 533 #define ID_AA64PFR0_GIC_MASK (UL(0xf) << ID_AA64PFR0_GIC_SHIFT) 534 #define ID_AA64PFR0_GIC_VAL(x) ((x) & ID_AA64PFR0_GIC_MASK) 535 #define ID_AA64PFR0_GIC_CPUIF_NONE (UL(0x0) << ID_AA64PFR0_GIC_SHIFT) 536 #define ID_AA64PFR0_GIC_CPUIF_EN (UL(0x1) << ID_AA64PFR0_GIC_SHIFT) 537 #define ID_AA64PFR0_RAS_SHIFT 28 538 #define ID_AA64PFR0_RAS_MASK (UL(0xf) << ID_AA64PFR0_RAS_SHIFT) 539 #define ID_AA64PFR0_RAS_VAL(x) ((x) & ID_AA64PFR0_RAS_MASK) 540 #define ID_AA64PFR0_RAS_NONE (UL(0x0) << ID_AA64PFR0_RAS_SHIFT) 541 #define ID_AA64PFR0_RAS_V1 (UL(0x1) << ID_AA64PFR0_RAS_SHIFT) 542 #define ID_AA64PFR0_SVE_SHIFT 32 543 #define ID_AA64PFR0_SVE_MASK (UL(0xf) << ID_AA64PFR0_SVE_SHIFT) 544 #define ID_AA64PFR0_SVE_VAL(x) ((x) & ID_AA64PFR0_SVE_MASK) 545 #define ID_AA64PFR0_SVE_NONE (UL(0x0) << ID_AA64PFR0_SVE_SHIFT) 546 #define ID_AA64PFR0_SVE_IMPL (UL(0x1) << ID_AA64PFR0_SVE_SHIFT) 547 #define ID_AA64PFR0_SEL2_SHIFT 36 548 #define ID_AA64PFR0_SEL2_MASK (UL(0xf) << ID_AA64PFR0_SEL2_SHIFT) 549 #define ID_AA64PFR0_SEL2_VAL(x) ((x) & ID_AA64PFR0_SEL2_MASK) 550 #define ID_AA64PFR0_SEL2_NONE (UL(0x0) << ID_AA64PFR0_SEL2_SHIFT) 551 #define ID_AA64PFR0_SEL2_IMPL (UL(0x1) << ID_AA64PFR0_SEL2_SHIFT) 552 #define ID_AA64PFR0_MPAM_SHIFT 40 553 #define ID_AA64PFR0_MPAM_MASK (UL(0xf) << ID_AA64PFR0_MPAM_SHIFT) 554 #define ID_AA64PFR0_MPAM_VAL(x) ((x) & ID_AA64PFR0_MPAM_MASK) 555 #define ID_AA64PFR0_MPAM_NONE (UL(0x0) << ID_AA64PFR0_MPAM_SHIFT) 556 #define ID_AA64PFR0_MPAM_IMPL (UL(0x1) << ID_AA64PFR0_MPAM_SHIFT) 557 #define ID_AA64PFR0_AMU_SHIFT 44 558 #define ID_AA64PFR0_AMU_MASK (UL(0xf) << ID_AA64PFR0_AMU_SHIFT) 559 #define ID_AA64PFR0_AMU_VAL(x) ((x) & ID_AA64PFR0_AMU_MASK) 560 #define ID_AA64PFR0_AMU_NONE (UL(0x0) << ID_AA64PFR0_AMU_SHIFT) 561 #define ID_AA64PFR0_AMU_V1 (UL(0x1) << ID_AA64PFR0_AMU_SHIFT) 562 #define ID_AA64PFR0_DIT_SHIFT 48 563 #define ID_AA64PFR0_DIT_MASK (UL(0xf) << ID_AA64PFR0_DIT_SHIFT) 564 #define ID_AA64PFR0_DIT_VAL(x) ((x) & ID_AA64PFR0_DIT_MASK) 565 #define ID_AA64PFR0_DIT_NONE (UL(0x0) << ID_AA64PFR0_DIT_SHIFT) 566 #define ID_AA64PFR0_DIT_PSTATE (UL(0x1) << ID_AA64PFR0_DIT_SHIFT) 567 #define ID_AA64PFR0_CSV2_SHIFT 56 568 #define ID_AA64PFR0_CSV2_MASK (UL(0xf) << ID_AA64PFR0_CSV2_SHIFT) 569 #define ID_AA64PFR0_CSV2_VAL(x) ((x) & ID_AA64PFR0_CSV2_MASK) 570 #define ID_AA64PFR0_CSV2_NONE (UL(0x0) << ID_AA64PFR0_CSV2_SHIFT) 571 #define ID_AA64PFR0_CSV2_ISOLATED (UL(0x1) << ID_AA64PFR0_CSV2_SHIFT) 572 #define ID_AA64PFR0_CSV2_SCXTNUM (UL(0x2) << ID_AA64PFR0_CSV2_SHIFT) 573 #define ID_AA64PFR0_CSV3_SHIFT 60 574 #define ID_AA64PFR0_CSV3_MASK (UL(0xf) << ID_AA64PFR0_CSV3_SHIFT) 575 #define ID_AA64PFR0_CSV3_VAL(x) ((x) & ID_AA64PFR0_CSV3_MASK) 576 #define ID_AA64PFR0_CSV3_NONE (UL(0x0) << ID_AA64PFR0_CSV3_SHIFT) 577 #define ID_AA64PFR0_CSV3_ISOLATED (UL(0x1) << ID_AA64PFR0_CSV3_SHIFT) 578 579 /* ID_AA64PFR1_EL1 */ 580 #define ID_AA64PFR1_EL1 MRS_REG(3, 0, 0, 4, 1) 581 #define ID_AA64PFR1_BT_SHIFT 0 582 #define ID_AA64PFR1_BT_MASK (UL(0xf) << ID_AA64PFR1_BT_SHIFT) 583 #define ID_AA64PFR1_BT_VAL(x) ((x) & ID_AA64PFR1_BT_MASK) 584 #define ID_AA64PFR1_BT_NONE (UL(0x0) << ID_AA64PFR1_BT_SHIFT) 585 #define ID_AA64PFR1_BT_IMPL (UL(0x1) << ID_AA64PFR1_BT_SHIFT) 586 #define ID_AA64PFR1_SSBS_SHIFT 4 587 #define ID_AA64PFR1_SSBS_MASK (UL(0xf) << ID_AA64PFR1_SSBS_SHIFT) 588 #define ID_AA64PFR1_SSBS_VAL(x) ((x) & ID_AA64PFR1_SSBS_MASK) 589 #define ID_AA64PFR1_SSBS_NONE (UL(0x0) << ID_AA64PFR1_SSBS_SHIFT) 590 #define ID_AA64PFR1_SSBS_PSTATE (UL(0x1) << ID_AA64PFR1_SSBS_SHIFT) 591 #define ID_AA64PFR1_SSBS_PSTATE_MSR (UL(0x2) << ID_AA64PFR1_SSBS_SHIFT) 592 #define ID_AA64PFR1_MTE_SHIFT 8 593 #define ID_AA64PFR1_MTE_MASK (UL(0xf) << ID_AA64PFR1_MTE_SHIFT) 594 #define ID_AA64PFR1_MTE_VAL(x) ((x) & ID_AA64PFR1_MTE_MASK) 595 #define ID_AA64PFR1_MTE_NONE (UL(0x0) << ID_AA64PFR1_MTE_SHIFT) 596 #define ID_AA64PFR1_MTE_IMPL_EL0 (UL(0x1) << ID_AA64PFR1_MTE_SHIFT) 597 #define ID_AA64PFR1_MTE_IMPL (UL(0x2) << ID_AA64PFR1_MTE_SHIFT) 598 #define ID_AA64PFR1_RAS_frac_SHIFT 12 599 #define ID_AA64PFR1_RAS_frac_MASK (UL(0xf) << ID_AA64PFR1_RAS_frac_SHIFT) 600 #define ID_AA64PFR1_RAS_frac_VAL(x) ((x) & ID_AA64PFR1_RAS_frac_MASK) 601 #define ID_AA64PFR1_RAS_frac_V1 (UL(0x0) << ID_AA64PFR1_RAS_frac_SHIFT) 602 #define ID_AA64PFR1_RAS_frac_V2 (UL(0x1) << ID_AA64PFR1_RAS_frac_SHIFT) 603 604 /* MAIR_EL1 - Memory Attribute Indirection Register */ 605 #define MAIR_ATTR_MASK(idx) (0xff << ((n)* 8)) 606 #define MAIR_ATTR(attr, idx) ((attr) << ((idx) * 8)) 607 #define MAIR_DEVICE_nGnRnE 0x00 608 #define MAIR_NORMAL_NC 0x44 609 #define MAIR_NORMAL_WT 0xbb 610 #define MAIR_NORMAL_WB 0xff 611 612 /* PAR_EL1 - Physical Address Register */ 613 #define PAR_F_SHIFT 0 614 #define PAR_F (0x1 << PAR_F_SHIFT) 615 #define PAR_SUCCESS(x) (((x) & PAR_F) == 0) 616 /* When PAR_F == 0 (success) */ 617 #define PAR_SH_SHIFT 7 618 #define PAR_SH_MASK (0x3 << PAR_SH_SHIFT) 619 #define PAR_NS_SHIFT 9 620 #define PAR_NS_MASK (0x3 << PAR_NS_SHIFT) 621 #define PAR_PA_SHIFT 12 622 #define PAR_PA_MASK 0x0000fffffffff000 623 #define PAR_ATTR_SHIFT 56 624 #define PAR_ATTR_MASK (0xff << PAR_ATTR_SHIFT) 625 /* When PAR_F == 1 (aborted) */ 626 #define PAR_FST_SHIFT 1 627 #define PAR_FST_MASK (0x3f << PAR_FST_SHIFT) 628 #define PAR_PTW_SHIFT 8 629 #define PAR_PTW_MASK (0x1 << PAR_PTW_SHIFT) 630 #define PAR_S_SHIFT 9 631 #define PAR_S_MASK (0x1 << PAR_S_SHIFT) 632 633 /* SCTLR_EL1 - System Control Register */ 634 #define SCTLR_RES0 0xc8222440 /* Reserved ARMv8.0, write 0 */ 635 #define SCTLR_RES1 0x30d00800 /* Reserved ARMv8.0, write 1 */ 636 637 #define SCTLR_M 0x00000001 638 #define SCTLR_A 0x00000002 639 #define SCTLR_C 0x00000004 640 #define SCTLR_SA 0x00000008 641 #define SCTLR_SA0 0x00000010 642 #define SCTLR_CP15BEN 0x00000020 643 /* Bit 6 is reserved */ 644 #define SCTLR_ITD 0x00000080 645 #define SCTLR_SED 0x00000100 646 #define SCTLR_UMA 0x00000200 647 /* Bit 10 is reserved */ 648 /* Bit 11 is reserved */ 649 #define SCTLR_I 0x00001000 650 #define SCTLR_EnDB 0x00002000 /* ARMv8.3 */ 651 #define SCTLR_DZE 0x00004000 652 #define SCTLR_UCT 0x00008000 653 #define SCTLR_nTWI 0x00010000 654 /* Bit 17 is reserved */ 655 #define SCTLR_nTWE 0x00040000 656 #define SCTLR_WXN 0x00080000 657 /* Bit 20 is reserved */ 658 #define SCTLR_IESB 0x00200000 /* ARMv8.2 */ 659 /* Bit 22 is reserved */ 660 #define SCTLR_SPAN 0x00800000 /* ARMv8.1 */ 661 #define SCTLR_EOE 0x01000000 662 #define SCTLR_EE 0x02000000 663 #define SCTLR_UCI 0x04000000 664 #define SCTLR_EnDA 0x08000000 /* ARMv8.3 */ 665 #define SCTLR_nTLSMD 0x10000000 /* ARMv8.2 */ 666 #define SCTLR_LSMAOE 0x20000000 /* ARMv8.2 */ 667 #define SCTLR_EnIB 0x40000000 /* ARMv8.3 */ 668 #define SCTLR_EnIA 0x80000000 /* ARMv8.3 */ 669 670 /* SPSR_EL1 */ 671 /* 672 * When the exception is taken in AArch64: 673 * M[3:2] is the exception level 674 * M[1] is unused 675 * M[0] is the SP select: 676 * 0: always SP0 677 * 1: current ELs SP 678 */ 679 #define PSR_M_EL0t 0x00000000 680 #define PSR_M_EL1t 0x00000004 681 #define PSR_M_EL1h 0x00000005 682 #define PSR_M_EL2t 0x00000008 683 #define PSR_M_EL2h 0x00000009 684 #define PSR_M_64 0x00000000 685 #define PSR_M_32 0x00000010 686 #define PSR_M_MASK 0x0000000f 687 688 #define PSR_T 0x00000020 689 690 #define PSR_AARCH32 0x00000010 691 #define PSR_F 0x00000040 692 #define PSR_I 0x00000080 693 #define PSR_A 0x00000100 694 #define PSR_D 0x00000200 695 #define PSR_DAIF (PSR_D | PSR_A | PSR_I | PSR_F) 696 #define PSR_IL 0x00100000 697 #define PSR_SS 0x00200000 698 #define PSR_V 0x10000000 699 #define PSR_C 0x20000000 700 #define PSR_Z 0x40000000 701 #define PSR_N 0x80000000 702 #define PSR_FLAGS 0xf0000000 703 704 /* TCR_EL1 - Translation Control Register */ 705 #define TCR_HD_SHIFT 40 706 #define TCR_HD (0x1UL << TCR_HD_SHIFT) 707 #define TCR_HA_SHIFT 39 708 #define TCR_HA (0x1UL << TCR_HA_SHIFT) 709 710 #define TCR_ASID_SHIFT 36 711 #define TCR_ASID_WIDTH 1 712 #define TCR_ASID_16 (0x1UL << TCR_ASID_SHIFT) 713 714 #define TCR_IPS_SHIFT 32 715 #define TCR_IPS_WIDTH 3 716 #define TCR_IPS_32BIT (0 << TCR_IPS_SHIFT) 717 #define TCR_IPS_36BIT (1 << TCR_IPS_SHIFT) 718 #define TCR_IPS_40BIT (2 << TCR_IPS_SHIFT) 719 #define TCR_IPS_42BIT (3 << TCR_IPS_SHIFT) 720 #define TCR_IPS_44BIT (4 << TCR_IPS_SHIFT) 721 #define TCR_IPS_48BIT (5 << TCR_IPS_SHIFT) 722 723 #define TCR_TG1_SHIFT 30 724 #define TCR_TG1_16K (1 << TCR_TG1_SHIFT) 725 #define TCR_TG1_4K (2 << TCR_TG1_SHIFT) 726 #define TCR_TG1_64K (3 << TCR_TG1_SHIFT) 727 728 #define TCR_SH1_SHIFT 28 729 #define TCR_SH1_IS (0x3UL << TCR_SH1_SHIFT) 730 #define TCR_ORGN1_SHIFT 26 731 #define TCR_ORGN1_WBWA (0x1UL << TCR_ORGN1_SHIFT) 732 #define TCR_IRGN1_SHIFT 24 733 #define TCR_IRGN1_WBWA (0x1UL << TCR_IRGN1_SHIFT) 734 #define TCR_A1_SHIFT 22 735 #define TCR_A1 (0x1UL << TCR_A1_SHIFT) 736 #define TCR_SH0_SHIFT 12 737 #define TCR_SH0_IS (0x3UL << TCR_SH0_SHIFT) 738 #define TCR_ORGN0_SHIFT 10 739 #define TCR_ORGN0_WBWA (0x1UL << TCR_ORGN0_SHIFT) 740 #define TCR_IRGN0_SHIFT 8 741 #define TCR_IRGN0_WBWA (0x1UL << TCR_IRGN0_SHIFT) 742 743 #define TCR_CACHE_ATTRS ((TCR_IRGN0_WBWA | TCR_IRGN1_WBWA) |\ 744 (TCR_ORGN0_WBWA | TCR_ORGN1_WBWA)) 745 746 #ifdef SMP 747 #define TCR_SMP_ATTRS (TCR_SH0_IS | TCR_SH1_IS) 748 #else 749 #define TCR_SMP_ATTRS 0 750 #endif 751 752 #define TCR_T1SZ_SHIFT 16 753 #define TCR_T0SZ_SHIFT 0 754 #define TCR_T1SZ(x) ((x) << TCR_T1SZ_SHIFT) 755 #define TCR_T0SZ(x) ((x) << TCR_T0SZ_SHIFT) 756 #define TCR_TxSZ(x) (TCR_T1SZ(x) | TCR_T0SZ(x)) 757 758 /* Saved Program Status Register */ 759 #define DBG_SPSR_SS (0x1 << 21) 760 761 /* Monitor Debug System Control Register */ 762 #define DBG_MDSCR_SS (0x1 << 0) 763 #define DBG_MDSCR_KDE (0x1 << 13) 764 #define DBG_MDSCR_MDE (0x1 << 15) 765 766 /* Perfomance Monitoring Counters */ 767 #define PMCR_E (1 << 0) /* Enable all counters */ 768 #define PMCR_P (1 << 1) /* Reset all counters */ 769 #define PMCR_C (1 << 2) /* Clock counter reset */ 770 #define PMCR_D (1 << 3) /* CNTR counts every 64 clk cycles */ 771 #define PMCR_X (1 << 4) /* Export to ext. monitoring (ETM) */ 772 #define PMCR_DP (1 << 5) /* Disable CCNT if non-invasive debug*/ 773 #define PMCR_LC (1 << 6) /* Long cycle count enable */ 774 #define PMCR_IMP_SHIFT 24 /* Implementer code */ 775 #define PMCR_IMP_MASK (0xff << PMCR_IMP_SHIFT) 776 #define PMCR_IDCODE_SHIFT 16 /* Identification code */ 777 #define PMCR_IDCODE_MASK (0xff << PMCR_IDCODE_SHIFT) 778 #define PMCR_IDCODE_CORTEX_A57 0x01 779 #define PMCR_IDCODE_CORTEX_A72 0x02 780 #define PMCR_IDCODE_CORTEX_A53 0x03 781 #define PMCR_N_SHIFT 11 /* Number of counters implemented */ 782 #define PMCR_N_MASK (0x1f << PMCR_N_SHIFT) 783 784 #endif /* !_MACHINE_ARMREG_H_ */ 785