1 /*- 2 * Copyright (c) 2013, 2014 Andrew Turner 3 * Copyright (c) 2015 The FreeBSD Foundation 4 * All rights reserved. 5 * 6 * This software was developed by Andrew Turner under 7 * sponsorship from the FreeBSD Foundation. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * $FreeBSD$ 31 */ 32 33 #ifndef _MACHINE_ARMREG_H_ 34 #define _MACHINE_ARMREG_H_ 35 36 #define INSN_SIZE 4 37 38 #define READ_SPECIALREG(reg) \ 39 ({ uint64_t val; \ 40 __asm __volatile("mrs %0, " __STRING(reg) : "=&r" (val)); \ 41 val; \ 42 }) 43 #define WRITE_SPECIALREG(reg, val) \ 44 __asm __volatile("msr " __STRING(reg) ", %0" : : "r"((uint64_t)val)) 45 46 /* CNTHCTL_EL2 - Counter-timer Hypervisor Control register */ 47 #define CNTHCTL_EVNTI_MASK (0xf << 4) /* Bit to trigger event stream */ 48 #define CNTHCTL_EVNTDIR (1 << 3) /* Control transition trigger bit */ 49 #define CNTHCTL_EVNTEN (1 << 2) /* Enable event stream */ 50 #define CNTHCTL_EL1PCEN (1 << 1) /* Allow EL0/1 physical timer access */ 51 #define CNTHCTL_EL1PCTEN (1 << 0) /*Allow EL0/1 physical counter access*/ 52 53 /* CPACR_EL1 */ 54 #define CPACR_FPEN_MASK (0x3 << 20) 55 #define CPACR_FPEN_TRAP_ALL1 (0x0 << 20) /* Traps from EL0 and EL1 */ 56 #define CPACR_FPEN_TRAP_EL0 (0x1 << 20) /* Traps from EL0 */ 57 #define CPACR_FPEN_TRAP_ALL2 (0x2 << 20) /* Traps from EL0 and EL1 */ 58 #define CPACR_FPEN_TRAP_NONE (0x3 << 20) /* No traps */ 59 #define CPACR_TTA (0x1 << 28) 60 61 /* CTR_EL0 - Cache Type Register */ 62 #define CTR_DLINE_SHIFT 16 63 #define CTR_DLINE_MASK (0xf << CTR_DLINE_SHIFT) 64 #define CTR_DLINE_SIZE(reg) (((reg) & CTR_DLINE_MASK) >> CTR_DLINE_SHIFT) 65 #define CTR_ILINE_SHIFT 0 66 #define CTR_ILINE_MASK (0xf << CTR_ILINE_SHIFT) 67 #define CTR_ILINE_SIZE(reg) (((reg) & CTR_ILINE_MASK) >> CTR_ILINE_SHIFT) 68 69 /* DCZID_EL0 - Data Cache Zero ID register */ 70 #define DCZID_DZP (1 << 4) /* DC ZVA prohibited if non-0 */ 71 #define DCZID_BS_SHIFT 0 72 #define DCZID_BS_MASK (0xf << DCZID_BS_SHIFT) 73 #define DCZID_BS_SIZE(reg) (((reg) & DCZID_BS_MASK) >> DCZID_BS_SHIFT) 74 75 /* ESR_ELx */ 76 #define ESR_ELx_ISS_MASK 0x00ffffff 77 #define ISS_INSN_FnV (0x01 << 10) 78 #define ISS_INSN_EA (0x01 << 9) 79 #define ISS_INSN_S1PTW (0x01 << 7) 80 #define ISS_INSN_IFSC_MASK (0x1f << 0) 81 #define ISS_DATA_ISV (0x01 << 24) 82 #define ISS_DATA_SAS_MASK (0x03 << 22) 83 #define ISS_DATA_SSE (0x01 << 21) 84 #define ISS_DATA_SRT_MASK (0x1f << 16) 85 #define ISS_DATA_SF (0x01 << 15) 86 #define ISS_DATA_AR (0x01 << 14) 87 #define ISS_DATA_FnV (0x01 << 10) 88 #define ISS_DATa_EA (0x01 << 9) 89 #define ISS_DATa_CM (0x01 << 8) 90 #define ISS_INSN_S1PTW (0x01 << 7) 91 #define ISS_DATa_WnR (0x01 << 6) 92 #define ISS_DATA_DFSC_MASK (0x3f << 0) 93 #define ISS_DATA_DFSC_ASF_L0 (0x00 << 0) 94 #define ISS_DATA_DFSC_ASF_L1 (0x01 << 0) 95 #define ISS_DATA_DFSC_ASF_L2 (0x02 << 0) 96 #define ISS_DATA_DFSC_ASF_L3 (0x03 << 0) 97 #define ISS_DATA_DFSC_TF_L0 (0x04 << 0) 98 #define ISS_DATA_DFSC_TF_L1 (0x05 << 0) 99 #define ISS_DATA_DFSC_TF_L2 (0x06 << 0) 100 #define ISS_DATA_DFSC_TF_L3 (0x07 << 0) 101 #define ISS_DATA_DFSC_AFF_L1 (0x09 << 0) 102 #define ISS_DATA_DFSC_AFF_L2 (0x0a << 0) 103 #define ISS_DATA_DFSC_AFF_L3 (0x0b << 0) 104 #define ISS_DATA_DFSC_PF_L1 (0x0d << 0) 105 #define ISS_DATA_DFSC_PF_L2 (0x0e << 0) 106 #define ISS_DATA_DFSC_PF_L3 (0x0f << 0) 107 #define ISS_DATA_DFSC_EXT (0x10 << 0) 108 #define ISS_DATA_DFSC_EXT_L0 (0x14 << 0) 109 #define ISS_DATA_DFSC_EXT_L1 (0x15 << 0) 110 #define ISS_DATA_DFSC_EXT_L2 (0x16 << 0) 111 #define ISS_DATA_DFSC_EXT_L3 (0x17 << 0) 112 #define ISS_DATA_DFSC_ECC (0x18 << 0) 113 #define ISS_DATA_DFSC_ECC_L0 (0x1c << 0) 114 #define ISS_DATA_DFSC_ECC_L1 (0x1d << 0) 115 #define ISS_DATA_DFSC_ECC_L2 (0x1e << 0) 116 #define ISS_DATA_DFSC_ECC_L3 (0x1f << 0) 117 #define ISS_DATA_DFSC_ALIGN (0x21 << 0) 118 #define ISS_DATA_DFSC_TLB_CONFLICT (0x30 << 0) 119 #define ESR_ELx_IL (0x01 << 25) 120 #define ESR_ELx_EC_SHIFT 26 121 #define ESR_ELx_EC_MASK (0x3f << 26) 122 #define ESR_ELx_EXCEPTION(esr) (((esr) & ESR_ELx_EC_MASK) >> ESR_ELx_EC_SHIFT) 123 #define EXCP_UNKNOWN 0x00 /* Unkwn exception */ 124 #define EXCP_FP_SIMD 0x07 /* VFP/SIMD trap */ 125 #define EXCP_ILL_STATE 0x0e /* Illegal execution state */ 126 #define EXCP_SVC 0x15 /* SVC trap */ 127 #define EXCP_MSR 0x18 /* MSR/MRS trap */ 128 #define EXCP_INSN_ABORT_L 0x20 /* Instruction abort, from lower EL */ 129 #define EXCP_INSN_ABORT 0x21 /* Instruction abort, from same EL */ 130 #define EXCP_PC_ALIGN 0x22 /* PC alignment fault */ 131 #define EXCP_DATA_ABORT_L 0x24 /* Data abort, from lower EL */ 132 #define EXCP_DATA_ABORT 0x25 /* Data abort, from same EL */ 133 #define EXCP_SP_ALIGN 0x26 /* SP slignment fault */ 134 #define EXCP_TRAP_FP 0x2c /* Trapped FP exception */ 135 #define EXCP_SERROR 0x2f /* SError interrupt */ 136 #define EXCP_SOFTSTP_EL0 0x32 /* Software Step, from lower EL */ 137 #define EXCP_SOFTSTP_EL1 0x33 /* Software Step, from same EL */ 138 #define EXCP_WATCHPT_EL1 0x35 /* Watchpoint, from same EL */ 139 #define EXCP_BRK 0x3c /* Breakpoint */ 140 141 /* ICC_CTLR_EL1 */ 142 #define ICC_CTLR_EL1_EOIMODE (1U << 1) 143 144 /* ICC_IAR1_EL1 */ 145 #define ICC_IAR1_EL1_SPUR (0x03ff) 146 147 /* ICC_IGRPEN0_EL1 */ 148 #define ICC_IGRPEN0_EL1_EN (1U << 0) 149 150 /* ICC_PMR_EL1 */ 151 #define ICC_PMR_EL1_PRIO_MASK (0xFFUL) 152 153 /* ICC_SGI1R_EL1 */ 154 #define ICC_SGI1R_EL1_TL_MASK 0xffffUL 155 #define ICC_SGI1R_EL1_AFF1_SHIFT 16 156 #define ICC_SGI1R_EL1_SGIID_SHIFT 24 157 #define ICC_SGI1R_EL1_AFF2_SHIFT 32 158 #define ICC_SGI1R_EL1_AFF3_SHIFT 48 159 #define ICC_SGI1R_EL1_SGIID_MASK 0xfUL 160 #define ICC_SGI1R_EL1_IRM (0x1UL << 40) 161 162 /* ICC_SRE_EL1 */ 163 #define ICC_SRE_EL1_SRE (1U << 0) 164 165 /* ICC_SRE_EL2 */ 166 #define ICC_SRE_EL2_SRE (1U << 0) 167 #define ICC_SRE_EL2_EN (1U << 3) 168 169 /* ID_AA64DFR0_EL1 */ 170 #define ID_AA64DFR0_MASK 0xf0f0ffff 171 #define ID_AA64DFR0_DEBUG_VER_SHIFT 0 172 #define ID_AA64DFR0_DEBUG_VER_MASK (0xf << ID_AA64DFR0_DEBUG_VER_SHIFT) 173 #define ID_AA64DFR0_DEBUG_VER(x) ((x) & ID_AA64DFR0_DEBUG_VER_MASK) 174 #define ID_AA64DFR0_DEBUG_VER_8 (0x6 << ID_AA64DFR0_DEBUG_VER_SHIFT) 175 #define ID_AA64DFR0_DEBUG_VER_8_VHE (0x7 << ID_AA64DFR0_DEBUG_VER_SHIFT) 176 #define ID_AA64DFR0_TRACE_VER_SHIFT 4 177 #define ID_AA64DFR0_TRACE_VER_MASK (0xf << ID_AA64DFR0_TRACE_VER_SHIFT) 178 #define ID_AA64DFR0_TRACE_VER(x) ((x) & ID_AA64DFR0_TRACE_VER_MASK) 179 #define ID_AA64DFR0_TRACE_VER_NONE (0x0 << ID_AA64DFR0_TRACE_VER_SHIFT) 180 #define ID_AA64DFR0_TRACE_VER_IMPL (0x1 << ID_AA64DFR0_TRACE_VER_SHIFT) 181 #define ID_AA64DFR0_PMU_VER_SHIFT 8 182 #define ID_AA64DFR0_PMU_VER_MASK (0xf << ID_AA64DFR0_PMU_VER_SHIFT) 183 #define ID_AA64DFR0_PMU_VER(x) ((x) & ID_AA64DFR0_PMU_VER_MASK) 184 #define ID_AA64DFR0_PMU_VER_NONE (0x0 << ID_AA64DFR0_PMU_VER_SHIFT) 185 #define ID_AA64DFR0_PMU_VER_3 (0x1 << ID_AA64DFR0_PMU_VER_SHIFT) 186 #define ID_AA64DFR0_PMU_VER_3_1 (0x4 << ID_AA64DFR0_PMU_VER_SHIFT) 187 #define ID_AA64DFR0_PMU_VER_IMPL (0xf << ID_AA64DFR0_PMU_VER_SHIFT) 188 #define ID_AA64DFR0_BRPS_SHIFT 12 189 #define ID_AA64DFR0_BRPS_MASK (0xf << ID_AA64DFR0_BRPS_SHIFT) 190 #define ID_AA64DFR0_BRPS(x) \ 191 ((((x) >> ID_AA64DFR0_BRPS_SHIFT) & 0xf) + 1) 192 #define ID_AA64DFR0_WRPS_SHIFT 20 193 #define ID_AA64DFR0_WRPS_MASK (0xf << ID_AA64DFR0_WRPS_SHIFT) 194 #define ID_AA64DFR0_WRPS(x) \ 195 ((((x) >> ID_AA64DFR0_WRPS_SHIFT) & 0xf) + 1) 196 #define ID_AA64DFR0_CTX_CMPS_SHIFT 28 197 #define ID_AA64DFR0_CTX_CMPS_MASK (0xf << ID_AA64DFR0_CTX_CMPS_SHIFT) 198 #define ID_AA64DFR0_CTX_CMPS(x) \ 199 ((((x) >> ID_AA64DFR0_CTX_CMPS_SHIFT) & 0xf) + 1) 200 201 /* ID_AA64ISAR0_EL1 */ 202 #define ID_AA64ISAR0_MASK 0xf0fffff0 203 #define ID_AA64ISAR0_AES_SHIFT 4 204 #define ID_AA64ISAR0_AES_MASK (0xf << ID_AA64ISAR0_AES_SHIFT) 205 #define ID_AA64ISAR0_AES(x) ((x) & ID_AA64ISAR0_AES_MASK) 206 #define ID_AA64ISAR0_AES_NONE (0x0 << ID_AA64ISAR0_AES_SHIFT) 207 #define ID_AA64ISAR0_AES_BASE (0x1 << ID_AA64ISAR0_AES_SHIFT) 208 #define ID_AA64ISAR0_AES_PMULL (0x2 << ID_AA64ISAR0_AES_SHIFT) 209 #define ID_AA64ISAR0_SHA1_SHIFT 8 210 #define ID_AA64ISAR0_SHA1_MASK (0xf << ID_AA64ISAR0_SHA1_SHIFT) 211 #define ID_AA64ISAR0_SHA1(x) ((x) & ID_AA64ISAR0_SHA1_MASK) 212 #define ID_AA64ISAR0_SHA1_NONE (0x0 << ID_AA64ISAR0_SHA1_SHIFT) 213 #define ID_AA64ISAR0_SHA1_BASE (0x1 << ID_AA64ISAR0_SHA1_SHIFT) 214 #define ID_AA64ISAR0_SHA2_SHIFT 12 215 #define ID_AA64ISAR0_SHA2_MASK (0xf << ID_AA64ISAR0_SHA2_SHIFT) 216 #define ID_AA64ISAR0_SHA2(x) ((x) & ID_AA64ISAR0_SHA2_MASK) 217 #define ID_AA64ISAR0_SHA2_NONE (0x0 << ID_AA64ISAR0_SHA2_SHIFT) 218 #define ID_AA64ISAR0_SHA2_BASE (0x1 << ID_AA64ISAR0_SHA2_SHIFT) 219 #define ID_AA64ISAR0_CRC32_SHIFT 16 220 #define ID_AA64ISAR0_CRC32_MASK (0xf << ID_AA64ISAR0_CRC32_SHIFT) 221 #define ID_AA64ISAR0_CRC32(x) ((x) & ID_AA64ISAR0_CRC32_MASK) 222 #define ID_AA64ISAR0_CRC32_NONE (0x0 << ID_AA64ISAR0_CRC32_SHIFT) 223 #define ID_AA64ISAR0_CRC32_BASE (0x1 << ID_AA64ISAR0_CRC32_SHIFT) 224 #define ID_AA64ISAR0_ATOMIC_SHIFT 20 225 #define ID_AA64ISAR0_ATOMIC_MASK (0xf << ID_AA64ISAR0_ATOMIC_SHIFT) 226 #define ID_AA64ISAR0_ATOMIC(x) ((x) & ID_AA64ISAR0_ATOMIC_MASK) 227 #define ID_AA64ISAR0_ATOMIC_NONE (0x0 << ID_AA64ISAR0_ATOMIC_SHIFT) 228 #define ID_AA64ISAR0_ATOMIC_IMPL (0x2 << ID_AA64ISAR0_ATOMIC_SHIFT) 229 #define ID_AA64ISAR0_RDM_SHIFT 28 230 #define ID_AA64ISAR0_RDM_MASK (0xf << ID_AA64ISAR0_RDM_SHIFT) 231 #define ID_AA64ISAR0_RDM(x) ((x) & ID_AA64ISAR0_RDM_MASK) 232 #define ID_AA64ISAR0_RDM_NONE (0x0 << ID_AA64ISAR0_RDM_SHIFT) 233 #define ID_AA64ISAR0_RDM_IMPL (0x1 << ID_AA64ISAR0_RDM_SHIFT) 234 235 /* ID_AA64MMFR0_EL1 */ 236 #define ID_AA64MMFR0_MASK 0xffffffff 237 #define ID_AA64MMFR0_PA_RANGE_SHIFT 0 238 #define ID_AA64MMFR0_PA_RANGE_MASK (0xf << ID_AA64MMFR0_PA_RANGE_SHIFT) 239 #define ID_AA64MMFR0_PA_RANGE(x) ((x) & ID_AA64MMFR0_PA_RANGE_MASK) 240 #define ID_AA64MMFR0_PA_RANGE_4G (0x0 << ID_AA64MMFR0_PA_RANGE_SHIFT) 241 #define ID_AA64MMFR0_PA_RANGE_64G (0x1 << ID_AA64MMFR0_PA_RANGE_SHIFT) 242 #define ID_AA64MMFR0_PA_RANGE_1T (0x2 << ID_AA64MMFR0_PA_RANGE_SHIFT) 243 #define ID_AA64MMFR0_PA_RANGE_4T (0x3 << ID_AA64MMFR0_PA_RANGE_SHIFT) 244 #define ID_AA64MMFR0_PA_RANGE_16T (0x4 << ID_AA64MMFR0_PA_RANGE_SHIFT) 245 #define ID_AA64MMFR0_PA_RANGE_256T (0x5 << ID_AA64MMFR0_PA_RANGE_SHIFT) 246 #define ID_AA64MMFR0_ASID_BITS_SHIFT 4 247 #define ID_AA64MMFR0_ASID_BITS_MASK (0xf << ID_AA64MMFR0_ASID_BITS_SHIFT) 248 #define ID_AA64MMFR0_ASID_BITS(x) ((x) & ID_AA64MMFR0_ASID_BITS_MASK) 249 #define ID_AA64MMFR0_ASID_BITS_8 (0x0 << ID_AA64MMFR0_ASID_BITS_SHIFT) 250 #define ID_AA64MMFR0_ASID_BITS_16 (0x2 << ID_AA64MMFR0_ASID_BITS_SHIFT) 251 #define ID_AA64MMFR0_BIGEND_SHIFT 8 252 #define ID_AA64MMFR0_BIGEND_MASK (0xf << ID_AA64MMFR0_BIGEND_SHIFT) 253 #define ID_AA64MMFR0_BIGEND(x) ((x) & ID_AA64MMFR0_BIGEND_MASK) 254 #define ID_AA64MMFR0_BIGEND_FIXED (0x0 << ID_AA64MMFR0_BIGEND_SHIFT) 255 #define ID_AA64MMFR0_BIGEND_MIXED (0x1 << ID_AA64MMFR0_BIGEND_SHIFT) 256 #define ID_AA64MMFR0_S_NS_MEM_SHIFT 12 257 #define ID_AA64MMFR0_S_NS_MEM_MASK (0xf << ID_AA64MMFR0_S_NS_MEM_SHIFT) 258 #define ID_AA64MMFR0_S_NS_MEM(x) ((x) & ID_AA64MMFR0_S_NS_MEM_MASK) 259 #define ID_AA64MMFR0_S_NS_MEM_NONE (0x0 << ID_AA64MMFR0_S_NS_MEM_SHIFT) 260 #define ID_AA64MMFR0_S_NS_MEM_DISTINCT (0x1 << ID_AA64MMFR0_S_NS_MEM_SHIFT) 261 #define ID_AA64MMFR0_BIGEND_EL0_SHIFT 16 262 #define ID_AA64MMFR0_BIGEND_EL0_MASK (0xf << ID_AA64MMFR0_BIGEND_EL0_SHIFT) 263 #define ID_AA64MMFR0_BIGEND_EL0(x) ((x) & ID_AA64MMFR0_BIGEND_EL0_MASK) 264 #define ID_AA64MMFR0_BIGEND_EL0_FIXED (0x0 << ID_AA64MMFR0_BIGEND_EL0_SHIFT) 265 #define ID_AA64MMFR0_BIGEND_EL0_MIXED (0x1 << ID_AA64MMFR0_BIGEND_EL0_SHIFT) 266 #define ID_AA64MMFR0_TGRAN16_SHIFT 20 267 #define ID_AA64MMFR0_TGRAN16_MASK (0xf << ID_AA64MMFR0_TGRAN16_SHIFT) 268 #define ID_AA64MMFR0_TGRAN16(x) ((x) & ID_AA64MMFR0_TGRAN16_MASK) 269 #define ID_AA64MMFR0_TGRAN16_NONE (0x0 << ID_AA64MMFR0_TGRAN16_SHIFT) 270 #define ID_AA64MMFR0_TGRAN16_IMPL (0x1 << ID_AA64MMFR0_TGRAN16_SHIFT) 271 #define ID_AA64MMFR0_TGRAN64_SHIFT 24 272 #define ID_AA64MMFR0_TGRAN64_MASK (0xf << ID_AA64MMFR0_TGRAN64_SHIFT) 273 #define ID_AA64MMFR0_TGRAN64(x) ((x) & ID_AA64MMFR0_TGRAN64_MASK) 274 #define ID_AA64MMFR0_TGRAN64_IMPL (0x0 << ID_AA64MMFR0_TGRAN64_SHIFT) 275 #define ID_AA64MMFR0_TGRAN64_NONE (0xf << ID_AA64MMFR0_TGRAN64_SHIFT) 276 #define ID_AA64MMFR0_TGRAN4_SHIFT 28 277 #define ID_AA64MMFR0_TGRAN4_MASK (0xf << ID_AA64MMFR0_TGRAN4_SHIFT) 278 #define ID_AA64MMFR0_TGRAN4(x) ((x) & ID_AA64MMFR0_TGRAN4_MASK) 279 #define ID_AA64MMFR0_TGRAN4_IMPL (0x0 << ID_AA64MMFR0_TGRAN4_SHIFT) 280 #define ID_AA64MMFR0_TGRAN4_NONE (0xf << ID_AA64MMFR0_TGRAN4_SHIFT) 281 282 /* ID_AA64MMFR1_EL1 */ 283 #define ID_AA64MMFR1_MASK 0x00ffffff 284 #define ID_AA64MMFR1_HAFDBS_SHIFT 0 285 #define ID_AA64MMFR1_HAFDBS_MASK (0xf << ID_AA64MMFR1_HAFDBS_SHIFT) 286 #define ID_AA64MMFR1_HAFDBS(x) ((x) & ID_AA64MMFR1_HAFDBS_MASK) 287 #define ID_AA64MMFR1_HAFDBS_NONE (0x0 << ID_AA64MMFR1_HAFDBS_SHIFT) 288 #define ID_AA64MMFR1_HAFDBS_AF (0x1 << ID_AA64MMFR1_HAFDBS_SHIFT) 289 #define ID_AA64MMFR1_HAFDBS_AF_DBS (0x2 << ID_AA64MMFR1_HAFDBS_SHIFT) 290 #define ID_AA64MMFR1_VMIDBITS_SHIFT 4 291 #define ID_AA64MMFR1_VMIDBITS_MASK (0xf << ID_AA64MMFR1_VMIDBITS_SHIFT) 292 #define ID_AA64MMFR1_VMIDBITS(x) ((x) & ID_AA64MMFR1_VMIDBITS_MASK) 293 #define ID_AA64MMFR1_VMIDBITS_8 (0x0 << ID_AA64MMFR1_VMIDBITS_SHIFT) 294 #define ID_AA64MMFR1_VMIDBITS_16 (0x2 << ID_AA64MMFR1_VMIDBITS_SHIFT) 295 #define ID_AA64MMFR1_VH_SHIFT 8 296 #define ID_AA64MMFR1_VH_MASK (0xf << ID_AA64MMFR1_VH_SHIFT) 297 #define ID_AA64MMFR1_VH(x) ((x) & ID_AA64MMFR1_VH_MASK) 298 #define ID_AA64MMFR1_VH_NONE (0x0 << ID_AA64MMFR1_VH_SHIFT) 299 #define ID_AA64MMFR1_VH_IMPL (0x1 << ID_AA64MMFR1_VH_SHIFT) 300 #define ID_AA64MMFR1_HPDS_SHIFT 12 301 #define ID_AA64MMFR1_HPDS_MASK (0xf << ID_AA64MMFR1_HPDS_SHIFT) 302 #define ID_AA64MMFR1_HPDS(x) ((x) & ID_AA64MMFR1_HPDS_MASK) 303 #define ID_AA64MMFR1_HPDS_NONE (0x0 << ID_AA64MMFR1_HPDS_SHIFT) 304 #define ID_AA64MMFR1_HPDS_IMPL (0x1 << ID_AA64MMFR1_HPDS_SHIFT) 305 #define ID_AA64MMFR1_LO_SHIFT 16 306 #define ID_AA64MMFR1_LO_MASK (0xf << ID_AA64MMFR1_LO_SHIFT) 307 #define ID_AA64MMFR1_LO(x) ((x) & ID_AA64MMFR1_LO_MASK) 308 #define ID_AA64MMFR1_LO_NONE (0x0 << ID_AA64MMFR1_LO_SHIFT) 309 #define ID_AA64MMFR1_LO_IMPL (0x1 << ID_AA64MMFR1_LO_SHIFT) 310 #define ID_AA64MMFR1_PAN_SHIFT 20 311 #define ID_AA64MMFR1_PAN_MASK (0xf << ID_AA64MMFR1_PAN_SHIFT) 312 #define ID_AA64MMFR1_PAN(x) ((x) & ID_AA64MMFR1_PAN_MASK) 313 #define ID_AA64MMFR1_PAN_NONE (0x0 << ID_AA64MMFR1_PAN_SHIFT) 314 #define ID_AA64MMFR1_PAN_IMPL (0x1 << ID_AA64MMFR1_PAN_SHIFT) 315 316 /* ID_AA64PFR0_EL1 */ 317 #define ID_AA64PFR0_MASK 0x0fffffff 318 #define ID_AA64PFR0_EL0_SHIFT 0 319 #define ID_AA64PFR0_EL0_MASK (0xf << ID_AA64PFR0_EL0_SHIFT) 320 #define ID_AA64PFR0_EL0(x) ((x) & ID_AA64PFR0_EL0_MASK) 321 #define ID_AA64PFR0_EL0_64 (1 << ID_AA64PFR0_EL0_SHIFT) 322 #define ID_AA64PFR0_EL0_64_32 (2 << ID_AA64PFR0_EL0_SHIFT) 323 #define ID_AA64PFR0_EL1_SHIFT 4 324 #define ID_AA64PFR0_EL1_MASK (0xf << ID_AA64PFR0_EL1_SHIFT) 325 #define ID_AA64PFR0_EL1(x) ((x) & ID_AA64PFR0_EL1_MASK) 326 #define ID_AA64PFR0_EL1_64 (1 << ID_AA64PFR0_EL1_SHIFT) 327 #define ID_AA64PFR0_EL1_64_32 (2 << ID_AA64PFR0_EL1_SHIFT) 328 #define ID_AA64PFR0_EL2_SHIFT 8 329 #define ID_AA64PFR0_EL2_MASK (0xf << ID_AA64PFR0_EL2_SHIFT) 330 #define ID_AA64PFR0_EL2(x) ((x) & ID_AA64PFR0_EL2_MASK) 331 #define ID_AA64PFR0_EL2_NONE (0 << ID_AA64PFR0_EL2_SHIFT) 332 #define ID_AA64PFR0_EL2_64 (1 << ID_AA64PFR0_EL2_SHIFT) 333 #define ID_AA64PFR0_EL2_64_32 (2 << ID_AA64PFR0_EL2_SHIFT) 334 #define ID_AA64PFR0_EL3_SHIFT 12 335 #define ID_AA64PFR0_EL3_MASK (0xf << ID_AA64PFR0_EL3_SHIFT) 336 #define ID_AA64PFR0_EL3(x) ((x) & ID_AA64PFR0_EL3_MASK) 337 #define ID_AA64PFR0_EL3_NONE (0 << ID_AA64PFR0_EL3_SHIFT) 338 #define ID_AA64PFR0_EL3_64 (1 << ID_AA64PFR0_EL3_SHIFT) 339 #define ID_AA64PFR0_EL3_64_32 (2 << ID_AA64PFR0_EL3_SHIFT) 340 #define ID_AA64PFR0_FP_SHIFT 16 341 #define ID_AA64PFR0_FP_MASK (0xf << ID_AA64PFR0_FP_SHIFT) 342 #define ID_AA64PFR0_FP(x) ((x) & ID_AA64PFR0_FP_MASK) 343 #define ID_AA64PFR0_FP_IMPL (0x0 << ID_AA64PFR0_FP_SHIFT) 344 #define ID_AA64PFR0_FP_NONE (0xf << ID_AA64PFR0_FP_SHIFT) 345 #define ID_AA64PFR0_ADV_SIMD_SHIFT 20 346 #define ID_AA64PFR0_ADV_SIMD_MASK (0xf << ID_AA64PFR0_ADV_SIMD_SHIFT) 347 #define ID_AA64PFR0_ADV_SIMD(x) ((x) & ID_AA64PFR0_ADV_SIMD_MASK) 348 #define ID_AA64PFR0_ADV_SIMD_IMPL (0x0 << ID_AA64PFR0_ADV_SIMD_SHIFT) 349 #define ID_AA64PFR0_ADV_SIMD_NONE (0xf << ID_AA64PFR0_ADV_SIMD_SHIFT) 350 #define ID_AA64PFR0_GIC_BITS 0x4 /* Number of bits in GIC field */ 351 #define ID_AA64PFR0_GIC_SHIFT 24 352 #define ID_AA64PFR0_GIC_MASK (0xf << ID_AA64PFR0_GIC_SHIFT) 353 #define ID_AA64PFR0_GIC(x) ((x) & ID_AA64PFR0_GIC_MASK) 354 #define ID_AA64PFR0_GIC_CPUIF_NONE (0x0 << ID_AA64PFR0_GIC_SHIFT) 355 #define ID_AA64PFR0_GIC_CPUIF_EN (0x1 << ID_AA64PFR0_GIC_SHIFT) 356 357 /* MAIR_EL1 - Memory Attribute Indirection Register */ 358 #define MAIR_ATTR_MASK(idx) (0xff << ((n)* 8)) 359 #define MAIR_ATTR(attr, idx) ((attr) << ((idx) * 8)) 360 #define MAIR_DEVICE_nGnRnE 0x00 361 #define MAIR_NORMAL_NC 0x44 362 #define MAIR_NORMAL_WT 0x88 363 #define MAIR_NORMAL_WB 0xff 364 365 /* PAR_EL1 - Physical Address Register */ 366 #define PAR_F_SHIFT 0 367 #define PAR_F (0x1 << PAR_F_SHIFT) 368 #define PAR_SUCCESS(x) (((x) & PAR_F) == 0) 369 /* When PAR_F == 0 (success) */ 370 #define PAR_SH_SHIFT 7 371 #define PAR_SH_MASK (0x3 << PAR_SH_SHIFT) 372 #define PAR_NS_SHIFT 9 373 #define PAR_NS_MASK (0x3 << PAR_NS_SHIFT) 374 #define PAR_PA_SHIFT 12 375 #define PAR_PA_MASK 0x0000fffffffff000 376 #define PAR_ATTR_SHIFT 56 377 #define PAR_ATTR_MASK (0xff << PAR_ATTR_SHIFT) 378 /* When PAR_F == 1 (aborted) */ 379 #define PAR_FST_SHIFT 1 380 #define PAR_FST_MASK (0x3f << PAR_FST_SHIFT) 381 #define PAR_PTW_SHIFT 8 382 #define PAR_PTW_MASK (0x1 << PAR_PTW_SHIFT) 383 #define PAR_S_SHIFT 9 384 #define PAR_S_MASK (0x1 << PAR_S_SHIFT) 385 386 /* SCTLR_EL1 - System Control Register */ 387 #define SCTLR_RES0 0xc8222400 /* Reserved, write 0 */ 388 #define SCTLR_RES1 0x30d00800 /* Reserved, write 1 */ 389 390 #define SCTLR_M 0x00000001 391 #define SCTLR_A 0x00000002 392 #define SCTLR_C 0x00000004 393 #define SCTLR_SA 0x00000008 394 #define SCTLR_SA0 0x00000010 395 #define SCTLR_CP15BEN 0x00000020 396 #define SCTLR_THEE 0x00000040 397 #define SCTLR_ITD 0x00000080 398 #define SCTLR_SED 0x00000100 399 #define SCTLR_UMA 0x00000200 400 #define SCTLR_I 0x00001000 401 #define SCTLR_DZE 0x00004000 402 #define SCTLR_UCT 0x00008000 403 #define SCTLR_nTWI 0x00010000 404 #define SCTLR_nTWE 0x00040000 405 #define SCTLR_WXN 0x00080000 406 #define SCTLR_EOE 0x01000000 407 #define SCTLR_EE 0x02000000 408 #define SCTLR_UCI 0x04000000 409 410 /* SPSR_EL1 */ 411 /* 412 * When the exception is taken in AArch64: 413 * M[4] is 0 for AArch64 mode 414 * M[3:2] is the exception level 415 * M[1] is unused 416 * M[0] is the SP select: 417 * 0: always SP0 418 * 1: current ELs SP 419 */ 420 #define PSR_M_EL0t 0x00000000 421 #define PSR_M_EL1t 0x00000004 422 #define PSR_M_EL1h 0x00000005 423 #define PSR_M_EL2t 0x00000008 424 #define PSR_M_EL2h 0x00000009 425 #define PSR_M_MASK 0x0000001f 426 427 #define PSR_F 0x00000040 428 #define PSR_I 0x00000080 429 #define PSR_A 0x00000100 430 #define PSR_D 0x00000200 431 #define PSR_IL 0x00100000 432 #define PSR_SS 0x00200000 433 #define PSR_V 0x10000000 434 #define PSR_C 0x20000000 435 #define PSR_Z 0x40000000 436 #define PSR_N 0x80000000 437 438 /* TCR_EL1 - Translation Control Register */ 439 #define TCR_ASID_16 (1 << 36) 440 441 #define TCR_IPS_SHIFT 32 442 #define TCR_IPS_32BIT (0 << TCR_IPS_SHIFT) 443 #define TCR_IPS_36BIT (1 << TCR_IPS_SHIFT) 444 #define TCR_IPS_40BIT (2 << TCR_IPS_SHIFT) 445 #define TCR_IPS_42BIT (3 << TCR_IPS_SHIFT) 446 #define TCR_IPS_44BIT (4 << TCR_IPS_SHIFT) 447 #define TCR_IPS_48BIT (5 << TCR_IPS_SHIFT) 448 449 #define TCR_TG1_SHIFT 30 450 #define TCR_TG1_16K (1 << TCR_TG1_SHIFT) 451 #define TCR_TG1_4K (2 << TCR_TG1_SHIFT) 452 #define TCR_TG1_64K (3 << TCR_TG1_SHIFT) 453 454 #define TCR_SH1_SHIFT 28 455 #define TCR_SH1_IS (0x3UL << TCR_SH1_SHIFT) 456 #define TCR_ORGN1_SHIFT 26 457 #define TCR_ORGN1_WBWA (0x1UL << TCR_ORGN1_SHIFT) 458 #define TCR_IRGN1_SHIFT 24 459 #define TCR_IRGN1_WBWA (0x1UL << TCR_IRGN1_SHIFT) 460 #define TCR_SH0_SHIFT 12 461 #define TCR_SH0_IS (0x3UL << TCR_SH0_SHIFT) 462 #define TCR_ORGN0_SHIFT 10 463 #define TCR_ORGN0_WBWA (0x1UL << TCR_ORGN0_SHIFT) 464 #define TCR_IRGN0_SHIFT 8 465 #define TCR_IRGN0_WBWA (0x1UL << TCR_IRGN0_SHIFT) 466 467 #define TCR_CACHE_ATTRS ((TCR_IRGN0_WBWA | TCR_IRGN1_WBWA) |\ 468 (TCR_ORGN0_WBWA | TCR_ORGN1_WBWA)) 469 470 #ifdef SMP 471 #define TCR_SMP_ATTRS (TCR_SH0_IS | TCR_SH1_IS) 472 #else 473 #define TCR_SMP_ATTRS 0 474 #endif 475 476 #define TCR_T1SZ_SHIFT 16 477 #define TCR_T0SZ_SHIFT 0 478 #define TCR_T1SZ(x) ((x) << TCR_T1SZ_SHIFT) 479 #define TCR_T0SZ(x) ((x) << TCR_T0SZ_SHIFT) 480 #define TCR_TxSZ(x) (TCR_T1SZ(x) | TCR_T0SZ(x)) 481 482 /* Saved Program Status Register */ 483 #define DBG_SPSR_SS (0x1 << 21) 484 485 /* Monitor Debug System Control Register */ 486 #define DBG_MDSCR_SS (0x1 << 0) 487 #define DBG_MDSCR_KDE (0x1 << 13) 488 #define DBG_MDSCR_MDE (0x1 << 15) 489 490 /* Perfomance Monitoring Counters */ 491 #define PMCR_E (1 << 0) /* Enable all counters */ 492 #define PMCR_P (1 << 1) /* Reset all counters */ 493 #define PMCR_C (1 << 2) /* Clock counter reset */ 494 #define PMCR_D (1 << 3) /* CNTR counts every 64 clk cycles */ 495 #define PMCR_X (1 << 4) /* Export to ext. monitoring (ETM) */ 496 #define PMCR_DP (1 << 5) /* Disable CCNT if non-invasive debug*/ 497 #define PMCR_LC (1 << 6) /* Long cycle count enable */ 498 #define PMCR_IMP_SHIFT 24 /* Implementer code */ 499 #define PMCR_IMP_MASK (0xff << PMCR_IMP_SHIFT) 500 #define PMCR_IDCODE_SHIFT 16 /* Identification code */ 501 #define PMCR_IDCODE_MASK (0xff << PMCR_IDCODE_SHIFT) 502 #define PMCR_IDCODE_CORTEX_A57 0x01 503 #define PMCR_IDCODE_CORTEX_A72 0x02 504 #define PMCR_IDCODE_CORTEX_A53 0x03 505 #define PMCR_N_SHIFT 11 /* Number of counters implemented */ 506 #define PMCR_N_MASK (0x1f << PMCR_N_SHIFT) 507 508 #endif /* !_MACHINE_ARMREG_H_ */ 509