xref: /freebsd/sys/arm64/include/armreg.h (revision db27818234e734a9042648471c36a507c6c80bdc)
1e5acd89cSAndrew Turner /*-
2e5acd89cSAndrew Turner  * Copyright (c) 2013, 2014 Andrew Turner
3e5acd89cSAndrew Turner  * Copyright (c) 2015 The FreeBSD Foundation
4e5acd89cSAndrew Turner  * All rights reserved.
5e5acd89cSAndrew Turner  *
6e5acd89cSAndrew Turner  * This software was developed by Andrew Turner under
7e5acd89cSAndrew Turner  * sponsorship from the FreeBSD Foundation.
8e5acd89cSAndrew Turner  *
9e5acd89cSAndrew Turner  * Redistribution and use in source and binary forms, with or without
10e5acd89cSAndrew Turner  * modification, are permitted provided that the following conditions
11e5acd89cSAndrew Turner  * are met:
12e5acd89cSAndrew Turner  * 1. Redistributions of source code must retain the above copyright
13e5acd89cSAndrew Turner  *    notice, this list of conditions and the following disclaimer.
14e5acd89cSAndrew Turner  * 2. Redistributions in binary form must reproduce the above copyright
15e5acd89cSAndrew Turner  *    notice, this list of conditions and the following disclaimer in the
16e5acd89cSAndrew Turner  *    documentation and/or other materials provided with the distribution.
17e5acd89cSAndrew Turner  *
18e5acd89cSAndrew Turner  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19e5acd89cSAndrew Turner  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20e5acd89cSAndrew Turner  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21e5acd89cSAndrew Turner  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22e5acd89cSAndrew Turner  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23e5acd89cSAndrew Turner  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24e5acd89cSAndrew Turner  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25e5acd89cSAndrew Turner  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26e5acd89cSAndrew Turner  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27e5acd89cSAndrew Turner  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28e5acd89cSAndrew Turner  * SUCH DAMAGE.
29e5acd89cSAndrew Turner  *
30e5acd89cSAndrew Turner  * $FreeBSD$
31e5acd89cSAndrew Turner  */
32e5acd89cSAndrew Turner 
33e5acd89cSAndrew Turner #ifndef _MACHINE_ARMREG_H_
34e5acd89cSAndrew Turner #define	_MACHINE_ARMREG_H_
35e5acd89cSAndrew Turner 
368a1867f4SWojciech Macek #define	INSN_SIZE		4
378a1867f4SWojciech Macek 
38e5acd89cSAndrew Turner #define	READ_SPECIALREG(reg)						\
39e5acd89cSAndrew Turner ({	uint64_t val;							\
40e5acd89cSAndrew Turner 	__asm __volatile("mrs	%0, " __STRING(reg) : "=&r" (val));	\
41e5acd89cSAndrew Turner 	val;								\
42e5acd89cSAndrew Turner })
43e5acd89cSAndrew Turner #define	WRITE_SPECIALREG(reg, val)					\
44e5acd89cSAndrew Turner 	__asm __volatile("msr	" __STRING(reg) ", %0" : : "r"((uint64_t)val))
45e5acd89cSAndrew Turner 
46b1bacc1cSAndrew Turner /* CNTHCTL_EL2 - Counter-timer Hypervisor Control register */
47b1bacc1cSAndrew Turner #define	CNTHCTL_EVNTI_MASK	(0xf << 4) /* Bit to trigger event stream */
48b1bacc1cSAndrew Turner #define	CNTHCTL_EVNTDIR		(1 << 3) /* Control transition trigger bit */
49b1bacc1cSAndrew Turner #define	CNTHCTL_EVNTEN		(1 << 2) /* Enable event stream */
50b1bacc1cSAndrew Turner #define	CNTHCTL_EL1PCEN		(1 << 1) /* Allow EL0/1 physical timer access */
51b1bacc1cSAndrew Turner #define	CNTHCTL_EL1PCTEN	(1 << 0) /*Allow EL0/1 physical counter access*/
52b1bacc1cSAndrew Turner 
53e5acd89cSAndrew Turner /* CPACR_EL1 */
54e5acd89cSAndrew Turner #define	CPACR_FPEN_MASK		(0x3 << 20)
55e5acd89cSAndrew Turner #define	 CPACR_FPEN_TRAP_ALL1	(0x0 << 20) /* Traps from EL0 and EL1 */
56e5acd89cSAndrew Turner #define	 CPACR_FPEN_TRAP_EL0	(0x1 << 20) /* Traps from EL0 */
57e5acd89cSAndrew Turner #define	 CPACR_FPEN_TRAP_ALL2	(0x2 << 20) /* Traps from EL0 and EL1 */
58e5acd89cSAndrew Turner #define	 CPACR_FPEN_TRAP_NONE	(0x3 << 20) /* No traps */
59e5acd89cSAndrew Turner #define	CPACR_TTA		(0x1 << 28)
60e5acd89cSAndrew Turner 
61e5acd89cSAndrew Turner /* CTR_EL0 - Cache Type Register */
62e5acd89cSAndrew Turner #define	CTR_DLINE_SHIFT		16
63e5acd89cSAndrew Turner #define	CTR_DLINE_MASK		(0xf << CTR_DLINE_SHIFT)
64e5acd89cSAndrew Turner #define	CTR_DLINE_SIZE(reg)	(((reg) & CTR_DLINE_MASK) >> CTR_DLINE_SHIFT)
65e5acd89cSAndrew Turner #define	CTR_ILINE_SHIFT		0
66e5acd89cSAndrew Turner #define	CTR_ILINE_MASK		(0xf << CTR_ILINE_SHIFT)
67e5acd89cSAndrew Turner #define	CTR_ILINE_SIZE(reg)	(((reg) & CTR_ILINE_MASK) >> CTR_ILINE_SHIFT)
68e5acd89cSAndrew Turner 
69*db278182SWojciech Macek /* DCZID_EL0 - Data Cache Zero ID register */
70*db278182SWojciech Macek #define DCZID_DZP		(1 << 4) /* DC ZVA prohibited if non-0 */
71*db278182SWojciech Macek #define DCZID_BS_SHIFT		0
72*db278182SWojciech Macek #define DCZID_BS_MASK		(0xf << DCZID_BS_SHIFT)
73*db278182SWojciech Macek #define	DCZID_BS_SIZE(reg)	(((reg) & DCZID_BS_MASK) >> DCZID_BS_SHIFT)
74*db278182SWojciech Macek 
75e5acd89cSAndrew Turner /* ESR_ELx */
76e5acd89cSAndrew Turner #define	ESR_ELx_ISS_MASK	0x00ffffff
77e5acd89cSAndrew Turner #define	 ISS_INSN_FnV		(0x01 << 10)
78e5acd89cSAndrew Turner #define	 ISS_INSN_EA		(0x01 << 9)
79e5acd89cSAndrew Turner #define	 ISS_INSN_S1PTW		(0x01 << 7)
80e5acd89cSAndrew Turner #define	 ISS_INSN_IFSC_MASK	(0x1f << 0)
81e5acd89cSAndrew Turner #define	 ISS_DATA_ISV		(0x01 << 24)
82e5acd89cSAndrew Turner #define	 ISS_DATA_SAS_MASK	(0x03 << 22)
83e5acd89cSAndrew Turner #define	 ISS_DATA_SSE		(0x01 << 21)
84e5acd89cSAndrew Turner #define	 ISS_DATA_SRT_MASK	(0x1f << 16)
85e5acd89cSAndrew Turner #define	 ISS_DATA_SF		(0x01 << 15)
86e5acd89cSAndrew Turner #define	 ISS_DATA_AR		(0x01 << 14)
87e5acd89cSAndrew Turner #define	 ISS_DATA_FnV		(0x01 << 10)
88e5acd89cSAndrew Turner #define	 ISS_DATa_EA		(0x01 << 9)
89e5acd89cSAndrew Turner #define	 ISS_DATa_CM		(0x01 << 8)
90e5acd89cSAndrew Turner #define	 ISS_INSN_S1PTW		(0x01 << 7)
91e5acd89cSAndrew Turner #define	 ISS_DATa_WnR		(0x01 << 6)
92e5acd89cSAndrew Turner #define	 ISS_DATA_DFSC_MASK	(0x1f << 0)
93e5acd89cSAndrew Turner #define	ESR_ELx_IL		(0x01 << 25)
94e5acd89cSAndrew Turner #define	ESR_ELx_EC_SHIFT	26
95e5acd89cSAndrew Turner #define	ESR_ELx_EC_MASK		(0x3f << 26)
96e5acd89cSAndrew Turner #define	ESR_ELx_EXCEPTION(esr)	(((esr) & ESR_ELx_EC_MASK) >> ESR_ELx_EC_SHIFT)
97e5acd89cSAndrew Turner #define	 EXCP_UNKNOWN		0x00	/* Unkwn exception */
98e5acd89cSAndrew Turner #define	 EXCP_FP_SIMD		0x07	/* VFP/SIMD trap */
99e5acd89cSAndrew Turner #define	 EXCP_ILL_STATE		0x0e	/* Illegal execution state */
100e5acd89cSAndrew Turner #define	 EXCP_SVC		0x15	/* SVC trap */
101e5acd89cSAndrew Turner #define	 EXCP_MSR		0x18	/* MSR/MRS trap */
102e5acd89cSAndrew Turner #define	 EXCP_INSN_ABORT_L	0x20	/* Instruction abort, from lower EL */
103e5acd89cSAndrew Turner #define	 EXCP_INSN_ABORT	0x21	/* Instruction abort, from same EL */
104e5acd89cSAndrew Turner #define	 EXCP_PC_ALIGN		0x22	/* PC alignment fault */
105e5acd89cSAndrew Turner #define	 EXCP_DATA_ABORT_L	0x24	/* Data abort, from lower EL */
106e5acd89cSAndrew Turner #define	 EXCP_DATA_ABORT	0x25	/* Data abort, from same EL */
107e5acd89cSAndrew Turner #define	 EXCP_SP_ALIGN		0x26	/* SP slignment fault */
108e5acd89cSAndrew Turner #define	 EXCP_TRAP_FP		0x2c	/* Trapped FP exception */
109e5acd89cSAndrew Turner #define	 EXCP_SERROR		0x2f	/* SError interrupt */
11087e19994SAndrew Turner #define	 EXCP_SOFTSTP_EL0	0x32	/* Software Step, from lower EL */
111e5acd89cSAndrew Turner #define	 EXCP_SOFTSTP_EL1	0x33	/* Software Step, from same EL */
112e5acd89cSAndrew Turner #define	 EXCP_WATCHPT_EL1	0x35	/* Watchpoint, from same EL */
113e5acd89cSAndrew Turner #define	 EXCP_BRK		0x3c	/* Breakpoint */
114e5acd89cSAndrew Turner 
11542cb216aSZbigniew Bodek /* ICC_CTLR_EL1 */
11642cb216aSZbigniew Bodek #define	ICC_CTLR_EL1_EOIMODE	(1U << 1)
11742cb216aSZbigniew Bodek 
11842cb216aSZbigniew Bodek /* ICC_IAR1_EL1 */
11942cb216aSZbigniew Bodek #define	ICC_IAR1_EL1_SPUR	(0x03ff)
12042cb216aSZbigniew Bodek 
12142cb216aSZbigniew Bodek /* ICC_IGRPEN0_EL1 */
12242cb216aSZbigniew Bodek #define	ICC_IGRPEN0_EL1_EN	(1U << 0)
12342cb216aSZbigniew Bodek 
12442cb216aSZbigniew Bodek /* ICC_PMR_EL1 */
12542cb216aSZbigniew Bodek #define	ICC_PMR_EL1_PRIO_MASK	(0xFFUL)
12642cb216aSZbigniew Bodek 
1278133eda9SZbigniew Bodek /* ICC_SGI1R_EL1 */
1288133eda9SZbigniew Bodek #define	ICC_SGI1R_EL1_TL_MASK		0xffffUL
1298133eda9SZbigniew Bodek #define	ICC_SGI1R_EL1_AFF1_SHIFT	16
1308133eda9SZbigniew Bodek #define	ICC_SGI1R_EL1_SGIID_SHIFT	24
1318133eda9SZbigniew Bodek #define	ICC_SGI1R_EL1_AFF2_SHIFT	32
1328133eda9SZbigniew Bodek #define	ICC_SGI1R_EL1_AFF3_SHIFT	48
1338133eda9SZbigniew Bodek #define	ICC_SGI1R_EL1_SGIID_MASK	0xfUL
1348133eda9SZbigniew Bodek #define	ICC_SGI1R_EL1_IRM		(0x1UL << 40)
1358133eda9SZbigniew Bodek 
13642cb216aSZbigniew Bodek /* ICC_SRE_EL1 */
13742cb216aSZbigniew Bodek #define	ICC_SRE_EL1_SRE		(1U << 0)
13842cb216aSZbigniew Bodek 
13942cb216aSZbigniew Bodek /* ICC_SRE_EL2 */
140b2552c46SWojciech Macek #define	ICC_SRE_EL2_SRE		(1U << 0)
14142cb216aSZbigniew Bodek #define	ICC_SRE_EL2_EN		(1U << 3)
14242cb216aSZbigniew Bodek 
1435f0a5fefSAndrew Turner /* ID_AA64DFR0_EL1 */
1445f0a5fefSAndrew Turner #define	ID_AA64DFR0_MASK		0xf0f0ffff
1455f0a5fefSAndrew Turner #define	ID_AA64DFR0_DEBUG_VER_SHIFT	0
1465f0a5fefSAndrew Turner #define	ID_AA64DFR0_DEBUG_VER_MASK	(0xf << ID_AA64DFR0_DEBUG_VER_SHIFT)
1475f0a5fefSAndrew Turner #define	ID_AA64DFR0_DEBUG_VER(x)	((x) & ID_AA64DFR0_DEBUG_VER_MASK)
1485f0a5fefSAndrew Turner #define	 ID_AA64DFR0_DEBUG_VER_8	(0x6 << ID_AA64DFR0_DEBUG_VER_SHIFT)
1495f0a5fefSAndrew Turner #define	ID_AA64DFR0_TRACE_VER_SHIFT	4
1505f0a5fefSAndrew Turner #define	ID_AA64DFR0_TRACE_VER_MASK	(0xf << ID_AA64DFR0_TRACE_VER_SHIFT)
1515f0a5fefSAndrew Turner #define	ID_AA64DFR0_TRACE_VER(x)	((x) & ID_AA64DFR0_TRACE_VER_MASK)
1525f0a5fefSAndrew Turner #define	 ID_AA64DFR0_TRACE_VER_NONE	(0x0 << ID_AA64DFR0_TRACE_VER_SHIFT)
1535f0a5fefSAndrew Turner #define	 ID_AA64DFR0_TRACE_VER_IMPL	(0x1 << ID_AA64DFR0_TRACE_VER_SHIFT)
1545f0a5fefSAndrew Turner #define	ID_AA64DFR0_PMU_VER_SHIFT	8
1555f0a5fefSAndrew Turner #define	ID_AA64DFR0_PMU_VER_MASK	(0xf << ID_AA64DFR0_PMU_VER_SHIFT)
1565f0a5fefSAndrew Turner #define	ID_AA64DFR0_PMU_VER(x)		((x) & ID_AA64DFR0_PMU_VER_MASK)
1575f0a5fefSAndrew Turner #define	 ID_AA64DFR0_PMU_VER_NONE	(0x0 << ID_AA64DFR0_PMU_VER_SHIFT)
1585f0a5fefSAndrew Turner #define	 ID_AA64DFR0_PMU_VER_3		(0x1 << ID_AA64DFR0_PMU_VER_SHIFT)
1595f0a5fefSAndrew Turner #define	 ID_AA64DFR0_PMU_VER_IMPL	(0xf << ID_AA64DFR0_PMU_VER_SHIFT)
1605f0a5fefSAndrew Turner #define	ID_AA64DFR0_BRPS_SHIFT		12
1615f0a5fefSAndrew Turner #define	ID_AA64DFR0_BRPS_MASK		(0xf << ID_AA64DFR0_BRPS_SHIFT)
1625f0a5fefSAndrew Turner #define	ID_AA64DFR0_BRPS(x)		\
1635f0a5fefSAndrew Turner     ((((x) >> ID_AA64DFR0_BRPS_SHIFT) & 0xf) + 1)
1645f0a5fefSAndrew Turner #define	ID_AA64DFR0_WRPS_SHIFT		20
1655f0a5fefSAndrew Turner #define	ID_AA64DFR0_WRPS_MASK		(0xf << ID_AA64DFR0_WRPS_SHIFT)
1665f0a5fefSAndrew Turner #define	ID_AA64DFR0_WRPS(x)		\
1675f0a5fefSAndrew Turner     ((((x) >> ID_AA64DFR0_WRPS_SHIFT) & 0xf) + 1)
1685f0a5fefSAndrew Turner #define	ID_AA64DFR0_CTX_CMPS_SHIFT	28
1695f0a5fefSAndrew Turner #define	ID_AA64DFR0_CTX_CMPS_MASK	(0xf << ID_AA64DFR0_CTX_CMPS_SHIFT)
1705f0a5fefSAndrew Turner #define	ID_AA64DFR0_CTX_CMPS(x)		\
1715f0a5fefSAndrew Turner     ((((x) >> ID_AA64DFR0_CTX_CMPS_SHIFT) & 0xf) + 1)
1725f0a5fefSAndrew Turner 
1735f0a5fefSAndrew Turner /* ID_AA64ISAR0_EL1 */
1745f0a5fefSAndrew Turner #define	ID_AA64ISAR0_MASK		0x000ffff0
1755f0a5fefSAndrew Turner #define	ID_AA64ISAR0_AES_SHIFT		4
1765f0a5fefSAndrew Turner #define	ID_AA64ISAR0_AES_MASK		(0xf << ID_AA64ISAR0_AES_SHIFT)
1775f0a5fefSAndrew Turner #define	ID_AA64ISAR0_AES(x)		((x) & ID_AA64ISAR0_AES_MASK)
1785f0a5fefSAndrew Turner #define	 ID_AA64ISAR0_AES_NONE		(0x0 << ID_AA64ISAR0_AES_SHIFT)
1795f0a5fefSAndrew Turner #define	 ID_AA64ISAR0_AES_BASE		(0x1 << ID_AA64ISAR0_AES_SHIFT)
1805f0a5fefSAndrew Turner #define	 ID_AA64ISAR0_AES_PMULL		(0x2 << ID_AA64ISAR0_AES_SHIFT)
1815f0a5fefSAndrew Turner #define	ID_AA64ISAR0_SHA1_SHIFT		8
1825f0a5fefSAndrew Turner #define	ID_AA64ISAR0_SHA1_MASK		(0xf << ID_AA64ISAR0_SHA1_SHIFT)
1835f0a5fefSAndrew Turner #define	ID_AA64ISAR0_SHA1(x)		((x) & ID_AA64ISAR0_SHA1_MASK)
1845f0a5fefSAndrew Turner #define	 ID_AA64ISAR0_SHA1_NONE		(0x0 << ID_AA64ISAR0_SHA1_SHIFT)
1855f0a5fefSAndrew Turner #define	 ID_AA64ISAR0_SHA1_BASE		(0x1 << ID_AA64ISAR0_SHA1_SHIFT)
1865f0a5fefSAndrew Turner #define	ID_AA64ISAR0_SHA2_SHIFT		12
1875f0a5fefSAndrew Turner #define	ID_AA64ISAR0_SHA2_MASK		(0xf << ID_AA64ISAR0_SHA2_SHIFT)
1885f0a5fefSAndrew Turner #define	ID_AA64ISAR0_SHA2(x)		((x) & ID_AA64ISAR0_SHA2_MASK)
1895f0a5fefSAndrew Turner #define	 ID_AA64ISAR0_SHA2_NONE		(0x0 << ID_AA64ISAR0_SHA2_SHIFT)
1905f0a5fefSAndrew Turner #define	 ID_AA64ISAR0_SHA2_BASE		(0x1 << ID_AA64ISAR0_SHA2_SHIFT)
1915f0a5fefSAndrew Turner #define	ID_AA64ISAR0_CRC32_SHIFT	16
1925f0a5fefSAndrew Turner #define	ID_AA64ISAR0_CRC32_MASK		(0xf << ID_AA64ISAR0_CRC32_SHIFT)
1935f0a5fefSAndrew Turner #define	ID_AA64ISAR0_CRC32(x)		((x) & ID_AA64ISAR0_CRC32_MASK)
1945f0a5fefSAndrew Turner #define	 ID_AA64ISAR0_CRC32_NONE	(0x0 << ID_AA64ISAR0_CRC32_SHIFT)
1955f0a5fefSAndrew Turner #define	 ID_AA64ISAR0_CRC32_BASE	(0x1 << ID_AA64ISAR0_CRC32_SHIFT)
1965f0a5fefSAndrew Turner 
1975f0a5fefSAndrew Turner /* ID_AA64MMFR0_EL1 */
1985f0a5fefSAndrew Turner #define	ID_AA64MMFR0_MASK		0xffffffff
1995f0a5fefSAndrew Turner #define	ID_AA64MMFR0_PA_RANGE_SHIFT	0
2005f0a5fefSAndrew Turner #define	ID_AA64MMFR0_PA_RANGE_MASK	(0xf << ID_AA64MMFR0_PA_RANGE_SHIFT)
2015f0a5fefSAndrew Turner #define	ID_AA64MMFR0_PA_RANGE(x)	((x) & ID_AA64MMFR0_PA_RANGE_MASK)
2025f0a5fefSAndrew Turner #define	 ID_AA64MMFR0_PA_RANGE_4G	(0x0 << ID_AA64MMFR0_PA_RANGE_SHIFT)
2035f0a5fefSAndrew Turner #define	 ID_AA64MMFR0_PA_RANGE_64G	(0x1 << ID_AA64MMFR0_PA_RANGE_SHIFT)
2045f0a5fefSAndrew Turner #define	 ID_AA64MMFR0_PA_RANGE_1T	(0x2 << ID_AA64MMFR0_PA_RANGE_SHIFT)
2055f0a5fefSAndrew Turner #define	 ID_AA64MMFR0_PA_RANGE_4T	(0x3 << ID_AA64MMFR0_PA_RANGE_SHIFT)
2065f0a5fefSAndrew Turner #define	 ID_AA64MMFR0_PA_RANGE_16T	(0x4 << ID_AA64MMFR0_PA_RANGE_SHIFT)
2075f0a5fefSAndrew Turner #define	 ID_AA64MMFR0_PA_RANGE_256T	(0x5 << ID_AA64MMFR0_PA_RANGE_SHIFT)
2085f0a5fefSAndrew Turner #define	ID_AA64MMFR0_ASID_BITS_SHIFT	4
2095f0a5fefSAndrew Turner #define	ID_AA64MMFR0_ASID_BITS_MASK	(0xf << ID_AA64MMFR0_ASID_BITS_SHIFT)
2105f0a5fefSAndrew Turner #define	ID_AA64MMFR0_ASID_BITS(x)	((x) & ID_AA64MMFR0_ASID_BITS_MASK)
2115f0a5fefSAndrew Turner #define	 ID_AA64MMFR0_ASID_BITS_8	(0x0 << ID_AA64MMFR0_ASID_BITS_SHIFT)
2125f0a5fefSAndrew Turner #define	 ID_AA64MMFR0_ASID_BITS_16	(0x2 << ID_AA64MMFR0_ASID_BITS_SHIFT)
2135f0a5fefSAndrew Turner #define	ID_AA64MMFR0_BIGEND_SHIFT	8
2145f0a5fefSAndrew Turner #define	ID_AA64MMFR0_BIGEND_MASK	(0xf << ID_AA64MMFR0_BIGEND_SHIFT)
2155f0a5fefSAndrew Turner #define	ID_AA64MMFR0_BIGEND(x)		((x) & ID_AA64MMFR0_BIGEND_MASK)
2165f0a5fefSAndrew Turner #define	 ID_AA64MMFR0_BIGEND_FIXED	(0x0 << ID_AA64MMFR0_BIGEND_SHIFT)
2175f0a5fefSAndrew Turner #define	 ID_AA64MMFR0_BIGEND_MIXED	(0x1 << ID_AA64MMFR0_BIGEND_SHIFT)
2185f0a5fefSAndrew Turner #define	ID_AA64MMFR0_S_NS_MEM_SHIFT	12
2195f0a5fefSAndrew Turner #define	ID_AA64MMFR0_S_NS_MEM_MASK	(0xf << ID_AA64MMFR0_S_NS_MEM_SHIFT)
2205f0a5fefSAndrew Turner #define	ID_AA64MMFR0_S_NS_MEM(x)	((x) & ID_AA64MMFR0_S_NS_MEM_MASK)
2215f0a5fefSAndrew Turner #define	 ID_AA64MMFR0_S_NS_MEM_NONE	(0x0 << ID_AA64MMFR0_S_NS_MEM_SHIFT)
2225f0a5fefSAndrew Turner #define	 ID_AA64MMFR0_S_NS_MEM_DISTINCT	(0x1 << ID_AA64MMFR0_S_NS_MEM_SHIFT)
2235f0a5fefSAndrew Turner #define	ID_AA64MMFR0_BIGEND_EL0_SHIFT	16
2245f0a5fefSAndrew Turner #define	ID_AA64MMFR0_BIGEND_EL0_MASK	(0xf << ID_AA64MMFR0_BIGEND_EL0_SHIFT)
2255f0a5fefSAndrew Turner #define	ID_AA64MMFR0_BIGEND_EL0(x)	((x) & ID_AA64MMFR0_BIGEND_EL0_MASK)
2265f0a5fefSAndrew Turner #define	 ID_AA64MMFR0_BIGEND_EL0_FIXED	(0x0 << ID_AA64MMFR0_BIGEND_EL0_SHIFT)
2275f0a5fefSAndrew Turner #define	 ID_AA64MMFR0_BIGEND_EL0_MIXED	(0x1 << ID_AA64MMFR0_BIGEND_EL0_SHIFT)
2285f0a5fefSAndrew Turner #define	ID_AA64MMFR0_TGRAN16_SHIFT	20
2295f0a5fefSAndrew Turner #define	ID_AA64MMFR0_TGRAN16_MASK	(0xf << ID_AA64MMFR0_TGRAN16_SHIFT)
2305f0a5fefSAndrew Turner #define	ID_AA64MMFR0_TGRAN16(x)		((x) & ID_AA64MMFR0_TGRAN16_MASK)
2315f0a5fefSAndrew Turner #define	 ID_AA64MMFR0_TGRAN16_NONE	(0x0 << ID_AA64MMFR0_TGRAN16_SHIFT)
2325f0a5fefSAndrew Turner #define	 ID_AA64MMFR0_TGRAN16_IMPL	(0x1 << ID_AA64MMFR0_TGRAN16_SHIFT)
2335f0a5fefSAndrew Turner #define	ID_AA64MMFR0_TGRAN64_SHIFT	24
2345f0a5fefSAndrew Turner #define	ID_AA64MMFR0_TGRAN64_MASK	(0xf << ID_AA64MMFR0_TGRAN64_SHIFT)
2355f0a5fefSAndrew Turner #define	ID_AA64MMFR0_TGRAN64(x)		((x) & ID_AA64MMFR0_TGRAN64_MASK)
2365f0a5fefSAndrew Turner #define	 ID_AA64MMFR0_TGRAN64_IMPL	(0x0 << ID_AA64MMFR0_TGRAN64_SHIFT)
2375f0a5fefSAndrew Turner #define	 ID_AA64MMFR0_TGRAN64_NONE	(0xf << ID_AA64MMFR0_TGRAN64_SHIFT)
2385f0a5fefSAndrew Turner #define	ID_AA64MMFR0_TGRAN4_SHIFT	28
2395f0a5fefSAndrew Turner #define	ID_AA64MMFR0_TGRAN4_MASK	(0xf << ID_AA64MMFR0_TGRAN4_SHIFT)
2405f0a5fefSAndrew Turner #define	ID_AA64MMFR0_TGRAN4(x)		((x) & ID_AA64MMFR0_TGRAN4_MASK)
2415f0a5fefSAndrew Turner #define	 ID_AA64MMFR0_TGRAN4_IMPL	(0x0 << ID_AA64MMFR0_TGRAN4_SHIFT)
2425f0a5fefSAndrew Turner #define	 ID_AA64MMFR0_TGRAN4_NONE	(0xf << ID_AA64MMFR0_TGRAN4_SHIFT)
2435f0a5fefSAndrew Turner 
244e5acd89cSAndrew Turner /* ID_AA64PFR0_EL1 */
2455f0a5fefSAndrew Turner #define	ID_AA64PFR0_MASK		0x0fffffff
2465f0a5fefSAndrew Turner #define	ID_AA64PFR0_EL0_SHIFT		0
2475f0a5fefSAndrew Turner #define	ID_AA64PFR0_EL0_MASK		(0xf << ID_AA64PFR0_EL0_SHIFT)
2485f0a5fefSAndrew Turner #define	ID_AA64PFR0_EL0(x)		((x) & ID_AA64PFR0_EL0_MASK)
2495f0a5fefSAndrew Turner #define	 ID_AA64PFR0_EL0_64		(1 << ID_AA64PFR0_EL0_SHIFT)
2505f0a5fefSAndrew Turner #define	 ID_AA64PFR0_EL0_64_32		(2 << ID_AA64PFR0_EL0_SHIFT)
2515f0a5fefSAndrew Turner #define	ID_AA64PFR0_EL1_SHIFT		4
2525f0a5fefSAndrew Turner #define	ID_AA64PFR0_EL1_MASK		(0xf << ID_AA64PFR0_EL1_SHIFT)
2535f0a5fefSAndrew Turner #define	ID_AA64PFR0_EL1(x)		((x) & ID_AA64PFR0_EL1_MASK)
2545f0a5fefSAndrew Turner #define	 ID_AA64PFR0_EL1_64		(1 << ID_AA64PFR0_EL1_SHIFT)
2555f0a5fefSAndrew Turner #define	 ID_AA64PFR0_EL1_64_32		(2 << ID_AA64PFR0_EL1_SHIFT)
2565f0a5fefSAndrew Turner #define	ID_AA64PFR0_EL2_SHIFT		8
2575f0a5fefSAndrew Turner #define	ID_AA64PFR0_EL2_MASK		(0xf << ID_AA64PFR0_EL2_SHIFT)
2585f0a5fefSAndrew Turner #define	ID_AA64PFR0_EL2(x)		((x) & ID_AA64PFR0_EL2_MASK)
2595f0a5fefSAndrew Turner #define	 ID_AA64PFR0_EL2_NONE		(0 << ID_AA64PFR0_EL2_SHIFT)
2605f0a5fefSAndrew Turner #define	 ID_AA64PFR0_EL2_64		(1 << ID_AA64PFR0_EL2_SHIFT)
2615f0a5fefSAndrew Turner #define	 ID_AA64PFR0_EL2_64_32		(2 << ID_AA64PFR0_EL2_SHIFT)
2625f0a5fefSAndrew Turner #define	ID_AA64PFR0_EL3_SHIFT		12
2635f0a5fefSAndrew Turner #define	ID_AA64PFR0_EL3_MASK		(0xf << ID_AA64PFR0_EL3_SHIFT)
2645f0a5fefSAndrew Turner #define	ID_AA64PFR0_EL3(x)		((x) & ID_AA64PFR0_EL3_MASK)
2655f0a5fefSAndrew Turner #define	 ID_AA64PFR0_EL3_NONE		(0 << ID_AA64PFR0_EL3_SHIFT)
2665f0a5fefSAndrew Turner #define	 ID_AA64PFR0_EL3_64		(1 << ID_AA64PFR0_EL3_SHIFT)
2675f0a5fefSAndrew Turner #define	 ID_AA64PFR0_EL3_64_32		(2 << ID_AA64PFR0_EL3_SHIFT)
2685f0a5fefSAndrew Turner #define	ID_AA64PFR0_FP_SHIFT		16
2695f0a5fefSAndrew Turner #define	ID_AA64PFR0_FP_MASK		(0xf << ID_AA64PFR0_FP_SHIFT)
2705f0a5fefSAndrew Turner #define	ID_AA64PFR0_FP(x)		((x) & ID_AA64PFR0_FP_MASK)
2715f0a5fefSAndrew Turner #define	 ID_AA64PFR0_FP_IMPL		(0x0 << ID_AA64PFR0_FP_SHIFT)
2725f0a5fefSAndrew Turner #define	 ID_AA64PFR0_FP_NONE		(0xf << ID_AA64PFR0_FP_SHIFT)
2735f0a5fefSAndrew Turner #define	ID_AA64PFR0_ADV_SIMD_SHIFT	20
2745f0a5fefSAndrew Turner #define	ID_AA64PFR0_ADV_SIMD_MASK	(0xf << ID_AA64PFR0_ADV_SIMD_SHIFT)
2755f0a5fefSAndrew Turner #define	ID_AA64PFR0_ADV_SIMD(x)		((x) & ID_AA64PFR0_ADV_SIMD_MASK)
2765f0a5fefSAndrew Turner #define	 ID_AA64PFR0_ADV_SIMD_IMPL	(0x0 << ID_AA64PFR0_ADV_SIMD_SHIFT)
2775f0a5fefSAndrew Turner #define	 ID_AA64PFR0_ADV_SIMD_NONE	(0xf << ID_AA64PFR0_ADV_SIMD_SHIFT)
2785f0a5fefSAndrew Turner #define	ID_AA64PFR0_GIC_BITS		0x4 /* Number of bits in GIC field */
2795f0a5fefSAndrew Turner #define	ID_AA64PFR0_GIC_SHIFT		24
28042cb216aSZbigniew Bodek #define	ID_AA64PFR0_GIC_MASK		(0xf << ID_AA64PFR0_GIC_SHIFT)
2815f0a5fefSAndrew Turner #define	ID_AA64PFR0_GIC(x)		((x) & ID_AA64PFR0_GIC_MASK)
2825f0a5fefSAndrew Turner #define	 ID_AA64PFR0_GIC_CPUIF_NONE	(0x0 << ID_AA64PFR0_GIC_SHIFT)
28342cb216aSZbigniew Bodek #define	 ID_AA64PFR0_GIC_CPUIF_EN	(0x1 << ID_AA64PFR0_GIC_SHIFT)
284e5acd89cSAndrew Turner 
285e5acd89cSAndrew Turner /* MAIR_EL1 - Memory Attribute Indirection Register */
286e5acd89cSAndrew Turner #define	MAIR_ATTR_MASK(idx)	(0xff << ((n)* 8))
287e5acd89cSAndrew Turner #define	MAIR_ATTR(attr, idx) ((attr) << ((idx) * 8))
288e5acd89cSAndrew Turner 
289e5acd89cSAndrew Turner /* SCTLR_EL1 - System Control Register */
290e5acd89cSAndrew Turner #define	SCTLR_RES0	0xc8222400	/* Reserved, write 0 */
291e5acd89cSAndrew Turner #define	SCTLR_RES1	0x30d00800	/* Reserved, write 1 */
292e5acd89cSAndrew Turner 
293e5acd89cSAndrew Turner #define	SCTLR_M		0x00000001
294e5acd89cSAndrew Turner #define	SCTLR_A		0x00000002
295e5acd89cSAndrew Turner #define	SCTLR_C		0x00000004
296e5acd89cSAndrew Turner #define	SCTLR_SA	0x00000008
297e5acd89cSAndrew Turner #define	SCTLR_SA0	0x00000010
298e5acd89cSAndrew Turner #define	SCTLR_CP15BEN	0x00000020
299e5acd89cSAndrew Turner #define	SCTLR_THEE	0x00000040
300e5acd89cSAndrew Turner #define	SCTLR_ITD	0x00000080
301e5acd89cSAndrew Turner #define	SCTLR_SED	0x00000100
302e5acd89cSAndrew Turner #define	SCTLR_UMA	0x00000200
303e5acd89cSAndrew Turner #define	SCTLR_I		0x00001000
304e5acd89cSAndrew Turner #define	SCTLR_DZE	0x00004000
305e5acd89cSAndrew Turner #define	SCTLR_UCT	0x00008000
306e5acd89cSAndrew Turner #define	SCTLR_nTWI	0x00010000
307e5acd89cSAndrew Turner #define	SCTLR_nTWE	0x00040000
308e5acd89cSAndrew Turner #define	SCTLR_WXN	0x00080000
309e5acd89cSAndrew Turner #define	SCTLR_EOE	0x01000000
310e5acd89cSAndrew Turner #define	SCTLR_EE	0x02000000
311e5acd89cSAndrew Turner #define	SCTLR_UCI	0x04000000
312e5acd89cSAndrew Turner 
313e5acd89cSAndrew Turner /* SPSR_EL1 */
314e5acd89cSAndrew Turner /*
315e5acd89cSAndrew Turner  * When the exception is taken in AArch64:
316e5acd89cSAndrew Turner  * M[4]   is 0 for AArch64 mode
317e5acd89cSAndrew Turner  * M[3:2] is the exception level
318e5acd89cSAndrew Turner  * M[1]   is unused
319e5acd89cSAndrew Turner  * M[0]   is the SP select:
320e5acd89cSAndrew Turner  *         0: always SP0
321e5acd89cSAndrew Turner  *         1: current ELs SP
322e5acd89cSAndrew Turner  */
323e5acd89cSAndrew Turner #define	PSR_M_EL0t	0x00000000
324e5acd89cSAndrew Turner #define	PSR_M_EL1t	0x00000004
325e5acd89cSAndrew Turner #define	PSR_M_EL1h	0x00000005
326e5acd89cSAndrew Turner #define	PSR_M_EL2t	0x00000008
327e5acd89cSAndrew Turner #define	PSR_M_EL2h	0x00000009
328e5acd89cSAndrew Turner #define	PSR_M_MASK	0x0000001f
329e5acd89cSAndrew Turner 
330e5acd89cSAndrew Turner #define	PSR_F		0x00000040
331e5acd89cSAndrew Turner #define	PSR_I		0x00000080
332e5acd89cSAndrew Turner #define	PSR_A		0x00000100
333e5acd89cSAndrew Turner #define	PSR_D		0x00000200
334e5acd89cSAndrew Turner #define	PSR_IL		0x00100000
335e5acd89cSAndrew Turner #define	PSR_SS		0x00200000
336e5acd89cSAndrew Turner #define	PSR_V		0x10000000
337e5acd89cSAndrew Turner #define	PSR_C		0x20000000
338e5acd89cSAndrew Turner #define	PSR_Z		0x40000000
339e5acd89cSAndrew Turner #define	PSR_N		0x80000000
340e5acd89cSAndrew Turner 
341e5acd89cSAndrew Turner /* TCR_EL1 - Translation Control Register */
342e5acd89cSAndrew Turner #define	TCR_ASID_16	(1 << 36)
343e5acd89cSAndrew Turner 
344e5acd89cSAndrew Turner #define	TCR_IPS_SHIFT	32
345e5acd89cSAndrew Turner #define	TCR_IPS_32BIT	(0 << TCR_IPS_SHIFT)
346e5acd89cSAndrew Turner #define	TCR_IPS_36BIT	(1 << TCR_IPS_SHIFT)
347e5acd89cSAndrew Turner #define	TCR_IPS_40BIT	(2 << TCR_IPS_SHIFT)
348e5acd89cSAndrew Turner #define	TCR_IPS_42BIT	(3 << TCR_IPS_SHIFT)
349e5acd89cSAndrew Turner #define	TCR_IPS_44BIT	(4 << TCR_IPS_SHIFT)
350e5acd89cSAndrew Turner #define	TCR_IPS_48BIT	(5 << TCR_IPS_SHIFT)
351e5acd89cSAndrew Turner 
352e5acd89cSAndrew Turner #define	TCR_TG1_SHIFT	30
353e5acd89cSAndrew Turner #define	TCR_TG1_16K	(1 << TCR_TG1_SHIFT)
354e5acd89cSAndrew Turner #define	TCR_TG1_4K	(2 << TCR_TG1_SHIFT)
355e5acd89cSAndrew Turner #define	TCR_TG1_64K	(3 << TCR_TG1_SHIFT)
356e5acd89cSAndrew Turner 
3571038d102SZbigniew Bodek #define	TCR_SH1_SHIFT	28
3581038d102SZbigniew Bodek #define	TCR_SH1_IS	(0x3UL << TCR_SH1_SHIFT)
3591038d102SZbigniew Bodek #define	TCR_ORGN1_SHIFT	26
3601038d102SZbigniew Bodek #define	TCR_ORGN1_WBWA	(0x1UL << TCR_ORGN1_SHIFT)
3611038d102SZbigniew Bodek #define	TCR_IRGN1_SHIFT	24
3621038d102SZbigniew Bodek #define	TCR_IRGN1_WBWA	(0x1UL << TCR_IRGN1_SHIFT)
3631038d102SZbigniew Bodek #define	TCR_SH0_SHIFT	12
3641038d102SZbigniew Bodek #define	TCR_SH0_IS	(0x3UL << TCR_SH0_SHIFT)
3651038d102SZbigniew Bodek #define	TCR_ORGN0_SHIFT	10
3661038d102SZbigniew Bodek #define	TCR_ORGN0_WBWA	(0x1UL << TCR_ORGN0_SHIFT)
3671038d102SZbigniew Bodek #define	TCR_IRGN0_SHIFT	8
3681038d102SZbigniew Bodek #define	TCR_IRGN0_WBWA	(0x1UL << TCR_IRGN0_SHIFT)
3691038d102SZbigniew Bodek 
3701038d102SZbigniew Bodek #define	TCR_CACHE_ATTRS	((TCR_IRGN0_WBWA | TCR_IRGN1_WBWA) |\
3711038d102SZbigniew Bodek 				(TCR_ORGN0_WBWA | TCR_ORGN1_WBWA))
3721038d102SZbigniew Bodek 
3731038d102SZbigniew Bodek #ifdef SMP
3741038d102SZbigniew Bodek #define	TCR_SMP_ATTRS	(TCR_SH0_IS | TCR_SH1_IS)
3751038d102SZbigniew Bodek #else
3761038d102SZbigniew Bodek #define	TCR_SMP_ATTRS	0
3771038d102SZbigniew Bodek #endif
3781038d102SZbigniew Bodek 
379e5acd89cSAndrew Turner #define	TCR_T1SZ_SHIFT	16
380e5acd89cSAndrew Turner #define	TCR_T0SZ_SHIFT	0
38180c4b9e5SAndrew Turner #define	TCR_T1SZ(x)	((x) << TCR_T1SZ_SHIFT)
38280c4b9e5SAndrew Turner #define	TCR_T0SZ(x)	((x) << TCR_T0SZ_SHIFT)
38380c4b9e5SAndrew Turner #define	TCR_TxSZ(x)	(TCR_T1SZ(x) | TCR_T0SZ(x))
384e5acd89cSAndrew Turner 
385e5acd89cSAndrew Turner /* Saved Program Status Register */
386e5acd89cSAndrew Turner #define	DBG_SPSR_SS	(0x1 << 21)
387e5acd89cSAndrew Turner 
388e5acd89cSAndrew Turner /* Monitor Debug System Control Register */
389e5acd89cSAndrew Turner #define	DBG_MDSCR_SS	(0x1 << 0)
390e5acd89cSAndrew Turner #define	DBG_MDSCR_KDE	(0x1 << 13)
391e5acd89cSAndrew Turner #define	DBG_MDSCR_MDE	(0x1 << 15)
392e5acd89cSAndrew Turner 
393bc88bb2bSRuslan Bukin /* Perfomance Monitoring Counters */
394bc88bb2bSRuslan Bukin #define	PMCR_E		(1 << 0) /* Enable all counters */
395bc88bb2bSRuslan Bukin #define	PMCR_P		(1 << 1) /* Reset all counters */
396bc88bb2bSRuslan Bukin #define	PMCR_C		(1 << 2) /* Clock counter reset */
397bc88bb2bSRuslan Bukin #define	PMCR_D		(1 << 3) /* CNTR counts every 64 clk cycles */
398bc88bb2bSRuslan Bukin #define	PMCR_X		(1 << 4) /* Export to ext. monitoring (ETM) */
399bc88bb2bSRuslan Bukin #define	PMCR_DP		(1 << 5) /* Disable CCNT if non-invasive debug*/
400bc88bb2bSRuslan Bukin #define	PMCR_LC		(1 << 6) /* Long cycle count enable */
401bc88bb2bSRuslan Bukin #define	PMCR_IMP_SHIFT	24 /* Implementer code */
402bc88bb2bSRuslan Bukin #define	PMCR_IMP_MASK	(0xff << PMCR_IMP_SHIFT)
403bc88bb2bSRuslan Bukin #define	PMCR_IDCODE_SHIFT	16 /* Identification code */
404bc88bb2bSRuslan Bukin #define	PMCR_IDCODE_MASK	(0xff << PMCR_IDCODE_SHIFT)
405bc88bb2bSRuslan Bukin #define	 PMCR_IDCODE_CORTEX_A57	0x01
406bc88bb2bSRuslan Bukin #define	 PMCR_IDCODE_CORTEX_A72	0x02
407bc88bb2bSRuslan Bukin #define	 PMCR_IDCODE_CORTEX_A53	0x03
408bc88bb2bSRuslan Bukin #define	PMCR_N_SHIFT	11       /* Number of counters implemented */
409bc88bb2bSRuslan Bukin #define	PMCR_N_MASK	(0x1f << PMCR_N_SHIFT)
410bc88bb2bSRuslan Bukin 
411e5acd89cSAndrew Turner #endif /* !_MACHINE_ARMREG_H_ */
412